BUK112-50GL

Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET DESCRIPTION Monolithic temperature and overload protected logic level power MOSFET in a 5 pin plastic envelope, intended as a low side switch for automotive applications. BUK112-50GL QUICK REFERENCE DATA SYMBOL VDS ID Tj RDS(ON) SYMBOL VPS PARAMETER Continuous drain source voltage Continuous drain current Continuous junction temperature Drain-source on-state resistance PARAMETER Protection supply voltage MAX. 50 12 150 93 NOM. 5 UNIT V A ˚C mΩ UNIT V FEATURES Vertical power DMOS output stage Low on-state resistance Low operating supply current Overtemperature protection Overload protection against short circuit load with drain current limiting Latched overload protection reset by protection supply Protection circuit condition indicated by flag pin Off-state detection of open circuit load indicated by flag pin 5 V logic compatible input level Integral input resistors. ESD protection on all pins Over voltage clamping FUNCTIONAL BLOCK DIAGRAM PROTECTION SUPPLY DRAIN FLAG OC LOAD DETECT O/V CLAMP INPUT POWER RIG MOSFET LOGIC AND PROTECTION RIS SOURCE Fig.1. Elements of the TOPFET. PINNING - SOT263 PIN 1 2 3 4 5 tab input flag drain protection supply source DESCRIPTION PIN CONFIGURATION tab SYMBOL D TOPFET P F I P 1 2345 leadform 263-01 S Fig. 2. drain Fig. 3. September 1996 1 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET LIMITING VALUES Limiting values in accordance with the Absolute Maximum Rating System (IEC 134) SYMBOL VDS ID II IF IP Ptot Tstg Tj Tsold PARAMETER Continuous voltage Drain source voltage1 Continuous currents Drain current Input current Flag current Protection supply current Thermal Total power dissipation Storage temperature Junction temperature2 Lead temperature Tmb = 25 ˚C continuous during soldering -55 VPS = 5 V; Tmb = 25 ˚C VPS = 0 V; Tmb = 94 ˚C -5 -5 -5 VIS = 0 V CONDITIONS MIN. BUK112-50GL MAX. 50 self limited 12 5 5 5 52 175 150 260 UNIT V A A mA mA mA W ˚C ˚C ˚C ESD LIMITING VALUES SYMBOL PARAMETER Electrostatic discharge capacitor voltages VC1 VC2 Drain to source Input, flag or protection to source CONDITIONS Human body model; C = 100 pF; R = 1.5 kΩ 4.5 2 kV kV MIN. MAX. UNIT OVERLOAD PROTECTION LIMITING VALUE With the protection supply connected, TOPFET can protect itself from two types of overload short circuit load and overtemperature. SYMBOL VPSP PARAMETER Protection supply voltage 3 For overload conditions an n-MOS transistor turns on between the gate and source to quickly discharge the power MOSFET gate capacitance. CONDITIONS for valid protection The drain current is limited to reduce dissipation in case of short circuit load. Refer to OVERLOAD CHARACTERISTICS. MIN. 4.5 MAX. UNIT V OVERVOLTAGE CLAMPING LIMITING VALUES At a drain source voltage above 50 V the power MOSFET is actively turned on to clamp overvoltage transients. SYMBOL EDSM EDRM PARAMETER Non-repetitive clamping energy Repetitive clamping energy CONDITIONS IDM = 6 A; Tmb = 25˚C IDM = 3.1 A; VDD ≤ 20 V; Tmb ≤ 120˚C; f = 250 Hz MIN. MAX. 200 20 UNIT mJ mJ 1 Prior to the onset of overvoltage clamping. For voltages above this value, safe operation is limited by the overvoltage clamping energy. 2 A higher Tj is allowed as an overload condition but at the threshold Tj(TO) the over temperature trip operates to protect the switch. 3 The minimum supply voltage required for correct operation of the overload protection circuits. September 1996 2 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET THERMAL CHARACTERISTICS SYMBOL Rth j-mb Rth j-a PARAMETER Thermal resistance Junction to mounting base Junction to ambient in free air CONDITIONS MIN. BUK112-50GL TYP. 60 MAX. 2.38 - UNIT K/W K/W OUTPUT CHARACTERISTICS Tmb = 25 ˚C; VPS = 0 V unless otherwise specified SYMBOL V(CL)DSS IDSS PARAMETER Off-state Drain-source clamping voltage Drain-source leakage current 1 CONDITIONS ID = 10 mA; VIS = 0 V; -40˚C ≤ Tmb ≤ 150˚C MIN. 50 50 - TYP. 60 0.5 1 10 70 135 MAX. 70 70 10 20 100 93 165 UNIT V V µA µA µA mΩ mΩ IDM = 0.75 A; tp ≤ 300 µs; δ ≤ 0.01 VDS = 13 V VDS = 50 V Tmb = 125 ˚C; VDS = 40 V On-state RDS(ON) Drain-source on-resistance tp ≤ 300 µs; δ ≤ 0.01 IDM = 6 A; VIS = 4.4 V; VPS = 4.5 V Tmb = 150 ˚C INPUT CHARACTERISTICS Tmb = 25 ˚C unless otherwise specified SYMBOL VIS(TO) IIS V(CL)IS RIG IISL PARAMETER Normal operation Input threshold voltage Input current Input clamping voltage Internal series resistance Overload protection latched Input current VPS = 5 V; VIS = 5 V 1.5 3.2 4 mA VDS = 13 V; VPS = 0 V; ID = 1 mA -40˚C ≤ Tmb ≤ 150˚C VIS = 5 V II = 1.5 mA to gate of power MOSFET -40˚C ≤ Tmb ≤ 150˚C 1 0.5 200 6 1.5 350 7.1 1.5 2 2.5 500 V V µA V kΩ CONDITIONS MIN. TYP. MAX. UNIT REVERSE CHARACTERISTICS Tmb = 25 ˚C SYMBOL -VDS -VIS -VPS -VFS PARAMETER Reverse drain voltage Reverse input voltage Reverse protection pin voltage Reverse flag voltage 2 CONDITIONS -ID = 6 A -II = 5 mA -IP = 5 mA -IF = 5 mA MIN. - TYP. 0.8 0.7 0.7 0.7 MAX. - UNIT V V V V 1 The drain current required for open circuit load detection is switched off when there is no protection supply, in order to ensure a low off-state quiescent current. Refer to OPEN CIRCUIT LOAD DETECTION CHARACTERISTICS. 2 Protection functions are disabled during reverse conduction. September 1996 3 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET PROTECTION SUPPLY CHARACTERISTICS Tmb = 25 ˚C unless otherwise specified SYMBOL PARAMETER Normal operation or protection latched IPS, IPSL V(CL)PS VPSR t pr Supply current Clamping voltage Overload protection latched Reset voltage Reset time VPS = 0 V -40˚C ≤ Tmb ≤ 150˚C -40˚C ≤ Tmb ≤ 150˚C 1.5 VPS = 4.5 V IP = 1.5 mA -40˚C ≤ Tmb ≤ 150˚C 6 CONDITIONS MIN. BUK112-50GL TYP. MAX. UNIT 330 7.1 400 450 - µA µA V 2.1 25 - 3 150 V V µs µs OPEN CIRCUIT LOAD DETECTION CHARACTERISTICS An open circuit load condition can be detected while the TOPFET is in the off-state. -40˚C ≤ Tmb ≤ 150˚C; VPS = 5 V; VDS = 13 V unless otherwise specified SYMBOL IDSP IDSF VISF PARAMETER Off-state drain current 1 CONDITIONS VIS = 0 V IF = 100 µA; ID = 100 µA; Tmb = 25 ˚C MIN. 0.5 0.4 - TYP. 1.4 1.1 1.2 MAX. 2 - UNIT mA mA V Off-state drain threshold current VIS = 0 V; IF = 100 µA Input threshold voltage2 TRUTH TABLE For normal, open-circuit load and overload conditions or inadequate protection supply voltage. CONDITION Normal on-state Normal off-state Open circuit load Open circuit load Short circuit load Over temperature Low protection supply voltage Low protection supply voltage PROTECTION 1 1 1 1 1 1 0 0 INPUT 1 0 1 0 1 X 1 0 FLAG 0 0 0 1 1 1 1 1 OUTPUT 1 0 1 0 0 0 1 0 For protection ‘0’ equals low, ‘1’ equals high. For input ‘0’ equals low, ‘1’ equals high, ‘X’ equals don’t care. For flag ‘0’ equals low, ‘1’ equals open or high. For output switch ‘0’ equals off, ‘1’ equals on. 1 The drain source current which flows when the protection supply is high and the input is low. 2 For open circuit load indication, VIS must be less than VISF. September 1996 4 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET OVERLOAD CHARACTERISTICS Tmb = 25 ˚C; VPS = 5 V unless otherwise specified SYMBOL ID PD(TO) EDSC IDM PARAMETER Short circuit load protection Drain current limiting Overload power threshold1 Characteristic energy Peak drain current3 Overtemperature protection Tj(TO) Threshold temperature ID ≥ 1 A 150 CONDITIONS VIS = 5 V VDS = 13 V -40˚C ≤ Tmb ≤ 150˚C MIN. 12 - BUK112-50GL TYP. 24 100 200 45 MAX. 36 - UNIT A W mJ A for protection to operate which determines trip time2 VDD = 13 V; RL ≤ 10 mΩ 185 215 ˚C FLAG CHARACTERISTICS The flag is an open drain transistor which requires an external pull-up circuit. Tmb = 25 ˚C unless otherwise specified SYMBOL VFSF IFSF IFSO V(CL)FS VPSF PARAMETER Flag ‘low’ Flag voltage Flag saturation current Flag ‘high’ Flag leakage current Flag clamping voltage Protection supply threshold voltage4 Application information RF Suitable external pull-up resistance VFF = 5 V 50 kΩ CONDITIONS normal operation; VPS = 5 V IF = 100 µA -40˚C ≤ Tmb ≤ 150˚C VFS = 5 V overload or fault VFS = 5 V IF = 100 µA IF = 100 µA; VDS = 5 V -40˚C ≤ Tmb ≤ 150˚C Tmb = 150˚C 6 2.5 2 0.1 1 6.9 3 1 10 4 4 µA µA V V V 0.7 10 0.9 V V mA MIN. TYP. MAX. UNIT 1 Refer to figure 15. 2 Trip time td sc ≈ EDSC / [ PD - PD(TO) ]. Refer also to figure 15. 3 For short circuit load connected after turn-on. 4 When VPS is less than VPSF the flag pin indicates low protection supply voltage. Refer to TRUTH TABLE. September 1996 5 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET SWITCHING CHARACTERISTICS Tmb = 25 ˚C SYMBOL td on tr td off tf PARAMETER Resistive load Turn-on delay time Rise time Turn-off delay time Fall time Inductive load td on tr td off tf Turn-on delay time Rise time Turn-off delay time Fall time VIS: 5 V ⇒ 0 V ID = 3 A; VDD = 13 V; with freewheel diode VIS: 0 V ⇒ 5 V VIS: 5 V ⇒ 0 V CONDITIONS RL = 4 Ω; ID = 3 A VIS: 0 V ⇒ 5 V MIN. BUK112-50GL TYP. 0.6 2.8 3.5 3.2 MAX. - UNIT µs µs µs µs 0.9 1.2 6.7 0.6 - µs µs µs µs September 1996 6 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET BUK112-50GL VIN VIS (input) 0V VCC VGS (internal) 0V VDS(OFF) VDS (output) VDS(ON) SHORT CIRCUIT FAULT PROTECTION RESET VCC LOSS OF PROT’N SUPPLY PROTECTION RESET VPS (protection supply) 0V VCC VFS (flag) 0V NORMAL OPERATION FAULT CONDITION NORMAL OPERATION FAULT CONDITION NORMAL OPERATION Fig. 4. Waveforms for normal and fault conditions. VIN VIS (input) 0V VCC VGS (internal) 0V VDS(OFF) VDS (output) VDS(ON) VCC VPS (protection supply) 0V VCC VFS (flag) 0V NORMAL OPERATION OPEN LOAD NORMAL OPERATION OPEN LOAD NORMAL OPERATION Fig. 5. Waveforms for normal and open circuit load. September 1996 7 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET BUK112-50GL 120 110 100 90 80 70 60 50 40 30 20 10 0 PD% Normalised Power Derating 50 ID / A WITHOUT PROTECTION BUK112-50GL VIS / V = 40 7 6 30 5 20 4 10 3 0 20 40 60 80 100 Tmb / C 120 140 0 0 5 10 VDS / V 15 20 Fig.6. Normalised limiting power dissipation. PD% = 100⋅PD/PD(25˚C) = f(Tmb) ID / A BUK112-50GL Fig.9. Typical output characteristics, Tj = 25˚C. ID = f(VDS); tp = 250 µs; VPS = 0 V; parameter VIS ID / A WITHOUT PROTECTION 25 20 15 BUK112-50GL VPS = 0 V 14 12 10 8 6 4 2 0 30 VPS = 5 V CURRENT LIMITING 10 5 0 WITH PROTECTION 0 50 Tmb / C 100 150 0 1 2 VDS / V 3 4 5 Fig.7. Continuous limiting drain current. ID = f(Tmb); conditions: VIS = 5 V; VPS = 5 V ID / A WITH PROTECTION BUK112-50GL VIS / V = 7 6 5 15 CURRENT LIMITING 4 Fig.10. Typical on-state characteristics, Tj = 25˚C. ID = f(VDS); VIS = 5 V; tp = 250 µs; parameter VPS RDS(ON) / mOhm BUK112-50GL 25 200 20 150 100 TYP. 10 3 50 5 0 0 5 10 15 VDS / V 20 25 30 0 0 1 2 3 4 VIS / V 5 6 7 8 Fig.8. Typical output characteristics, Tj = 25˚C. ID = f(VDS); tp = 250 µs; VPS = 5 V; parameter VIS Fig.11. Typical on-state resistance, Tj = 25˚C. RDS(ON) = f(VIS); tp = 250 µs; parameter VIS September 1996 8 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET BUK112-50GL a Normalised RDS(ON) = f(Tj) 5 1 / [td sc / ms] RECIPROCAL TRIP TIME BUK112-50GL 1.5 4 1.0 3 intercept = PD(TO) 2 1/slope = EDSC 0.5 1 0 OVERLOAD DISSIPATION -60 -40 -20 0 20 40 60 Tj / C 80 100 120 140 0 0 200 400 600 PD / W 800 1000 1200 Fig.12. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25˚C = f(Tj); ID = 6 A; VIS ≥ 4.4 V ID / A BUK112-50GL Fig.15. Typical reciprocal overload trip time. 1/td sc = f(PD); conditions: VPS = 5 V, Tmb = 25˚C ESC(TO) / mJ BUK112-50GL 50 500 40 VPS = 0 V 400 30 300 TYP. 20 VPS = 5 V 10 200 100 0 0 1 2 3 4 VIS / V 5 6 7 8 0 0 50 100 Tmb / C 150 200 Fig.13. Typical transfer characteristics, Tj = 25˚C. ID = f(VIS) ; conditions: VDS = 10 V; tp = 250 µs ID / A VIS / V = 25 20 15 10 5 0 VPSP MIN. 7 6 5 4.4 4 BUK112-50GL Fig.16. Typical overload protection energy. ESC(TO) = f(Tmb); VDD = 13 V; VPS = 5 V, VIS = 5 V Tj(TO) / C BUK112-50GL 30 210 200 190 180 170 160 150 TYP. VPSP MIN. 4 5 6 VPS / V 7 8 3 4 5 VPS / V 6 7 8 Fig.14. Typical output current limiting, Tj = 25˚C. ID = f(VPS); tp = 250 µs; VDS = 10 V; parameter VIS Fig.17. Typical overtemperature protection threshold. Tj(TO) = f(VPS); VIS = 5 V; ID ≥ 1 A September 1996 9 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET BUK112-50GL 2 II / mA BUK112-50GL 2 IP / mA BUK112-50GL 1.5 1.5 1 1 0.5 0.5 0 0 0 1 2 3 4 VIS / V 5 6 7 8 0 1 2 3 4 VPS / V 5 6 7 8 Fig.18. Typical DC input characteristic. II = f(VIS) normal operation; Tj = 25˚C IISL / mA BUK112-50GL Fig.21. Typical protection supply characteristics. IP = f(VPS); normal or overload operation; Tj = 25˚C IF / mA BUK112-50GL 8 7 6 5 4 3 2 1 0 2 1.5 1 0.5 0 0 1 2 3 4 VIS / V 5 6 7 8 0 1 2 3 4 VFS / V 5 6 7 8 Fig.19. Typical DC input characteristic, Tj = 25˚C. IISL = f(VIS) overload protection latched; VPS = 5 V VIS(TO) / V Fig.22. Typical flag high characteristic, Tj = 25˚C. IF = f(VFS); refer to TRUTH TABLE IF / uA BUK112-50GL 200 max. 2 150 typ. 100 1 min. 50 0 -60 -40 -20 0 20 40 60 Tj / C 80 100 120 140 0 0 0.1 0.2 0.3 0.4 VFS / F 0.5 0.6 0.7 0.8 Fig.20. Input threshold voltage. VIS(TO) = f(Tj); conditions: ID = 1 mA; VDS = 5 V Fig.23. Typical flag low characteristic, Tj = 25˚C. IF = f(VFS); VPS = 5 V; refer to TRUTH TABLE September 1996 10 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET BUK112-50GL 20 IF / mA BUK112-50GL 3 VPSR / V BUK112-50GL 15 2.5 typ. 10 2 5 1.5 0 0 1 2 3 4 5 VFS / V 6 7 8 9 1 -50 0 50 Tj / C 100 150 200 Fig.24. Typical flag saturation current, Tj = 25˚C. IF = f(VFS); flag ’low’; external RF = 0 kΩ; VPS = 5 V VFSF / V BUK112-50GL Fig.27. Protection supply reset voltage. VPSR = f(Tj) IP / uA BUK112-50GL 1 600 500 400 0.8 0.6 300 0.4 200 0.2 100 0 -50 0 -50 0 50 Tj / C 100 150 200 0 50 Tmb / C 100 150 200 Fig.25. Typical flag low voltage. VFSF = f(Tj); VPS = 5 V; VIS = 5 V; VDS = 0 V VPSF / V BUK112-50GL Fig.28. Typical protection supply current. IP = f(Tj); VPS = 4.5 V IS / A BUK112-50GL 4 40 3.5 typ. 3 30 20 2.5 10 2 -50 0 50 Tj / C 100 150 200 0 0 0.2 0.4 0.6 0.8 VSD / V 1 1.2 1.4 Fig.26. Protection supply threshold voltage. VPSF = f(Tj); condition: VDS = 5 V Fig.29. Typical reverse diode current, Tj = 25˚C. IS = f(VSD); conditions: VIS = 0 V; tp = 250 µs September 1996 11 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET BUK112-50GL 12 10 8 ID / A BUK112-50GL 5 ID / mA OVERVOLTAGE CLAMPING BUK112-50GL 4 3 6 OPEN CIRCUIT LOAD DETECTION 2 VPS = 5 V 1 IDSF VPS = 0 V 20 30 40 VDS / V IDSS 50 60 70 IDSP 4 2 0 50 55 60 VIS / V 65 70 0 0 10 Fig.30. Typical clamping characteristics, 25˚C. ID = f(VDS); conditions: VIS = 0 V; tp ≤ 50 µs EDSM% Fig.33. Typical off-state characteristics, Tj = 25˚C. ID = f(VDS); VIS = 0 V; parameter VPS IDSP & IDSF / mA BUK112-50GL 120 110 100 90 80 70 60 50 40 30 20 10 0 2 IDSP 1.5 IDSF 1 0.5 0 0 20 40 60 80 Tmb / C 100 120 140 0 2 4 VPS / V 6 8 Fig.31. Normalised limiting clamping energy. EDSM% = f(Tmb); conditions: ID = 6 A V(CL)DSP VDS VDD 0 ID 0 VIS 0 RF P F I P Fig.34. Typical open circuit load detect currents. IDSP & IDSF = f(VPS); VIS = 0 V; VDS ≥ 5 V; Tj = 25˚C IDSP & IDSF / mA BUK112-50GL 2 + L VDS D TOPFET VDD 1.5 IDSP + VPS -ID/100 D.U.T. 1 IDSF 0.5 S R 01 shunt 0 -50 0 50 Tmb / C 100 150 200 Fig.32. Clamping energy test circuit. 2 EDSM = 0.5 ⋅ LID ⋅ V(CL )DSS /(V(CL )DSS − VDD ) Fig.35. Typical open circuit load detect currents. IDSP & IDSF = f(Tj); VPS = 5 V; VIS = 0 V September 1996 12 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET BUK112-50GL 1 mA Idss 10 Zth / (K/W) BUK112-50GL D= 100 uA 1 10 uA 0.5 0.2 0.1 typ. 0.1 1 uA 0.05 0.02 0 P D tp D= tp T t 100 nA 0 20 40 60 80 Tj / C 100 120 140 0.01 1E-07 T 1E-05 1E-03 t/s 1E-01 1E+01 Fig.36. Typical off-state leakage current. IDSS = f(Tj); Conditions: VDS = 40 V; VIS = 0 V. ID & IDM / A S/ ID Fig.38. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T Coss BUK112-50GL 100 BUK112-50GL tp = 10 us 10 nF RD S( ON ) D =V 10 DC Overload protection characteristics not shown. 100 us 1 nF 1 ms 10 ms 100 ms 100 pF 1 1 10 VDS / V 100 0 10 20 VDS / V 30 40 50 Fig.37. Safe operating area, VPS = 0 V, Tmb = 25˚C. ID & IDM = f(VDS); IDM single pulse; parameter tp Fig.39. Typical output capacitance. Coss = f(VDS); conditions: VIS = 0 V; f = 1 MHz September 1996 13 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET APPLICATION INFORMATION From main control loop BUK112-50GL Take input low Wait typ 15 us no Is Flag High? yes Wait for cooling Wait >= 1 min Return to main control loop RESET Take prot’n supply low Wait >= 150 us Take prot’n supply high Wait typ 15 us yes Is Flag High? no Take input high Wait typ 15 us yes Is Flag High? no Take input low Take input low Record fault S/C or over temp. Record Fault Open load Record Fault Low prot’n supply Fig. 40. Possible fault diagnosis procedure. September 1996 14 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET MECHANICAL DATA Dimensions in mm Net Mass: 2 g BUK112-50GL 4.5 max 10.3 max 1.3 3.6 2.8 mounting base 5.9 min 3.5 max not tinned R 0. (2) 5 m 2.4 max 15.8 max in 5.6 0.5 12 3 45 (1) 9.75 0. 5 m in 5 R 0.6 min (4 x) 0.9 max (5 x) NOTES (1) (2) 1.7 (4 x) 0.6 4.5 2.4 0.4 (1) M 8.2 positional accuracy of the terminals is controlled in this zone only. terminal dimensions in this zone are uncontrolled. Fig.41. SOT263 leadform 263-01; pin 3 connected to mounting base. Note 1. Refer to mounting instructions for TO220 envelopes. 2. Epoxy meets UL94 V0 at 1/8". September 1996 15 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET DEFINITIONS Data sheet status Objective specification Product specification Limiting values BUK112-50GL This data sheet contains target or goal specifications for product development. This data sheet contains final product specifications. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. © Philips Electronics N.V. 1996 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. September 1996 16 Rev 1.000