BUK543-100B

Philips Semiconductors Product Specification PowerMOS transistor Logic level FET GENERAL DESCRIPTION N-channel enhancement mode logic level field-effect power transistor in a plastic full-pack envelope. The device is intended for use in Switched Mode Power Supplies (SMPS), motor control, welding, DC/DC and AC/DC converters, and in automotive and general purpose switching applications. BUK543-100A/B QUICK REFERENCE DATA SYMBOL VDS ID Ptot RDS(ON) PARAMETER BUK543 Drain-source voltage Drain current (DC) Total power dissipation Drain-source on-state resistance; VGS = 5 V MAX. -100A 100 8.3 25 0.18 MAX. -100B 100 7.5 25 0.22 UNIT V A W Ω PINNING - SOT186 PIN 1 2 3 gate drain source DESCRIPTION PIN CONFIGURATION case SYMBOL d g case isolated 123 s LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL VDS VDGR ±VGS ±VGSM ID ID IDM Ptot Tstg Tj PARAMETER Drain-source voltage Drain-gate voltage Gate-source voltage Non-repetitive gate-source voltage Drain current (DC) Drain current (DC) Drain current (pulse peak value) Total power dissipation Storage temperature Junction Temperature CONDITIONS RGS = 20 kΩ tp ≤ 50 µs Ths = 25 ˚C Ths = 100 ˚C Ths = 25 ˚C Ths = 25 ˚C MIN. - 55 -100A 8.3 5.2 33 25 150 150 MAX. 100 100 15 20 -100B 7.5 4.7 30 UNIT V V V V A A A W ˚C ˚C THERMAL RESISTANCES SYMBOL Rth j-hs Rth j-a PARAMETER Thermal resistance junction to heatsink Thermal resistance junction to ambient CONDITIONS with heatsink compound MIN. TYP. 55 MAX. 5.0 UNIT K/W K/W April 1993 1 Rev 1.100 Philips Semiconductors Product Specification PowerMOS transistor Logic level FET STATIC CHARACTERISTICS Ths = 25 ˚C unless otherwise specified SYMBOL V(BR)DSS VGS(TO) IDSS IDSS IGSS RDS(ON) PARAMETER Drain-source breakdown voltage Gate threshold voltage Zero gate voltage drain current Zero gate voltage drain current Gate source leakage current Drain-source on-state resistance CONDITIONS VGS = 0 V; ID = 0.25 mA VDS = VGS; ID = 1 mA VDS = 100 V; VGS = 0 V; Tj = 25 ˚C VDS = 100 V; VGS = 0 V; Tj =125 ˚C VGS = ±15 V; VDS = 0 V VGS = 5 V; BUK543-100A BUK543-100B ID = 5 A MIN. 100 1.0 - BUK543-100A/B TYP. 1.5 1 0.1 10 0.17 0.20 MAX. 2.0 10 1.0 100 0.18 0.22 UNIT V V µA mA nA Ω Ω DYNAMIC CHARACTERISTICS Ths = 25 ˚C unless otherwise specified SYMBOL gfs Ciss Coss Crss td on tr td off tf Ld Ls PARAMETER Forward transconductance Input capacitance Output capacitance Feedback capacitance Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal source inductance CONDITIONS VDS = 25 V; ID = 5 A VGS = 0 V; VDS = 25 V; f = 1 MHz VDD = 30 V; ID = 3 A; VGS = 5 V; RGS = 50 Ω; Rgen = 50 Ω Measured from drain lead 6 mm from package to centre of die Measured from source lead 6 mm from package to source bond pad MIN. 6.0 TYP. 8.0 620 180 90 10 45 90 40 4.5 7.5 MAX. 825 250 120 20 60 115 55 UNIT S pF pF pF ns ns ns ns nH nH ISOLATION LIMITING VALUE & CHARACTERISTIC Ths = 25 ˚C unless otherwise specified SYMBOL Visol PARAMETER Repetitive peak voltage from all three terminals to external heatsink CONDITIONS R.H. ≤ 65% ; clean and dustfree MIN. TYP. MAX. 1500 UNIT V Cisol Capacitance from T2 to external f = 1 MHz heatsink - 12 - pF REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Ths = 25 ˚C unless otherwise specified SYMBOL IDR IDRM VSD trr Qrr PARAMETER Continuous reverse drain current Pulsed reverse drain current Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS IF = 8.3 A ; VGS = 0 V IF = 8.3 A; -dIF/dt = 100 A/µs; VGS = 0 V; VR = 30 V MIN. TYP. 1.1 80 0.5 MAX. 8.3 33 1.3 UNIT A A V ns µC April 1993 2 Rev 1.100 Philips Semiconductors Product Specification PowerMOS transistor Logic level FET AVALANCHE LIMITING VALUE Ths = 25 ˚C unless otherwise specified SYMBOL WDSS PARAMETER Drain-source non-repetitive unclamped inductive turn-off energy CONDITIONS ID = 13 A ; VDD ≤ 50 V ; VGS = 5 V ; RGS = 50 Ω MIN. - BUK543-100A/B TYP. - MAX. 70 UNIT mJ 120 110 100 90 80 70 60 50 40 30 20 10 0 PD% Normalised Power Derating with heatsink compound 100 ID / A S/ ID BUK543-100 A B 10 S RD (O N )= VD tp = 10 us 100 us 1 ms 1 DC 10 ms 100 ms 0 20 40 60 80 Ths / C 100 120 140 0.1 1 10 VDS / V 100 Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Ths) Normalised Current Derating with heatsink compound Fig.3. Safe operating area. Ths = 25 ˚C ID & IDM = f(VDS); IDM single pulse; parameter tp Zth j-hs / (K/W) ZTHX43 120 110 100 90 80 70 60 50 40 30 20 10 0 ID% 1E+01 0.5 1E+00 0.2 0.1 0.05 P D tp D= tp T t 1E-01 0.02 0 0 20 40 60 80 Ths / C 100 120 140 1E-02 1E-07 T 1E-05 1E-03 t/s 1E-01 1E+01 Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Ths); conditions: VGS ≥ 5 V Fig.4. Transient thermal impedance. Zth j-hs = f(t); parameter D = tp/T April 1993 3 Rev 1.100 Philips Semiconductors Product Specification PowerMOS transistor Logic level FET BUK543-100A/B ID / A 24 20 16 12 8 4 0 10 7 BUK553-100A 5 VGS / V = 10 9 8 7 6 5 4 gfs / S BUK543-100A 4 3 3 2 1 2 0 2 4 VDS / V 6 8 10 0 0 2 4 6 8 10 12 ID / A 14 16 18 20 Fig.5. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS); parameter VGS RDS(ON) / Ohm BUK553-100A VGS / V = 3 3.5 4 4.5 5 0.3 Fig.8. Typical transconductance, Tj = 25 ˚C. gfs = f(ID); conditions: VDS = 25 V a Normalised RDS(ON) = f(Tj) 0.5 0.4 2.0 2.5 1.5 1.0 10 0.2 0.5 0.1 0 0 0 4 8 12 16 ID / A 20 24 28 -60 -40 -20 0 20 40 60 Tj / C 80 100 120 140 Fig.6. Typical on-state resistance, Tj = 25 ˚C. RDS(ON) = f(ID); parameter VGS ID / A 15 Tj / C = 25 150 BUK543-100A Fig.9. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 5 A; VGS = 5 V VGS(TO) / V max. 2 typ. 10 min. 1 5 0 0 2 4 VGS / V 6 8 0 -60 -40 -20 0 20 40 60 Tj / C 80 100 120 140 Fig.7. Typical transfer characteristics. ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS April 1993 4 Rev 1.100 Philips Semiconductors Product Specification PowerMOS transistor Logic level FET BUK543-100A/B 1E-01 ID / A SUB-THRESHOLD CONDUCTION 30 IF / A BUK553-100A 1E-02 2% 98 % 1E-03 typ 20 Tj / C = 150 25 1E-04 10 1E-05 1E-06 0 0.4 0.8 1.2 VGS / V 1.6 2 2.4 0 0 1 VSDS / V 2 Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS C / pF BUK5y3-100 Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj WDSS% 10000 120 110 100 90 1000 Ciss 80 70 60 50 40 30 20 10 100 Coss Crss 10 0 20 VDS / V 40 0 20 40 60 80 100 Ths / C 120 140 Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz VGS / V BUK553-100 Fig.15. Normalised avalanche energy rating. WDSS% = f(Ths); conditions: ID = 13 A 12 10 8 6 4 2 0 + VDS / V =20 80 VDD L VDS VGS 0 RGS T.U.T. R 01 shunt -ID/100 0 2 4 6 8 10 12 QG / nC 14 16 18 20 Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG); conditions: ID = 13 A; parameter VDS Fig.16. Avalanche energy test circuit. 2 WDSS = 0.5 ⋅ LID ⋅ BVDSS /(BVDSS − VDD ) April 1993 5 Rev 1.100 Philips Semiconductors Product Specification PowerMOS transistor Logic level FET MECHANICAL DATA Dimensions in mm Net Mass: 2 g BUK543-100A/B 10.2 max 5.7 max 3.2 3.0 0.9 0.5 4.4 max 2.9 max 4.4 4.0 7.9 7.5 17 max seating plane 3.5 max not tinned 4.4 13.5 min 1 0.4 M 2 3 0.9 0.7 2.54 5.08 top view 1.3 0.55 max Fig.17. SOT186; The seating plane is electrically isolated from all terminals. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Refer to mounting instructions for F-pack envelopes. 3. Epoxy meets UL94 V0 at 1/8". April 1993 6 Rev 1.100 Philips Semiconductors Product Specification PowerMOS transistor Logic level FET DEFINITIONS Data sheet status Objective specification Product specification Limiting values BUK543-100A/B This data sheet contains target or goal specifications for product development. This data sheet contains final product specifications. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. © Philips Electronics N.V. 1996 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. April 1993 7 Rev 1.100 Error Log 543-100.A&B 1) Level: Format Error Message: Page break required with Keep enabled Location: Document Body Page E1 96-11-11 04:07 pm