BUK6C2R1-55C

D2 PA K BUK6C2R1-55C N-channel TrenchMOS intermediate level FET Rev. 3 — 18 January 2012 Product data sheet 1. Product profile 1.1 General description Intermediate level gate drive N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product has been designed and qualified to the appropriate AEC standard for use in high-performance automotive applications. 1.2 Features and benefits  AEC Q101 compliant  High current handling capability, up to 320 A  Low conduction losses due to very low on-state resistance  Suitable for standard and logic level gate drive sources  Suitable for thermally demanding environments due to 175 °C rating 1.3 Applications  12 V automotive systems  Electric and electro-hydraulic power steering  Motors, lamps and solenoids  Start-Stop micro-hybrid applications  Transmission control  Ultra high performance power switching 1.4 Quick reference data Table 1. Symbol VDS ID Ptot RDSon Quick reference data Parameter drain-source voltage drain current total power dissipation drain-source on-state resistance Conditions Tj ≥ 25 °C; Tj ≤ 175 °C VGS = 10 V; Tmb = 25 °C; see Figure 1 Tmb = 25 °C; see Figure 2 VGS = 10 V; ID = 90 A; Tj = 25 °C; see Figure 11 Min Typ 1.9 Max 55 228 300 2.3 Unit V A W mΩ Static characteristics NXP Semiconductors BUK6C2R1-55C N-channel TrenchMOS intermediate level FET Quick reference data …continued Parameter gate-drain charge Conditions ID = 180 A; VDS = 44 V; VGS = 10 V; see Figure 13; see Figure 14 ID = 120 A; Vsup ≤ 55 V; RGS = 50 Ω; VGS = 10 V; Tj(init) = 25 °C; unclamped Min Typ 79 Max Unit nC Table 1. Symbol QGD Dynamic characteristics Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy 770 mJ 2. Pinning information Table 2. Pin 1 2 3 4 5 6 7 mb Pinning information Symbol Description G S S D S S S D gate source source drain[1] source source source mounting base; connected to drain 4 123 567 mb D Simplified outline Graphic symbol G mbb076 S SOT427 (D2PAK) [1] It is not possible to connect to pin 4 of the SOT427 package. 3. Ordering information Table 3. Ordering information Package Name BUK6C2R1-55C D2PAK Description Version plastic single-ended surface-mounted package (D2PAK); 7 leads SOT427 (one lead cropped) Type number BUK6C2R1-55C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 3 — 18 January 2012 2 of 13 NXP Semiconductors BUK6C2R1-55C N-channel TrenchMOS intermediate level FET 4. Limiting values Table 4. Symbol VDS VGS ID Limiting values Parameter drain-source voltage gate-source voltage drain current Conditions Tj ≥ 25 °C; Tj ≤ 175 °C Pulsed DC Tmb = 25 °C; VGS = 10 V; see Figure 1 Tamb = 100 °C; VGS = 10 V; see Figure 1 IDM Ptot Tstg Tj IS ISM EDS(AL)S peak drain current total power dissipation storage temperature junction temperature source current peak source current non-repetitive drain-source avalanche energy Tmb = 25 °C pulsed; tp ≤ 10 µs; Tmb = 25 °C ID = 120 A; Vsup ≤ 55 V; RGS = 50 Ω; VGS = 10 V; Tj(init) = 25 °C; unclamped Tmb = 25 °C; pulsed; tp ≤ 10 µs; see Figure 3 Tmb = 25 °C; see Figure 2 [1] [2] In accordance with the Absolute Maximum Rating System (IEC 60134). Min -20 -16 -55 -55 Max 55 20 16 228 162 914 300 175 175 228 914 770 Unit V V V A A A W °C °C A A mJ Source-drain diode Avalanche ruggedness [1] [2] Accumulated pulse duration not to exceed 5mins. -16V accumulated duration not to exceed 168 hrs. 250 ID (A) 200 003aaf964 120 Pder (%) 80 03na19 150 100 40 50 0 0 50 100 150 200 Tmb (°C) 0 0 50 100 150 Tmb (°C) 200 Fig 1. Continuous drain current as a function of mounting base temperature Fig 2. Normalized total power dissipation as a function of mounting base temperature BUK6C2R1-55C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 3 — 18 January 2012 3 of 13 NXP Semiconductors BUK6C2R1-55C N-channel TrenchMOS intermediate level FET 104 ID (A) 103 Limit RDSon = VDS / ID tp =10 μ s 10 2 003aaf965 100 μ s 10 1 ms DC 1 10 ms 100 ms 10-1 10-1 1 10 102 V DS ( V) 103 Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage 5. Thermal characteristics Table 5. Symbol Rth(j-mb) Thermal characteristics Parameter thermal resistance from junction to mounting base Conditions see Figure 4 Min Typ Max 0.5 Unit K/W 1 Zth(j-mb) (K/W) 10-1 δ = 0.5 0.2 0.1 0.05 0.02 10-2 single shot tp T P 003aaf930 δ= tp T t 10-3 10-6 10-5 10-4 10-3 10-2 10-1 tp (s) 1 Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration BUK6C2R1-55C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 3 — 18 January 2012 4 of 13 NXP Semiconductors BUK6C2R1-55C N-channel TrenchMOS intermediate level FET 6. Characteristics Table 6. Symbol V(BR)DSS VGS(th) VGSth Characteristics Parameter drain-source breakdown voltage gate-source threshold voltage gate-source threshold voltage Conditions ID = 250 µA; VGS = 0 V; Tj = 25 °C ID = 250 µA; VGS = 0 V; Tj = -55 °C ID = 1 mA; VDS = VGS; Tj = 25 °C; see Figure 9; see Figure 10 ID = 2.5 mA; VDS = VGS; Tj = 175 °C; see Figure 10 ID = 1 mA; VDS = VGS; Tj = -55 °C; see Figure 10 IDSS IGSS RDSon drain leakage current gate leakage current drain-source on-state resistance VDS = 55 V; VGS = 0 V; Tj = 25 °C VDS = 55 V; VGS = 0 V; Tj = 175 °C VGS = 20 V; VDS = 0 V; Tj = 25 °C VGS = -20 V; VDS = 0 V; Tj = 25 °C VGS = 10 V; ID = 90 A; Tj = 25 °C; see Figure 11 VGS = 5 V; ID = 90 A; Tj = 25 °C; see Figure 11 VGS = 4.5 V; ID = 90 A; Tj = 25 °C; see Figure 11 VGS 10 V; ID = 90 A; Tj = 175 °C; see Figure 11; see Figure 12 Dynamic characteristics QG(tot) total gate charge ID = 180 A; VDS = 44 V; VGS = 10 V; see Figure 13; see Figure 14 ID = 180 A; VDS = 44 V; VGS = 5 V; see Figure 13; see Figure 14 QGS QGD Ciss Coss Crss td(on) tr td(off) tf VSD trr Qr gate-source charge gate-drain charge input capacitance output capacitance reverse transfer capacitance turn-on delay time rise time turn-off delay time fall time source-drain voltage reverse recovery time recovered charge IS = 80 A; VGS = 0 V; Tj = 25 °C; see Figure 16 IS = 50 A; dIS/dt = -100 A/µs; VGS = 0 V; VDS = 30 V; Tj = 25 °C VDS = 30 V; RL = 0.3 Ω; VGS = 10 V; RG(ext) = 10 Ω ID = 180 A; VDS = 44 V; VGS = 10 V; see Figure 13; see Figure 14 VGS = 0 V; VDS = 25 V; f = 1 MHz; Tj = 25 °C; see Figure 15 253 140 40 79 12000 1075 730 43 206 412 190 0.8 56 115 16000 1290 1000 1.2 nC nC nC nC pF pF pF ns ns ns ns V ns nC Min 55 50 1.8 0.8 Typ 2.3 0.04 2 2 1.9 2.4 2.6 Max 2.8 3.3 1 500 100 100 2.3 3.1 3.7 5.7 Unit V V V V V µA µA nA nA mΩ mΩ mΩ mΩ Static characteristics Source-drain diode BUK6C2R1-55C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 3 — 18 January 2012 5 of 13 NXP Semiconductors BUK6C2R1-55C N-channel TrenchMOS intermediate level FET 400 ID (A) 300 VGS ( V) =10.0 6.0 5.0 003aaf967 300 ID (A) 003aaf968 4.5 4.0 200 200 3.8 3.6 100 Tj = 175 °C 3 .4 3.3 Tj = 25 °C 100 0 0 0.5 1 1.5 VDS ( V) 2 0 0 2 4 VGS ( V) 6 Tj = 25 °C; tp = 300 μs Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values 003aaf969 Fig 6. Transfer characteristics: drain current as a function of gate-source voltage; typical values 10 003aaf972 400 gfs (S) 300 RDSon (mΩ) 8 6 200 4 100 2 0 0 100 200 I D (A) 300 0 0 5 10 15 VGS ( V) 20 Fig 7. Forward transconductance as a function of drain current; typical values Fig 8. Drain-source on-state resistance as a function of gate-source voltage; typical values BUK6C2R1-55C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 3 — 18 January 2012 6 of 13 NXP Semiconductors BUK6C2R1-55C N-channel TrenchMOS intermediate level FET 10-1 ID (A) 10-2 003aad806 4 VGS(th) (V) 3 max @1mA 003aae542 min 10-3 typ max 2 typ @1mA 10 -4 10-5 1 min @2.5mA 10-6 0 1 2 3 VGS (V) 4 0 -60 0 60 120 Tj (°C) 180 Fig 9. Sub-threshold drain current as a function of gate-source voltage 10 003aaf971 Fig 10. Gate-source threshold voltage as a function of junction temperature 3 a 2.4 003aag554 RDSon (mΩ) 8 VGS (V) = 3.8 4.0 6 1.8 4 4.5 5 .0 1.2 2 10.0 0.6 0 0 100 200 300 I D (A) 400 0 -60 0 60 120 Tj (°C) 180 Tj = 25 °C; tp = 300 µs Fig 11. Drain-source on-state resistance as a function of drain current; typical values Fig 12. Normalized drain-source on-state resistance factor as a function of junction temperature BUK6C2R1-55C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 3 — 18 January 2012 7 of 13 NXP Semiconductors BUK6C2R1-55C N-channel TrenchMOS intermediate level FET 10 VGS (V) 8 VDS = 44V 003aaf973 VDS ID 6 VGS(pl) 4 VGS(th) VGS 2 QGS1 QGS2 QGD QG(tot) 003aaa508 QGS 0 0 100 200 QG (nC) 300 Tj = 25 °C; ID = 180 A Fig 13. Gate-source voltage as a function of gate charge; typical values 105 C (pF) 104 003aaf970 Fig 14. Gate charge waveform definitions 300 IS (A) 003aaf974 Ciss 200 103 Coss Crss 100 Tj = 175 °C Tj = 25 °C 102 10-1 1 10 VDS ( V) 102 0 0 0.5 1 VSD ( V) 1.5 VGS = 0 V; f = 1 MHz Fig 15. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values VGS = 0 V Fig 16. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values BUK6C2R1-55C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 3 — 18 January 2012 8 of 13 NXP Semiconductors BUK6C2R1-55C N-channel TrenchMOS intermediate level FET 7. Package outline Plastic single-ended surface-mounted package (D2PAK); 7 leads (one lead cropped) SOT427 A E A1 D1 mounting base D HD 4 Lp 1 7 b e e e e e e c Q 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 4.50 4.10 A1 1.40 1.27 b 0.85 0.60 c 0.64 0.46 D max. 11 D1 1.60 1.20 E 10.30 9.70 e 1.27 Lp 2.90 2.10 HD 15.80 14.80 Q 2.60 2.20 OUTLINE VERSION SOT427 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 05-03-09 06-03-16 Fig 17. Package outline SOT427 (D2PAK) BUK6C2R1-55C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 3 — 18 January 2012 9 of 13 NXP Semiconductors BUK6C2R1-55C N-channel TrenchMOS intermediate level FET 8. Revision history Table 7. Revision history Release date 20120118 Data sheet status Product data sheet Preliminary data sheet Change notice Supersedes BUK6C2R1-55C v.2 BUK6C2R1-55C v.1 Document ID BUK6C2R1-55C v.3 Modifications: BUK6C2R1-55C v.2 • Status changed from preliminary to product. 20111221 BUK6C2R1-55C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 3 — 18 January 2012 10 of 13 NXP Semiconductors BUK6C2R1-55C N-channel TrenchMOS intermediate level FET 9. Legal information 9.1 Data sheet status Product status [3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Document status [1] [2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 9.2 Definitions Preview — The document is a preview version only. The document is still subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the 9.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. BUK6C2R1-55C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 3 — 18 January 2012 11 of 13 NXP Semiconductors BUK6C2R1-55C N-channel TrenchMOS intermediate level FET Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 9.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV, FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE, ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight, MoReUse, QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET, TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V. HD Radio and HD Radio logo — are trademarks of iBiquity Digital Corporation. 10. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com BUK6C2R1-55C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 3 — 18 January 2012 12 of 13 NXP Semiconductors BUK6C2R1-55C N-channel TrenchMOS intermediate level FET 11. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 9.1 9.2 9.3 9.4 10 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General description . . . . . . . . . . . . . . . . . . . . . .1 Features and benefits . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Quick reference data . . . . . . . . . . . . . . . . . . . . .1 Pinning information . . . . . . . . . . . . . . . . . . . . . . .2 Ordering information . . . . . . . . . . . . . . . . . . . . . .2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .3 Thermal characteristics . . . . . . . . . . . . . . . . . . .4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . .9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . .10 Legal information. . . . . . . . . . . . . . . . . . . . . . . . 11 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Contact information. . . . . . . . . . . . . . . . . . . . . .12 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 18 January 2012 Document identifier: BUK6C2R1-55C