BUK9615-100A

Philips Semiconductors Product specification TrenchMOS transistor Logic level FET GENERAL DESCRIPTION N-channel enhancement mode logic level field-effect power transistor in a plastic envelope available in TO220AB and SOT404 . Using ’trench’ technology which features very low on-state resistance. It is intended for use in automotive and general purpose switching applications. BUK9515-100A BUK9615-100A QUICK REFERENCE DATA SYMBOL VDS ID Ptot Tj RDS(ON) PARAMETER Drain-source voltage Drain current (DC) Total power dissipation Junction temperature Drain-source on-state resistance VGS = 5 V VGS = 10 V MAX. 100 75 230 175 15 14.4 UNIT V A W ˚C mΩ mΩ PINNING TO220AB & SOT404 PIN 1 2 3 DESCRIPTION gate drain 2 PIN CONFIGURATION mb tab SYMBOL d g 3 SOT404 1 23 source 1 tab/mb drain TO220AB s LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL VDS VDGR ±VGS ±VGSM ID ID IDM Ptot Tstg, Tj PARAMETER Drain-source voltage Drain-gate voltage Gate-source voltage Non-repetitive gate-source voltage Drain current (DC) Drain current (DC) Drain current (pulse peak value) Total power dissipation Storage & operating temperature CONDITIONS RGS = 20 kΩ tp≤50µS Tmb = 25 ˚C Tmb = 100 ˚C Tmb = 25 ˚C Tmb = 25 ˚C MIN. - 55 MAX. 100 100 10 15 75 53 313 230 175 UNIT V V V V A A A W ˚C THERMAL RESISTANCES SYMBOL Rth j-mb Rth j-a Rth j-a PARAMETER Thermal resistance junction to mounting base Thermal resistance junction to ambient(TO220AB) Thermal resistance junction to ambient(SOT404) CONDITIONS in free air Minimum footprint, FR4 board TYP. 60 50 MAX. 0.65 UNIT K/W K/W K/W November 1999 1 Rev 1.000 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET STATIC CHARACTERISTICS Tj= 25˚C unless otherwise specified SYMBOL V(BR)DSS VGS(TO) IDSS IGSS RDS(ON) PARAMETER Drain-source breakdown voltage Gate threshold voltage Zero gate voltage drain current Gate source leakage current Drain-source on-state resistance CONDITIONS VGS = 0 V; ID = 0.25 mA; Tj = -55˚C VDS = VGS; ID = 1 mA Tj = 175˚C Tj = -55˚C VDS = 100 V; VGS = 0 V; VGS = ±10 V; VDS = 0 V VGS = 5 V; ID = 25 A VGS = 10 V; ID = 25 A VGS = 4.5 V; ID = 25 A Tj = 175˚C Tj = 175˚C MIN. 100 89 1 0.5 - BUK9515-100A BUK9615-100A TYP. 1.5 0.05 2 12 11.5 - MAX. 2.0 2.3 10 500 100 15 40.5 14.4 16 UNIT V V V V V µA µA nA mΩ mΩ mΩ mΩ DYNAMIC CHARACTERISTICS Tmb = 25˚C unless otherwise specified SYMBOL Ciss Coss Crss td on tr td off tf Ld Ld Ld Ls PARAMETER Input capacitance Output capacitance Feedback capacitance Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal drain inductance Internal drain inductance Internal source inductance VDD = 30 V; Rload =1.2Ω; VGS = 5 V; RG = 10 Ω CONDITIONS VGS = 0 V; VDS = 25 V; f = 1 MHz MIN. TYP. 6500 550 325 45 130 400 130 4.5 3.5 2.5 7.5 MAX. 8600 660 400 65 195 560 190 UNIT pF pF pF ns ns ns ns nH nH nH nH Measured from drain lead 6 mm from package to centre of die Measured from contact screw on tab to centre of die(TO220AB) Measured from upper edge of drain tab to centre of die(SOT404) Measured from source lead to source bond pad REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25˚C unless otherwise specified SYMBOL IDR IDRM VSD trr Qrr PARAMETER Continuous reverse drain current Pulsed reverse drain current Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS MIN. IF = 25 A; VGS = 0 V IF = 75 A; VGS = 0 V IF = 75 A; -dIF/dt = 100 A/µs; VGS = -10 V; VR = 30 V TYP. 0.85 1.1 60 0.24 MAX. 75 313 1.2 UNIT A A V V ns µC November 1999 2 Rev 1.000 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET AVALANCHE LIMITING VALUE SYMBOL WDSS PARAMETER Drain-source non-repetitive unclamped inductive turn-off energy CONDITIONS ID = 35 A; VDD ≤ 25 V; VGS = 5 V; RGS = 50 Ω; Tmb = 25 ˚C MIN. - BUK9515-100A BUK9615-100A TYP. - MAX. 120 UNIT mJ 120 110 100 90 80 70 60 50 40 30 20 10 0 PD% Normalised Power Derating 1000 ID/A RDS(ON) = VDS/ID 100 tp = 1uS 100uS 1mS 10 DC 10mS 100mS 0 20 40 60 80 100 Tmb / C 120 140 160 180 1 1 10 VDS/V 100 Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Tmb) Fig.3. Safe operating area. Tmb = 25 ˚C ID & IDM = f(VDS); IDM single pulse; parameter tp Zth / (K/W) D= 0.5 0.2 0.1 0.1 0.05 0.02 0.01 0 T P D tp D= tp T t 120 110 100 90 80 70 60 50 40 30 20 10 0 ID% Normalised Current Derating 1 0 20 40 60 80 100 Tmb / C 120 140 160 180 0.001 0.00001 0.001 t/S 0.1 10 Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T November 1999 3 Rev 1.000 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET BUK9515-100A BUK9615-100A 250 ID/A 200 VGS/V = 10.0 5.0 100 4.0 3.8 3.6 3.4 ID/A 80 150 3.2 100 3.0 2.8 50 2.6 2.4 0 60 40 Tj/C = 175 25 20 0 2 4 VDS/V 6 8 10 0 0 0.5 1 1.5 VGS/V 2 2.5 3 3.5 Fig.5. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS); parameter VGS RDS(ON)/mOhm Fig.8. Typical transfer characteristics. ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj 150 gfs/S 20 19 18 17 100 VGS/V = 16 15 14 13 12 11 0 3.0 3.2 3.4 3.6 4.0 5.0 20 40 60 80 100 50 0 ID/A 0 20 40 ID/A 60 80 100 Fig.6. Typical on-state resistance, Tj = 25 ˚C. RDS(ON) = f(ID); parameter VGS RDS(ON)/mOhm Fig.9. Typical transconductance, Tj = 25 ˚C. gfs = f(ID); conditions: VDS = 25 V Rds(on) normalised to 25degC 15 14.5 14 13.5 3 a 2.5 2 13 12.5 12 11.5 11 10.5 0.5 1 1.5 3 4 5 6 VGS/V 7 8 9 10 -100 -50 0 50 100 Tmb / degC 150 200 Fig.7. Typical on-state resistance, Tj = 25 ˚C. RDS(ON) = f(VGS); conditions: ID = 25 A; Fig.10. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 25 A; VGS = 5 V November 1999 4 Rev 1.000 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET BUK9515-100A BUK9615-100A 2.5 VGS(TO) / V max. 6 VGS/V 5 2 typ. 1.5 3 4 VDS = 14V 80V min. 1 2 0.5 1 0 -100 -50 0 50 Tj / C 100 150 200 0 0 10 20 30 40 50 60 70 QG/nC 80 90 100 110 Fig.11. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS Sub-Threshold Conduction Fig.14. Typical turn-on gate-charge characteristics. VGS = f(QG); conditions: ID = 25 A; parameter VDS 100 ID/A 80 1E-01 1E-02 2% typ 98% 60 Tj/C = 40 175 25 1E-03 1E-04 20 1E-05 0 1E-05 0 0.1 0.2 0.3 0.4 0.5 0 0.5 1 1.5 2 2.5 3 0.6 0.7 VSDS/V 0.8 0.9 1 1.1 Fig.12. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS 20 Fig.15. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj WDSS% 120 110 100 15 90 80 70 Thousands 10 60 50 Ciss 40 30 20 10 0 20 40 60 80 100 120 Tmb / C 140 160 180 5 0 0.01 0.1 1 VDS/V 10 100 Coss Crss Fig.13. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz Fig.16. Normalised avalanche energy rating. WDSS% = f(Tmb); conditions: ID = 75 A November 1999 5 Rev 1.000 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET BUK9515-100A BUK9615-100A + L VDS VGS 0 RGS T.U.T. R 01 shunt VDD + RD VDS VDD -ID/100 VGS 0 RG T.U.T. - Fig.17. Avalanche energy test circuit. 2 WDSS = 0.5 ⋅ LID ⋅ BVDSS /(BVDSS − VDD ) Fig.19. Switching test circuit. 100 IAV 25ºC 10 Tj prior to avanche 150ºC 1 0.001 0.01 0.1 Avalanche Time, tAV (ms) 1 10 Fig.18. Maximum permissible repetitive avalanche current(IAV) versus avalanche time(tAV) for unclamped inductive loads. November 1999 6 Rev 1.000 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET MECHANICAL DATA Dimensions in mm Net Mass: 2 g BUK9515-100A BUK9615-100A 4,5 max 10,3 max 1,3 3,7 2,8 5,9 min 15,8 max 3,0 max not tinned 3,0 13,5 min 1,3 max 1 2 3 (2x) 2,54 2,54 0,9 max (3x) 0,6 2,4 Fig.20. SOT78 (TO220AB); pin 2 connected to mounting base. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Refer to mounting instructions for SOT78 (TO220) envelopes. 3. Epoxy meets UL94 V0 at 1/8". November 1999 7 Rev 1.000 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET MECHANICAL DATA Plastic single-ended surface mounted package (Philips version of D2-PAK); 3 leads (one lead cropped) BUK9515-100A BUK9615-100A SOT404 A E A1 mounting base D1 D HD 2 Lp 1 3 b c Q e e 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 4.50 4.10 A1 1.40 1.27 b 0.85 0.60 c 0.64 0.46 D max. 11 D1 1.60 1.20 E 10.30 9.70 e 2.54 Lp 2.90 2.10 HD 15.40 14.80 Q 2.60 2.20 OUTLINE VERSION SOT404 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 98-12-14 99-06-25 Fig.21. SOT404 surface mounting package. Centre pin connected to mounting base. Notes 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18. 3. Epoxy meets UL94 V0 at 1/8". November 1999 8 Rev 1.000 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET MOUNTING INSTRUCTIONS Dimensions in mm 11.5 BUK9515-100A BUK9615-100A 9.0 17.5 2.0 3.8 5.08 Fig.22. SOT404 : soldering pattern for surface mounting. DEFINITIONS Data sheet status Objective specification Product specification Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification.  Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. This data sheet contains target or goal specifications for product development. This data sheet contains final product specifications. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. November 1999 9 Rev 1.000