BUK9621-30

Philips Semiconductors Product specification TrenchMOS™ transistor Logic level FET GENERAL DESCRIPTION N-channel enhancement mode logic level field-effect power transistor in a plastic envelope suitable for surface mounting using ’trench’ technology. The device features very low on-state resistance and has integral zener diodes giving ESD protection up to 2kV. It is intended for use in automotive and general purpose switching applications. BUK9621-30 QUICK REFERENCE DATA SYMBOL VDS ID Ptot Tj RDS(ON) PARAMETER Drain-source voltage Drain current (DC) Total power dissipation Junction temperature Drain-source on-state resistance VGS = 5 V MAX. 30 50 94 175 21 UNIT V A W ˚C mΩ PINNING - SOT404 (D2PAK) PIN 1 2 3 mb gate drain source drain DESCRIPTION PIN CONFIGURATION mb SYMBOL d g 2 1 3 s LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL VDS VDGR ±VGS ID ID IDM Ptot Tstg, Tj PARAMETER Drain-source voltage Drain-gate voltage Gate-source voltage Drain current (DC) Drain current (DC) Drain current (pulse peak value) Total power dissipation Storage & operating temperature CONDITIONS RGS = 20 kΩ Tmb = 25 ˚C Tmb = 100 ˚C Tmb = 25 ˚C Tmb = 25 ˚C MIN. - 55 MAX. 30 30 10 50 29 200 94 175 UNIT V V V A A A W ˚C THERMAL RESISTANCES SYMBOL Rth j-mb Rth j-a PARAMETER Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS pcb mounted, minimum footprint TYP. 50 MAX. 1.6 UNIT K/W K/W ESD LIMITING VALUE SYMBOL VC PARAMETER Electrostatic discharge capacitor voltage, all pins CONDITIONS Human body model (100 pF, 1.5 kΩ) MIN. MAX. 2 UNIT kV July 1997 1 Rev 1.000 Philips Semiconductors Product specification TrenchMOS™ transistor Logic level FET STATIC CHARACTERISTICS Tj= 25˚C unless otherwise specified SYMBOL V(BR)DSS VGS(TO) IDSS IGSS ±V(BR)GSS RDS(ON) PARAMETER Drain-source breakdown voltage Gate threshold voltage Zero gate voltage drain current Gate source leakage current Gate-source breakdown voltage Drain-source on-state resistance CONDITIONS VGS = 0 V; ID = 0.25 mA; Tj = -55˚C VDS = VGS; ID = 1 mA Tj = 175˚C Tj = -55˚C VDS = 30 V; VGS = 0 V; VGS = ±5 V; VDS = 0 V IG = ±1 mA; VGS = 5 V; ID = 25 A Tj = 175˚C Tj = 175˚C Tj = 175˚C MIN. 30 27 1 0.5 10 TYP. 1.5 0.05 0.02 19 - BUK9621-30 MAX. 2 2.3 10 500 1 10 21 39 UNIT V V V V V µA µA µA µA V mΩ mΩ DYNAMIC CHARACTERISTICS Tj = 25˚C unless otherwise specified SYMBOL gfs Qg(tot) Qgs Qgd Ciss Coss Crss td on tr td off tf Ld Ld Ls PARAMETER Forward transconductance Total gate charge Gate-source charge Gate-drain (Miller) charge Input capacitance Output capacitance Feedback capacitance Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal drain inductance Internal source inductance CONDITIONS VDS = 25 V; ID = 25 A ID = 25 A; VDD = 30 V; VGS = 5 V MIN. 8 TYP. 30 21 6 14 1325 336 171 20 106 72 77 3.5 4.5 7.5 MAX. UNIT S nC nC nC pF pF pF ns ns ns ns nH nH nH VGS = 0 V; VDS = 25 V; f = 1 MHz VDD = 30 V; ID = 25 A; VGS = 5 V; RG = 10 Ω Resistive load Measured from tab to centre of die Measured from drain lead solder point to centre of die Measured from source lead solder point to source bond pad REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25˚C unless otherwise specified SYMBOL IDR IDRM VSD trr Qrr PARAMETER Continuous reverse drain current Pulsed reverse drain current Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS MIN. IF = 25 A; VGS = 0 V IF = 25 A; -dIF/dt = 100 A/µs; VGS = -10 V; VR = 25 V TYP. 0.95 128 0.5 MAX. 50 200 1.2 UNIT A A V ns µC July 1997 2 Rev 1.000 Philips Semiconductors Product specification TrenchMOS™ transistor Logic level FET AVALANCHE LIMITING VALUE SYMBOL WDSS PARAMETER Drain-source non-repetitive unclamped inductive turn-off energy CONDITIONS ID = 25 A; VDD ≤ 25 V; VGS = 10 V; RGS = 50 Ω; Tmb = 25 ˚C MIN. TYP. - BUK9621-30 MAX. 70 UNIT mJ 120 110 100 90 80 70 60 50 40 30 20 10 0 PD% Normalised Power Derating 1000 ID, Drain current (Amps) PHP50N03T 100 RD S(O = N) VD S/I D tp = 10 us 100 us 1 ms 10 DC 10 ms Tmb = 25 C 0 20 40 60 80 100 Tmb / C 120 140 160 180 1 1 10 VDS, Drain-source voltage (Volts) 100 Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Tmb) Normalised Current Derating Fig.3. Safe operating area. Tmb = 25 ˚C ID & IDM = f(VDS); IDM single pulse; parameter tp Transient thermal impedance, Zth j-mb (K/W) PHP50N03T 120 110 100 90 80 70 60 50 40 30 20 10 0 ID% 10 D= 1 0.5 0.2 0.1 0.1 0.05 0.02 0 0.01 P D tp D= tp T t T 0 20 40 60 80 100 Tmb / C 120 140 160 180 1us 10us 100us 1ms 10ms pulse width, tp (s) 0.1s 1s 10s Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T July 1997 3 Rev 1.000 Philips Semiconductors Product specification TrenchMOS™ transistor Logic level FET BUK9621-30 50 ID, Drain current (Amps) 5V 15 V PHP50N03LT Tj = 25 C 3.5 V 40 Transconductance, gfs (S) VDS = 30 V PHP50N03LT 40 30 Tj = 25 C 30 20 20 3V 175 C 10 10 VGS = 2.5 V 0 0 5 10 15 20 25 VDS, Drain-Source voltage (Volts) 30 0 0 10 20 30 Drain current, ID (A) 40 50 Fig.5. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS); parameter VGS RDS(on), Drain-Source on resistance (Ohms) VGS = 2.5 V 0.05 3V PHP50N03LT Fig.8. Typical transconductance, Tj = 25 ˚C. gfs = f(ID) Rds(on) normlised to 25degC BUK959-60 0.06 2.5 Tj = 25 C 2 0.04 0.03 0.02 0.01 0 1.5 3.5 V 5V 10 V 15 V 1 0 10 20 30 ID, Drain current (Amps) 40 50 0.5 -100 -50 0 50 Tmb / degC 100 150 200 Fig.6. Typical on-state resistance, Tj = 25 ˚C. RDS(ON) = f(ID); parameter VGS Fig.9. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 25 A; VGS = 5 V VGS(TO) / V max. BUK959-60 50 Drain current, ID (A) VDS = 30 V PHP50N03LT 2.5 40 2 typ. 30 1.5 min. 20 1 10 175 C Tj = 25 C 0.5 0 0 1 2 3 Gate-source voltage, VGS (V) 4 5 0 -100 -50 0 50 Tj / C 100 150 200 Fig.7. Typical transfer characteristics. ID = f(VGS); parameter Tj Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS July 1997 4 Rev 1.000 Philips Semiconductors Product specification TrenchMOS™ transistor Logic level FET BUK9621-30 1E-01 Sub-Threshold Conduction 50 Source-Drain diode current, IF(A) VGS = 0 V PHP50N03LT 1E-02 2% typ 98% 40 1E-03 30 175 C Tj = 25 C 1E-04 20 1E-05 10 0 1E-05 0 0.2 0 0.5 1 1.5 2 2.5 3 0.4 0.6 0.8 1 Source-Drain voltage, VSDS (V) 1.2 1.4 Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS Capacitances, Ciss, Coss, Crss (pF) PHP50N03LT Fig.14. Typical reverse diode current. IF = f(VSDS); parameter Tj WDSS% 10000 120 110 100 90 80 70 60 50 40 30 20 10 0 Ciss 1000 Coss Crss 100 1 10 Drain-source voltage, VDS (V) 100 20 40 60 80 100 120 Tmb / C 140 160 180 Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz Fig.15. Normalised avalanche energy rating. WDSS% = f(Tmb) 15 VGS, Gate-Source voltage (Volts) VDD = 30 V ID = 25 A Tj = 25 C PHP50N03LT + L VDS VGS VDD 10 -ID/100 T.U.T. R 01 shunt 5 0 RGS 0 0 10 20 Qg, Gate charge (nC) 30 40 Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG); parameter VDS Fig.16. Avalanche energy test circuit. 2 WDSS = 0.5 ⋅ LID ⋅ BVDSS /(BVDSS − VDD ) July 1997 5 Rev 1.000 Philips Semiconductors Product specification TrenchMOS™ transistor Logic level FET MECHANICAL DATA Plastic single-ended package (Philips version of D2-PAK); 2 leads SOT404 BUK9621-30 A E A1 D1 D HD Lp b e e c Q 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 4.5 4.1 A1 1.40 1.27 b 0.85 0.60 c 0.64 0.46 D 9.65 8.65 D1 1.6 1.2 E 10.3 9.7 e 2.54 Lp 2.9 2.1 HD 15.4 14.8 Q 2.60 2.20 OUTLINE VERSION SOT404 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 97-06-16 Fig.17. SOT404 surface mounting package. Centre pin connected to mounting base. Notes 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18. 3. Epoxy meets UL94 V0 at 1/8". July 1997 6 Rev 1.000 Philips Semiconductors Product specification TrenchMOS™ transistor Logic level FET MOUNTING INSTRUCTIONS Dimensions in mm 11.5 BUK9621-30 9.0 17.5 2.0 3.8 5.08 Fig.18. SOT404 : soldering pattern for surface mounting. DEFINITIONS Data sheet status Objective specification Product specification Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. © Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. This data sheet contains target or goal specifications for product development. This data sheet contains final product specifications. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. July 1997 7 Rev 1.000