CBTL04DP211BS

CBTL04DP211 DisplayPort 2 : 1 multiplexer Rev. 1 — 30 March 2011 Product data sheet 1. General description CBTL04DP211 is an (Embedded) DisplayPort multiplexer for DisplayPort v1.1a switching and multiplexing applications on PC platforms. It is capable of 1 : 2 switching or 2 : 1 multiplexing of 2-lane DisplayPort Main Link signals, using high-bandwidth pass-gate technology. Also, it can switch/multiplex Hot Plug Detect (HPD) signal and AUX signals, for a total of four channels on the display side. To facilitate DisplayPort switching/multiplexing scheme on PC platforms suitably, CBTL04DP211 provides two separate selection pins (GPU_SEL, AUX_SEL). The selection pin GPU_SEL performs switching from one Main Link to another Main Link. HPD signals will also be switched using the same selection pin. A separate select pin (AUX_SEL) provides additional selection between two AUX channels such that the AUX channel selection is independent of the Main Link and HPD signal selection. A typical application of CBTL04DP211 is on motherboards where one of two GPU/CPU display sources needs to be selected to connect to a DisplayPort sink device or connector. A controller chip selects which path to use by setting a select signal HIGH or LOW. Due to the non-directional nature of the signal paths (which use high-bandwidth pass-gate technology), the CBTL04DP211 can also be used in the reverse topology, e.g., to connect one DisplayPort source device to one of two DisplayPort sink devices or connectors. 2. Features and benefits     Supports DisplayPort v1.1a: 1.62 Gbit/s, 2.7 Gbit/s Supports Embedded DisplayPort v1.2: 1.62 Gbit/s, 2.7 Gbit/s Supports 1-lane, 2-lane Main Link operation 1 : 2 switching or 2 : 1 multiplexing of DisplayPort Main Link signals  2 high-speed differential channels with 2 : 1 multiplexing/switching for DisplayPort Main Link signals  1 channel with 2 : 1 multiplexing/switching for AUX signals  1 channel with 2 : 1 multiplexing/switching for single-ended HPD signals High-bandwidth analog pass-gate technology Very low intra-pair differential skew (5 ps typical) Very low inter-pair skew (< 180 ps) Switch/multiplexer position select CMOS input Single 3.3 V power supply Very low operation current of 0.2 mA typical ESD 8 kV HBM, 1 kV CDM ESD 2 kV HBM, 500 V CDM for control pins Available in 3 mm  6 mm, 0.4 mm pitch HVQFN32 package          NXP Semiconductors CBTL04DP211 DisplayPort 2 : 1 multiplexer 3. Applications     Motherboard applications requiring (embedded) DisplayPort switching/multiplexing Docking stations Notebook computers Chip sets requiring flexible allocation of DisplayPort I/O pins to board connectors 4. Ordering information Table 1. Ordering information Package Name CBTL04DP211BS HVQFN32 Description plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 3  6  0.85 mm[1] Version SOT1185-1 Type number [1] Total height after printed-circuit board mounting = 1 mm (maximum). 5. Marking Table 2. Line A B C Package marking Marking 04DP211[1] xxxxxxx ZPGyyww Description basic type number diffusion lot number manufacturing code: Z = diffusion site P = assembly site G = lead-free yy = year code ww = week code [1] Industrial temperature range. CBTL04DP211 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 1 — 30 March 2011 2 of 17 NXP Semiconductors CBTL04DP211 DisplayPort 2 : 1 multiplexer 6. Functional diagram IN1_0+ IN1_0IN2_0+ IN2_0- 2:1 MUX OUT_0+ OUT_0- IN1_1+ IN1_1IN2_1+ IN2_1- 2:1 MUX OUT_1+ OUT_1- HPD_1 2:1 MUX HPD_2 HPD_IN AUX1+ AUX1AUX2+ AUX2- 2:1 MUX AUX+ AUX- AUX_SEL GPU_SEL 002aag018 Fig 1. Functional diagram CBTL04DP211 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 1 — 30 March 2011 3 of 17 NXP Semiconductors CBTL04DP211 DisplayPort 2 : 1 multiplexer 7. Pinning information 7.1 Pinning 32 AUX_SEL 31 IN1_0+ 30 IN1_0- OUT_0+ OUT_0VDD OUT_1+ OUT_1AUX+ AUXHPD_IN VDD 1 2 3 4 5 6 7 8 9 28 GND 27 IN1_1+ 26 IN1_125 IN2_0+ 24 IN2_023 IN2_1+ 21 GND 20 VDD 19 AUX1+ 18 AUX117 HPD_1 VDD 16 002aag019 CBTL04DP211BS 22 IN2_1- GPU_SEL 10 n.c. 11 VDD 12 HPD_2 13 AUX2- 14 AUX2+ 15 Transparent top view Fig 2. Pin configuration for HVQFN32 7.2 Pin description Table 3. Symbol GPU_SEL Pin description Pin 10 Type Description 3.3 V CMOS Selection for Main Link and Hot Plug Detect single-ended input signals between two multiplexer/switch paths. When HIGH, path 2 is connected to its corresponding I/O. When LOW, path 1 is connected to its corresponding I/O. 3.3 V CMOS Selects between AUX paths. When HIGH, AUX2 single-ended input (path 2) input is connected to AUX output. When LOW, AUX1 (path 1) input is connected to AUX output. differential I/O differential I/O differential I/O differential I/O differential I/O differential I/O differential I/O differential I/O All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. AUX_SEL 32 IN1_0+ IN1_0 IN1_1+ IN1_1 IN2_0+ IN2_0 IN2_1+ IN2_1 CBTL04DP211 31 30 27 26 25 24 23 22 Two bidirectional high-speed differential pairs for DisplayPort Main Link signals, path 1. Two bidirectional high-speed differential pairs for DisplayPort Main Link signals, path 2. Product data sheet Rev. 1 — 30 March 2011 29 VDD 4 of 17 NXP Semiconductors CBTL04DP211 DisplayPort 2 : 1 multiplexer Pin description …continued Pin 1 2 4 5 19 18 15 14 6 7 17 13 8 Type differential I/O differential I/O differential I/O differential I/O differential I/O differential I/O differential I/O differential I/O differential I/O differential I/O single-ended I/O single-ended I/O single-ended I/O Single-ended channel for the HPD signal, path 1. Single-ended channel for the HPD signal, path 2. Single-ended channel for the HPD signal. 3.3 V power supply. Ground. Not connected. This pin is not connected to any signal internally. High-speed differential pair for AUX signals, path 1. High-speed differential pair for AUX signals, path 2. High-speed differential pair for AUX signals. Description Two bidirectional high-speed differential pairs for DisplayPort Main Link signals. Table 3. Symbol OUT_0+ OUT_0 OUT_1+ OUT_1 AUX1+ AUX1 AUX2+ AUX2 AUX+ AUX HPD_1 HPD_2 HPD_IN VDD GND[1] n.c. 3, 9, 12, 16, power supply 20, 29 21, 28, center pad 11 ground - [1] HVQFN32 package die supply ground is connected to both GND pins and exposed center pad. GND pins and the exposed center pad must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the printed-circuit board in the thermal pad region. CBTL04DP211 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 1 — 30 March 2011 5 of 17 NXP Semiconductors CBTL04DP211 DisplayPort 2 : 1 multiplexer 8. Functional description Refer to Figure 1 “Functional diagram”. The CBTL04DP211 uses a 3.3 V power supply. All Main Link signal paths are implemented using high-bandwidth pass-gate technology and are non-directional. No clock or reset signal is needed for the multiplexer to function. The switch position for the main link differential channels and Hot Plug Detect signals is selected using the select signal GPU_SEL. Additionally, the signal AUX_SEL selects between two AUX positions. The detailed operation is described in Section 8.1 “Multiplexer/switch select functions”. 8.1 Multiplexer/switch select functions The internal multiplexer switch position is controlled by two logic inputs GPU_SEL and AUX_SEL as described below. Table 4. GPU_SEL 0 1 Table 5. GPU_SEL 0 1 Table 6. AUX_SEL 0 1 Multiplexer/switch select control for IN and OUT channels IN1_n active; connected to OUT_n high-impedance IN2_n high-impedance active; connected to OUT_n Multiplexer/switch select control for HPD channel HPD_1 active; connected to HPD_IN high-impedance HPD_2 high-impedance active; connected to HPD_IN Multiplexer/switch select control for AUX channels AUX1 active; connected to AUX high-impedance AUX2 high-impedance active; connected to AUX CBTL04DP211 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 1 — 30 March 2011 6 of 17 NXP Semiconductors CBTL04DP211 DisplayPort 2 : 1 multiplexer 9. Limiting values Table 7. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD Tcase VESD Parameter supply voltage case temperature electrostatic discharge HBM voltage HBM; CMOS inputs CDM CDM; CMOS inputs [1] [2] [1] [1] [2] [2] Conditions Min 0.3 40 - Max +5 +85 8000 2000 1000 500 Unit V C V V V V Human Body Model: ANSI/EOS/ESD-S5.1-1994, standard for ESD sensitivity testing, Human Body Model Component level; Electrostatic Discharge Association, Rome, NY, USA. Charged Device Model: ANSI/EOS/ESD-S5.3-1-1999, standard for ESD sensitivity testing, Charged Device Model - Component level; Electrostatic Discharge Association, Rome, NY, USA. 10. Recommended operating conditions Table 8. Symbol VDD VI Recommended operating conditions Parameter supply voltage input voltage CMOS inputs Main Link HPD inputs AUX Tamb [1] [2] [1] [2] Conditions Min 3.0 0.3 0.3 0.3 0.3 40 Typ 3.3 - Max 3.6 VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 +85 Unit V V V V V C ambient temperature operating in free air HPD input is tolerant to 5 V input, provided a 1 k series resistor between the voltage source and the pin is placed in series. See Section 12.1 “Special considerations”. AUX input is tolerant to 5 V input, provided a 2.2 k series resistor between the voltage source and the pin is placed in series. See Section 12.1 “Special considerations”. CBTL04DP211 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 1 — 30 March 2011 7 of 17 NXP Semiconductors CBTL04DP211 DisplayPort 2 : 1 multiplexer 11. Characteristics 11.1 General characteristics Table 9. Symbol IDD Pcons tstartup trcfg General characteristics Parameter supply current power consumption start-up time reconfiguration time Conditions VDD = 3.3 V VDD = 3.3 V supply voltage valid to channel specified operating characteristics GPU_SEL or AUX_SEL state change to channel specified operating characteristics Min Typ 200 Max 500 4 10 1 Unit A mW s s 11.2 DisplayPort Main Link channel characteristics Table 10. Symbol VI VIC VID DDIL DisplayPort Main Link channel characteristics Parameter input voltage common-mode input voltage differential input voltage differential insertion loss peak-to-peak channel is on; f = 100 MHz channel is on; f = 1.5 GHz channel is off; 0 Hz  f  1.5 GHz DDRL differential return loss channel is on; 0 Hz  f  1.5 GHz adjacent channels are on; 0 Hz  f  1.5 GHz 3.0 dB intercept from INx_n+/INx_n port to OUT_n+/OUT_n port or vice versa intra-pair inter-pair DDNEXT differential near-end crosstalk B tPD tsk(dif) tsk bandwidth propagation delay differential skew time skew time Conditions Min 0.3 0 Typ 1.6 2.7 35 10 40 2.0 100 5 Max +3.3 2.0 +1.2 180 Unit V V V dB dB dB dB dB GHz ps ps ps CBTL04DP211 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 1 — 30 March 2011 8 of 17 NXP Semiconductors CBTL04DP211 DisplayPort 2 : 1 multiplexer 11.3 AUX ports Table 11. Symbol VI VO Vbias Ron VID tPD AUX port characteristics Parameter input voltage output voltage bias voltage ON-state resistance differential input voltage propagation delay 50  load AUX Vbias  2.0 V 2.0 V < Vbias < VDD peak-to-peak from AUXn port to AUX port or vice versa [1] Conditions Min 0.3 0 - Typ 15 30 100 Max VDD + 0.3 VDD + 0.3 VDD +1.4 - Unit V V V   V ps [1] Time from AUX input changing state to AUX output changing state. Includes AUX rise/fall time. 11.4 HPD_IN input, HPD_x outputs Table 12. Symbol VI VO tPD [1] HPD input and output characteristics Parameter input voltage output voltage propagation delay from HPD_IN to HPD_x or vice versa [1] Conditions Min 0.3 - Typ 100 Max VDD + 0.3 VDD + 0.3 - Unit V V ps Time from HPD_IN changing state to HPD_x changing state. Includes HPD rise/fall time. 11.5 GPU_SEL and AUX_SEL inputs Table 13. Symbol VIH VIL ILI GPU_SEL and AUX_SEL input characteristics Parameter HIGH-level input voltage LOW-level input voltage input leakage current VDD = 3.6 V; 0.3 V  VI  3.9 V Conditions Min 2.0 Typ Max 0.8 10 Unit V V A CBTL04DP211 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 1 — 30 March 2011 9 of 17 NXP Semiconductors CBTL04DP211 DisplayPort 2 : 1 multiplexer 12. Application information 12.1 Special considerations Certain cable or dongle misplug scenarios make it possible for a 5 V input condition to occur on pins AUX+ and AUX, as well as HPD_IN. When AUX+ and AUX are connected through a minimum of 2.2 k each, the CBTL04DP211 will sink current but will not be damaged. Similarly, HPD_IN may be connected to 5 V via at least a 1 k resistor. (Correct functional operation to specification is not expected in these scenarios.) The latter also prevents the HPD_OUT output from loading down the system HPD signal when power to the CBTL04DP211 is off. GPU A HPDA D1A+ AUXAAUXA+ D0A+ D1AD0A- CBTL04DP211 2:1 MUX OUT_0+ OUT_0- 2:1 MUX OUT_1+ OUT_1CONNECTOR 2:1 MUX HPD_IN GND 100 kΩ 2:1 MUX AUX+ AUX100 kΩ AUXB+ VDD D1B+ D0B+ D1BD0BAUX_SEL GPU_SEL AUXB- HPDB GPU B 002aag022 Fig 3. Application diagram CBTL04DP211 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 1 — 30 March 2011 10 of 17 NXP Semiconductors CBTL04DP211 DisplayPort 2 : 1 multiplexer 13. Package outline HVQFN32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; 3 x 6 x 0.85 mm SOT1185-1 D B A terminal 1 index area E A A1 c detail X e1 e b 12 L 11 17 e 16 v w CAB C C y1 C y Eh e2 1 terminal 1 index area 27 32 Dh 28 X 0 Dimensions Unit mm A(1) A1 b c 0.2 D(1) 3.1 3.0 2.9 Dh 1.9 1.8 1.7 E(1) 6.1 6.0 5.9 Eh 4.9 4.8 4.7 e 0.4 2.5 scale e1 1.6 e2 4 L 0.4 0.3 0.2 5 mm v w y y1 0.1 max 1.00 0.05 0.25 nom 0.85 0.02 0.20 min 0.80 0.00 0.15 0.07 0.05 0.08 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. Outline version SOT1185-1 References IEC --JEDEC --JEITA --European projection sot1185-1_po Issue date 10-07-26 10-08-09 Fig 4. CBTL04DP211 Package outline SOT1185-1 (HVQFN32) All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 1 — 30 March 2011 11 of 17 NXP Semiconductors CBTL04DP211 DisplayPort 2 : 1 multiplexer 14. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 14.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 14.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 14.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities CBTL04DP211 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 1 — 30 March 2011 12 of 17 NXP Semiconductors CBTL04DP211 DisplayPort 2 : 1 multiplexer 14.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 5) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 14 and 15 Table 14. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5  2.5 Table 15. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245  350 220 220 Package thickness (mm) Package thickness (mm) Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 5. CBTL04DP211 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 1 — 30 March 2011 13 of 17 NXP Semiconductors CBTL04DP211 DisplayPort 2 : 1 multiplexer temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 5. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 15. Abbreviations Table 16. Acronym AUX CDM CMOS CPU ESD GPU HBM HPD I/O PC Abbreviations Description Auxiliary channel (in DisplayPort definition) Charged-Device Model Complementary Metal-Oxide Semiconductor Central Processing Unit ElectroStatic Discharge Graphics Processor Unit Human Body Model Hot Plug Detect Input/Output Personal Computer 16. Revision history Table 17. Revision history Release date 20110330 Data sheet status Product data sheet Change notice Supersedes Document ID CBTL04DP211 v.1 CBTL04DP211 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 1 — 30 March 2011 14 of 17 NXP Semiconductors CBTL04DP211 DisplayPort 2 : 1 multiplexer 17. Legal information 17.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 17.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. 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NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. 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This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or CBTL04DP211 All information provided in this document is subject to legal disclaimers. Product data sheet Rev. 1 — 30 March 2011 15 of 17 NXP Semiconductors CBTL04DP211 DisplayPort 2 : 1 multiplexer NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond 17.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 18. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com CBTL04DP211 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 1 — 30 March 2011 16 of 17 NXP Semiconductors CBTL04DP211 DisplayPort 2 : 1 multiplexer 19. Contents 1 2 3 4 5 6 7 7.1 7.2 8 8.1 9 10 11 11.1 11.2 11.3 11.4 11.5 12 12.1 13 14 14.1 14.2 14.3 14.4 15 16 17 17.1 17.2 17.3 17.4 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 6 Multiplexer/switch select functions . . . . . . . . . . 6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7 Recommended operating conditions. . . . . . . . 7 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 8 General characteristics . . . . . . . . . . . . . . . . . . . 8 DisplayPort Main Link channel characteristics . 8 AUX ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 HPD_IN input, HPD_x outputs . . . . . . . . . . . . . 9 GPU_SEL and AUX_SEL inputs . . . . . . . . . . . 9 Application information. . . . . . . . . . . . . . . . . . 10 Special considerations . . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 Soldering of SMD packages . . . . . . . . . . . . . . 12 Introduction to soldering . . . . . . . . . . . . . . . . . 12 Wave and reflow soldering . . . . . . . . . . . . . . . 12 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 12 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information. . . . . . . . . . . . . . . . . . . . . 16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 30 March 2011 Document identifier: CBTL04DP211