HEF4022BT

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4022B MSI 4-stage divide-by-8 Johnson counter Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification 4-stage divide-by-8 Johnson counter DESCRIPTION The HEF4022B is a 4-stage divide-by-8 Johnson counter with eight spike-free decoded active HIGH outputs (O0 to O7), an active LOW output from the most significant flip-flop (O4-7), active HIGH and active LOW clock inputs (CP0, CP1) and an overriding asynchronous master reset input (MR). The counter is advanced by either a LOW to HIGH transition at CP0 while CP1 is LOW or a HIGH to LOW transition at CP1 while CP0 is HIGH (see also function table). Either CP0 or CP1 may be used as clock input to the HEF4022B MSI counter and the other clock input may be used as a clock enable input. When cascading counters, the O4-7 output, which is LOW while the counter is in states, 4, 5, 6 and 7, can be used to drive the CP0 input of the next counter. A HIGH on MR resets the counter to zero (O0 = O4-7 = HIGH; O1 to O7 = LOW) independent of the clock inputs (CP0, CP1). Automatic code correction of the counter is provided by an internal circuit, following any illegal code the counter returns to a proper counting mode within 11 clock pulses. Fig.1 Functional diagram. HEF4022BP(N): HEF4022BD(F): HEF4022BT(D): 16-lead DIL; plastic (SOT38-1) 16-lead DIL; ceramic (cerdip) (SOT74) 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America Fig.2 Pinning diagram. FAMILY DATA, IDD LIMITS category MSI See Family Specifications PINNING CPO CP1 MR O0 to O7 O4-7 clock input (LOW to HIGH; edge-triggered) clock input (HIGH to LOW; edge-triggered) master reset input decoded outputs carry output (active LOW) January 1995 2 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... January 1995 3 Product specification Fig.3 Logic diagram. Philips Semiconductors 4-stage divide-by-8 Johnson counter HEF4022B MSI Philips Semiconductors Product specification 4-stage divide-by-8 Johnson counter FUNCTION TABLE MR H L L L L L L L X H L CP0 X H L X H CP1 X OPERATION O0 = O4-7 = H; O1 to O7 = L Counter advances Counter advances No change No change No change No change Notes HEF4022B MSI 1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state is immaterial = positive-going transition = negative-going transition AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V Propagation delays CP0, CP1 → On HIGH to LOW 5 10 15 5 LOW to HIGH CP0, CP1 → O4-7 HIGH to LOW 10 15 5 10 15 5 LOW to HIGH MR → O1 to O7 HIGH to LOW MR → O0 LOW to HIGH MR → O4-7 LOW to HIGH Output transition times HIGH to LOW 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 LOW to HIGH 10 15 January 1995 4 tTLH tTHL tPLH tPLH tPHL tPLH tPHL tPLH tPHL 195 75 50 245 95 60 245 90 60 190 75 50 130 55 40 130 55 40 110 45 35 60 30 20 60 30 20 390 145 100 485 195 125 485 185 120 380 145 105 260 105 75 260 105 75 220 90 70 120 60 40 120 60 40 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 168 ns + (0,55 ns/pF) CL 64 ns + (0,23 ns/pF) CL 42 ns + (0,16 ns/pF) CL 218 ns + (0,55 ns/pF) CL 84 ns + (0,23 ns/pF) CL 52 ns + (0,16 ns/pF) CL 218 ns + (0,55 ns/pF) CL 79 ns + (0,23 ns/pF) CL 52 ns + (0,16 ns/pF) CL 163 ns + (0,55 ns/pF) CL 64 ns + (0,23 ns/pF) CL 42 ns + (0,16 ns/pF) CL 103 ns + (0,55 ns/pF) CL 44 ns + (0,23 ns/pF) CL 32 ns + (0,16 ns/pF) CL 103 ns + (0,55 ns/pF) CL 44 ns + (0,23 ns/pF) CL 32 ns + (0,16 ns/pF) CL 83 ns + (0,55 ns/pF) CL 34 ns + (0,23 ns/pF) CL 27 ns + (0,16 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL SYMBOL MIN. TYP. MAX. TYPICAL EXTRAPOLATION FORMULA Philips Semiconductors Product specification 4-stage divide-by-8 Johnson counter AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V Hold times CP0 → CP1 5 10 15 5 CP1 → CP0 Minimum clock pulse width Minimum MR pulse width; HIGH Recovery time for MR Maximum clock pulse frequency 10 15 5 10 15 5 10 15 5 10 15 5 10 15 fmax tRMR tWMRH tWCP thold thold SYMBOL MIN. 140 50 30 170 60 40 75 30 20 70 30 20 30 15 10 3 8 12 TYP. 70 25 15 85 30 20 35 15 10 35 15 10 10 5 5 6 16 24 MAX. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz HEF4022B MSI see also waveforms Figs 4 and 5 VDD V Dynamic power dissipation per package (P) 5 10 15 TYPICAL FORMULA FOR P (µW) 475 fi + ∑ (fo CL) × VDD 2 2400 fi + ∑ (fo CL) × VDD 2 6700 fi + ∑ (fo CL) × VDD 2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = total load capacitance (pF) ∑ (foCL) = sum of outputs VDD = supply voltage (V) January 1995 5 Philips Semiconductors Product specification 4-stage divide-by-8 Johnson counter HEF4022B MSI Fig.4 Waveforms showing hold times for CP0 to CP1 and CP1 to CP0. Hold times are shown as positive values, but may be specified as negative values. Conditions: CP1 = LOW while CP0 is triggered on a LOW to HIGH transition. tWCP and tRMR also apply when CP0 = HIGH and CP1 is triggered on a HIGH to LOW transition. Fig.5 Waveforms showing recovery time for MR; minimum CP0 and MR pulse widths. January 1995 6 Philips Semiconductors Product specification 4-stage divide-by-8 Johnson counter HEF4022B MSI Fig.6 Timing diagram. January 1995 7 Philips Semiconductors Product specification 4-stage divide-by-8 Johnson counter APPLICATION INFORMATION Some of the features of the HEF4022B are: • High speed • Spike-free decoded outputs • Carry output for cascading HEF4022B MSI Figure 7 shows a technique for extending the number of decoded output states for the HEF4022B. Decoded outputs are sequential within each stage and from stage to stage, with no dead time (except propagation delay). Fig.7 Counter expansion. January 1995 8