HEF4531BT

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4531B MSI 13-input parity checker/generator Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification 13-input parity checker/generator DESCRIPTION The HEF4531B is a parity checker/generator with 13 parity inputs (I0 to I12) and a parity output (O). When the number of parity inputs that are HIGH is even, the output is LOW. When the number of parity inputs that are HIGH is odd, the output is HIGH. For words of 12 bits or less, the output can be used to generate either odd or even parity by appropriate termination of the unused parity input(s). For words of 14 or more bits, the devices can be cascaded by connecting the output of one device to any parity input of another device. When cascading devices, it is recommended that the output of one device be connected to the I12 input of the other device since there is less delay to the output from the I12 input than from any other input (I0 to I11). HEF4531B MSI Fig.1 Functional diagram. HEF4531BP(N): HEF4531BD(F): HEF4531BT(D): 16-lead DIL; plastic (SOT38-1) 16-lead DIL; ceramic (cerdip) (SOT74) 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America FAMILY DATA, IDD LIMITS category MSI Fig.2 Pinning diagram. See Family Specifications January 1995 2 Philips Semiconductors Product specification 13-input parity checker/generator HEF4531B MSI Fig.3 Logic diagram. FUNCTION TABLE INPUTS I0 L I1 L I2 L I3 L I4 L I5 L I6 L I7 L I8 L I9 L I10 L I11 L I12 L OUTPUT O L H L H H H H H any odd number of inputs HIGH any even number of inputs HIGH H Notes 1. H = HIGH state (the more positive voltage) 2. L = LOW state (the less positive voltage) AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; input transition times ≤ 20 ns VDD V Dynamic power dissipation per package (P) 5 10 15 TYPICAL FORMULA FOR P (µW) 425 fi + ∑ (foCL) × VDD2 2 400 fi + ∑ (foCL) × VDD2 7 700 fi + ∑ (foCL) × VDD2 where H H H H H H H H fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) ∑ (foCL) = sum of outputs VDD = supply voltage (V) January 1995 3 Philips Semiconductors Product specification 13-input parity checker/generator AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V Propagation delays I0 to I11 → O HIGH to LOW 5 10 15 5 LOW to HIGH I12 → 0 HIGH to LOW 10 15 5 10 15 5 LOW to HIGH Output transition times HIGH to LOW 10 15 5 10 15 5 LOW to HIGH 10 15 tTLH tTHL tPLH tPHL tPLH tPHL 145 60 45 135 55 45 105 45 35 85 35 25 60 30 20 60 30 20 290 120 90 270 110 90 210 90 70 170 70 50 120 60 40 120 60 40 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL TYP. MAX. HEF4531B MSI TYPICAL EXTRAPOLATION FORMULA 118 ns + (0,55 ns/pF) CL 49 ns + (0,23 ns/pF) CL 37 ns + (0,16 ns/pF) CL 108 ns + (0,55 ns/pF) CL 44 ns + (0,23 ns/pF) CL 37 ns + (0,16 ns/pF) CL 78 ns + (0,55 ns/pF) CL 34 ns + (0,23 ns/pF) CL 27 ns + (0,16 ns/pF) CL 58 ns + (0,55 ns/pF) CL 24 ns + (0,23 ns/pF) CL 17 ns + (0,16 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL January 1995 4