HEF4724BD

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4724B MSI 8-bit addressable latch Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification 8-bit addressable latch DESCRIPTION The HEF4724B is an 8-bit addressable latch with three address inputs (A0 to A2), a data input (D), an active LOW enable input (E), an active HIGH clear input (CL), and eight parallel latch outputs (O0 to O7). When E and CL are HIGH, all outputs (O0 to O7) are LOW. Eight-channel demultiplexing or active HIGH 1-of-8 decoding with output enable operation occurs when CL is HIGH and E is LOW. When CL and E are LOW, the HEF4724B MSI selected output (O0 to O7; determined by A0 to A2) follows D. When E goes HIGH, the contents of the latch are stored. When operating in the addressable latch mode (E = CL = LOW), changing more than one bit of A0 to A2 could impose a transient wrong address. Therefore, this should only be done while in the memory mode (E = HIGH, CL = LOW). Fig.2 Pinning diagram. HEF4724BP(N): HEF4724BD(F): HEF4724BT(D): 16-lead DIL; plastic (SOT38-1) 16-lead DIL; ceramic (cerdip) (SOT74) 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America PINNING A0 to A2 Fig.1 Functional diagram. A E CL O0 to O7 address inputs data input enable input (active LOW) clear input (active HIGH) parallel latch outputs FAMILY DATA, IDD LIMITS category MSI See Family Specifications January 1995 2 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... January 1995 3 Fig.3 Logic diagram. Product specification Fig.4 Logic diagram (one latch). Philips Semiconductors 8-bit addressable latch HEF4724B MSI Philips Semiconductors Product specification 8-bit addressable latch MODE SELECTION E L H L H CL L L H H addressable latch memory active HIGH 8-channel demultiplexer clear MODE HEF4724B MSI FUNCTION TABLE CL H H H H H H H H H L L L L L L L L L Notes 1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state is immaterial On-1 = state before the positive transition of E D1 = either HIGH or LOW E H L L L L L L L L H L L L L L L L L D X D1 D1 D1 D1 D1 D1 D1 D1 X D1 D1 D1 D1 D1 D1 D1 D1 A0 X L H L H L H L H X L H L H L H L H A1 X L L H H L L H H X L L H H L L H H A2 X L L L L H H H H X L L L L H H H H O0 L D1 L L L L L L L On-1 D1 On-1 On-1 On-1 On-1 On-1 On-1 On-1 O1 L L D1 L L L L L L On-1 On-1 D1 On-1 On-1 On-1 On-1 On-1 On-1 O2 L L L D1 L L L L L On-1 On-1 On-1 D1 On-1 On-1 On-1 On-1 On-1 O3 L L L L D1 L L L L On-1 On-1 On-1 On-1 D1 On-1 On-1 On-1 On-1 O4 L L L L L D1 L L L On-1 On-1 On-1 On-1 On-1 D1 On-1 On-1 On-1 O5 L L L L L L D1 L L O6 L L L L L L L D1 L O7 L L L L L L L L D1 demultiplexer; unaddressed latch is cleared MODE clear On-1 On-1 On-1 memory On-1 On-1 On-1 On-1 On-1 On-1 addressable On-1 On-1 On-1 latch; On-1 On-1 On-1 unaddressed On-1 On-1 On-1 latch holds D1 On-1 On-1 previous state On-1 D1 On-1 On-1 On-1 D1 January 1995 4 Philips Semiconductors Product specification 8-bit addressable latch AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; input transition times ≤ 20 ns VDD V Dynamic power dissipation per package (P) 5 10 15 TYPICAL FORMULA FOR P (µW) 700 fi + ∑ (foCL) × VDD2 3700 fi + ∑ (foCL) × 10 800 fi + ∑ (foCL) × VDD2 VDD2 where HEF4724B MSI fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) ∑ (foCL) = sum of outputs VDD = supply voltage (V) AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V Propagation delays E → On HIGH to LOW 5 10 15 5 LOW to HIGH D → On HIGH to LOW 10 15 5 10 15 5 LOW to HIGH An → On HIGH to LOW 10 15 5 10 15 5 LOW to HIGH CL → On HIGH to LOW 10 15 5 10 15 tPHL tPLH tPHL tPLH tPHL tPLH tPHL 115 50 35 95 40 30 95 35 25 85 35 25 110 45 35 95 40 30 85 35 25 230 95 70 195 80 55 190 75 55 170 75 55 225 95 70 190 80 55 165 70 50 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 88 ns + (0,55 ns/pF) CL 39 ns + (0,23 ns/pF) CL 27 ns + (0,16 ns/pF) CL 68 ns + (0,55 ns/pF) CL 29 ns + (0,23 ns/pF) CL 22 ns + (0,16 ns/pF) CL 68 ns + (0,55 ns/pF) CL 24 ns + (0,23 ns/pF) CL 17 ns + (0,16 ns/pF) CL 58 ns + (0,55 ns/pF) CL 24 ns + (0,23 ns/pF) CL 17 ns + (0,16 ns/pF) CL 83 ns + (0,55 ns/pF) CL 34 ns + (0,23 ns/pF) CL 27 ns + (0,16 ns/pF) CL 68 ns + (0,55 ns/pF) CL 29 ns + (0,23 ns/pF) CL 22 ns + (0,16 ns/pF) CL 58 ns + (0,55 ns/pF) CL 24 ns + (0,23 ns/pF) CL 17 ns + (0,16 ns/pF) CL SYMBOL MIN. TYP. MAX. TYPICAL EXTRAPOLATION FORMULA January 1995 5 Philips Semiconductors Product specification 8-bit addressable latch HEF4724B MSI SYMBOL MIN. 40 tsu 15 10 40 tsu 20 15 20 thold 15 15 50 thold 20 15 75 tWEL 30 20 70 tWCLH 30 20 TYP. 20 5 0 20 10 5 0 5 5 25 10 5 35 15 10 35 15 10 MAX. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns see also waveforms Fig.5 TYPICAL EXTRAPOLATION FORMULA VDD V Set-up times D→E 5 10 15 5 An → E Hold times D→E 10 15 5 10 15 5 An → E Minimum E pulse width; LOW Minimum CL pulse width; HIGH 10 15 5 10 15 5 10 15 AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V Output transition times HIGH to LOW 5 10 15 5 LOW to HIGH 10 15 tTLH tTHL 60 30 20 60 30 20 120 60 40 120 60 40 ns ns ns ns ns ns 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL SYMBOL MIN. TYP. MAX. TYPICAL EXTRAPOLATION FORMULA January 1995 6 Philips Semiconductors Product specification 8-bit addressable latch HEF4724B MSI (1) The address to enable set-up time is the time before the HIGH to LOW enable transition that the address must be stable so that the correct latch is addressed and the other latches are not affected. Fig.5 Waveforms showing minimum E and CL pulse widths, set-up times, hold times. Set-up and hold times are shown as positive values but may be specified as negative values. January 1995 7