N74F382N

INTEGRATED CIRCUITS 74F382 Arithmetic Logic Unit Product specification IC15 Data Handbook 1990 Jul 12 Philips Semiconductors Philips Semiconductors Product specification Arithmetic logic unit 74F382 FEATURES • Performs six arithmetic and logic functions • Selectable Low (clear) and High (preset) functions • Low-input loading minimizes drive requirements • Carry output for ripple expansion • Overflow output for Two’s Complement arithmetic DESCRIPTION The 74F382 performs three arithmetic and three logic operations on two 4-bit words, A and B. Two additional Select (S0–S2) input codes force the Function outputs Low or High. An overflow output is provided for convenience in Two’s Complement arithmetic. A carry output is provided for ripple expansion. For high-speed expansion using a carry look-ahead generator, refer to the 74F381 data sheet. Signals applied to the Select inputs, S0–S2, determine the mode of operation, as indicated in the Function Select Table. An extensive listing of input and output levels is shown in the Function Table. The circuit performs the arithmetic functions for either active-HIgh or active-Low operands, with output levels in the same convention. In the subtract operating modes, it is necessary to force a carry (High for active-HIgh operands, Low for active-Low operands) into the Cn input of the least significant package. Ripple expansion is illustrated in Figure 1. The overflow output OVR is the Exclusive-OR of Cn+3 and Cn+4; a High signal on OVR indicates overflow in Two’s complement operation (See Table 2 for Two’s complement arithmetic). Typical delays for Figure 1 are given in Table 1. When the 74F382 is cascaded to handle word lengths longer than 4 bits, only the most significant overflow (OVR) output is used. PIN CONFIGURATION A1 1 B1 2 A0 3 B0 4 S0 5 S1 6 S2 7 F0 8 20 V CC 19 A2 18 B2 17 A3 16 B3 15 Cn 14 Cn+4 13 OVR 12 F3 11 F2 F1 9 GND 10 SF00935 TYPE 74F382 TYPICAL PROPAGATION DELAY 7.0ns TYPICAL SUPPLY CURRENT (TOTAL) 54mA ORDERING INFORMATION DESCRIPTION 20-pin plastic DIP 20-pin plastic SO COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F382N N74F382D PKG DWG # SOT146-1 SOT163-1 INPUT AND OUTPUT LOADING AND FAN OUT TABLE PINS A0 – A3 B0 – B3 S0 – S2 Cn Cn+4 OVR A operand inputs B operand inputs Function select inputs Carry input Carry output Overflow output DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/4.0 1.0/4.0 1.0/1.0 1.0/5.0 50/33 50/33 50/33 LOAD VALUE HIGH/LOW 20µA/2.4mA 20µA/2.4mA 20µA/0.6mA 20µA/3.0mA 1.0mA/20mA 1.0mA/20mA 1.0mA/20mA F0–F3 Outputs NOTE: One (1.0) FAST unit load is defined as 20µA in the High state and 0.6mA in the Low state. 1990 Jul 12 2 853–0419 99966 Philips Semiconductors Product specification Arithmetic logic unit 74F382 LOGIC SYMBOL 3 4 1 2 19 18 17 16 IEC/IEEE SYMBOL 5 6 7 A0 B0 A1 B1 A2 B2 A3 B3 15 2 (1/2) Bl 3 Cl 0 M 0 7 ALU 15 5 6 7 Cn S0 S1 S2 F0 F1 F2 F3 OVR Cn+4 13 14 3 4 1 2 19 P Q P Q P Q P Q [1] 8 [2] [4] BO/CO BO/CO [8] 9 VCC = Pin 20 GND = Pin 10 8 9 11 12 11 =1 (1/2)BO 3CO 13 14 12 SF00936 18 17 16 SF00937 1990 Jul 12 3 Philips Semiconductors Product specification Arithmetic logic unit 74F382 LOGIC DIAGRAM Cn 15 A0 3 8 F0 B0 A1 4 1 9 F1 B1 2 A2 19 11 F2 B2 18 A3 17 12 F3 B3 16 13 OVR S0 5 14 Cn+4 S1 6 7 S2 VCC = Pin 20 GND = Pin 10 SF00938 1990 Jul 12 4 Philips Semiconductors Product specification Arithmetic logic unit 74F382 FUNCTION TABLE INPUTS S0 L L H H H H H H H H L L L L L L L L H H H H H H H H L L L L L H H H H H L L L L L H H H H H S1 L L L L L L L L L L H H H H H H H H H H H H H H H H L L L L L L L L L L H H H H H H H H H H S2 L L L L L L L L L L L L L L L L L L L L L L L L L L H H H H H H H H H H H H H H H H H H H H Cn L H L L L L H H H H L L L L H H H H L L L L H H H H X X L X H X X X L H X X X L H X X X L H An X X L L H H L L H H L L H H L L H H L L H H L L H H L L H H H L L H H H L L H H H L L H H H Bn X X L H L H L H L H L H L H L H L H L H L H L H L H L H L H L L H L H H L H L H H L H L H H F0 L L H L L H L H H L H L L H L H H L L H H L H L L H L H H L H L H H H H L L L H H H H H H H F1 L L H H L H L H L L H L H H L L H L L H H H L L L H L H H L H L H H H H L L L H H H H H H H OUTPUTS F2 L L H H L H L H L L H L H H L L H L L H H H L L L H L H H L H L H H H H L L L H H H H H H H F3 L L H H L H L H L L H L H H L L H L L H H H L L L H L H H L H L H H H H L L L H H H H H H H OVR H H L L L L L L L L L L L L L L L L L L L L L L L L L L L H H L L L L H H L H L H L L L L H Cn+4 H H L H L L H H L H L L H L H L H H L L L H L H H H L L L H H L L L L H H L H L H L L L L H Preset AB A+B A B A Plus B Plus Active Active-High Active-Low Active Low A minus B minus Active-High Active Active-Low Active Low B minus A minus OPERANDS OPERATING MODE Clear H = High voltage level L = Low voltage level X = Don’t care 1990 Jul 12 5 Philips Semiconductors Product specification Arithmetic logic unit 74F382 FUNCTION SELECT TABLE SELECT S0 L H L H L H L S1 L L H H L L H S2 L L L L H H H H OPERATING MODE Clear B minus A A minus B A Plus B A AB Preset B A+B Table 2. Two’s Complement Arithmetic MSB L L L L L L L L H H H H OUTPUT Cn+4, OVR 6.5ns 6.3ns 6.3ns – 8.0ns 27.1ns H H H H L L L L H H H H L L L L H H H L L H H L L H H L L H H L L H H LSB L H L H L H L H L H L H L H L H Numerical Values 0 1 2 3 4 5 6 7 –8 –7 –6 –5 –4 –3 –2 –1 H H H = High voltage level L = Low voltage level Table 1. 16-Bit Delay Tabulation PATH SEGMENT Ai or Bi to Cn+4 Cn to Cn+4 Cn to Cn+4 Cn to F Cn to Cn+4, OVR Total Delay TOWARD F 6.5ns 6.3ns 6.3ns 8.1ns – 27.2ns H H = High voltage level L = Low voltage level APPLICATION A0–A3 B0–B3 A4–A7 B4–B7 A8–A11 B8–B11 A12–A15 B12–B15 4 A CIN Cn S 3 SELECT 3 F0–F3 B 4 A Cn S 3 4 B 4 A Cn S 3 4 B 4 A Cn S 3 4 B 4 Cn+4 74F382 F Cn+4 74F382 F Cn+4 74F382 F Cn+4 74F382 F OVR COUT OVERFLOW F4–F7 F8–F11 F12–F15 SF00939 Figure 1. 16-bit Look-ahead Carry ALU Expansion 1990 Jul 12 6 Philips Semiconductors Product specification Arithmetic logic unit 74F382 ABSOLUTE MAXIMUM RATINGS (Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL VCC VIN IIN VOUT IOUT Tamb Tstg Supply voltage Input voltage Input current Voltage applied to output in High output state Current applied to output in Low output state Operating free-air temperature range Storage temperature range PARAMETER RATING –0.5 to +7.0 –0.5 to +7.0 –30 to +1 –0.5 to +VCC 40 0 to +70 –65 to +150 UNIT V V mA V mA °C °C RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL VCC VIH VIL IIK IOH IOL Tamb Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current Operating free-air temperature range 0 PARMETER SYMBOL MIN 4.5 2.0 0.8 –18 –1 20 70 NOM 5.0 MAX 5.5 UNIT V V V mA mA mA °C DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST CONDITIONS1 VCC = MIN, VIL = MAX, VOH High level output voltage High-level output voltage VIH = MIN, IOH = MAX Low-level output voltage Low level output voltage Input clamp voltage Input current at maximum input voltage High-level input current Cn IIL Low-level input current A0–A3, B0–B3 S0, S1, S2 IOS Short-circuit output current3 VCC = MAX –60 VCC = MAX, VI = 0.5V VCC = MIN, VIL = MAX, VIH = MIN, IOL = MAX VCC = MIN, II = IIK VCC = MAX, VI = 7.0V VCC = MAX, VI = 2.7V ±10%VCC ±5%VCC ±10%VCC ±5%VCC MIN 2.5 2.7 3.4 0.30 0.30 –0.73 0.50 0.50 –1.2 100 20 –3.0 –2.4 –0.6 –150 LIMITS TYP2 MAX V V V V V µA µA mA mA mA mA UNIT VO OL VIK II IIH ICC Supply current (total) VCC = MAX 54 81 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. 1990 Jul 12 7 Philips Semiconductors Product specification Arithmetic logic unit 74F382 AC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25°C VCC = +5.0V CL = 50pF, RL = 500Ω MIN tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Propagation delay Cn to Fn Propagation delay An or Bn to Fn Propagation delay Si to Fi Propagation delay Ai to Bi to Cn+4 Propagation delay Si to OVR or Cn+4 Propagation delay Cn to Cn+4 Propagation delay Cn to OVR Propagation delay Ai or Bi to OVR Waveform 1 Waveform 1 Waveform 1 Waveform 1 Waveform 1 Waveform 1 Waveform 1 Waveform 1 3.0 2.5 3.5 3.0 5.5 5.5 3.5 3.5 7.0 5.0 3.0 3.5 4.5 3.0 6.0 3.5 TYP 7.0 4.5 8.0 6.0 9.0 7.5 7.0 6.5 10.5 8.0 4.5 5.0 9.0 5.0 9.0 6.5 MAX 12.0 6.5 13.5 10.0 15.0 10.5 10.5 9.5 14.5 11.0 6.0 6.5 13.5 6.5 12.5 9.0 Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω MIN 2.5 2.5 3.5 2.5 5.5 5.5 3.5 3.5 6.5 5.0 2.5 3.5 4.0 3.0 5.5 3.5 MAX 13.5 7.5 17.0 11.0 16.0 12.0 11.5 10.5 17.0 12.0 6.5 7.0 15.0 7.0 16.5 10.0 ns ns ns ns ns ns ns ns UNIT AC WAVEFORMS For all waveforms, VM = 1.5V. VIN VM tPLH VM tPHL VOUT VM VM SF00940 Waveform 1. Propagation Delay for Non-Inverting or Inverting paths 1990 Jul 12 8 Philips Semiconductors Product specification Arithmetic logic unit 74F382 TEST CIRCUIT AND WAVEFORM VCC NEGATIVE PULSE VIN PULSE GENERATOR RT D.U.T. VOUT 90% VM 10% tTHL (tf ) CL RL tw VM 10% tTLH (tr ) 0V 90% AMP (V) tTLH (tr ) 90% POSITIVE PULSE VM 10% tw tTHL (tf ) AMP (V) 90% VM 10% 0V Test Circuit for Totem-Pole Outputs DEFINITIONS: RL = Load resistor; see AC ELECTRICAL CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC ELECTRICAL CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate 1MHz tw 500ns tTLH 2.5ns tTHL 2.5ns SF00006 1990 Jul 12 9 Philips Semiconductors Product specification Arithmetic Logic Unit 74F382 DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1 1990 Jul 12 10 Philips Semiconductors Product specification Arithmetic Logic Unit 74F382 SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 1990 Jul 12 11 Philips Semiconductors Product specification Arithmetic Logic Unit 74F382 Data sheet status Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Production [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 © Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 10-98 9397-750-05124 Philips Semiconductors yyyy mmm dd 12