N74F604N

Philips Semiconductors Product specification Dual octal latch (3-State) 74F604 FEATURES • High impedance NPN base inputs for reduced loading (20µA in High and Low states) PIN CONFIGURATION LE SELECT A/B A0 B0 A1 B1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC A4 B4 A5 B5 A6 B6 A7 B7 Q7 Q6 Q5 Q4 Q0 • Stores 16-bit–wide Data inputs, multiplexed 8-bit outputs • 3-State outputs • Power supply current 75mA typical DESCRIPTION The 74F604 multiplexed latch is ideal for storing data from two input buses, A or B, and providing data from either the A or B latches to the output bus. Organized as 8-bit A and B latches, the latch outputs are connected by pairs to eight 2-input multiplexers. A Select (SELECT A/B) input determines whether the A or B latch contents are multiplexed to the eight 3-State outputs. Data entered from the B inputs are selected when SELECT A/B is Low; data from the A inputs are selected when SELECT A/B is High. Data enters the latches when the Latch Enable (LE) input is Low and is latched on the LE rising edge. The outputs are enabled when LE is High and disabled when LE is Low. A2 B2 A3 B3 Q3 Q2 Q1 GND SF01115 TYPE 74F604 TYPICAL PROPAGATION DELAY 7.5ns TYPICAL SUPPLY CURRENT (TOTAL) 75mA ORDERING INFORMATION DESCRIPTION 28-pin plastic DIP 28-pin plastic SOL COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F604N N74F604D INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS A0–A7, B0–B7 SELECT A/B LE Q0–Q7 Data inputs Select input Latch Enable input (active Low) Data outputs DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/0.033 1.0/0.033 1.0/0.033 150/40 LOAD VALUE HIGH/LOW 20µA/20µA 20µA/20µA 20µA/20µA 3mA/24mA NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state. 1990 Mar 01 1 853–0029 98991 Philips Semiconductors Product specification Dual octal latch (3-State) 74F604 LOGIC SYMBOL 3 4 5 6 7 8 9 10 27 26 25 24 23 22 21 20 IEC/IEEE SYMBOL (IEEE/IEC) 2 1 G2 E1 EN 3 4 5 6 7 8 9 10 27 26 25 24 23 22 21 20 A0 B0 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 1 2 LE SELECT A/B 1D 2 1D 2 ≥1 15 13 12 11 16 17 18 19 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 15 13 12 11 16 17 18 19 VCC = Pin 28 GND = Pin 14 SF01116 SF01117 FUNCTION TABLE INPUTS A0–A7 A data A data X X X H L X Z ↑ = = = = = B0–B7 B data B data X X X SELECT A/B L H X L H LE ↑ ↑ L H H OUTPUTS Q0–Q7 B data B data Z B latched data A latched data High voltage level Low voltage level Don’t care High impedance “off” state Low-to-High clock transition 1990 Mar 01 2 Philips Semiconductors Product specification Dual octal latch (3-State) 74F604 LOGIC DIAGRAM 2 SELECT A/B LE 1 A0 B0 3 4 D E D E 15 Q0 A1 B1 5 6 D E D E 13 Q1 A2 B2 7 8 D E D E 12 Q2 A3 B3 9 10 D E D E 11 Q3 A4 B4 27 26 D E D E 16 Q4 A5 B5 25 24 D E D E 17 Q5 A6 B6 23 22 D E D E 18 Q6 A7 B7 21 20 D E D E 19 Q7 VCC = Pin 28 GND = Pin 14 SF01118 1990 Mar 01 3 Philips Semiconductors Product specification Dual octal latch (3-State) 74F604 ABSOLUTE MAXIMUM RATINGS (Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL VCC VIN IIN VOUT IOUT Tamb Tstg Supply voltage Input voltage Input current Voltage applied to output in High output state Current applied to output in Low output state Operating free-air temperature range Storage temperature range PARAMETER RATING –0.5 to +7.0 –0.5 to +7.0 –30 to +5 –0.5 to +VCC 48 0 to +70 –65 to +150 UNIT V V mA V mA °C °C RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL VCC VIH VIL IIK IOH IOL Tamb Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current Operating free-air temperature range 0 PARAMETER MIN 4.5 2.0 0.8 –18 –3 24 70 NOM 5.0 MAX 5.5 V V V mA mA mA °C UNIT 1990 Mar 01 4 Philips Semiconductors Product specification Dual octal latch (3-State) 74F604 DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST CONDITIONS1 CONDITIONS VCC = MIN, VIL = MAX, VIH = MIN, IOH = MAX VCC = MIN, VIL = MAX, VIH = MIN, IOL = MAX VCC = MIN, II = IIK VCC = 0.0V, VI = 7.0V VCC = MAX, VI = 2.7V VCC = MAX, VI = 0.5V VCC = MAX, VO = 2.7V VCC = MAX, VO = 0.5V VCC = MAX An, Bn, SELECT A/B = 4.5V, LE = ↑ VCC = MAX MAX An, Bn, SELECT A/B=GND, LE = ↑ An, Bn, SELECT A/B = GND, LE = GND –60 60 75 75 ±10%VCC ±5%VCC ±10%VCC ±5%VCC LIMITS MIN 2.4 2.7 3.4 0.35 0.35 –0.73 0.50 0.50 –1.2 100 20 –20 50 –50 –150 82 100 100 TYP2 MAX UNIT V V V V V µA µA µA µA µA mA mA mA mA VOH High-level output voltage High-level output voltage VOL VIK II IIH IIL IOZH IOZL IOS Low-level output voltage Low-level output voltage Input clamp voltage Input current at maximum input voltage High-level input current Low-level input current Off state output current, High-level voltage applied Off state output current, Low-level voltage applied Short-circuit output current3 ICCH ICC Supply current (total) S l current (total) l) ICCL ICCZ NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. AC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITION VCC = +5V Tamb = +25°C CL = 50pF, RL = 500Ω MIN tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation delay SELECT A/B to Qn (B latch) Propagation delay SELECT A/B to Qn (A latch) Output Enable time to High or Low level Output Disable time from High or Low level Waveform 1 Waveform 2 Waveform 4 Waveform 5 Waveform 4 Waveform 5 5.0 6.0 6.0 4.0 5.0 5.0 5.0 5.0 TYP 7.0 8.5 8.0 6.5 7.5 7.5 7.0 7.0 MAX 9.0 10.5 10.0 8.5 9.5 9.5 9.5 9.5 VCC = +5V ± 10% Tamb = 0°C to +70°C CL = 50pF, RL = 500Ω MIN 4.5 5.5 5.5 3.5 4.5 4.5 4.5 4.5 MAX 10.0 11.5 11.5 9.0 10.5 11.0 11.0 11.0 ns ns ns ns UNIT 1990 Mar 01 5 Philips Semiconductors Product specification Dual octal latch (3-State) 74F604 AC SETUP REQUIREMENTS LIMITS SYMBOL PARAMETER TEST CONDITION VCC = +5V Tamb = +25°C CL = 50pF, RL = 500Ω MIN ts(H) ts(L) th(H) th(L) tW(L) Setup time, High or Low An, Bn to LE Hold time, High or Low An, Bn to LE LE Pulse width, Low Waveform 3 Waveform 3 Waveform 3 1.0 2.0 0 1.0 5.0 TYP MAX VCC = +5V ± 10% Tamb = 0°C to +70°C CL = 50pF, RL = 500Ω MIN 2.0 3.0 0 1.5 6.0 MAX ns ns ns UNIT AC WAVEFORMS For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance. SELECT A/B VM tPHL VM tPLH VM VM SELECT A/B VM tPHL VM tPLH VM VM Qn Qn SF01119 SF01120 Waveform 1. Propagation Delay, SELECT A/B To Output (B latched data=Low. LE=H) Waveform 2. Propagation Delay, SELECT A/B to Output (A latched data=Low. LE=H) An, Bn VM ts(H) VM th(H) VM ts(L) tw(L) VM th(L) LE VM VM VM SF01121 Waveform 3. Data Setup and Hold Times, Latch Enable Pulse Width LE VM tPZH VM tPHZ VM 0V VOH -0.3V LE VM tPZL VM tPLZ VM VOL +0.3V Qn Qn SF01122 SF01123 Waveform 4. 3-State Output Enable Time to High Level and Output Disable Time from High Level Waveform 5. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level 1990 Mar 01 6 Philips Semiconductors Product specification Dual octal latch (3-State) 74F604 TEST CIRCUIT AND WAVEFORMS VCC 7.0V VIN PULSE GENERATOR RT D.U.T. VOUT RL NEGATIVE PULSE 90% VM 10% tTHL (tf ) CL RL tTLH (tr ) 90% POSITIVE PULSE 10% tTHL (tf ) AMP (V) 90% VM tw 10% 0V tw VM 10% tTLH (tr ) 0V AMP (V) 90% Test Circuit for 3-State Outputs SWITCH POSITION TEST tPLZ tPZL All other SWITCH closed closed open VM Input Pulse Definition DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators. INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate 1MHz tw 500ns tTLH 2.5ns tTHL 2.5ns SF00777 1990 Mar 01 7