N74F835N

Philips Semiconductors Product specification 8-bit shift register with 2:1 mux-in, latched “B” inputs, and serial out 74F835 FEATURES • Specifically designed for Video applications • Combines the 74F373, two 74F157s, and the 74F166 functions in • Interleaved loading with 2:1 mux • Dual 8-bit parallel inputs • Transparent latch on all “B” inputs • Guaranteed serial shift frequency to 100MHz • Expandable to 16-bits or more with serial input DESCRIPTION The 74F835 is a high speed 8-bit parallel/serial-in, serial-out shift register whose parallel inputs have been connected to an internal octal two-to-one multiplexer with all the “B” inputs connected to an octal latch. This 24-pin part is specifically designed for video bit shifting, where interleaved loading is desired and parts count is critical. It is useful in any design where a 2:1 mux input with a transparent latch is needed. TYPICAL SUPPLY CURRENT (TOTAL) 45mA one package PIN CONFIGURATION PE 1 CP D4A D4B D5A D5B D6A D6B D7A 2 3 4 5 6 7 8 9 24 VCC 23 D3B 22 D3A 21 D2B 20 D2A 19 D1B 18 D1A 17 D0B 16 D0A 15 DS 14 SA/B 13 LE D7B 10 Q7 11 GND 12 SF01355 ORDERING INFORMATION DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F835N N74F835D PACKAGE DRAWING NUMBER SOT222-1 SOT137-1 TYPE 74F835 TYPICAL fMAX 150MHz 24-pin plastic Slim DIP (300 mil) 24-pin plastic SOL INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS D0A – D7A D0B – D7B DS CP SA/B LE PE Q7 DESCRIPTION Parallel data inputs Latched Parallel data inputs Serial data input Shift Register Clock input (active rising edge) Mux Select Latch Enable input (for B inputs) Parallel Enable input Output 74F (U.L.) HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33 LOAD VALUE HIGH/LOW 20µA/0.6mA 20µA/0.6mA 20µA/0.6mA 20µA/0.6mA 20µA/0.6mA 20µA/0.6mA 20µA/0.6mA 1.0mA/20mA NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state. 1990 Jan 08 1 853–0615 99490 Philips Semiconductors Product specification 8-bit shift register with 2:1 mux-in, latched “B” inputs, and serial out 74F835 LOGIC SYMBOL IEC/IEEE SYMBOL 2 SRG 8 C1 MUX 1 13 M4 EN3 G2 15 16 17 18 19 20 21 22 23 3 4 5 6 7 8 9 10 DS 2 1 13 14 CP PE LE D0B D1B D2B D3B D4B D5B D6B D7B D0A D1A D2A D3A D4A D5A D6A D7A 14 15 16 17 Q7 18 19 20 11 21 22 23 1,4 1, 2, 3, 4 1, 2, 3, 4 SA/B VCC = PIN 24 GND = PIN 12 SF01356 3 4 5 6 7 8 9 10 11 SF01357 TYPICAL TIMING DIAGRAM LOAD A PE SHIFT A CP LOAD B LATCH SHIFT B UNLOAD B LATCH SA/B SET B D0A D7A D0B D7B q7A q6A q1A q0A q7B q6B q5B Q7 1990 Jan 08 2 ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ q0B ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ É ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ LE SF01359 Philips Semiconductors Product specification 8-bit shift register with 2:1 mux-in, latched “B” inputs, and serial out 74F835 LOGIC DIAGRAM D0A 16 13 LE D Q E D Q E D Q E D Q E D Q E D Q E D Q E D Q E D0B 17 D1A 18 D1B 19 D2A 20 D2B 21 D3A 22 D3B 23 D4A 3 D4B 4 D5A 5 D5B 6 D6A 7 D6B 8 D7A 9 D7B 10 SA/B 14 PE 1 DS 15 D CP CP 2 Q D CP Q D CP Q D CP Q D CP Q D CP Q D CP Q D CP Q 11 Q7 VCC = PIN 24 GND = PIN 12 SF01358 FUNCTION TABLE INTERNAL OPERATING MODE PE Parallel load A data Latch B data Parallel load B data (from Latch) Parallel load B data (Transparent Mode) Serial Shift H L h l X qn ↑ = = = = = = = L X L L H CP ↑ X ↑ ↑ ↑ LE X L L H X INPUTS SA/B L X H H X DnA h l X X X X X X X X DnB X X h l X X h l X X DS X X X X X X X X h l B LATCH X X H L h l h l X X SERIAL REGISTER Q0 H L X X H L H L H L Q1–6 H L X X H L H L qn–1 qn–1 OUTPUT Q7 H L X X H L H L q6 q6 High voltage level Low voltage level High voltage level one setup time prior to the Low-to-High clock transition Low voltage level one setup time prior to the Low-to-High clock transition Don’t care Lower case letters indicate the state of the referenced flop cell one cycle prior to the Low-to-High clock transition Low-to-High clock transition 1990 Jan 08 3 Philips Semiconductors Product specification 8-bit shift register with 2:1 mux-in, latched “B” inputs, and serial out 74F835 ABSOLUTE MAXIMUM RATINGS (Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL VCC VIN IIN VOUT IOUT Tamb Tstg Supply voltage Input voltage Input current Voltage applied to output in High output state Current applied to output in Low output state Operating free-air temperature range Storage temperature range PARAMETER RATING –0.5 to +7.0 –0.5 to +7.0 –30 to +5 –0.5 to VCC 40 0 to +70 –65 to +150 UNIT V V mA V mA °C °C RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL VCC VIH VIL IIK IOH IOL Tamb Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current Operating free-air temperature range 0 PARAMETER MIN 4.5 2.0 0.8 –18 –1 20 +70 NOM 5.0 MAX 5.5 UNIT V V V mA mA mA °C DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST CONDITIONS1 VCC = MIN, VIL = MAX VIH = MIN, IOH = MAX VCC = MIN, VIL = MAX VIH = MIN, IOHL= MAX VCC = MIN, II = IIK VCC = MAX, VI = 7.0V VCC = MAX, VI = 2.7V VCC = MAX, VI = 0.5V VCC = MAX VCC = MAX –60 45 ±10% VCC ±5% VCC ±10% VCC ±5% VCC LIMITS MIN 2.5 2.7 3.4 0.30 0.30 –0.73 0.50 0.50 –1.2 100 20 –0.6 –150 65 TYP2 MAX UNIT V V V V V µA µA mA mA mA VOH High-level output voltage VOL VIK II IIH IIL IOS ICC Low-level output voltage Input clamp voltage Input current at maximum input voltage High-level input current Low-level input current Short circuit output current3 Supply current (total) NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V. Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other tests. In any sequence of parameter tests, IOS tests should be performed last. 1990 Jan 08 4 Philips Semiconductors Product specification 8-bit shift register with 2:1 mux-in, latched “B” inputs, and serial out 74F835 AC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25°C VCC = +5.0V CL = 50pF, RL = 500Ω MIN fMAX tPLH tPHL tPLH tPHL Maximum clock frequency Propagation delay CP to Q7 (Load) Propagation delay CP to Q7 (Shift) Waveform 1 Waveform 1 Waveform 1 130 5.0 5.0 5.0 5.0 TYP 150 7.0 7.0 7.0 7.0 9.5 9.5 9.5 9.5 MAX Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω MIN 100 5.0 5.0 5.0 5.0 10.0 10.0 10.0 10.0 MAX MHz ns ns UNIT AC SETUP REQUIREMENTS LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25°C VCC = +5.0V CL = 50pF, RL = 500Ω MIN ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) tw(H) tw(L) tw(H) Setup time DnA or DnB to CP Hold time DnA or DnB to CP Setup time DS to CP Hold time DS to CP Setup time PE to CP Hold time PE to CP Setup time DnB to LE Hold time DnB to LE Setup time SA/B to CP Hold time SA/B to CP clock pulse width, High or Low Latch Enable pulse width, High Waveform 2 Waveform 2 Waveform 2 Waveform 2 Waveform 2 Waveform 2 Waveform 2 Waveform 2 Waveform 2 Waveform 2 Waveform 1 Waveform 1 3.5 3.5 1.0 1.0 1.0 1.0 2.0 2.0 3.5 3.5 0.0 0.0 0.0 0.0 3.0 3.0 4.5 4.5 0.0 0.0 4.5 4.5 4.5 TYP MAX Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω MIN 3.5 3.5 1.5 1.5 1.5 1.5 2.5 2.5 4.0 4.0 0.0 0.0 0.0 0.0 4.0 4.0 5.0 5.0 0.0 0.0 5.5 5.0 5.0 MAX ns ns ns ns ns ns ns ns ns ns ns ns UNIT 1990 Jan 08 5 Philips Semiconductors Product specification 8-bit shift register with 2:1 mux-in, latched “B” inputs, and serial out 74F835 AC WAVEFORMS For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance. 1/fMAX CP VM tW(H) tPHL Q7 VM VM tW(L) tPLH VM DS, PE DnA, DnB SA/B VM ts(H) CP, LE VM VM th(H) VM ts(L) VM th(L) VM VM SF00287 SF01360 Waveform 1. Propagation Delay, Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency Waveform 2. Data and Select Setup and Hold Times TEST CIRCUIT AND WAVEFORMS VCC NEGATIVE PULSE VIN PULSE GENERATOR RT D.U.T. VOUT 90% VM 10% tTHL (tf ) CL RL tw VM 10% tTLH (tr ) 0V 90% AMP (V) tTLH (tr ) 90% POSITIVE PULSE VM 10% tw tTHL (tf ) AMP (V) 90% VM 10% 0V Test Circuit for Totem-Pole Outputs DEFINITIONS: RL = Load resistor; see AC ELECTRICAL CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC ELECTRICAL CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate 1MHz tw 500ns tTLH 2.5ns tTHL 2.5ns SF00006 1990 Jan 08 6