N74F841N

INTEGRATED CIRCUITS 74F841/842 Bus interface latches Product data Replaces datasheet 74F841/842/843/845/846 of 1999 Jun 23 2004 Jan 23 Philips Semiconductors Philips Semiconductors Product data 10-bit bus interface latches, non-inverting/inverting (3-State) 74F841/74F842 FEATURES • High speed parallel latches • Extra data width for wide address/data paths or buses carrying parity DESCRIPTION The 74F841 and 74F842 bus interface latches are designed to provide extra data width for wider address/data paths of buses carrying parity. The 74F841 consists of ten D-type latches with 3-State outputs. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. This allows asynchronous operation, as the output transition follows the data in transition. On the LE HIGH-to-LOW transition, the data that meets the set-up and hold time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH the output is in the high-impedance state. The 74F842 is the inverted output version of the 74F841. TYPICAL PROPAGATION DELAY 5.5 ns TYPICAL SUPPLY CURRENT (TOTAL) 60 mA • High impedance NPN base input structure minimizes bus loading • IIL is 20 µA for minimum bus loading • Buffered control inputs to reduce AC effects • Ideal where high speed, light loading, or increased fan-in are required as with MOS microprocessors • Positive and negative over-shoots are clamped to ground • 3-State outputs glitch free during power-up and power-down • 48 mA sink current • Slim dual in-line 300 mil package • Broadside pinout ORDERING INFORMATION COMMERCIAL RANGE: VCC = 5 V ± 10%; Tamb = 0 °C to +70 °C Type number Package Name N74F841N, N74F842N N74F841D, N74F842D DIP24 SO24 Description TYPE 74F841, 74F842 Version SOT222-1 SOT137-1 plastic dual in-line package; 24 leads (300 mil) plastic small outline package; 24 leads; body width 7.5 mm INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS Dn LE OE Qn Qn Data inputs Latch Enable input Output Enable input (active-LOW) Data outputs Data outputs DESCRIPTION 74F(U.L.) HIGH/LOW 1.0/0.033 1.0/0.033 1.0/0.033 1200/80 1200/80 LOAD VALUE HIGH/LOW 20 µA / 20 µA 20 µA / 20 µA 20 µA / 20 µA 24 mA / 48 mA 24 mA / 48 mA NOTE: One (1.0) FAST Unit Load is defined as: 20 µA in the HIGH state and 0.6 mA in the LOW state. 2004 Jan 23 2 Philips Semiconductors Product data 10-bit bus interface latches, non-inverting/inverting (3-State) 74F841/74F842 PIN CONFIGURATION for 74F841 OE 1 D0 D1 D2 D3 D4 D5 D6 D7 2 3 4 5 6 7 8 9 24 VCC 23 Q0 22 Q1 21 Q2 20 Q3 19 Q4 18 Q5 17 Q6 16 Q7 15 Q8 14 Q9 13 LE PIN CONFIGURATION for 74F842 OE 1 D0 D1 D2 D3 D4 D5 D6 D7 2 3 4 5 6 7 8 9 24 VCC 23 Q0 22 Q1 21 Q2 20 Q3 19 Q4 18 Q5 17 Q6 16 Q7 15 Q8 14 Q9 13 LE D8 10 D9 11 GND 12 D8 10 D9 11 GND 12 SF01279 SF01282 LOGIC SYMBOL for 74F841 2 3 4 5 6 7 8 9 10 11 LOGIC SYMBOL for 74F842 2 3 4 5 6 7 8 9 10 11 D0 13 1 LE OE Q0 D1 D2 D3 D4 D5 D6 D7 D8 D9 13 1 LE D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 23 VCC = Pin 24 GND = Pin 12 22 21 20 19 18 17 16 15 14 23 VCC = Pin 24 GND = Pin 12 22 21 20 19 18 17 16 15 14 SF01280 SF01283 LOGIC SYMBOL (IEEE/IEC) for 74F841 1 13 EN C1 LOGIC SYMBOL (IEEE/IEC) for 74F842 1 13 EN C1 2 3 4 5 6 7 8 9 10 11 1D 23 22 21 20 19 18 17 16 15 14 2 3 4 5 6 7 8 9 10 11 1D 23 22 21 20 19 18 17 16 15 14 SF01281 SF01284 2004 Jan 23 3 Philips Semiconductors Product data 10-bit bus interface latches, non-inverting/inverting (3-State) 74F841/74F842 LOGIC DIAGRAM for 74F841 74F841 D0 2 D1 3 D2 4 D3 5 D4 6 D5 7 D6 8 D7 9 D8 10 D9 11 D L Q D L Q D L Q D L Q D L Q D L Q D L Q D L Q D L Q D L Q C LE 13 OE 1 23 Q0 22 Q1 21 Q2 20 Q3 19 Q4 18 Q5 17 Q6 16 Q7 15 Q8 14 Q9 VCC = Pin 24 GND = Pin 12 SF01297 LOGIC DIAGRAM for 74F842 74F842 D0 2 D1 3 D2 4 D3 5 D4 6 D5 7 D6 8 D7 9 D8 10 D9 11 D L Q D L Q D L Q D L Q D L Q D L Q D L Q D L Q D L Q D L Q C LE 13 OE 1 23 Q0 22 Q1 21 Q2 20 Q3 19 Q4 18 Q5 17 Q6 16 Q7 15 Q8 14 Q9 VCC = Pin 24 GND = Pin 12 SF01298 FUNCTION TABLE for 74F841 and 74F842 OUTPUTS INPUTS 74F841 OE L L L L H L H= L= h= l= ↓= X= NC= Z= LE H H ↓ ↓ X L Dn L H l h X X Qn L H L H Z NC 74F842 Qn H Transparent Transparent L H Latched L Z NC High Impedance Hold OPERATING MODE HIGH voltage level LOW voltage level HIGH state one set-up time before the HIGH-to-LOW LE transition LOW state one set-up time before the HIGH-to-LOW LE transition HIGH-to-LOW transition Don’t care No change High impedance “off” state 2004 Jan 23 4 Philips Semiconductors Product data 10-bit bus interface latches, non-inverting/inverting (3-State) 74F841/74F842 ABSOLUTE MAXIMUM RATINGS Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range. SYMBOL VCC VIN IIN VOUT IOUT Tamb Tstg supply voltage input voltage input current voltage applied to output in HIGH output state current applied to output in LOW output state operating free-air temperature range storage temperature range PARAMETER RATING –0.5 to +7.0 –0.5 to +7.0 –30 to +5 –0.5 to VCC 84 0 to +70 –65 to +150 UNIT V V mA V mA °C °C RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL VCC VIH VIL IIK IOH IOL Tamb supply voltage HIGH-level input voltage LOW-level input voltage input clamp current HIGH-level output current LOW-level output current operating free-air temperature range PARAMETER MIN 4.5 2.0 – – – – 0 NOM 5.0 – – – – – – MAX 5.5 – 0.8 –18 –24 48 +70 V V V mA mA mA °C UNIT 2004 Jan 23 5 Philips Semiconductors Product data 10-bit bus interface latches, non-inverting/inverting (3-State) 74F841/74F842 DC ELECTRICAL CHARACTERISTICS Over recommended operating free-air temperature range unless otherwise noted. SYMBOL PARAMETER TEST CONDITIONS1 CONDITIONS MIN IO = –15 mA mA OH ± 10%VCC ± 5%VCC ± 10%VCC ± 5%VCC ± 10%VCC ± 5%VCC 2.2 2.2 2.0 2.0 – – – – – – – – –100 – VCC = MAX – – – VCC = MAX – – LIMITS TYP2 – 3.3 – – 0.38 0.38 –0.73 – – – – – – 50 60 70 40 65 60 UNIT MAX – – – – 0.55 0.55 –1.2 100 20 –20 50 –50 –225 65 80 92 60 90 90 V V V V V V V µA µA µA µA µA mA mA mA mA mA mA mA VO OH HIGH-level output voltage level output voltage VCC = MIN; VIL = MAX; MAX; VIH = MIN IO = –24 mA mA OH IOL = 32 mA IOL = 48 mA VCC = MIN; II = IIK VO OL VIK II IIH IIL IOZH IOZL IOS LOW-level output voltage level output voltage Input clamp voltage Input current at maximum input voltage HIGH-level input current LOW-level input current Off-state output current, HIGH-level voltage applied Off-state output current, LOW-level voltage applied Short-circuit output current3 ICCH 74F841 ICCL ICCZ ICCH 74F842 ICCL ICCZ VCC = MIN; VIL = MAX; MAX; VIH = MIN VCC = 0 V; VI = 7.0 V VCC = MAX; VI = 2.7 V VCC = MAX; VI = 0.5 V VCC = MAX; VO = 2.7 V VCC = MAX; VO = 0.5 V VCC = MAX ICC Supply current y (total) NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5 V, Tamb = 25 °C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a HIGH output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter test, IOS tests should be performed last. 2004 Jan 23 6 Philips Semiconductors Product data 10-bit bus interface latches, non-inverting/inverting (3-State) 74F841/74F842 AC ELECTRICAL CHARACTERISTICS for 74F841/74F842 LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25 °C VCC = +5.0 V CL = 50 pF; RL = 500 Ω MIN tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation delay Dn to Qn 74F841 Propagation delay LE to Qn Propagation delay Dn to Qn 74F842 74F842 Propagation delay LE to Qn Output enable time HIGH or LOW-level OE to Qn or Qn Output disable time HIGH or LOW-level OE to Qn or Qn Waveform 1, 2 Waveform 4 Waveform 5 Waveform 4 Waveform 5 5.0 4.5 2.5 4.0 1.0 1.0 7.0 6.5 4.5 6.0 4.5 5.0 10.0 9.0 8.0 9.5 8.0 8.0 3.0 3.0 2.0 3.0 1.0 1.0 10.5 9.5 8.5 10.5 8.5 8.5 ns ns ns Waveform 1, 2 Waveform 1, 2 4.5 4.0 3.5 3.0 6.5 6.0 5.5 5.0 9.5 9.0 8.5 8.0 4.0 3.5 4.5 4.0 10.0 9.5 9.0 8.5 ns ns Waveform 1, 2 2.0 2.5 TYP 4.0 4.5 MAX 7.5 7.5 Tamb = 0 °C to +70 °C VCC = +5.0 V ± 10% CL = 50 pF; RL = 500 Ω MIN 2.0 2.5 MAX 8.0 8.0 ns UNIT AC SET-UP REQUIREMENTS for 74F841/74F842 LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25 °C VCC = +5.0 V CL = 50 pF; RL = 500 Ω MIN ts(H) ts(L) th(H) th(L) tw(H) th(H) th(L) tw(H) Set-up time, HIGH or LOW Dn to LE Hold time, HIGH or LOW Dn to LE LE pulse width, HIGH Hold time, HIGH or LOW Dn to LE LE pulse width, HIGH 74F842 Waveform 3 74F841 Waveform 3 Waveform 3 Waveform 3 Waveform 3 0.0 0.0 2.5 3.0 3.5 3.0 3.5 3.0 TYP – – – – – – – – Tamb = 0 °C to +70 °C VCC = +5.0 V ± 10% CL = 50 pF; RL = 500 Ω MIN 1.0 1.0 3.0 4.0 4.0 3.5 4.5 3.0 MAX – – – – – – – – ns ns ns ns ns UNIT 2004 Jan 23 7 Philips Semiconductors Product data 10-bit bus interface latches, non-inverting/inverting (3-State) 74F841/74F842 AC WAVEFORMS For all waveforms, VM = 1.5 V. The shaded areas indicate when the input is permitted to change for predictable output performance. Dn, LE VM tPLH Qn VM VM tPHL VM Qn Dn, LE VM tPHL VM VM tPLH VM SF01303 SF01304 Waveform 1. Propagation delay, non-inverting path Waveform 2. Propagation delay, inverting path Dn VM ts(H) VM th(H) VM ts(L) VM th(L) LE VM VM tw(H) VM SF01306 Waveform 3. Data set-up and hold times OEn VM tPZH VM tPHZ VM 0V VOH – 0.3 V OEn VM tPZL VM tPLZ VM VOL + 0.3 V 3.5V Qn, Qn Qn, Qn SF00509 SF00510 Waveform 4. 3-State Output Enable time to HIGH level and Output Disable time from HIGH level Waveform 5. 3-State Output Enable time to LOW level and Output Disable time from LOW level 2004 Jan 23 8 Philips Semiconductors Product data 10-bit bus interface latches, non-inverting/inverting (3-State) 74F841/74F842 TEST CIRCUIT AND WAVEFORMS VCC 7.0 V VIN PULSE GENERATOR RT D.U.T. VOUT RL NEGATIVE PULSE 90% VM 10% tTHL (tf ) CL RL tTLH (tr ) 90% POSITIVE PULSE 10% tTHL (tf ) AMP (V) 90% VM tw 10% 0V tw VM 10% tTLH (tr ) 0V AMP (V) 90% Test Circuit for 3-State Outputs SWITCH POSITION TEST tPLZ tPZL All other SWITCH closed closed open VM Input Pulse Definition DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators. INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0 V 1.5 V rep. rate 1 MHz tw tTLH tTHL 2.5 ns SF00777 500 ns 2.5 ns 2004 Jan 23 9 Philips Semiconductors Product data 10-bit bus interface latches, non-inverting/inverting (3-State) 74F841/74F842 DIP24: plastic dual in-line package; 24 leads (300 mil) SOT222-1 2004 Jan 23 10 Philips Semiconductors Product data 10-bit bus interface latches, non-inverting/inverting (3-State) 74F841/74F842 SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 2004 Jan 23 11 Philips Semiconductors Product data 10-bit bus interface latches, non-inverting/inverting (3-State) 74F841/74F842 REVISION HISTORY Rev _4 Date 20040123 Description Product data (9397 750 12746). ECN 853-1208 A15379 of 22 January 2004. Replaces Product specification 74F841/842/843/845/846_3 dated 1999 Jun 23 (9397 750 06143). Modifications: • Delete all references to 74F843, 74F845, 74F846 (products discontinued). _3 19990623 Product specification (9397 750 06143). ECN 853-1208 21851 of 23 June 1999. Replaces datasheet 74F841/842/843/844/845/846 of 1999 Jan 08. Data sheet status Level I Data sheet status [1] Objective data Product status [2] [3] Development Definitions This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). II Preliminary data Qualification III Product data Production [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 © Koninklijke Philips Electronics N.V. 2004 All rights reserved. Printed in U.S.A. Date of release: 01-04 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. Document order number: 9397 750 12746 Philips Semiconductors 2004 Jan 23 12