NE5241N

Philips Semiconductors Product specification Dolby ADM digital audio decoder NE5241 DESCRIPTION The NE5241 is a complete stereo digital to audio converter for the Dolby ADM digital audio system, which allows CD quality stereo audio to be delivered with data rates on the order of 400 to 600kb/s. The NE5241 is intended for use in high quality consumer digital audio equipment for the reproduction of broadcast (or pre-recorded) digital audio. The IC contains channel de-multiplexing data input latches, control signal filter drivers and buffers, variable gain integrators, and variable de-emphasis filters. Precision, temperature compensated voltage reference circuitry assures accurate performance over temperature. The IC is implemented in a bipolar process to achieve low noise, low distortion, and wide dynamic range. The NE5241 is an improved version of the NE5240, which has been discontinued. Note: The NE5241 is available only to licensees of Dolby Laboratories Licensing Corporation, from who licensing and applications information must be obtained. Dolby is a registered trademark of Dolby Laboratories Licensing Corporation, San Francisco, California. PIN CONFIGURATION N, D Packages MULTI OUT 1 1 VCC 2 VARZ 1 3 OUT 1 4 FEEDBACK 1 5 INT IN 1 6 EM FILT IN 1 7 EM FILT OUT 1 8 SS FILT IN 1 9 SS FILT OUT 1 10 VDD 11 SS 12 AD 13 28 MULTI OUT 2 27 AGND 26 VARZ 2 25 OUT 2 24 FEEDBACK 2 23 INT IN 2 22 EM FILT IN 2 21 EM FILT OUT 2 20 SS FILT IN 2 19 SS FILT OUT 2 18 DGND 17 REX 16 VREF 15 CK TOP VIEW APPLICATIONS EM 14 • High quality digital audio transmission systems • Pre-recorded digital audio • Satellite delivered digital audio • Cable TV delivered digital audio • Microwave delivered digital audio • Terrestrial delivered digital audio • Digital audio for advanced television sound SR01021 Figure 1. Pin Configuration FEATURES • Wide dynamic range: >95dB • Low distortion: 20kHz • Complete decoder implementation in one IChip ORDERING INFORMATION DESCRIPTION 28-Pin Plastic Dual In-Line Package (DIP) 28-Pin Small Outline Large (SOL) Package TEMPERATURE RANGE 0 to +70°C 0 to +70°C ORDER CODE NE5241N NE5241D DWG # SOT117-2 SOT136-1 ABSOLUTE MAXIMUM RATINGS SYMBOL VCC VDD TA TSTG TJ TSOLD θJA Analog supply voltage Logic supply voltage Operating ambient temperature range Storage temperature range Junction temperature Lead temperature (soldering 60 sec) Thermal impedance N package D package 48 70 °C/W °C/W PARAMETER RATING +15 +7 0 to +70 –65 to +150 –65 to +150 +300 UNIT V V °C °C °C °C March 19, 1992 1 853-1602 06126 Philips Semiconductors Product specification Dolby ADM digital audio decoder NE5241 PIN DESCRIPTIONS PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 SYMBOL MULTI OUT 1 VCC VARZ 1 OUT 1 FEEDBACK 1 INT IN 1 EM FILTER IN 1 EM FILTER OUT 1 SS FILTER IN 1 SS FILTER OUT 1 VDD SS AD EM CK VREF REX DGND SS FILTER OUT 2 SS FILTER IN 2 EM FILTER OUT 2 EM FILTER IN 2 INT IN 2 FEEDBACK 2 OUT 2 VARZ 2 AGND MULT OUT 2 Multiplier output, channel 1 Analog supply voltage Variable impedance, channel 1 Main output, channel 1 Summing amp input, channel 1 Integrator amp input, channel 1 Emphasis filter buffer input, channel 1 Emphasis filter driver output, channel 1 Step-size filter buffer input, channel 1 Step-size filter driver output, channel 1 Logic supply voltage Step-size data input Audio data input Emphasis data input Data clock input Reference voltage bypass Variable impedance reference resistor Digital ground Step-size filter driver output, channel 2 Step-size filter buffer input, channel 2 Emphasis filter driver output, channel 2 Emphasis filter buffer input, channel 2 Integrator amp input, channel 2 Summing amp input, channel 2 Main output, channel 2 Variable impedance, channel 2 Analog ground Multiplier output, channel 2 DESCRIPTION March 19, 1992 2 Philips Semiconductors Product specification Dolby ADM digital audio decoder NE5241 DC ELECTRICAL CHARACTERISTICS All specifications are at TA=25°C, VDD=5V, VCC=12V. Test circuit Figure 1. SYMBOL VCC VDD ICC IDD VIH VIL IIH IIL tS tH IB PARAMETER Analog supply voltage Digital supply voltage Analog supply current Digital supply current HIGH level input voltage LOW level input voltage HIGH level input current LOW level input current Data setup time Data hold time Control signal buffer bias current Integrating amp gain Pins SS, AD, EM Pins SS, AD, EM = 2V Pins SS, AD, EM = 0.8V 150 150 10 22 30 1 1 2.0 0.8 10 5 TEST CONDITIONS LIMITS Min 10.8 4.7 Typ 12 5 25 12 Max 13.2 5.3 40 20 UNIT V V mA mA V V µA µA ns ns nA dB AC ELECTRICAL CHARACTERISTICS All specifications are at TA=25°C, VDD=5V, VCC=12V, Audio data rate = 204kHz. 0dB is defined as 0.775VRMS. Test circuit Figure 4. SYMBOL PARAMETER Output voltage (reference level)1 Channel balance (reference level)1 Channel balance change2 Channel balance change2 Step-size tracking Headroom4 Noise5 Noise5 Mute noise6 Dynamic range7 THD THD Total harmonic distortion1 Total harmonic distortion8 Variable de-emph calibration Freq. response error Freq. response error Freq. response error Dynamic offset, emphasis10 Dynamic offset, step-size11 Channel separation error9 0dB (ref level) +13dB (max level) 8kHz EM = 40% 2kHz EM = 10% 12kHz EM = 60% 15kHz EM = 70% AC measurement AC measurement 1kHz –1 –1.8 –2.3 –2.5 20Hz – 20kHz CCIR/ARM CCIR/ARM error3 Step-size tracking error3 20% < SS < 80% 10% < SS < 90% 20% < SS < 80% 10% < SS < 90% 13 –80 –89 –93 98 0.8 0.13 0.2 0.2 0.25 0.5 –43 –39 75 0.2 0.5 1 1.5 2.3 2.5 –30 –24 % % dB dB dB dB dB dB dB –78 –85 –88 dBu dBu dBu TEST CONDITIONS LIMITS Min –6 Typ –4.5 0.2 0.2 0.4 0.5 1.0 Max –2.5 1.2 1.0 1.5 3.0 4.0 UNIT dBu dB dB dB dB dB NOTES: Test patterns referred to are produced by the Dolby Cat. No. 346 ADM Test Data Generator. 1. Dolby ADM reference level, Dolby test pattern 00. This is 10dB below the nominal 100% modulation level. 2. The channel balance may change over the operating range. This specification is the channel balance change from the intial channel balance which was measured at reference level. 3. The gain should change by 36.12dB as the step-size data is changed from 20% to 80% duty cycle, or 48.16dB as the data changes from 10% to 90%. The tracking error is the amount by which the gain change deviates from the desired value. 4. This is headroom over Dolby ADM reference level. 5. Idling data patterns, Dolby test pattern 02 with respect to test 01. 6. Muted data patterns, Dolby test pattern 04. 7. Difference between output voltage plus headroom, and CCIR/ARM weighted mute noise level. 8. Test level is 13dB over Dolby ADM reference level. Dolby test pattern 08. 9. Measured at 8.00kHz, with emphasis data at 40% duty cycle. This may be trimmed to zero by adjusting the resistor at Pin 17. 10. Dolby test pattern 48 relative to test 00. Duty cycle alternates from 10 to 70%. 11. Dolby test pattern 49 relative to test 00. Duty cycle alternates from 10 to 70%. March 19, 1992 3 Philips Semiconductors Product specification Dolby ADM digital audio decoder NE5241 APPLICATIONS INFORMATION The application diagram shows the complete Dolby ADM decoder using the NE5241. The decoder is followed by a line driving amplifier, which, depending on the application, may not be necessary. For best frequency response accuracy, the following parts should be tight tolerance: R13 to R21 should be 1%, and C13 to C20 should be 2.5%. The variable de-emphasis pole position may be trimmed by adjusting the value of R17. The variable impedance Pins 3 and 26 are very sensitive to noise pickup. Keep the lead to C15 and C18 as short as possible. Excessive stray capacitance on the multiplier output, Pins 1 and 28, will adversely affect performance. Keep the leads to R13 and R19 short. It is desirable to place a ground plane under the NE5241. This reduces the inevitable cross-talk of the digital data (with several volts of swing) into the audio (which has a noise level on the order of 40µV). A ground plane is necessary to obtain the ultimate in noise performance. The timing diagram illustrates how the data is clocked into the NE5241. The two audio channels share the three data input lines: audio data, step-size data, and emphasis data. During the low-to-high clock transition, the data is clocked into channel 1. During the high-to-low clock transition, the data is clocked into channel 2. The data must be stable during the clock transition. TIMING DIAGRAM CLOCK tS tH AUDIO DATA STEP-SIZE DATA EMPHASIS DATA CH 1 CH 2 CH 1 CH 2 CH 1 SR01022 Figure 2. Timing Diagram March 19, 1992 4 Philips Semiconductors Product specification Dolby ADM digital audio decoder NE5241 BLOCK DIAGRAM AND TEST CIRCUIT R1 4.3k C1 0.47µF R4 4.3k VDD 11 C4 0.47µF 10 8 R5 43k C5 47nF R2 43k R3 360k C2 47nF R6 360k C6 4.7nF 7 9 1 6 INTEGRATOR AMP 22dB VDD SSD 12 NE5241 3 13 2 REFERENCE GENERATOR REX VH VR VL AGND CK 15 26 eX SUMMING AMP INTEGRATOR AMP + – 25 R18 6.34k C18 220pF VREF 17 16 27 220µF C17 R17 118k VCC eX 14dB 5 C3 4.7nF R13 4.99k C13 0.1µF R15 4.87k R14 499k C14 10nF SUMMING AMP – + 4 R16 VOUT 6.34k CH.A C15 220pF C16 3.9nF AD SBD 14 INPUT LOGIC DGND VOUT CH.B C19 3.9nF 18 19 21 22 20 28 23 24 NOTE: One channel of the application shown with external components. SR01023 Figure 3. Block Diagram and Test Circuit March 19, 1992 5 Philips Semiconductors Product specification Dolby ADM digital audio decoder NE5241 DOLBY ADM DECODER R1 4.3k C1 0.47µF R4 4.3k C4 0.47µF DATA INPUT IC 10 8 R5 43k C5 47nF R2 43k R3 360k C2 47nF R6 360k C6 4.7nF 7 9 MULT OUT 1 INT FEED– IN 1 BACK 1 6.3k 4 OUT 1 3 C15 220pF + C16 3.9nF 22µF R26 22k R13 4.99k EM SS FILTER IN 1 0.1µF C3 4.7nF LINE DRIVE AMPLIFIER R14 499 C14 10nF R15 4.87k – 1nF R22 1k R24 100 C24 CH 1 OUT STEP-SIZE DATA AUDIO DATA EMPHASIS DATA DATA CLOCK 12VDC 5VDC SS EM FILTER 12 SS OUT 1 13 AD 14 EM 15 CK 2 11 27 18 17 R17 118k VCC VDD AGND DGND REX FILTER OUT 2 SS EM 19 21 R10 4.3k C10 0.47µF R7 4.3k C7 0.47µF R11 43k C11 47nF R8 43k R12 360k C12 4.7nF R9 360k C8 47nF VARZ NE5241 16 100µF VARZ C18 220pF FILTER IN 2 EM SS 22 20 OUT 2 MULT OUT 2 28 R19 4.99k INT FEED– IN 2 BACK 2 23 24 2 6.3k C18 3.9nF + 4.87k 1nF 0.1µF R21 499 10nF R23 1k – R25 100 C26 22µF CH 2 OUT R27 22k C9 4.7nF SR01024 Figure 4. NE5241 Application Circuit March 19, 1992 6