NE56610-42GW

NE56610/11/12 Series System Reset Rev 0 February, 2001 Preliminary Product Specification General Description The NE56610/11/12 series is a family of devices designed to generate a reset signal for a variety of microprocessor and logic systems. Accurate reset signals are generated during momentary power interruptions or when ever power supply voltages sag to intolerable levels. The NE56610/11/12 incorporates an internal timer to provide reset delay and ensure proper operating voltage has been attained. In addition, a manual reset pin is available. An Open Collector output topology is incorporated to provide adaptability for a wide variety of logic and microprocessor systems. NE56610/11/12 is available in the TSSOP5 surface mount package. M/R SUB GND 1 2 3 4 5 VCC VOUT TSSOP5 Features • 12V DC Maximum Operating Voltage • Low Operating Voltage (0.65 V) • Internal Reset Delay Timer • NE56610 (50 mS Typical) • NE56611 (100mS Typical) • NE56612 (200mS Typical) • Offered in Reset Thresholds of 2.0, 2.7, 2.8, 2.9, 3.0, 3.1, 4.2, 4.3, 4.4, 4.5, 4.7 V DC • Available in SSOP5 Surface Mount Package • Manual Reset Input Applications • Micro-Computer Systems • Logic Systems • Battery Monitoring Systems • Back-Up Power Supply Circuits • Voltage Detection Circuits • Mechanical Reset Circuits Simplified Device Diagram VCC 5 NE56610/11/12 4 VOUT Reset Delay + GND M/R 3 VREF 1 2 SUB Ordering Information Description 5-pin SOT23 (TSSOP5) plastic surface mount System Reset (100mS Typical Internal Reset Delay) System Reset (200mS Typical Internal Reset Delay) Temperature Range -20 - +75 °C -20 - +75 °C -20 - +75 °C Order Code NE56610-xxGW NE56611-xxGW NE56612-xxGW DWG# TSSOP5 TSSOP5 TSSOP5 Note: Each device has 6 (six) detection voltage options, indicated by the -xx on the order code: XX -25 -27 -29 Detect Voltage (Typ.) 2.5 2.7 2.9 XX -39 -42 -45 Detect Voltage (Typ.) 3.9 4.2 4.5 Philips Semiconductors NE56610/11/12 Series System Reset Pin Designation and Description Pin Designation 1 2 3 4 5 Pin No 1 2 3 4 5 Pin Name M/R SUB GND VOUT VCC Function Manual Reset input. Connect to ground when not using. Substrate Pin. Connect to ground. Ground Reset High Output pin Positive Power Supply Input Maximum Ratings Parameter Storage Temperature Range Ambient Operating Temperature Range Power Supply Voltage Manual Reset Input Voltage Power Dissipation Symbol TSTG TA VCC max. VRES max Pd Rating -40 - +125 -20 - +75 -0.3 - +12 -0.3 - +12 150 Unit °C °C V V mW Recommended Operating Conditions Parameter Ambient Operating Temperature Range Power Supply Voltage Symbol TA VCC max. Rating -20 - +75 -0.3 - +12 Unit °C V February 23, 2001 2 of 9 document number here Philips Semiconductors NE56610/11/12 Series System Reset DC ELECTRICAL CHARACTERISTICS TA = 25°C, unless otherwise specified. Note 1: Unless otherwise stated, M/R pin should always be connected to ground. Parameter Threshold Detection VCC Falling RL = 470Ω, VOL ≤ 0.4V Symbol VS Test Circuit 1 Part# -45 -42 -39 -29 -27 -25 All Min 4.3 4.0 3.7 2.75 2.55 2.35 30 Typ 4.5 4.2 3.9 2.90 2.70 2.50 50 Max 4.7 4.4 4.1 3.05 2.85 2.65 100 Unit V Hysteresis Voltage VCC = Rising then Falling (∆VS = VSH-VSL) RL = 470Ω Threshold Temperature Coefficient RL = 470Ω, TA = -20°C - +75°C Low-level Output Voltage VCC = VS min. -0.05V, RL = 470Ω Output Leakage Current VCC = 10V Circuit ON Current VCC = VS min. -0.05V, RL = ∞ Circuit OFF Current VCC = VS typ./0.85V, RL = ∞ Reset Delay Time High (see note 1) RL = 4.7kΩ CL = 100pF Reset Delay Time Low (see note 2) RL = 4.7kΩ, CL = 100pF Operating Supply Voltage RL = 4.7kΩ, VOL ≤ 0.4V Output ON Current 1 VCC = VS min. -0.05V, RL = 0 Output On Current 2 VCC = VS min. -0.05V, RL = 0 TA = -20°C - +75°C M/R Threshold High M/R Threshold High VM/RH = 2.0v M/R Threshold Low ∆VS 1 mV TC / V S VOL IOH ICCL ICCH TDLH 1 1 1 1 1 2 All All All All All NE56610 NE56611 NE56612 All All All All 8 6 30 60 120 ±0.01 0.1 0.4 ±0.1 300 15 50 100 200 20 0.65 500 25 75 150 300 % / °C V µA µA µA mS TPHL VOPL IOL1 IOL2 2 1 1 1 mS 0.85 V mA mA VM/RH IM/RH VM/RL All All All 2.0 10 -0.3 60 0.8 V µA V NOTES: 2. TDLH measured with VCC = (VS typ. -0.4V) and abruptly transitioning to (VS typ. +0.4)V. TDLH is duration from VCC transition high to output transition high. 3. TDHL measured with VCC ≥ (VS typ. +0.4V) and abruptly transitioning to (VS typ. -0.4)V. TDHL is duration from VCC transition low to output transition low. 4. Ramp M/R voltage until Output Reset goes low. February 23, 2001 3 of 9 document number here Philips Semiconductors NE56610/11/12 Series System Reset Typical Performance Curves Figure 1. Normalized Detection versus Temperature 0.10 Figure 2. Circuit ON Current versus Temperature 500 VS, NORMALIZED DETECTION (V) ICCL, CIRCUIT ON CURRENT (µA) 0.05 Threshold Normalized to 25°C RL (Pull-Up to VCC) 470Ω VOL ≤ 0.4V VCC = VS min. -0.05V RL = ∞ 400 0.00 300 -0.05 200 -0.10 -50 -25 0 25 50 75 100 125 100 -50 -25 0 25 50 75 100 125 TA, TEMPERATURE (°C) Figure 3.Detection Hysteresis versus Temperature 80 ∆VS, DETECTION HYSTERESIS (mV) ∆VS = VSH - VSL RL (Pull-Up to VCC) = 470Ω TA, TEMPERATURE (°C) Figure 4. Circuit OFF Current versus Temperature 30 ICCH, CIRCUIT OFF CURRENT (µA) VCC = VS typ. +0.85V RL = ∞ 25 70 60 20 50 15 40 -50 -25 0 25 50 75 100 125 10 -50 -25 0 25 50 75 100 125 TA, TEMPERATURE (°C) Figure 5. Low-Level Output Voltage versus Temperature 120 TA, TEMPERATURE (°C) Figure 6. Operating Supply Voltage versus Temperature 900 VOL, LOW-LEVEL OUTPUT (mV) VOPL, OPERATING SUPPLY (mV) VCC = VS min. -0.05V RL (Pull-Up to VCC) 470Ω 100 800 700 VOL ≤ 0.4V RL4.7kΩ 80 600 500 400 -50 60 40 -50 -25 0 25 50 75 100 125 -25 0 25 50 75 100 125 TA, TEMPERATURE (°C) TA, TEMPERATURE (°C) February 23, 2001 4 of 9 document number here Philips Semiconductors NE56610/11/12 Series System Reset Typical Performance Curves (continued) Figure 7. Output ON Current versus Temperature 70 Figure 8. M/R Input High Current versus Temperature IM/RH, M/R INPUT HIGH CURRENT (µA) 25 VCC = 5.0V VM/RH = 2.0V 20 IOL, OUTPUT ON CURRENT (µA) VCC = VS min. -0.05V RL = 0 60 50 15 40 10 30 -50 -25 0 25 50 75 100 125 5.0 -50 -25 0 25 50 75 100 125 TA, TEMPERATURE (°C) Figure 9. Reset Delay Time High versus Temperature tDLH, RESET DELAY TIME HIGH (mS) 250 TA, TEMPERATURE (°C) Figure 10. M/R Threshold High versus Temperature 1.6 VM/RH, M/R THRESHOLD HIGH (V) 225 200 175 150 125 100 75 50 25 -50 -25 0 25 50 75 100 125 SA56610 SA56612 VCC = 5.0V 1.4 1.2 RL4.7kΩ CL = 100pF SA56611 1.0 0.8 0.6 -50 -25 0 25 50 75 100 125 TA, TEMPERATURE (°C) Figure 11. Reset Delay Time Low versus Temperature 14 RL4.7kΩ CL = 100pF tDHL, RESET DELAY TIME LOW (µS) 13 TA, TEMPERATURE (°C) Figure 12. Icc and Vout versus Supply Voltage 500 5.0 4.0 400 300 12 ICC 200 100 0 0 1.0 2.0 ∆VS 3.0 2.0 1.0 0 11 10 -50 -25 0 25 50 75 100 125 3.0 4.0 5.0 TA, TEMPERATURE (°C) VCC, SUPPLY VOLTAGE (V) February 23, 2001 5 of 9 document number here VOUT, OUTPUT VOLTAGE (V) ICC, SUPPLY CURRENT (µA) RL = 470Ω TA = 25°C VOUT Philips Semiconductors NE56610/11/12 Series System Reset Typical Performance Curves (continued) Figure 13. Output Sink Current versus Output Voltage IOUT, OUTPUT SINK CURRENT (mA) 40 35 30 25 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1.0 VCC = VS min. -0.05V RL = 0 TA = 25°C VOUT, OUTPUT VOLTAGE (V) Technical Discussion Figure 14. Functional Schematic VCC 5 delay OSC T R Q 4 VOUT Reset 3 GND SUB M/R 1 2 February 23, 2001 6 of 9 document number here Philips Semiconductors NE56610/11/12 Series System Reset TIMING DIAGRAM The Timing Diagram shown in Figure 15 depicts the operation of the device. Letters indicate events on the Time axis. A: At start-up, event "A", the VCC and Reset voltages begin to rise. Also the Reset voltage initially rises but then abruptly returns to a low state. This is due to VCC reaching the level (approximately 0.8V) that activates the internal bias circuitry. B: At event "B", the "H" transport delay time (TPLH) is initiated. This is caused by and coincident to VCC reaching the threshold level of VSH. At this level the device is in full operation. The Reset output remains off as VCC rises above VSH. This is normal. C: At event "C" VCC is above the undervoltage detect threshold and the "H" transport delay time (TPLH) has elapsed. At this point the device removes the hold on the VOUT reset. VOUT Reset goes high. In a microprocessor based system these events remove the reset from the microprocessor, allowing it to function normally. D-E: At "D", VCC begins to ramp down causing VOUT to follow it. VCC continues to sag until the VSL undervoltage threshold is reached at "E". At that time, reset signal is generated (VOUT Reset goes low). E-F: Between "E" and "F", VCC recovers and starts increasing. F: At "F", VCC reaches the VSH upper threshold. Once again, the "H" transport delay time (TPLH) is initiated. G: At "G", VCC is above the undervoltage detect threshold and the "H" transport delay time (TPLH) has elapsed. At this point the device removes the hold on the VOUT reset. VOUT Reset goes high. H-J: At event "H", VCC is normal, but a manual reset signal from the logic device is applied at the M/R pin. With the falling edge of the manual reset signal, the "H" transport delay time (TPLH) is initiated. At "J", transport delay time (TPLH) has elapsed and the Vout reset goes high. K: At event "K" VCC sags to the point where the VSL undervoltage threshold point is reached and at that level VOUT reset goes low. L: At event "L" the VCC voltage has deteriorated to a level where normal internal circuit bias is no longer able to maintain a VOUT reset and as a result may exhibit a slight rise to something less than 0.8V. As VCC decays even further, VOUT reset also decreases to zero. Figure 15. Timing Diagram V VSH VSL VS VCC B C D F H K L ∆VS V VOUT TPLH TPLH TPLH A V M/R B C E G J K L VRES H TIME February 23, 2001 7 of 9 document number here Philips Semiconductors NE56610/11/12 Series System Reset Application Information When the manual reset is not needed, the M/R, manual reset pin is connected to ground as shown in Figure 16 - Typical Hard Reset Circuit. A capacitor connected from VCC to ground is recommended when the VCC supply impedance is appreciably high. This may be the situation with a poor quality or aged battery. Figure 16. Typical Hard Reset Circuit To VCC RL 5 VCC 4 VOUT To CPU Reset Pin The second example, shown in Figure 17 - Manual Reset Circuit, incorporates a manual reset switch from the M/R pin to VCC. When the manual switch is closed, VOUT reset is logic high. Conversely, when it is opened, VOUT reset is logic low. As a precaution a clamp diode is placed from the M/R pin to ground to insure that the pin does not go below - 0.3V. Figure 17. Manual Reset Circuit To VCC RL Manual Switch 5 VCC 4 VOUT To CPU Reset Pin M/R SUB GND 1 2 3 Clamp Diode M/R SUB GND 1 2 3 Test Circuits Figure 16. Test Circuit 1 A2 RL A1 10µF / 10V Figure 17. Test Circuit 2 5 5 4 4 RL VCC VCC V1 VRES VOUT V2 VCC Input Pulse VOUT 10µF / 10V M/R SUB GND 1 2 3 M/R SUB GND 1 2 3 CRT 5.0 V CL = 100pF CRT = Oscilliscope A - DC Ammeter V = DC Voltmeter Input Pulse VS typ +0.4V VS typ -0.4V 0V February 23, 2001 8 of 9 document number here Philips Semiconductors NE56610/11/12 Series System Reset Packing Method The NE56610/11/12 is packed in reels, as shown here Guard Band Tape Detail Tape Reel Assembly Cover Tape Carrier Tape Barcode Label Box LEGAL DISCLAIMER GOES HERE February 23, 2001 9 of 9 document number here