NE56632-42D

INTEGRATED CIRCUITS NE56632-XX Active-LOW system reset with adjustable delay time Product data 2002 Mar 25 Philips Semiconductors Philips Semiconductors Product data Active-LOW system reset with adjustable delay time NE56632-XX DESCRIPTION The NE56632-XX is a family of Active-LOW, power-on reset that offers precision threshold voltage detection within ±1.5% and super low operating supply current of typically 3.0 µA. It includes a reset delay that is user adjustable with an external capacitor. Several detection threshold voltages are available at 1.9V , 2.0 V, 2.7 V, 2.8 V, 2.9 V, 3.0 V, 3.1 V, 4.2 V, 4.3 V, 4.4 V, 4.5 V, and 4.6 V. Other thresholds are offered upon request at 100 mV steps from 1.9 V to 4.6 V. With its ultra low supply current and high precision voltage threshold detection capability, the NE56632-XX is well suited for various battery powered applications such as reset circuits for logic and microprocessors, voltage check, and level detecting. It is available in the SOT23-5 package. FEATURES • High precision threshold detection voltage: VS ±1.5% • Super low operating supply current: 3 µA typ. • Built-in hysteresis voltage: 50 mV typ. • Detection threshold voltage: 1.9 V, 2.0 V, 2.7 V, 2.8 V, 2.9 V, 3.0 V, 3.1 V, 4.2 V, 4.3 V, 4.4 V, 4.5 V, and 4.6 V. APPLICATIONS • Reset for microprocessor and logic circuits • Voltage level detection circuit • Battery voltage check circuit • Detection circuit for battery back-up • Reset Output: Active-LOW, open collector • Other detection threshold voltages available upon request at 100 mV steps from 1.9 V to 4.6 V. • Large low reset output current: 30 mA typ. • Power-on reset delay time adjustable with external capacitor: 200 µs to 200 ms • Reset assertion with VCC down to 0.65 V SIMPLIFIED SYSTEM DIAGRAM TO VCC RPU TO RESET TERMINAL OF CPU 4 5 NE56632-XX 1 2 3 CD SL01605 Figure 1. Simplified system diagram. 2002 Mar 25 2 853–2329 27919 Philips Semiconductors Product data Active-LOW system reset with adjustable delay time NE56632-XX ORDERING INFORMATION TYPE NUMBER NUMBER NE56632-XXD PACKAGE NAME SOT23-5 / SOT25 (SO5) DESCRIPTION plastic small outline package; 5 leads (see dimensional drawing) TEMPERATURE RANGE –20 to +75 °C NOTE: The device has 12 voltage output options, indicated by the XX on the ‘Type number’. XX 19 20 27 28 29 30 31 42 43 44 45 46 VOLTAGE (Typical) 1.9 V 2.0 V 2.7 V 2.8 V 2.9 V 3.0 V 3.1 V 4.2 V 4.3 V 4.4 V 4.5 V 4.6 V Part number marking The package is marked with a four letter code. The first three letters designate the product. The fourth letter, represented by ‘x’, is a date tracking code. Part Number NE56632-19D NE56632-20D NE56632-27D NE56632-28D NE56632-29D NE56632-30D NE56632-31D NE56632-42D NE56632-43D NE56632-44D NE56632-45D NE56632-46D Marking AKZx ALAx ALBx ALCx ALDx ALEx ALFx ALGx ALHx ALJx ALKx ALLx PIN CONFIGURATION PIN DESCRIPTION PIN SYMBOL TC SUB GND VOUT VCC DESCRIPTION Delay time control; set with external capacitor. Substrate. Connect to ground (GND). Ground. Negative supply. Reset output voltage. Active-LOW. Positive supply voltage; detection threshold voltage input. 1 2 3 TC 1 5 VCC SUB 2 NE56632-XX GND 3 4 VOUT 4 5 SL01604 Figure 2. Pin configuration. MAXIMUM RATINGS SYMBOL VCC Tamb Tstg P Supply voltage Ambient operating temperature Storage temperature Power dissipation PARAMETER MIN. –0.3 –20 –40 – MAX. +10 +75 +125 150 UNIT V °C °C mW 2002 Mar 25 3 Philips Semiconductors Product data Active-LOW system reset with adjustable delay time NE56632-XX ELECTRICAL CHARACTERISTICS Tamb = 25 °C, unless otherwise specified. SYMBOL VS PARAMETER Detection threshold CONDITIONS VCC = HIGH-to-LOW; RL = 4.7 kΩ; S1=ON; VOL ≤ 0.4 V; Test Circuit 1 (Figure 27) Circuit Figure 27) -XX 46 45 44 43 42 31 30 29 28 27 20 19 Vhys VS/∆T VOL ILO ICCL ICCH tPLH tPHL VOPL IOL1 IOL2 Hysteresis voltage Detection threshold voltage temperature coefficient LOW-level output voltage Output leakage current Supply current (ON time) Supply current (OFF time) LOW-to-HIGH delay time HIGH-to-LOW delay time Minimum operating threshold voltage Output current (ON Time 1) Output current (ON Time 2) RL = 4.7 kΩ; VCC = LOW-to-HIGH-to-LOW; S1 = ON; Test Circuit 1 (Figure 27) RL = 4.7 kΩ; Tamb = –20 °C to +75 °C; S1 = ON; Test Circuit 1 (Figure 27) VCC1 = VS(min) – 0.05 V; RL = 4.7 kΩ; S1 = ON; Test Circuit 1 (Figure 27) VCC1 = VCC2 = 10 V; S2 = ON; Test Circuit 1 (Figure 27) VCC1 = VS(min) – 0.05 V; RL = ∞; Test Circuit 1 (Figure 27) VCC1 = VS(typ)/0.85; RL = ∞; Test Circuit 1 (Figure 27) CL = 100 pF; RL = 4.7 kΩ; CD = 10 nF (Note 1) CL = 100 pF; RL = 4.7 kΩ; CD = 10 nF (Note 2) RL = 4.7 kΩ; VOL ≤ 0.4 V; S1 = ON; Test Circuit 1 (Figure 27) VO = 0.4 V; RL = 0; VCC1 = VS(min) – 0.05 V; VCC2 = 0.4 V; S2 = ON; Test Circuit 1 (Figure 27) VO = 0.4 V; RL = 0; VCC1 = VS(min) – 0.05 V; Tamb = –20 °C to +75 °C; S2 = ON; Test Circuit 1 (Figure 27) MIN. 4.531 4.432 4.334 4.235 4.137 3.053 2.955 2.856 2.758 2.659 1.970 1.871 25 – – – – – – – – 5 3 TYP. 4.600 4.500 4.400 4.300 4.200 3.100 3.000 2.900 2.800 2.700 2.000 1.900 50 ±0.01 0.2 – 5.0 3.0 (Note 3) (Note 3) 0.65 – – MAX. 4.669 4.568 4.466 4.365 4.263 3.147 3.045 2.944 2.842 2.741 2.030 1.929 100 – 0.4 ±0.1 9.0 5.0 – – 0.80 – – UNIT V V V V V V V V V V V V mV %/°C V µA µA µA ms µs V mA mA NOTES: 1. tPLH: VCC = (VS(typ) – 0.4 V) to (VS(typ) + 0.4 V); tPLH is release delay time (Test Circuit 2, Figure 28). 2. tPHL: VCC = (VS(typ) + 0.4 V) to (VS(typ) – 0.4 V); tPHL is assertion delay time (Test Circuit 2, Figure 28). 3. See Table 1. Table 1. NE56632-XX series typical delay time –XX 46 45 44 43 42 31 30 29 28 27 20 19 tPLH 195 ms 190 ms 185 ms 180 ms 175 ms 120 ms 115 ms 110 ms 105 ms 100 ms 65 ms 60 ms tPHL 140 µs 140 µs 140 µs 140 µs 140 µs 120 µs 120 µs 120 µs 100 µs 100 µs 100 µs 100 µs 2002 Mar 25 4 Philips Semiconductors Product data Active-LOW system reset with adjustable delay time NE56632-XX TYPICAL PERFORMANCE CURVES, NE56632-20 2.0050 Vhys , HYSTERESIS VOLTAGE (mV) VS, DETECTION THRESHOLD (V) 2.0025 2.0000 1.9975 1.9950 1.9925 1.9900 1.9875 1.9850 –40 Test Circuit 1 VCC = HIGH-to-LOW RL = 4.7 kΩ VOL ≤ 0.4 V S1 = ON –20 0 20 40 60 80 100 100 90 80 70 60 50 40 Test Circuit 1 VCC = LOW-to-HIGH-to-LOW RL = 4.7 kΩ S1 = ON –20 0 20 40 60 80 100 30 –40 AMBIENT TEMPERATURE, Tamb (°C) AMBIENT TEMPERATURE, Tamb (°C) SL01620 SL01621 Figure 3. Detection threshold versus temperature. Figure 4. Hysteresis voltage versus temperature. 0.225 VOL, LOW-LEVEL OUTPUT VOLTAGE (V) 0.220 0.215 0.210 0.205 0.200 0.195 0.190 0.185 –40 I CCL , SUPPLY CURRENT (ON time), (µA) 9 8 7 6 5 Test Circuit 1 VCC1 = VS(min) – 0.05 V RL = 4.7 kΩ S1 = ON –20 0 20 40 60 80 100 4 3 –40 Test Circuit 1 VCC1 = VS(min) – 0.05 V RL = ∞ –20 0 20 40 60 80 100 AMBIENT TEMPERATURE, Tamb (°C) AMBIENT TEMPERATURE, Tamb (°C) SL01622 SL01623 Figure 5. LOW-level output voltage versus temperature. Figure 6. Supply current (ON time) versus temperature. VOPL , MIN. OPERATING THRESHOLD VOLTAGE (V) 4.5 I CCH, SUPPLY CURRENT (OFF time), ( µA) 0.9 4.0 0.8 0.7 3.5 0.6 3.0 0.5 Test Circuit 1 RL = 4.7 kΩ VOL ≤ 0.4 V S1 = ON –20 0 20 40 60 80 100 2.5 Test Circuit 1 RL = ∞ VCC1 = VS(typ)/0.85 –20 0 20 40 60 80 100 0.4 2.0 –40 0.3 –40 AMBIENT TEMPERATURE, Tamb (°C) AMBIENT TEMPERATURE, Tamb (°C) SL01624 SL01625 Figure 7. Supply current (OFF time) versus temperature. Figure 8. Min. operating threshold voltage versus temperature. 2002 Mar 25 5 Philips Semiconductors Product data Active-LOW system reset with adjustable delay time NE56632-XX TYPICAL PERFORMANCE CURVES, NE56632-20 (continued) I OL1 , OUTPUT CURRENT (ON Time 1), (mA) 37 tPLH, LOW-to-HIGH DELAY TIME (ms) 100 Test Circuit 2 CL = 100 pF RL = 4.7 kΩ CD = 10 nF 35 90 33 80 31 70 29 27 Test Circuit 1 VCC1 = VS(min) – 0.05 V VCC2 = 0.4 V VO = 0.4 V RL = 0 Ω S2 = ON –20 0 20 40 60 80 100 60 50 VCC = (VS(typ) – 0.4 V) to (VS(typ)+ 0.4 V) 40 –40 tPLH = Release Delay Time –20 0 20 40 60 80 100 25 –40 AMBIENT TEMPERATURE, Tamb (°C) AMBIENT TEMPERATURE, Tamb (°C) SL01626 SL01627 Figure 9. Output current (ON time 1) versus temperature. Figure 10. LOW-to-HIGH delay time versus temperature. 120 tPHL, HIGH-to-LOW DELAY TIME (µs) 115 110 105 100 95 90 85 80 –40 VCC = (VS(typ) + 0.4 V) to (VS(typ)– 0.4 V) tPHL = Assertion Delay Time –20 0 20 40 60 80 100 Test Circuit 2 CL = 100 pF RL = 4.7 kΩ CD = 10 nF AMBIENT TEMPERATURE, Tamb (°C) SL01628 Figure 11. HIGH-to-LOW delay time versus temperature. 2002 Mar 25 6 Philips Semiconductors Product data Active-LOW system reset with adjustable delay time NE56632-XX TYPICAL PERFORMANCE CURVES, NE56632-31 3.11 90 VS, DETECTION THRESHOLD (V) 3.10 Vhys , HYSTERESIS VOLTAGE (mV) 80 70 60 3.09 Test Circuit 1 VCC = HIGH-to-LOW RL = 4.7 kΩ VOL ≤ 0.4 V S1 = ON 3.08 –40 –20 0 20 40 60 80 100 50 Test Circuit 1 VCC = LOW-to-HIGH RL = 4.7 kΩ S1 = ON –20 0 20 40 60 80 100 40 30 –40 AMBIENT TEMPERATURE, Tamb (°C) AMBIENT TEMPERATURE, Tamb (°C) SL01629 SL01630 Figure 12. Detection threshold versus temperature. Figure 13. Hysteresis voltage versus temperature. 0.23 VOL, LOW-LEVEL OUTPUT VOLTAGE (V) I CCL , SUPPLY CURRENT (ON time), (µA) 9 8 7 6 5 4 3 Test Circuit 1 VCC1 = VS(min) – 0.05 V RL = ∞ –20 0 20 40 60 80 100 0.22 0.21 0.20 0.19 Test Circuit 1 VCC1 = VS(min) – 0.05 V RL = 4.7 kΩ S1 = ON –20 0 20 40 60 80 100 0.18 0.17 –40 2 –40 AMBIENT TEMPERATURE, Tamb (°C) AMBIENT TEMPERATURE, Tamb (°C) SL01631 SL01632 Figure 14. LOW–level output voltage versus temperature. Figure 15. Supply current (ON time) versus temperature. VOPL , MIN. OPERATING THRESHOLD VOLTAGE (V) 4.5 I CCH, SUPPLY CURRENT (OFF time), (µA) 0.9 0.8 4.0 0.7 3.5 0.6 3.0 0.5 Test Circuit 1 RL = 4.7 kΩ VOL ≤ 0.4 V S1 = ON –20 0 20 40 60 80 100 2.5 Test Circuit 1 RL = ∞ VCC1 = VS(typ)/0.85 2.0 –40 –20 0 20 40 60 80 100 0.4 0.3 –40 AMBIENT TEMPERATURE, Tamb (°C) AMBIENT TEMPERATURE, Tamb (°C) SL01633 SL01634 Figure 16. Supply current (OFF time) versus temperature. Figure 17. Min. operating threshold voltage versus temperature. 2002 Mar 25 7 Philips Semiconductors Product data Active-LOW system reset with adjustable delay time NE56632-XX TYPICAL PERFORMANCE CURVES, NE56632-31 (continued) I OL1 , OUTPUT CURRENT (ON Time 1), (mA) I OL2 , OUTPUT CURRENT (ON Time 2), (mA) 36 34 32 30 28 26 24 22 Test Circuit 1 VCC1 = VS(min) – 0.05 V VCC2 = 0.4 V VO = 0.4 V RL = 0 Ω S2 = ON –20 0 20 40 60 80 100 37 35 33 31 Test Circuit 1 VCC1 = VS(min) – 0.05 V VCC2 = 0.4 V VO = 0.4 V RL = 0 Ω S2 = ON –20 0 20 40 60 80 100 29 20 –40 27 –40 AMBIENT TEMPERATURE, Tamb (°C) AMBIENT TEMPERATURE, Tamb (°C) SL01635 SL01636 Figure 18. Output current (ON time 1) versus temperature. Figure 19. Output current (ON time 2) versus temperature. 180 t PLH, LOW-to-HIGH DELAY TIME (ms) tPHL, HIGH-to-LOW DELAY TIME (µs) 160 140 120 100 80 60 40 –40 Test Circuit 2 CL = 100 pF RL = 4.7 kΩ CD = 10 nF 160 150 140 130 120 110 100 90 80 –40 VCC = (VS(typ) + 0.4 V) to (VS(typ)– 0.4 V) tPHL = Assertion Delay Time 80 100 –20 0 20 40 60 80 100 Test Circuit 2 CL = 100 pF RL = 4.7 kΩ CD = 10 nF VCC = (VS(typ) – 0.4 V) to (VS(typ)+ 0.4 V) tPLH = Release Delay Time –20 0 20 40 60 AMBIENT TEMPERATURE, Tamb (°C) AMBIENT TEMPERATURE, Tamb (°C) SL01637 SL01638 Figure 20. LOW-to-HIGH delay time versus temperature. Figure 21. HIGH-to-LOW delay time versus temperature. 2002 Mar 25 8 Philips Semiconductors Product data Active-LOW system reset with adjustable delay time NE56632-XX TECHNICAL DISCUSSION The NE56632-XX is a bipolar IC designed to provide power source monitoring and a system reset function in the event the power sags below an acceptable level for the system to operate reliably. The reset threshold incorporates a typical hysteresis of 50 mV to prevent erratic reasserts from being generated. An internal delay time circuit provides a adjustable power-on reset delay of typically 200 µs to 200 ms using an external capacitor. The output of the NE56632-XX utilizes an open collector topology, which requires an external pull-up resistor to VCC. Though this may be regarded as a disadvantage, it is advantageous in many sensitive applications. Because the open collector output cannot source reset current when both are operated from a common supply, the NE56632-XX offers a safe interconnect to a wide variety of microprocessors. The NE56632-XX operates at low supply currents, typically 3 µA, while offering precision threshold detection (±1.5%). Figure 22 is a functional block diagram of the NE56632-XX. The internal reference source voltage, VREF, is typically 0.65 V over the temperature range. The reference voltage is connected to the non-inverting inputs of the threshold Comparator 1 and Comparator 2, while the inverting input of Comparator 1 monitors the supply voltage through a voltage divider (R1 and R2). The output of the comparator drives the series base resistor, R3 of a common emitter amplifier, Q1. The collector of Q1 is connected to the inverting terminal of Comparator 2. The output of Comparator 2 is connected to the series base resistor, R4 of the output common emitter transistor, Q2. The open collector output of Q2 provides the reset output. The Delay Time Control is outputted at the junction of the collector of Q1 and the inverting input of Comparator 2. The reset release time delay, tPLH is set with an external capacitor. Figures 25 and 26 show tPLH as a function of the external delay capacitor, CD. When the supply voltage sags to the threshold detection voltage, the resistor divider network supplies a voltage to the inverting terminal of the threshold comparator which is less than VREF, causing the output of the comparator to go to a HIGH state. This causes the common emitter amplifier, Q1 to turn ON pulling down the non-inverting terminal of Comparator 2 which causes its output to go to a HIGH state. This HIGH output level turns on the output common emitter transistor, Q2. The collector output of Q2 is pulled LOW through the external pull-up resistor, thereby asserting the Active-LOW reset. Threshold hysteresis is established by turning on the bipolar common emitter transistor, Q1 when the input threshold Comparator 1 goes to a HIGH state. This occurs when VCC sags to or below the threshold level. With the output of Q1 connected to the non-inverting terminal of Comparator 2, the non-inverting terminal has a level near ground at about 0.4 V when the reset is asserted (Active-LOW). For the Comparator 2 to reverse its output, the Comparator 1 output and Q1 must overcome the additional pull-down voltage present on the inverting input of Comparator 2. The differential voltage required to do this establishes the hysteresis voltage of the sensed threshold voltage. Typically, it is 50 mV. When VCC sags, and it is below the detection Threshold (VSL), the device will assert a Reset LOW output at or near ground potential. As VCC rises from (VCC < VSL) to VSH or higher, the Reset is released and the output follows VCC. Conversely, decreases in VCC from (VCC > VSL) to VSL will cause the output to be pulled to ground. Hysteresis voltage = Release voltage – Detection Threshold voltage Vhys = VSH – VSL where: VSH = VSL + Vhys VSL = VSH – Vhys When VCC drops below the minimum operating voltage, typically 0.65 V, the output is undefined and the output reset low assertion is no longer guaranteed. At this level of VCC the output will try to rise to VCC. As VCC drops even further to zero, VOUT reset also goes to zero. VCC 5 R1 COMP1 VREF R2 ID COMP2 4 R3 Q1 R4 Q2 3 2 1 TC GND SUB VOUT (SUBSTRATE) SL01607 Figure 22. Functional diagram. 2002 Mar 25 9 Philips Semiconductors Product data Active-LOW system reset with adjustable delay time NE56632-XX TIMING DIAGRAM The timing diagram in Figure 23 depicts the operation of the device. Letters A–N on the TIME axis indicates specific events. A: At “A”, VCC begins to increase. Also the VOUT voltage initially increases but abruptly decreases when VCC reaches the level (approximately 0.65 V) that activates the internal bias circuitry and RESET is asserted. B: At “B”, VCC reaches the threshold level of VSH. At this point the delay time, tPLH is initiated while VCC rises above VSH to its normal operating level. The VOUT voltage remains in a low voltage state. C: At “C”, VCC is above VSL and the delay time elapses. At this instant, the IC releases the hold on the VOUT reset. The reset output then goes HIGH (assuming the reset pull-up resistor RPU is connected to VCC). In a microprocessor based system these events release the reset from the microprocessor, allowing the microprocessor to function normally. D-E: At “D”, VCC begins to fall, causing VOUT to follow. VCC continues to fall until the VSL undervoltage detection threshold is reached at “E”. This causes a reset signal to be generated (VOUT goes LOW). E-F: Between “E” and “F”, VCC continues to fall and then starts rising. F: At “F”, VCC rises to the VSH level. Once again, the device initiates the delay timer. F-G: VCC rises above VSH and returns to normal. At “G”, the delay (tPLH) times out and once again, then it releases the hold on the VOUT reset. G-H: At “G”, VCC is above the upper threshold and begins to fall, causing VOUT to follow it. As long as VCC remains above the VSH, no reset signal will be generated. H: At event “H”, VCC falls until the VSL undervoltage detection threshold is reached. At this level, a RESET signal is generated and VOUT goes LOW. H-I: Between “H” and “I”, VCC continues to fall and then starts to rise rising. VCC rises to the VSH level at “I”, where the delay time is again initiated. I-J: Between “I” and “J”, VCC rises above VSH to VCC normal and then falls back to VSL level at “J”. At “J”, the reset signal is reasserted before the delay time has elapsed. The time between “I” and “J” is less than tPLH (reset delay time). Thus, the reset is not released and the reset output remains LOW. K–L: Between “K” and “L”, VCC rises again back to normal operating level causing the reset delay to be initiated at “K” and the reset to be released at “L”. M: At “M”, VCC falls to VSL where the reset is asserted (VOUT Reset goes LOW). N: At “N”, the VCC voltage has decreased until normal internal circuit bias is unable to maintain a VOUT reset. As a result, VCC may rise to less than 0.65 V. As VCC decreases further, the VOUT reset also decreases to zero. V Vhys VSH VSL VCC < tPLH V VOUT (RESET) tPLH tPLH tPLH A B C DE F G H I J K L M N SL01606 Figure 23. Timing diagram. 2002 Mar 25 10 Philips Semiconductors Product data Active-LOW system reset with adjustable delay time NE56632-XX APPLICATION INFORMATION A typical application circuit for the NE56632-XX is shown in Figure 24. Note that a pull-up resistor, RPU is necessary since the output is an open collector. The value of RPU is calculated by the following expression. RPU ≥ (VCC – VRESET) / IOL t PLH (s) 1.0E+00 1.0E–01 where: VCC = VS(min) – 0.05 V (for a 3 V reset this is 2.905 V) VRESET = 0.4 V (this is VOL(max)) IOL = 5 mA; minimum output current at Tamb = 25 °C Substituting these values into the expression and calculating, finds RPU should be greater than or equal to 510 Ω. To ensure that the Active-LOW level is sufficient, a value of 4.7 kΩ is chosen in the test and application examples. 1.0E–02 1.0E–03 1.0E–04 1.0E–05 1.0E+00 1.0E+01 1.0E+02 CD (pF) 1.0E+03 1.0E+04 SL01611 TO VCC RPU TO RESET TERMINAL OF CPU 4 Figure 25. NE56632-20 CD versus tPLH characteristics. 5 1.0E+00 NE56632-XX 1.0E–01 CD t PLH (s) 1 2 3 1.0E–02 1.0E–03 SL01605 1.0E–04 Figure 24. Typical application. 1.0E–05 1.0E+00 1.0E+01 1.0E+02 CD (pF) 1.0E+03 1.0E+04 Figure 25 (NE56632-20 CD versus tPLH) and Figure 26 (NE56632-44 CD versus tPLH) show how tPHL, the “H” transmission delay or reset release delay time varies as a function of the external delay capacitance, CD. From Figure 26, typical range of the delay capacitance is 1 pF to 10 nF which yields typical delays from 200 µs to 200 ms. The following formula can be used to find the approximate delay time based on external delay capacitance, CD and the delay time coefficient, d shown in Table 2. tPLH (ms) ≈ CD (µF) × d For example, a NE56632-44 using an external capacitor, CD = 1 nF = 1000 pF yields: tPLH (ms) ≈ (1 × 10–3) (1.85 × 104) ≈ 18.5 ms Compare this to the value of tPLH ≈ 17 ms for CD = 1000 pF that is extracted from Figure 26. SL01612 Figure 26. NE56632-44 CD versus tPLH characteristics. Table 2. Delay time coefficient Device NE56632–46 NE56632–45 NE56632–44 NE56632–43 NE56632–42 NE56632–31 NE56632–30 NE56632–29 NE56632–28 NE56632–27 NE56632–20 NE56632–19 d 1.95 × 104 1.90 × 104 1.85 × 104 1.80 × 104 1.75 × 104 1.20 × 104 1.15 × 104 1.10 × 104 1.05 × 104 1.00 × 104 0.65 × 104 0.60 × 104 2002 Mar 25 11 Philips Semiconductors Product data Active-LOW system reset with adjustable delay time NE56632-XX TEST CIRCUITS RL A1 S1 S2 A2 5 10 µF /10 V 4 VCC1 V1 NE56632-XX 1 2 3 V2 VCC2 CD S3 SL01608 Figure 27. Test circuit 1. 5 4 RL 10 µF /10 V 5.0 V VS(typ) – 0.4 V VS(typ) + 0.4 V 0V INPUT PULSE NE56632-XX 1 2 3 SL01610 CL 100 pF CRT Figure 29. Input pulse. NOTES: A = DC amperemeter V = DC voltmeter CRT = oscilloscope CD SL01609 Figure 28. Test circuit 2. 2002 Mar 25 12 Philips Semiconductors Product data Active-LOW system reset with adjustable delay time NE56632-XX PACKING METHOD The NE56632-XX is packed in reels, as shown in Figure 30. GUARD BAND TAPE REEL ASSEMBLY TAPE DETAIL COVER TAPE CARRIER TAPE BARCODE LABEL BOX SL01305 Figure 30. Tape and reel packing method. 2002 Mar 25 13 Philips Semiconductors Product data Active-LOW system reset with adjustable delay time NE56632-XX SOT23-5: plastic small outline package; 5 leads; body width 1.5 mm 1.35 1.2 1.0 0.025 0.55 0.41 0.22 0.08 3.00 2.70 1.70 1.50 0.55 0.35 2002 Mar 25 14 Philips Semiconductors Product data Active-LOW system reset with adjustable delay time NE56632-XX NOTES 2002 Mar 25 15 Philips Semiconductors Product data Active-LOW system reset with adjustable delay time NE56632-XX Data sheet status Data sheet status [1] Objective data Preliminary data Product status [2] Development Qualification Definitions This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. Product data Production [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 © Koninklijke Philips Electronics N.V. 2002 All rights reserved. Printed in U.S.A. Date of release: 08-02 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. Document order number: 9397 750 10239 Philips Semiconductors 2002 Mar 25 16