OM62112

INTEGRATED CIRCUITS DATA SHEET OM6211 48 × 84 dot matrix LCD driver Product specification File under Integrated Circuits, IC12 2002 Jan 17 Philips Semiconductors Product specification 48 × 84 dot matrix LCD driver CONTENTS 1 2 3 4 5 6 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 9 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 9.10 9.11 FEATURES APPLICATIONS GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM PINNING PIN FUNCTIONS ROW 0 to ROW 47 row driver outputs COL 0 to COL 83 column driver outputs VSS1 and VSS2: negative power supply rails VDD1 to VDD3: positive power supply rails VLCDOUT, VLCDIN and VLCDSENSE: LCD power supply VOS4 to VOS0: calibration inputs SDIN: serial data input SDOUT: serial data output SCLK: serial clock input SCE: chip enable OSC: oscillator MX: horizontal mirroring ID3 and ID4: identification inputs RES: reset T1, T2, T3, T4, T5 and T6: test pins BLOCK DIAGRAM FUNCTIONS Oscillator Serial interface control Command decoder Display data RAM (DDRAM) Timing generator Address Counter (AC) Display address counter VLCD generator Bias voltage generator LCD row and column drivers Reset FUNCTIONAL DESCRIPTION Reset Power-down LCD voltage selector Oscillator Timing Column driver outputs Row driver outputs Drive waveforms Bias system Voltage multiplier control Temperature compensation 9.12 10 10.1 10.2 11 11.1 11.2 11.2.1 11.2.2 12 12.1 13 14 15 16 16.1 16.2 17 18 18.1 18.2 18.3 18.4 18.5 18.5.1 18.5.2 18.5.3 18.5.4 18.6 18.7 18.8 19 20 21 22 23 24 VLCD generator INITIALIZATION OM6211 Initialization sequence Frame frequency calibration (OC) ADDRESSING Addressing Serial interface Write mode Read mode INSTRUCTIONS Instruction set LIMITING VALUES HANDLING DC CHARACTERISTICS AC CHARACTERISTICS Serial interface timing Reset timing APPLICATION INFORMATION MODULE MAKER PROGRAMMING VLCD calibration VPR default value Seal bit OTP architecture Serial interface commands Enable OTP CALMM Load factory default Refresh Example of filling the shift register Programming flow Programming specification BONDING PAD LOCATIONS DEVICE PROTECTION DIAGRAM TRAY INFORMATION DATA SHEET STATUS DEFINITIONS DISCLAIMERS 2002 Jan 17 2 Philips Semiconductors Product specification 48 × 84 dot matrix LCD driver 1 FEATURES 2 APPLICATIONS OM6211 • Single-chip LCD controller/driver • 48 row, 84 column outputs • Display data RAM 48 × 84 bits • 3-line serial interface, maximum 4.0 Mbit/s • On-chip: – Generation of LCD supply voltage VLCD – Generation of intermediate LCD bias voltages – Oscillator (requires no external components). • CMOS compatible inputs • Mux rate 1 : 48 • Logic supply voltage range VDD1 to VSS: – 1.7 to 2.3 V. • Supply voltage range for high voltage part VDD2 to VSS: – 2.5 to 4.5 V. • LCD supply voltage range VLCD to VSS: – 4.5 to 9.0 V. • Low power consumption (typical 90 µA), suitable for battery operated systems • External reset • Temperature compensation of VLCD • Temperature range: Tamb = −40 to +85 °C • Manufactured in N-well silicon gate CMOS process. 4 ORDERING INFORMATION • Battery powered telecommunication systems. 3 GENERAL DESCRIPTION The OM6211 is a low power CMOS LCD row/column driver, designed to drive a dot matrix graphic display of 48 rows and 84 columns. All necessary functions for the display are provided in a single chip, including on-chip generation of LCD supply and bias voltages, resulting in a minimum of external components and low power consumption. The OM6211 interfaces to microcontrollers via a 3-line serial interface. PACKAGE TYPE NUMBER NAME OM6211U/2/F1 tray DESCRIPTION chip with bumps in tray VERSION − 2002 Jan 17 3 Philips Semiconductors Product specification 48 × 84 dot matrix LCD driver 5 BLOCK DIAGRAM OM6211 handbook, full pagewidth VDD1 VDD2 VDD3 COL0 to COL83 ROW0 to ROW47 48 ROW DRIVERS VSS1 VSS2 T4, T5, T6 T1, T2, T3 ID3, ID4 MX BIAS VOLTAGE GENERATOR 3 3 84 COLUMN DRIVERS SHIFT REGISTER OM6211 2 RESET DATA LATCHES OSCILLATOR OSC RES VLCDIN TIMING GENERATOR VLCDsense VLCDOUT VOS [4:0] 5 VLCD GENERATOR DISPLAY DATA RAM 48 × 84 bits DISPLAY ADDRESS COUNTER SCLK SDIN SDOUT SERIAL INTERFACE CONTROL COMMAND DECODER ADDRESS COUNTER MGU272 SCE Fig.1 Block diagram. 2002 Jan 17 4 Philips Semiconductors Product specification 48 × 84 dot matrix LCD driver 6 PINNING SYMBOL VOS4 VOS3 VOS2 VOS1 VOS0 T6 RES T5 T4 T3 T2 T1 SCE VSS2 VSS1 OSC SDOUT 7 7.1 PAD 3 4 5 6 7 8 to 11 16 17 18 19 20 21 22 23 to 30 31 to 38 40 41 DESCRIPTION input pin 4 for VLCD calibration input pin 3 for VLCD calibration input pin 2 for VLCD calibration input pin 1 for VLCD calibration input pin 0 for VLCD calibration test input 6 external reset input (active LOW) test input 5 test input 4 test output 3 test output 2 test output 1 chip enable input (active LOW) ground ground oscillator input serial data output 7.5 OM6211 SYMBOL SDIN SCLK ID4 ID3 MX VDD1 VDD2 VDD3 VLCDSENSE VLCDOUT VLCDIN ROW 0 to ROW 23 COL 0 to COL 83 ROW 47 to ROW 24 PAD 42 43 44 45 46 47 to 52 53 to 60 61 to 64 65 66 to 72 73 to 78 89 to 112 113 to 196 197 to 220 DESCRIPTION serial data input serial clock input module identification input module identification input horizontal mirroring input logic supply voltage voltage multiplier supply voltage voltage multiplier supply voltage VLCD generator regulation input VLCD generator output LCD supply voltage input LCD row driver outputs LCD column driver outputs LCD row driver outputs 1, 12 to 15, dummy pads 39, 79, 81 to 88 and 221 to 225 PIN FUNCTIONS ROW 0 to ROW 47 row driver outputs VLCDOUT, VLCDIN and VLCDSENSE: LCD power supply These pads output the display row signals. 7.2 COL 0 to COL 83 column driver outputs These pads output the display column signals. 7.3 VSS1 and VSS2: negative power supply rails If the internal VLCD generator is used, then all three pins must be connected together. If not (VLCD generator is disabled and an external voltage is applied to VLCDIN), then VLCDOUT must be left open-circuit, VLCDSENSE must be connected to VLCDIN, VDD2 and VDD3 should be applied according to the specified voltage range. The following settings are also required: HVE = 0, S1 = 1 and S0 = 0. 7.6 VOS4 to VOS0: calibration inputs Negative power supply rails VSS1 and VSS2 must be connected together, hereafter referred to as VSS. When a pin has to be connected externally to VSS, then pin VSS1 should be used. 7.4 VDD1 to VDD3: positive power supply rails Positive power supply rails: VDD1 for logic supply, VDD2 and VDD3 for voltage multiplier. VDD2 and VDD3 must be connected together, hereafter referred to as VDD2. Five pull-up input pins for on-glass VLCD calibration. Each pin may be connected to VSS, which corresponds to logic 0, or left open-circuit, which corresponds to logic 1. All five pins define a 5-bit two’s complement number ranging from −16 to 15 decimal (from 10000 to 01111). The default value, with all pins connected to VSS, is 0 decimal (00000). 2002 Jan 17 5 Philips Semiconductors Product specification 48 × 84 dot matrix LCD driver In order to reduce current consumption related to the pull-up circuitry, the 5-bit number is stored in a register when exiting the Power-down mode. The pull-up circuitry is then disabled. Additionally, the register is refreshed by each HVE command. 7.7 SDIN: serial data input 8 8.1 BLOCK DIAGRAM FUNCTIONS Oscillator OM6211 The on-chip oscillator provides the clock signal for the display system. It has no external components. 8.2 Serial interface control Serial data input. 7.8 SDOUT: serial data output Detects the serial interface protocol, commands and display data bytes. The serial interface converts the data input (serial-to-parallel) as well as the output bits. 8.3 Command decoder Serial data output (3-state, push-pull). If bidirectional data transmission is required, SDOUT and SDIN should be connected externally. If the read mode is not used, SDOUT should be left open-circuit. 7.9 SCLK: serial clock input Decodes all commands. 8.4 Display Data RAM (DDRAM) Serial clock input. 7.10 SCE: chip enable Chip enable input, active LOW. If SCE is HIGH, the SCLK pulses are ignored. 7.11 OSC: oscillator The OM6211 contains a 48 × 84 bit static RAM which stores the display data. The RAM is divided into six banks of 84 bytes (6 × 8 × 84 bits). During RAM access, data is transferred to the RAM via the serial interface. There is a direct correspondence between the X address and column output number. 8.5 Timing generator External clock input. The external clock is active only in a special test mode, so in the application it is not available. In normal mode (the internal on-chip oscillator used) this input must be connected to VSS. If OSC is held HIGH, the internal oscillator is disabled. 7.12 MX: horizontal mirroring The timing generator produces the various signals required to drive the internal circuitry. Internal chip operation is not disturbed by operations of the serial interface. 8.6 Address Counter (AC) Horizontal mirroring input. When MX = 1 the X address space is mirrored. 7.13 ID3 and ID4: identification inputs The address counter assigns addresses to the display data RAM for writing. The X address (X6 to X0) and the Y address (Y2 to Y0) are set separately. After a write operation the address counter is automatically incremented by 1. 8.7 Display address counter LCD module identification inputs. Their state can be read out via the serial interface in order to identify the module version. 7.14 RES: reset The display is generated by continuously shifting rows of RAM data to the dot matrix LCD via the column outputs. The display status (all dots on/off, normal/inverse video) is set via the serial interface. 8.8 VLCD generator External reset pin. When LOW the chip will be reset as defined in Section 9.1. The initialization by the RES pin is always required during power-on. Timing for the RES pin is illustrated in Fig.18. 7.15 T1, T2, T3, T4, T5 and T6: test pins A voltage multiplier (charge pump) with a programmable number of stages. Internal capacitors are used for the voltage multiplier, therefore only decoupling capacitors for VLCD and VDD2 are required. Test pins. In the application T4 and T5 must be connected to VSS. T1, T2, T3 and T6 must be left open-circuit (T6 has a pull-down resistor). 2002 Jan 17 6 Philips Semiconductors Product specification 48 × 84 dot matrix LCD driver 8.9 Bias voltage generator 9 FUNCTIONAL DESCRIPTION OM6211 Generates 4 intermediate LCD bias voltages. The bias system is selectable; see Section 9.9. 8.10 LCD row and column drivers The OM6211 is a low power LCD driver designed to interface with microprocessors/microcontrollers and a wide variety of LCDs. The host microprocessor or microcontroller and the OM6211 are connected via a serial interface. The internal oscillator requires no external components. The appropriate intermediate bias voltages for the multiplexed LCD waveforms are generated on-chip. The only other connections required to complete the system are to the power supplies (VDD1, VDD2, VSS and VLCD) and suitable capacitors for decoupling VLCD and VDD2. The OM6211 contains 48 row and 84 column drivers, which connect the appropriate LCD bias voltages in sequence to the display in accordance with the data to be displayed. Figure 3 shows typical waveforms. 8.11 Reset A reset initializes the chip. It can be performed either by the RES pin being LOW or by a command. handbook, full pagewidth VLCD VDD2 VDD1 VDD2, 3 VDD1 84 column drivers HOST MICROPROCESSOR/ MICROCONTROLLER LCD PANEL OM6211 48 row drivers VSS RES SCE SCLK VSS1, 2 MGU273 SDA VSS Fig.2 Typical system configuration. 2002 Jan 17 7 Philips Semiconductors Product specification 48 × 84 dot matrix LCD driver 9.1 Reset 9.3 LCD voltage selector OM6211 The OM6211 has no internal Power-on reset, only external reset and reset by command. After power-on an external reset is required. A reset initiated either from the RES pin or by command will initialize the chip to the following starting conditions: • Power-down mode (DON = 0 and DAL = 1): – Internal oscillator stopped – The VLCD generator (HV generator) is switched off (HVE = 0) and VLCDOUT is 3-state – Display is off and all LCD outputs are internally connected to VSS (DON = 0) – Display all points is on (DAL = 1). • Serial interface initialized; write mode • Display normal video (E = 0) • Address counter X6 to X0 = 0; Y2 to Y0 = 0; display start line Z5 to Z0 = 0; no Y mirroring (MY = 0) • Bias system 1⁄7 (BS2 to BS0 = 100) • VLCD selection VPR7 to VPR0 = 0 • Voltage multiplication factor 4 (S1 and S0 = 10) • Temperature control mode TC3 (TC1 and TC0 = 11) • Frequency not calibrated and OC = 0 • RAM data is unchanged (after power-up undefined). 9.2 Power-down The practical value for VLCD is determined by equating Voff(rms) with a defined LCD threshold voltage (Vth), typically when the LCD exhibits approximately 10% contrast. 9.4 Oscillator The internal logic operation and the multi-level drive signals of the OM6211 are clocked by the built-in RC oscillator. No external components are required. The oscillator is in operation as long as the chip is not in Power-down mode. 9.5 Timing The timing of the OM6211 organizes the internal data flow of the device. The timing also generates the LCD frame frequency that is derived from the clock frequency generated by the internal clock generator. 9.6 Column driver outputs The LCD drive section includes 84 column outputs, which should be connected directly to the LCD. The column output signals are generated in accordance with the multiplexed row signals and with the data in the display latch. If less than 84 columns are required, the unused column outputs should be left open-circuit. 9.7 Row driver outputs The chip is in Power-down mode if the display is off (DON = 0) and display all points is on (DAL = 1), regardless of the order in which both bits are set. During the Power-down mode almost all static currents are switched off (no internal oscillator, no timing and no LCD segment drive system), and all LCD outputs are internally connected to VSS. The VLCD generator is switched off (but HVE is not affected). The serial interface function remains. RAM data is unchanged. When exiting the Power-down mode, the VOS value is stored in a register. The LCD drive section includes 48 row outputs, which should be connected directly to the LCD. If less than 48 rows are required, the unused row outputs should be left open-circuit. 2002 Jan 17 8 Philips Semiconductors Product specification 48 × 84 dot matrix LCD driver 9.8 Drive waveforms OM6211 frame n VLCD V2 V3 V4 V5 VSS VLCD V2 V3 V4 V5 VSS VLCD V2 V3 V4 V5 VSS VLCD V2 V3 V4 V5 VSS frame n + 1 Vstate1(t) Vstate2 (t) ROW 0 R0 (t) ROW 1 R1 (t) COL 0 C0 (t) COL 1 C1 (t) VLCD V3 − VSS VLCD − V2 0V V3 − V2 V4 − V5 0V VSS − V5 V4 − VLCD − VLCD VLCD V3 − VSS VLCD − V2 0V V3 − V2 V4 − V5 0V VSS − V5 V4 − VLCD − VLCD Vstate1(t) Vstate2 (t) 0 1 2 3 4 5 6 7 8... ... 47 0 1 2 3 4 5 6 7 8... ... 47 MGU274 Vstate1(t) = C1(t) − R0(t). Vstate2(t) = C1(t) − R1(t). Fig.3 Typical LCD driver waveforms. 2002 Jan 17 9 Philips Semiconductors Product specification 48 × 84 dot matrix LCD driver 9.9 Bias system OM6211 One reason to depart from the optimum would be to reduce the required VLCD voltage. A compromise between contrast and VLCD must be found for any particular application. In the OM6211 one of three possible values of the bias system can be selected. The value 1⁄7 is default. The bias voltage levels are set in the ratio of R - R - nR - R - R. Different multiplex rates require different factors of n. This is programmed by BS2 to BS0. For optimum bias values, n can be calculated from the following equation: n= Mux rate – 3 ; where Mux rate is 48. Changing the bias system from the optimum setting will have a consequence on the contrast and viewing angle. Table 1 Programming the required bias system BS2 0 1 1 Table 2 BS1 1 0 0 BS0 1 0 1 n 4 3 2 BIAS MODE 1⁄ 8 1⁄ 7 1⁄ 6 TYPICAL MUX RATES 1 : 55 and 1 : 48 1 : 33 1 : 24 LCD bias voltages for 1⁄6 bias, 1⁄7 bias and 1⁄8 bias. BIAS VOLTAGE SYMBOL V1 V2 V3 V4 V5 V6 FOR 1⁄6 BIAS VLCD 5⁄ 4⁄ 2⁄ 1⁄ 6VLCD 6VLCD 6VLCD 6VLCD FOR 1⁄7 BIAS VLCD 6⁄ 5⁄ 2⁄ 1⁄ 7VLCD 7VLCD 7VLCD 7VLCD FOR 1⁄8 BIAS VLCD 7⁄ 6⁄ 2⁄ 1⁄ 8VLCD 8VLCD 8VLCD 8VLCD VSS VSS VSS 9.10 Voltage multiplier control The OM6211 incorporates a software configurable voltage multiplier. After reset (RES) the voltage multiplier is set to 4VDD2. Other voltage multiplier factors are set via the serial interface (S1 and S0). Table 3 HV generator multiplication S1 0 0 1 1 S0 0 1 0 1 MULTIPLICATION 2VDD2 3VDD2 4VDD2 not available 2002 Jan 17 10 Philips Semiconductors Product specification 48 × 84 dot matrix LCD driver 9.11 Temperature compensation OM6211 Due to the temperature dependency of the liquid crystals viscosity, the LCD controlling voltage (VLCD) must be increased at lower temperatures to maintain optimum contrast. Figure 4 shows VLCD as a function of temperature for a typical high multiplex rate liquid. In the OM6211 the temperature coefficient of VLCD can be selected from 4 values by setting bits TC1 and TC0, see Tables 4 and 8. handbook, full pagewidth MGT848 VLCD T Fig.4 VLCD as a function of liquid crystal temperature (typical values). 9.12 VLCD generator V LCD = ( a + V OP × b ) × [ 1 + TC × ( T – T nom ) ] (3) The binary number VOP representing the operating voltage can be set by the serial interface command and can be adjusted (calibrated) by 5 input pins according to the following formula: V OP = V PR + V OS (1) where: • VPR is an 8-bit unsigned number set by the serial interface command • VOS is a 5-bit two’s complement number set by the 5 input pins VOS4 to VOS0, see Table 9 • VOP is an 8-bit unsigned number used internally for generation of the LCD supply voltage VLCD. To avoid numerical overflow the allowed values of VPR should be limited to the range 32 to 225 (decimal). The corresponding voltage at the reference temperature, Tnom, can be calculated as follows: V LCD(Tnom) = ( a + V OP × b ) (2) The generated voltage at VLCD is dependent on the temperature, programmed Temperature Coefficient (TC) and the programmed voltage at the reference temperature (Tnom). 2002 Jan 17 11 Tnom, a and b for each temperature coefficient are given in Table 4. The maximum voltage that can be generated is dependent on the voltage of VDD2 and the display load current. As the programming range for the internally generated VLCD allows values above the maximum allowed VLCD, the user has to ensure while setting the VPR register and selecting the Temperature Compensation, that under all conditions and including all tolerances the VLCD limit of maximum 9 V will never be exceeded. For a particular liquid crystal, the optimum value of VLCD can be calculated for a given multiplex rate. For a Mux rate of 1 : 48, the optimum operating voltage of the liquid crystal can be calculated as follows; 1 + 48 V LCD = -------------------------------------- × V th = 6.06 × V th 1  1 – ---------- 2×  48 (4) where Vth is the threshold voltage of the liquid crystal used. Philips Semiconductors Product specification 48 × 84 dot matrix LCD driver Table 4 Typical values for parameters of the HV generator programming TC0 4.57 30.0 27 0 TC1 4.28 28.0 27 −0.25 TC2 4.04 26.5 27 −0.5 TC3 3.79 25.0 27 −0.75 V OM6211 SYMBOL a b Tnom TC UNIT mV °C 10-3/°C Example: to achieve VLCD = 8.3 V at temperature Tnom for TC3 it is necessary to set VPR = 180 (decimal). Example for calibration: Before calibration VPR = 180 was applied, but the measured voltage was VLCD = 8.4 V. To decrease VLCD by 100 mV the best value for VOS is −4 decimal (11100 binary in the two’s complement notation). So after calibration with VOS = −4 the proper VPR value is still 180. As VOS is used for calibration and the default value is 0, for selecting the value of VPR it can always be considered that VOS = 0. handbook, full pagewidth MGT847 V LCD b a 00 01 02 03 04 05 06 ... ... FD FE FF V OP VOP7 to VOP0 programming, (00H to FFH). Fig.5 VLCD programming of OM6211. 2002 Jan 17 12 Philips Semiconductors Product specification 48 × 84 dot matrix LCD driver 10 INITIALIZATION 10.1 Initialization sequence 11 ADDRESSING 11.1 Addressing OM6211 After reset (RES) it is recommended to initialize the VLCD generator using the following sequence; a starting state of HVE = 0, DON = 0 and DAL = 1 is assumed: 1. Set the required VOP and, if required, the voltage multiplier S1 and S0 2. Set DAL = 0 to leave the Power-down state (in order to precharge the charge pump VLCD is set to VDD2) 3. Wait for at least 1 ms and set HVE = 1 to switch-on the VLCD generator 4. Set DON = 1 to switch the display on. 10.2 Frame frequency calibration (OC) Data is downloaded in bytes into the RAM matrix of OM6211 as illustrated in Figs 6 and 7. The display RAM has a matrix of 48 × 84 bits. The columns are addressed by the address pointer. The address ranges are X = 0 to 83 (1010011) and Y = 0 to 5 (101). Addresses outside of these ranges are not allowed. The X address increments after each byte (see Fig.7). After the last X address (X = 83) X wraps around to 0 and Y increments to address the next row. After the very last address (X = 83 and Y = 5) the address pointers wrap around to address X = 0 and Y = 0. The selection of the MX input allows horizontal mirroring: when MX = 1, the X address space is mirrored (see Fig.6). When MX = 0 the mirroring is disabled. MX affects data only during writing to the RAM, so after a change of MX RAM data must be re-written. The MY bit allows vertical mirroring: when MY = 1, then the Y address space is mirrored. MY does not affect the RAM content, but defines the way RAM data is written to the display. A change of MY has an immediate effect on the display. Vertical scrolling of the display is controlled by the Z address with a range from 0 to 47 (101111). The Z address specifies which rows of the RAM are output to which row outputs. The value of the Z address defines which row of the RAM will be ROW 0 of the display (which is normally the top row of the display). For example, if the Z address is set to 31 (see Fig.8), then the data displayed on ROW 0 of the display will be the data from ROW 31 of the RAM and the data on ROW 1 will be from ROW 32 of the RAM. When the MY is active (MY = 1), then the Z address defines which row of the RAM is written to ROW 47 of the display. For example, when the Z address is set to 31, ROW 47 of the display would come from ROW 31 of the RAM and ROW 46 from ROW 32 of the RAM (see Fig.9). The Z address does not affect the RAM content, but defines the way RAM data is written to the display. A change of Z address has an immediate effect on the display. The OM6211 incorporates frame frequency calibration via software. The calibration is achieved by tuning the internal oscillator. After reset the frame frequency calibration is disabled (OC = 0). The calibration can only be performed if the driver is not in Power-down mode. The calibration is started by setting OC = 1 via the serial interface (start command) and will be stopped by setting OC = 0 (stop command). The time between start and stop of the calibration must be 200 ms to give a frame frequency of 80 Hz. Any variation in calibration time (deviation from 200 ms) results in a corresponding variation in frame frequency. During calibration all other commands are allowed. The calibration may be repeated and is always performed with the previously calibrated frequency. Through repeated calibrations a better accuracy can be expected and, most especially, the temperature drift can be compensated for. A minimum time delay of 500 ms between consecutive calibration events is necessary (between stop and start). The calibration will always be performed if the calibration time is between 190 and 210 ms. If, however, the calibration time is lower then 58 ms or higher than 690 ms (or the stop command does not occur at all), the calibration attempt is ignored and the previously selected frequency is maintained. For the remaining values of the calibration time (from 58 to 190 ms and from 210 to 690 ms) it cannot be determined if the calibration will be performed or ignored. 2002 Jan 17 13 Philips Semiconductors Product specification 48 × 84 dot matrix LCD driver OM6211 handbook, full pagewidth LSB 0 Y address MSB 5 MX = 0 MX = 1 0 83 X address 83 0 MGU275 Fig.6 RAM format, addressing. handbook, full pagewidth 0 84 168 252 336 420 0 1 85 169 253 337 421 2 86 170 254 338 422 X address 503 83 0 Y address 5 MGT845 Fig.7 Sequence of writing data bytes into RAM. 2002 Jan 17 14 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2002 Jan 17 15 3 4 5 Philips Semiconductors 48 × 84 dot matrix LCD driver Z address when MY = 0 Y address RAM 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 ROW 0 ROW 1 ROW 2 ROW 3 ROW 4 ROW 5 ROW 6 ROW 7 ROW 8 ROW 9 ROW 10 ROW 11 ROW 12 ROW 13 ROW 14 ROW 15 ROW 16 ROW 17 ROW 18 ROW 19 ROW 20 ROW 21 ROW 22 ROW 23 ROW 24 ROW 25 ROW 26 ROW 27 ROW 28 ROW 29 ROW 30 ROW 31 ROW 32 ROW 33 ROW 34 ROW 35 ROW 36 ROW 37 ROW 38 ROW 39 ROW 40 ROW 41 ROW 42 ROW 43 ROW 44 ROW 45 ROW 46 ROW 47 DISPLAY 0 1 2 Z address = 31 Product specification OM6211 MGU276 Fig.8 Programming the Z address when MY = 0. This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2002 Jan 17 16 3 4 5 Philips Semiconductors 48 × 84 dot matrix LCD driver Z address with MY = 1 Y address RAM 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 ROW 0 ROW 1 ROW 2 ROW 3 ROW 4 ROW 5 ROW 6 ROW 7 ROW 8 ROW 9 ROW 10 ROW 11 ROW 12 ROW 13 ROW 14 ROW 15 ROW 16 ROW 17 ROW 18 ROW 19 ROW 20 ROW 21 ROW 22 ROW 23 ROW 24 ROW 25 ROW 26 ROW 27 ROW 28 ROW 29 ROW 30 ROW 31 ROW 32 ROW 33 ROW 34 ROW 35 ROW 36 ROW 37 ROW 38 ROW 39 ROW 40 ROW 41 ROW 42 ROW 43 ROW 44 ROW 45 ROW 46 ROW 47 DISPLAY 0 1 2 Z address = 31 Product specification OM6211 MGU277 Fig.9 Programming the Z address when MY = 1. Philips Semiconductors Product specification 48 × 84 dot matrix LCD driver OM6211 DDRAM bank 0 top of LCD R0 bank 1 R8 bank 2 R16 LCD bank 3 R24 bank 4 R32 bank 5 R40 R47 MGT842 Fig.10 DDRAM to display mapping (Z = 0). 2002 Jan 17 17 Philips Semiconductors Product specification 48 × 84 dot matrix LCD driver 11.2 Serial interface OM6211 Figures 12, 13 and 14 show the protocol of the write mode: • When SCE is HIGH, SCLK clocks are ignored: during the HIGH time of SCE the serial interface is initialized (see Fig.12) • At the falling edge of SCE SCLK must be LOW (see Fig.16); for the transmission of each data bit a rising and then a falling edge of SCLK is necessary • SDIN is sampled at the rising edge of SCLK • D/C indicates whether the byte is a command (D/C = 0) or RAM data (D/C = 1); it is sampled with the first rising SCLK edge • If SCE stays LOW after the last bit of a command or data byte, the serial interface expects the D/C bit of the next byte at the next rising edge of SCLK (see Fig.13) • A reset pulse with RES interrupts the transmission. The data being written into the RAM may be corrupted. The registers are cleared. If SCE is LOW after the rising edge of RES, the serial interface is ready to receive the D/C bit of a command or data byte (see Fig.14). The serial interface is a 3-line bidirectional interface for communication between the microcontroller and the LCD driver chip. The 3 lines are: SCE (chip enable), SCLK (serial clock) and SDA (serial data). The OM6211 is connected to SDA by two pins: SDIN (data input) and SDOUT (data output) connected together. 11.2.1 WRITE MODE The write mode of the interface means that the microcontroller writes commands and data to the OM6211. Each data packet contains a control bit D/C and a transmission byte. If D/C is LOW, the following byte is interpreted as a command byte (see Table 5). If D/C is HIGH, the following byte is stored in the display data RAM. After every data byte the address counter is incremented automatically. Figure 11 shows the general format of the write mode and the definition of the transmission byte. Every command can be sent in any order to the OM6211. The MSB of a byte is transmitted first. The serial interface is initialized when SCE is HIGH. In this state, SCLK clock pulses have no effect and no power is consumed by the serial interface. A falling edge on SCE enables the serial interface and indicates the start of a data transmission. Transmission Byte (TB) (command byte OR data byte) handbook, full pagewidth D/C DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 MSB LSB D/C TB D/C TB D/C TB MGU278 Fig.11 Serial data stream, write mode. 2002 Jan 17 18 Philips Semiconductors Product specification 48 × 84 dot matrix LCD driver OM6211 handbook, full pagewidth SCE SCLK SDIN D/C DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 MGU279 Fig.12 Write mode: a control bit followed by a transmission byte. handbook, full pagewidth SCE SCLK SDIN D/C DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 D/C DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 D/C MGU280 Fig.13 Write mode: transmission of several bytes. handbook, full pagewidth SCE RES SCLK SDIN D/C DB7 DB6 DB5 DB4 D/C DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 D/C DB7 DB6 MGU281 Fig.14 Write mode: interrupted by reset (RES). 2002 Jan 17 19 Philips Semiconductors Product specification 48 × 84 dot matrix LCD driver 11.2.2 READ MODE OM6211 VM has a valid value 45 ms after a delay time of approximately 45 ms starting from the time the VLCD generator has been switched on (by setting HVE = 1). This delay time is dependent on the external VLCD decoupling capacitor (here 100 nF is assumed). For more details concerning the VM bit see Chapter 22 The reading out of the chip identification bits and module identification bits can be used to implement different initialization schemes for different applications. The reading out of VM can be used to check the proper electrical contacts of the LCD module. One read status command enables one status bit to be read, i.e. 5 commands are needed to read the status of all 5 bits. The first 4 bits of the read byte (DB7 to DB4) are always equal to the corresponding status bit and the next 4 bits (DB3 to DB0) are equal to the complement of this bit. As stated before the SDOUT data is supposed to be read on the rising edge of SCLK. Care must be taken, however, when running the SCLK at maximum frequency. Because of the access time limit t2 (see Section 10.1 and Fig.17) it might happen that the first bits of each group (DB7 to DB4 and DB3 to DB0) are not valid at the time of the corresponding SCLK edges. Thus it is recommended to read the bits DB4 and DB0 only. In the read mode of the interface the microcontroller reads data from the OM6211. To do so the microcontroller first has to send the read status command, and then the following byte is transmitted in the opposite direction (using SDOUT). After that SCE is required to go HIGH before a new command is sent (see Fig.15). The OM6211 samples the SDIN data on the rising edges of SCLK, but shifts SDOUT data on the falling edges of SCLK. Thus the microcontroller is supposed to read SDOUT data on the rising edges of SCLK. After the read status command has been sent, the SDIN line must be set to 3-state not later then the falling SCLK edge of the last bit (see Fig.15). The 8th read bit is shorter than the others because it is terminated by the rising edge of SCLK (see Fig.15). The last rising edge of SCLK sets SDOUT to 3-state after the delay time t3 (see Section 10.1 and Fig.17). There are 5 bits of information only that can be read by the microcontroller (see Table 7). Two of them are chip identification bits and have fixed values. The next two bits are LCD module identification bits and can be set by connecting the ID3 and ID4 pins to VDD1 or VSS. The fifth bit is the VLCD voltage monitor bit VM. It indicates that the charge pump is running and the voltage level of VLCD is sufficient to provide enough contrast of the display (VM = 1). If the VLCD generator cannot produce a voltage defined by VOP, then VM = 0. handbook, full pagewidth SCE SCLK SDIN D/C DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 D/C SDOUT DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 MGU282 Fig.15 Read mode. 2002 Jan 17 20 Philips Semiconductors Product specification 48 × 84 dot matrix LCD driver 12 INSTRUCTIONS 12.1 Instruction set Instruction set; see notes 1 and 2 and Table 6 D/C 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMMAND BYTE DB7 1 1 D7 1 1 1 1 1 1 0 0 0 0 1 0 1 0 0 0 1 1 1 1 DB6 1 1 D6 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 DB5 1 1 D5 0 1 1 1 0 1 0 0 Z5 1 0 1 1 1 1 1 1 1 1 1 DB4 0 0 D4 1 0 0 0 0 1 1 0 Z4 0 VPR4 0 0 1 1 1 0 0 0 0 DB3 0 0 D3 1 1 0 0 MY 0 X X3 Z3 1 VPR3 0 1 1 1 0 1 1 1 1 DB2 0 0 D2 SB2 1 1 1 X Y2 X6 X2 Z2 HVE VPR2 VPR7 1 0 1 BS2 0 0 1 1 DB1 1 1 D1 SB1 1 1 0 X Y1 X5 X1 Z1 HVE VPR1 VPR6 0 TC1 S1 BS1 0 1 0 1 DB0 1 0 D0 SB0 DON E DAL X Y0 X4 X0 Z0 HVE VPR0 VPR5 OC TC0 S0 BS0 X 1 0 1 OM6211 Table 5 INSTRUCTION NOP Reset Write data Read status Display control DESCRIPTION no operation software reset write data to display RAM read one of the status bits; Table 7 display on/off; see Table 6 normal, reverse mode; see Table 6 all pixels on; see Table 6 mirror Y; see Table 6 set Y address; 0 ≤ Y ≤ 5 set X address; 0 ≤ X ≤ 83 set X address; 0 ≤ X ≤ 83 set start ROW, 0 ≤ Z ≤ 47 switch HV-gen on/off; see Table 6 lower part of VPR; see Equation (1) higher part of VPR frame calibration start/stop; see Table 6 set temperature coefficient; see Table 8 set multiplication factor; see Table 3 set bias system; see Table 1 reserved reserved reserved reserved Address commands Display start line Power control Frame calibration TC HV-gen stages Bias system Test Notes 1. X = don’t care. 2. DB7 = MSB. 2002 Jan 17 21 Philips Semiconductors Product specification 48 × 84 dot matrix LCD driver Table 6 Explanations for symbols in Table 5 BIT DON DAL E HVE MY OC Table 7 display off normal display (only if DON = 1) normal display VLCD generator (HV generator) is switched off no Y mirroring stop frame frequency calibration Read status READ STATUS BIT ID1 ID2 ID3 ID4 VM DESCRIPTION fixed value 0 fixed value 1 defined by input pin ID3 defined by input pin ID4 VM LOGIC 0 display on all pixels on LOGIC 1 OM6211 inverse video mode (only if DAL = 0) VLCD generator is switched on Y mirroring start frame frequency calibration DECIMAL +9 +10 +11 +12 +13 +14 +15 −1 −2 −3 TC0 TC1 TC2 TC3 −4 −5 −6 −7 −8 −9 −10 −11 −12 −13 −14 −15 −16 BINARY 01001 01010 01011 01100 01101 01110 01111 11111 11110 11101 11100 11011 11010 11001 11000 10111 10110 10101 10100 10011 10010 10001 10000 SB[2:0] 010 011 100 101 111 Table 8 Temperature coefficients TC[1:0] 00 01 10 11 Table 9 VOS values in two’s complement notation DECIMAL +0 +1 +2 +3 +4 +5 +6 +7 +8 BINARY 00000 00001 00010 00011 00100 00101 00110 00111 01000 2002 Jan 17 22 Philips Semiconductors Product specification 48 × 84 dot matrix LCD driver 13 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); notes 1 and 2. SYMBOL VDD VLCD VI, VO II, IO IDD, ISS, ILCD Ptot Pout Tstg Tj(max) Notes 1. Stresses above those listed under limiting values may cause permanent damage to the device. PARAMETER supply voltage LCD supply voltage input/output voltage (any input/output) DC input or output current VDD, VSS or VLCD current total power dissipation per package power dissipation per output storage temperature maximum junction temperature CONDITIONS MIN. −0.5 −0.5 −0.5 −10 −50 − − −65 − MAX. OM6211 UNIT V V V mA mA mW mW °C °C note 3 +6.5 +9.0 VDD1 + 0.5 +10 +50 100 10 +150 150 2. Parameters are valid over operating temperature range unless otherwise specified. All voltages are referenced to VSS unless otherwise specified. 3. VSS = 0 V. 14 HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is recommended to take normal precautions appropriate to handling MOS devices (see “Handling MOS Devices”). 15 DC CHARACTERISTICS VDD1 = 1.7 to 2.3 V; VDD2 = 2.5 to 4.5 V; VSS = 0 V; VLCD = 4.5 to 9.0 V; Tamb = −40 to +85 °C; unless otherwise specified. SYMBOL Supplies VDD1 VDD2, VDD3 VLCDIN VLCDOUT VLCD(tol) IDD1 IDD2, IDD3 IDD(tot) logic supply voltage supply voltage for voltage multiplier LCD supply voltage generated LCD supply voltage tolerance of generated VLCD VDD1 supply current VDD2 and VDD3 supply current total supply current (VDD1 and VDD2, VDD3) note 2 with calibration; note 3 normal mode; note 4 normal mode; note 4 normal mode; note 4 normal mode; note 5 note 1 1.7 2.5 4.5 6.8 −70 − − − − 1.8 2.78 − − − 2 12 1 78 90 120 2.3 4.5 9.0 − +70 10 − 5 − − − V V V V mV µA µA µA µA µA µA PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Power-down mode; note 4 − Power-down mode; note 4 − 2002 Jan 17 23 Philips Semiconductors Product specification 48 × 84 dot matrix LCD driver OM6211 SYMBOL Logic VIL VIH IOL IOH IL Ro(col) Ro(row) Vbias(col) Vbias(row) Ron(Vos) Roff(Vos) Notes PARAMETER CONDITIONS MIN. TYP. − − − − 4 4 0 0 − − MAX. UNIT LOW-level input voltage HIGH-level input voltage LOW-level output current (SDOUT) HIGH-level output current (SDOUT) leakage current VOL = 0.4 V; VDD1 = 1.8 V VOH = 1.4 V; VDD1 = 1.8 V VI = VDD1 or VSS note 6 note 6 VSS 0.5 − −1 − − −100 −100 − 5 0.3VDD1 V VDD1 − −0.5 +1 V mA mA µA kΩ kΩ mV mV kΩ MΩ 0.7VDD1 − Column and row outputs column output resistance (COL 0 to COL 83) row output resistance (ROW 0 to ROW 47) bias tolerance (COL 0 to COL 83) bias tolerance (ROW 0 to ROW 47) 20 20 +100 +100 Calibration inputs external resistance between a VOS pin and the VSS1 pin for logic 0 external resistance between a VOS pin and the VSS1 pin for logic 1 10 − 1. VDD2 is always equal VDD3. 2. Conditions are: VDD2 = 2.5 V, voltage multiplier = 3VDD2, bias system 1⁄6, VLCD output is loaded by 10 µA, Tamb = 25 °C. 3. Valid for values of temperature, VPR and TC used at the calibration. 4. Conditions are: VDD1 = 1.8 V, VDD2 = 2.78 V, VLCD = 6.8 V, voltage multiplier = 3VDD2, bias system 1⁄6, inputs at VDD1 or VSS, serial interface inactive, internal VLCD generation, VLCD output is loaded by 10 µA; Tamb = 25 °C. 5. Conditions are: VDD1 = 1.8 V, VDD2 = 2.78 V, VLCD = 8.3 V, voltage multiplier = 4VDD2, bias system 1⁄7, inputs at VDD1 or VSS, serial interface inactive, internal VLCD generation, VLCD output is loaded by 10 µA; Tamb = 25 °C. 6. Load current 10 µA, outputs tested one at a time. 2002 Jan 17 24 Philips Semiconductors Product specification 48 × 84 dot matrix LCD driver OM6211 16 AC CHARACTERISTICS VDD1 = 1.7 to 2.3 V; VDD2 = 2.5 to 4.5 V; VSS = 0 V; VLCD = 4.5 to 9.0 V; Tamb = −40 to +85 °C; unless otherwise specified. SYMBOL fosc(int) fframe PARAMETER internal oscillator frequency frame frequency note 1 uncalibrated; note 2 calibrated; notes 3 and 4 calibrated; notes 3 and 5 tVHRL tRW tR(op) VDD1 to RES LOW reset LOW pulse width end of reset pulse to interface being operational see Fig.18; note 6 see Fig.18 CONDITIONS − 46 63 75 0 1000 − MIN. TYP. 251 80 80 80 − − − MAX. − 142 97 85 30 − 1000 UNIT kHz Hz Hz Hz ms ns ns Serial interface timing fSCLK tcyc tPWH1 tPWL1 tS2 tH2 tPWH2 tH5 tS1 tH1 t2 t3 t4 t5 Notes 1. f osc f frame = ------------3136 clock frequency clock cycle SCLK SCLK pulse width HIGH SCLK pulse width LOW SCE set-up time SCE hold time SCE minimum HIGH time SCE start hold time SDIN set-up time SDIN hold time SDOUT access time SDOUT disable time SCE hold time SCE hold time note 8 note 7 0 250 120 100 60 100 100 100 100 100 0 25 100 20 − − − − − − − − − − − − − − 4.00 − − − − − − − − − 450 450 − − MHz ns ns ns ns ns ns ns ns ns ns ns ns ns 2. Temperature range Tamb = −30 to +70 °C. 3. Calibrated at VDD1 = 1.8 V and Tamb = 25 °C, valid for both OTP calibration and software calibration, exact calibration time assumed. 4. Measured at VDD1 = 1.8 V, temperature range Tamb = −30 to +70 °C. 5. Measured at VDD1 = 1.8 V, Tamb = 25 °C. 6. It is recommended that RES is LOW before VDD1 goes HIGH 7. tH5 is the time from the previous SCLK rising edge (irrespective of the state of SCE) to the falling edge of SCE (see Fig.16). 8. Capacitive load at pin SDOUT less than 50 pF. 2002 Jan 17 25 Philips Semiconductors Product specification 48 × 84 dot matrix LCD driver 16.1 Serial interface timing OM6211 handbook, full pagewidth t S2 t H2 t PWH2 SCE t5 t PWL1 SCLK t PWH1 (t H5 ) t S2 t cyc t H5 t S1 SDIN t H1 MGU283 Fig.16 Serial interface timing: write mode. handbook, full pagewidth SCE t4 SCLK t H1 SDIN t3 t2 t S1 t2 SDOUT t2 MGU284 Fig.17 Serial interface timing: read mode. 2002 Jan 17 26 Philips Semiconductors Product specification 48 × 84 dot matrix LCD driver 16.2 Reset timing OM6211 handbook, full pagewidth VDD1 t VHRL RES t R(oper) SCE MGU285 t RW Fig.18 Reset timing. 17 APPLICATION INFORMATION The pinning of the OM6211 is optimized for single plane wiring e.g. for chip-on-glass display modules. Display size: 48 × 84 pixels. handbook, full pagewidth DISPLAY 48 × 84 PIXELS 24 84 24 OM6211 4 Cext I/O VDD1 VDD2 VSS VLCD MGU286 Fig.19 Application diagram. The required minimum value for the two external capacitors (Cext) in an application with the OM6211 is 100 nF (min.). Higher capacitor values are recommended for ripple reduction. 2002 Jan 17 27 Philips Semiconductors Product specification 48 × 84 dot matrix LCD driver 18 MODULE MAKER PROGRAMMING The One Time Programmable (OTP) technology has been implemented on the OM6211. It enables the module maker to program some extended features of the OM6211 after it has been assembled on an LCD module. Programming is made under the control of the serial interface and the use of one special pin. This pin must be made available on the module glass but needs not to be accessed by the set maker. As the module maker programming is an extension of the normal functions of the OM6211 it will not be effective until specifically instructed with the ‘Enable OTP’ command. The OM6211 features 3 module maker programmable parameters: • VLCD calibration • VPR default value • Seal bit. 18.1 VLCD calibration OM6211 This is in the same manner as the on-glass calibration pins VOS (laser trim pins). In theory, both may be used together but it is recommended that the laser trim pins are tied to VSS when OTP calibration is being used. This will set them to a default offset of zero. If both are used then the addition of the two 5-bit numbers must not exceed a 5-bit result otherwise the resultant value will be undefined. The final adder in the circuit has underflow and overflow protection. In the event of an overflow, the output will be clamped to 255; and during an underflow the output will be clamped to 0. The final control to the high voltage generator, VOP, will be the sum of all the calibration registers and pins. The VOP equation (1) given in Section 9.12 must be extended to include the OTP calibration. V OP = V PR + V OS + MMVOPCAL (5) The additional offset applied to VLCD can be calculated from equation (2) and (5), where b is the step size as defined in Table 4. (6) V LCD OFFSET = ( V OS + MMVOPCAL ) × b The possible MMVOPCAL4 to MMVOPCAL0 values are the same as the VOS[4:0] values, see Table 9. The first feature included is the ability to tune the VLCD voltage with a 5-bit code. This code is implemented in two’s complement notation giving rise to a positive or negative offset to the VPR register. handbook, full pagewidth OTP VLCD calibration: 5-bit offset range −16 to +15 MMVOPCAL[4:0] laser trim pins: 5-bit offset VOS[4:0] range −16 to +15 + + VOP [7:0] range: 0 to +255 to high voltage generator range 0 to +255 usable range +32 to +255 VPR register: 8-bit value VPR [7:0] MGU287 Fig.20 VLCD calibration. 2002 Jan 17 28 Philips Semiconductors Product specification 48 × 84 dot matrix LCD driver 18.2 VPR default value OM6211 The second feature is an OTP factory default setting for VPR. This is an 8-bit value from which the VPR register can be loaded using the ‘Load factory default’ command. The idea of this feature is to make it unnecessary for the set maker to specify the VPR value. The factory default may be overridden by the set maker in the normal fashion using the ‘Set VPR’ commands. handbook, full pagewidth interface data load VPR via the interface VPR register: 8-bit value + OTP VPR default register, 8-bit value load VPR from an OTP default register. MGU288 Fig.21 Load VPR register: default or specified via interface. 18.3 Seal bit The module maker programming is performed in a special mode: the calibration mode (CALMM). This mode is entered via a special interface command, CALMM. To prevent wrongful programming, a seal bit has been implemented which prevents the device from entering the calibration mode. This seal bit, once programmed, cannot be reversed, thus further changes in programmed values are not possible. However, it is possible to disable all programmed values by not applying the ‘Enable OTP’ command. Applying the programming voltages when not in CALMM mode will have no effect on the programmed values. Table 10 Seal bit definition SEAL BIT 0 1 18.4 ACTION possible to enter calibration mode calibration mode disabled Each OTP slice consists of 2 main parts: the OTP cell (a non-volatile memory cell) and the shift register cell (a flip-flop). The OTP cells are only accessible through their shift register cells: on the one hand both reading from and writing to the OTP cells is performed with the shift register cells, on the other hand only the shift register cells are visible to the rest of the circuit. The basic OTP architecture is shown in Fig.22. This OTP architecture enables the following operations: 1. Reading data from the OTP cells. The content of the non-volatile OTP cells is transferred to the shift register where it may affect the OM6211 operation (provided it has been enabled by the ‘Enable OTP’ command). 2. Writing data to the OTP cells. Firstly, all 14 bits of data are shifted into the shift register via the serial interface. The content of the shift register is then transferred to the OTP cells (there are some limitations related to storing data in these cells, see Section 18.7). 3. Checking calibration without writing to the OTP cells. Shifting data into the shift register allows the effects on the VLCD voltage to be observed. OTP architecture The OTP circuitry in the OM6211 contains 14 bits of data: 5 for VLCD calibration, 8 for VPR default and 1 seal bit. The circuitry for 1-bit is called an OTP slice, thus there are 14 OTP slices. 2002 Jan 17 29 Philips Semiconductors Product specification 48 × 84 dot matrix LCD driver All OTP circuitry of the OM6211 is disabled until the ‘Enable OTP’ command is given. Once enabled, the reading of data from the OTP cells is initiated by either: • Exit from Power-down mode • The ‘Refresh’ command. It should be noted that in both cases the reading operation needs up to 5 ms to complete. The shifting of data into the shift register is performed in a special mode called CALMM. In the OM6211 the CALMM mode is entered through the CALMM command. Once in the CALMM mode the data is shifted into the shift register via the serial interface at the rate of 1-bit per command. After transmitting the last (14th) bit and exiting the CALMM mode the serial interface returns to the normal mode and all other commands can be sent. Care should be taken that all 14 bits of data (or a multiple of 14) are transferred before exiting the CALMM mode, otherwise the bits will be in the wrong positions. OM6211 In the shift register the value of the seal bit is, like the others, always zero at reset. To ensure that the security feature works correctly, the CALMM command is disabled until a refresh has been performed. Once the refresh is completed, the seal bit value in the shift register is valid and permission to enter CALMM mode can thus be determined. The 14 bits are shifted into the shift register in a predefined order: firstly the 8 bits of MMOTPVOP7 to MMOTPVOP0, then the 5 bits of MMVOPCAL4 to MMVOPCAL0 and lastly the seal bit. The MSB is always first, thus the first bit shifted is MMOTPVOP7 and the two last bits are MMVOPCAL0 and the seal bit. handbook, full pagewidth DATA TO THE CIRCUIT FOR CONFIGURATION AND CALIBRATION OTP slice SHIFT REGISTER FLIP-FLOP SHIFT REGISTER DATA INPUT SHIFT REGISTER read data from the OTP cell write data to the OTP cell OTP CELLs MGU289 OTP CELL Fig.22 Basic OTP architecture. 2002 Jan 17 30 Philips Semiconductors Product specification 48 × 84 dot matrix LCD driver 18.5 Serial interface commands OM6211 These instructions are in addition to those indicated in Table 5. Table 11 Additional instructions COMMAND BYTE INSTRUCTION Enable OTP CALMM Load factory default Power control (refresh) 18.5.1 ENABLE OTP D/C DB7 0 0 0 0 1 1 1 0 DB6 1 1 1 0 DB5 1 1 1 1 DB4 0 0 0 0 DB3 1 1 1 1 DB2 0 1 1 HVE DB1 1 1 0 HVE DB0 1 1 0 enable OTP circuitry enter CALMM mode load MMOTPVOP7 to MMOTPVOP0 into VPR register ACTION HVE set HVE; force a refresh of the shift register This is a special instruction for the OM6211 which enables all included OTP circuitry. Once enabled the mode can only be disabled via a reset. 18.5.2 CALMM During this time all other instructions may be sent, however, instructions requiring the output of the shift register (‘Load factory default’) should be avoided as the register contents may not be valid. In the OM6211 the ‘Refresh’ instruction is associated to the ‘Set HVE’ instruction so that the shift register is automatically refreshed every time the high voltage generator is enabled or disabled. It should be noted however, that if this instruction is sent while in Power-down mode, then the HVE bit is updated but the refreshing is ignored. 18.6 Example of filling the shift register This instruction puts the device into the calibration mode. This mode enables the shift register for loading and allows programming of the non-volatile OTP cells to take place. If the seal bit is set then this mode cannot be accessed and the instruction will be ignored. Once in calibration mode all commands are interpreted as shift register data. The mode can only be exited by sending data with bit DB7 set to logic 0. A reset will also clear this mode. Each shift register data byte is preceded by D/C = 0 and has only 2 significant bits, thus the remaining 6 bits are ignored. Bit DB7 is the continuation bit (DB7 = 1 remain in CALMM mode, DB7 = 0 exit CALMM mode). Bit DB0 is the data bit and its value is shifted into the OTP shift register (on the falling edge of SCLK). 18.5.3 LOAD FACTORY DEFAULT An example sequence of commands and data is shown in Table 12. In this example the shift register is filled with the following data: MMVOPCAL = −4 (11100B), MMOTPVOP = 19 (00010011B) and the seal bit is 0. It is assumed that the OM6211 has just been reset. After transmitting the last bit the OM6211 can exit or remain in CALMM mode (see step 18). It should be noted that while in CALMM mode the interface does not recognize commands in the normal sense. After this sequence has been applied it is possible to observe the impact of the data shifted in. This sequence is, however, not useful for OTP programming because the number of bits with the value ‘1’ is greater than that allowed for programming (see Section 18.7). Figure 23 shows the shift register after this action. The ‘Load factory default’ instruction is used to transfer the contents of the OTP shift register bits MMOTPVOP7 to MMOTPVOP0 into the normal working register of VPR; see Fig.21. This is opposite to the calibration register MMVOPCAL4 to MMVOPCAL0 which is active immediately after a refresh. 18.5.4 REFRESH The action of the ‘Refresh’ instruction is to force the OTP shift register to re-load from the non-volatile OTP cells. This instruction takes up to 5 ms to complete. 2002 Jan 17 31 Philips Semiconductors Product specification 48 × 84 dot matrix LCD driver Table 12 Example sequence for filling the shift register; note 1 COMMAND BYTE STEP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 X X X X X X X X X X X X X X 1 X X X X X X X X X X X X X X 0 X X X X X X X X X X X X X X 1 X X X X X X X X X X X X X X 1 X X X X X X X X X X X X X X 1 X X X X X X X X X X X X X X 1 0 0 0 1 0 0 1 1 1 1 1 0 0 0 D/C DB7 0 0 1 1 DB6 1 0 DB5 1 1 DB4 0 0 DB3 1 1 DB2 0 1 DB1 1 1 DB0 1 1 send enable OTP command ACTION OM6211 exit Power-down (e.g. DON = 1) wait 5 ms for refresh to take effect. enter CALMM mode shift in data; MMOTPVOP7 is first bit; note 2 MMOTPVOP6 MMOTPVOP5 MMOTPVOP4 MMOTPVOP3 MMOTPVOP2 MMOTPVOP1 MMOTPVOP0 MMVOPCAL4 MMVOPCAL3 MMVOPCAL2 MMVOPCAL1 MMVOPCAL0 seal bit; exit CALMM mode An alternative ending could be to stay in CALMM mode 18 Notes 1. X = don’t care. 2. The data for the bits is not in the correct shift register position until all bits have been sent. 0 1 X X X X X X 0 seal bit; remain in CALMM mode handbook, full pagewidth OTP SHIFT REGISTER shifting direction SEAL LSB BIT = 0 0 MMVOPCAL[4:0] MSB LSB 0 1 1 1 1 1 MMOTPVOP[7:0] 0 0 1 0 0 MSB 0 MGU290 Fig.23 Shift register contents after example sequence of Table 12. 2002 Jan 17 32 Philips Semiconductors Product specification 48 × 84 dot matrix LCD driver 18.7 Programming flow OM6211 Once this bit has been programmed it will not be possible to re-enter the CALMM mode. During programming a substantial current flows in the VLCDIN pin. For this reason it is recommended to program only one OTP cell at a time. This is achieved by filling all but one shift register cells with logic 0. It should be noted that the programming specification refers to the voltages at the chip pins, contact resistance must therefore be considered by the user. An example sequence of commands and data for OTP programming is shown in Table 13. It is assumed that the OM6211 has just been reset. Programming is achieved whilst in CALMM mode and with the application of the programming voltages. As mentioned previously, the data for programming the OTP cell is contained in the corresponding shift register cell. The shift register cell must be loaded with a logic 1 in order to program the corresponding OTP cell. If the shift register cell contains a logic 0, then no action will take place when the programming voltages are applied. Once programmed, an OTP cell can not be un-programmed. An already programmed cell, that is an OTP cell containing a logic 1, must not be re-programmed. The order for programming cells is not significant. However, it is recommended that the seal bit is programmed last. Table 13 Example sequence for OTP programming; note 1 STEP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 D/C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMMAND BYTE DB7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DB6 1 0 0 1 X X X X X X X X X X X X X X DB5 1 1 1 1 X X X X X X X X X X X X X X DB4 0 0 0 0 X X X X X X X X X X X X X X DB3 1 1 1 1 X X X X X X X X X X X X X X DB2 0 1 1 1 X X X X X X X X X X X X X X DB1 1 1 1 1 X X X X X X X X X X X X X X DB0 1 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 ACTION send Enable OTP command exit Power-down (e.g. DON = 1) wait 5 ms for refresh to take effect re-enter Power-down (DON = 0) enter CALMM mode shift in data. MMOTPVOP7 MMOTPVOP6 MMOTPVOP5 MMOTPVOP4 (the only bit with the value 1) MMOTPVOP3 MMOTPVOP2 MMOTPVOP1 MMOTPVOP0 MMVOPCAL4 MMVOPCAL3 MMVOPCAL2 MMVOPCAL1 MMVOPCAL0 seal bit; remain in CALMM mode apply programming voltage at pins T6 and VLCDIN according to Section 18.8 apply external reset Repeat steps 6 to 20 for each bit that should be programmed to 1 21 Note 1. X = don’t care. 2002 Jan 17 33 Philips Semiconductors Product specification 48 × 84 dot matrix LCD driver 18.8 Programming specification OM6211 Table 14 Programming specification; see Fig.24 SYMBOL VT6 PARAMETER CONDITION MIN. 11 TYP. 11.5 MAX. 12 0.2 10 +4.5 1000 200 40 − − 10 10 200 UNIT V V V V µA µA °C µs µs ms ms ms voltage applied to T6 pin relative to VSS1 programming active; notes 1 and 2 programming inactive; notes 1 and 2 VSS − 0.2 0 9 −0.2 − − 0 1 1 1 1 100 9.5 0 850 100 25 − − − − 120 VLCDIN voltage applied to VLCDIN pin relative to VSS1 programming active; notes 1 and 3 programming inactive; notes 1 and 3 ILCDIN IT6 Tamb(prog) tsu;SCLK th;SCLK tsu;T6 th;T6 tW Notes current drawn by VLCDIN during programming current drawn by VT6 during programming ambient temperature during programming set-up of internal data after last clock hold of internal data before next clock set-up of VT6 prior to programming hold of VT6 after programming pulse width of programming voltage when programming a single bit to logic 1 1. The voltage drop across the ITO track and zebra connector must be taken into account to guarantee sufficient voltage at the chip pins. 2. The maximum voltage must not be exceeded even for a short period of time. Therefore care must be taken when applying programming waveforms to avoid overshoot. 3. The Power-down mode (DON = 0 and DAL = 1) and CALMM mode must be active while the VLCDIN pin is being driven. handbook, full pagewidth tsw;SCLK th;SCLK SCLK VT6 VLCDIN tsw;T6 tw th;T6 MGU291 Fig.24 Programming waveforms. 2002 Jan 17 34 Philips Semiconductors Product specification 48 × 84 dot matrix LCD driver 19 BONDING PAD LOCATIONS Table 15 Bonding pad information PAD Pad pitch Pad size (aluminium) CBB opening Bump dimensions Wafer thickness (excluding bumps) ROWS AND COLS SIDE minimum 60 50 × 90 26 × 66 40 × 80 × 17.5 (±5) 381 (±25) INTERFACE SIDE minimum 70 60 × 100 36 × 76 50 × 90 × 17.5 (±5) µm µm µm µm µm OM6211 UNIT handbook, halfpage 9.46 mm handbook, halfpage 1.91 mm OM6211 y center pitch y x 100 µm x center MGT855 MGU292 Fig.25 Chip size and pad pitch. Fig.26 Shape of alignment mark. 2002 Jan 17 35 Philips Semiconductors Product specification 48 × 84 dot matrix LCD driver Table 16 Bonding pad location All x and y co-ordinates are referenced to the centre of the chip (dimensions in µm; see Fig.27). COORDINATES SYMBOL Dummy Alignment mark VOS4 VOS3 VOS2 VOS1 VOS0 T6 T6 T6 T6 Dummy Dummy Dummy Dummy RES T5 T4 T3 T2 T1 SCE VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 2002 Jan 17 PAD x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 −835 −825 −835 −835 −835 −835 −835 −835 −835 −835 −835 −835 −835 −835 −835 −835 −835 −835 −835 −835 −835 −835 −835 −835 −835 −835 −835 −835 −835 −835 −835 −835 −835 −835 −835 −835 −835 y +4630 +4527.5 +4425 +4215 +4005 +3795 +3585 +3375 +3305 +3235 +3165 +3095 +3025 +2955 +2885 +2395 +2185 +1975 +1765 +1555 +1345 +1135 +1065 +995 +925 +855 +785 +715 +645 +575 +505 +435 +365 +295 +225 +155 +85 36 OM6211 COORDINATES SYMBOL VSS1 Dummy OSC SDOUT SDIN SCLK ID4 ID3 MX VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD3 VDD3 VDD3 VDD3 VLCDSENSE VLCDOUT VLCDOUT VLCDOUT VLCDOUT VLCDOUT VLCDOUT VLCDOUT VLCDIN VLCDIN VLCDIN VLCDIN PAD x 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 −835 −835 −835 −835 −835 −835 −835 −835 −835 −835 −835 −835 −835 −835 −835 −835 −835 −835 −835 −835 −835 −835 −835 −835 −835 −835 −835 −835 −835 −835 −835 −835 −835 −835 −835 −835 −835 −835 −835 y +15 −405 −825 −1035 −1245 −1455 −1665 −1875 −2085 −2155 −2225 −2295 −2365 −2435 −2505 −2575 −2645 −2715 −2785 −2855 −2925 −2995 −3065 −3135 −3205 −3275 −3345 −3415 −3485 −3555 −3625 −3695 −3765 −3835 −3905 −3975 −4045 −4115 −4185 Philips Semiconductors Product specification 48 × 84 dot matrix LCD driver OM6211 COORDINATES SYMBOL VLCDIN VLCDIN Dummy Alignment mark Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy ROW 0 ROW 1 ROW 2 ROW 3 ROW 4 ROW 5 ROW 6 ROW 7 ROW 8 ROW 9 ROW 10 ROW 11 ROW 12 ROW 13 ROW 14 ROW 15 ROW 16 ROW 17 ROW 18 ROW 19 ROW 20 ROW 21 ROW 22 ROW 23 COL 0 COL 1 COL 2 PAD x 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 −835 −835 −835 −825 −835 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 y −4255 −4325 −4395 −4500 −4605 −4590 −4530 −4470 −4410 −4350 −4290 −4230 −4050 −3990 −3930 −3870 −3810 −3750 −3690 −3630 −3570 −3510 −3450 −3390 −3330 −3270 −3210 −3150 −3090 −3030 −2970 −2910 −2850 −2790 −2730 −2670 −2490 −2430 −2370 COL 3 COL 4 COL 5 COL 6 COL 7 COL 8 COL 9 COL 10 COL 11 COL 12 COL 13 COL 14 COL 15 COL 16 COL 17 COL 18 COL 19 COL 20 COL 21 COL 22 COL 23 COL 24 COL 25 COL 26 COL 27 COL 28 COL 29 COL 30 COL 31 COL 32 COL 33 COL 34 COL 35 COL 36 COL 37 COL 38 COL 39 COL 40 COL 41 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 SYMBOL PAD COORDINATES x +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 y −2310 −2250 −2190 −2130 −2070 −2010 −1950 −1890 −1830 −1770 −1710 −1650 −1590 −1530 −1470 −1410 −1350 −1290 −1230 −1170 −1110 −1050 −990 −930 −870 −690 −630 −570 −510 −450 −390 −330 −270 −210 −150 −90 −30 +30 +90 2002 Jan 17 37 Philips Semiconductors Product specification 48 × 84 dot matrix LCD driver OM6211 COORDINATES SYMBOL COL 42 COL 43 COL 44 COL 45 COL 46 COL 47 COL 48 COL 49 COL 50 COL 51 COL 52 COL 53 COL 54 COL 55 COL 56 COL 57 COL 58 COL 59 COL 60 COL 61 COL 62 COL 63 COL 64 COL 65 COL 66 COL 67 COL 68 COL 69 COL 70 COL 71 COL 72 COL 73 COL 74 COL 75 COL 76 COL 77 COL 78 COL 79 COL 80 PAD x 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 y +150 +210 +270 +330 +390 +450 +510 +570 +630 +690 +750 +810 +870 +930 +1110 +1170 +1230 +1290 +1350 +1410 +1470 +1530 +1590 +1650 +1710 +1770 +1830 +1890 +1950 +2010 +2070 +2130 +2190 +2250 +2310 +2370 +2430 +2490 +2550 COL 81 COL 82 COL 83 ROW 47 ROW 46 ROW 45 ROW 44 ROW 43 ROW 42 ROW 41 ROW 40 ROW 39 ROW 38 ROW 37 ROW 36 ROW 35 ROW 34 ROW 33 ROW 32 ROW 31 ROW 30 ROW 29 ROW 28 ROW 27 ROW 26 ROW 25 ROW 24 Dummy Dummy Dummy Dummy Dummy 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 SYMBOL PAD COORDINATES x +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 +840 y +2610 +2670 +2730 +2910 +2970 +3030 +3090 +3150 +3210 +3270 +3330 +3390 +3450 +3510 +3570 +3630 +3690 +3750 +3810 +3870 +3930 +3990 +4050 +4110 +4170 +4230 +4290 +4350 +4410 +4470 +4530 +4590 2002 Jan 17 38 Philips Semiconductors Product specification 48 × 84 dot matrix LCD driver OM6211 dummy pad OM6211-1 VOS4 VOS3 VOS2 VOS1 VOS0 T6 dummy pad alignment mark dummy pad ROW 24 ROW 47 COL 83 RES T5 T4 T3 T2 T1 SCE VSS2 COL 56 COL 55 VSS1 y 0, 0 dummy pad x COL 28 OSC SDOUT SDIN SCLK ID4 ID3 MX VDD1 COL 27 COL 0 ROW 23 VDD2 VDD3 VLCDSENSE VLCDOUT VLCDIN dummy pad alignment mark dummy pad MGU293 ROW 0 dummy pad Fig.27 Pad locations. 2002 Jan 17 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Philips Semiconductors Product specification 48 × 84 dot matrix LCD driver 20 DEVICE PROTECTION DIAGRAM OM6211 handbook, full pagewidth VDD1 VDD2 VDD3 VSS1 VSS1 VSS2 VSS1 VSS2 VLCDIN(SUPPLY), VLCDSENSE VSS1 VLCDOUT VSS1 VSS1 VDD1 VDD1 VLCDIN VOS[4:0] T6 COL0 to COL83 ROW0 to ROW47 VSS1 VSS1 VSS1 VDD1 VLCDIN OSC, SDIN, SCLK, SCE, RES, T4, T5, MX, ID3, ID4 VSS1 SDOUT, T1, T2, T3 VSS1 MGU294 The conditions for continuity tests are as follows: Maximum forward current = 5 mA; Maximum reverse voltage = 5 V. Fig.28 Device protection diagram. 2002 Jan 17 40 Philips Semiconductors Product specification 48 × 84 dot matrix LCD driver 21 TRAY INFORMATION OM6211 handbook, full pagewidth x A C y 1,1 1,2 1,3 2,1 2,2 3,1 x,1 D B F 1,y x,y E MGU295 Fig.29 Tray details. Table 17 Tray dimensions DIMENSION handbook, halfpage DESCRIPTION pocket pitch x direction pocket pitch y direction VALUE 13.76 mm 4.45 mm A B C D E F x MGU296 pocket width x direction 9.56 mm pocket width y direction 2.00 mm tray width x direction tray width y direction number of pockets in x direction number of pockets in y direction 50.80 mm 50.80 mm 3 10 The orientation of the IC in a pocket is indicated by the position of the IC type name on the die surface with respect to the chamfer on the upper left corner of the tray. Refer to the bonding pad location diagram for the orientation and position of the type name on the surface. Fig.30 Tray alignment. 2002 Jan 17 OM6211-1 y 41 Philips Semiconductors Product specification 48 × 84 dot matrix LCD driver 22 APPLICATION NOTES When reading the VM bit in the OM6211 two problems have been observed: corrupted format and VM bit toggling. 22.1 Corrupted format OM6211 For the loop time limit a value of not less than 85 ms is suggested. It should be noted that the value of 45 ms specified in Section 11.2.2 means that after at least 45 ms the VM measurement is possible. In practice it can be expected that VM is valid earlier than 45 ms. Therefore the proposed algorithm results in an optimization of the 45 ms wait time needed to charge the external VLCD capacitor. So the selected loop time limit of 85 ms consists of 45 ms wait time and an additional 40 ms of measurement time. The loop time limit of 85 ms will ensure that even if the first VM = 1 value for any reason should be missed, there is always the possibility to hit the next VM = 1 value (note that the internal VM measurement is made once per 12.5 ms). However, the expectation is that the average running time of the loop will be less than 45 ms. There is another possibility for optimization: during the wait time of the loop (1 ms) other tasks can be performed. Furthermore the first part of the 45 ms wait time, just after setting HVE = 1, may also be used for other tasks. For instance when the first 20 ms are reserved for those tasks, then the corresponding loop time limit would be 65 ms and the expected average loop time would be less than 25 ms. After the VM test is completed the VPR can be set to the desired value (e.g. VPR = 137) without the charge pump being switched off. The read-out of the VM bit has a special format, 11110000 for VM = 1 and 00001111 for VM = 0. However, sometimes a wrong format of the read-out byte can be observed; the first or the fifth or the eighth bit appears to be wrong. There are two reasons for this behaviour. When the first bit happens to be read out at the end of a frame then it is possible that the first bit belongs to the old VM value and the 7 following bits belong to the new VM value. Such behaviour is possible for the first bit only. The second reason is the violation of the OM6211 timing, if the timing parameters t2 and t3 (see Fig.17) are violated, then it results in reading a wrong value for the first, the fifth or the eighth bit. Thus, to prevent any problems with the wrong format of the read-out byte, these bits should always be ignored. 22.2 VM bit toggling Under certain conditions it can happen that the result of reading VM is 0 even if the generated VLCD voltage is correct (VM bit toggles). It is therefore recommended to repeat the VM read command several times according to the algorithm described below. This algorithm is based on the observation that a single reading of VM = 1 (after numerous readings of VM = 0) is enough to ensure that the charge pump operation is correct. One possible method which gives minimum measurement duration is shown in Fig.31 and described in detail below: • Perform initialization with Enable OTP and set the operational parameters (VPR = 159, S = 10, BS = 101, TC = 1, E = 0 and MY = 0) this results in a slightly higher VLCD voltage than for normal operation (VLCD = 8.732 V at Tamb = 27 °C) • Select DAL = 1 and DON = 1 (for all pixels on) • After setting HVE = 1 start a loop of a continuous VM reading (for example, every 1 ms), at first occurrence of reading VM = 1 interrupt the loop and accept VM = 1 • When the reading is always VM = 0, stop the loop after a certain time and accept VM = 0. This loop time limit should be chosen sufficiently long, e.g. 85 ms. Given that the uncertainty is much less then 0.1%, much less then 1 ppm is expected to be read out wrong. 2002 Jan 17 42 Philips Semiconductors Product specification 48 × 84 dot matrix LCD driver OM6211 handbook, halfpage initialization HVE = 1 loop_time_limit = 85 ms reset time_counter read VM bit wait 1 ms VM = 1 ? no yes yes time_counter < loop_time_limit? no end MGU521 Fig.31 Algorithm of reliable and fast read-out of the VM bit. 2002 Jan 17 43 Philips Semiconductors Product specification 48 × 84 dot matrix LCD driver 23 DATA SHEET STATUS DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2) Development DEFINITIONS OM6211 This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. Preliminary data Qualification Product data Production Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 24 DEFINITIONS Short-form specification  The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition  Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information  Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 25 DISCLAIMERS Life support applications  These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes  Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 2002 Jan 17 44 Philips Semiconductors Product specification 48 × 84 dot matrix LCD driver NOTES OM6211 2002 Jan 17 45 Philips Semiconductors Product specification 48 × 84 dot matrix LCD driver NOTES OM6211 2002 Jan 17 46 Philips Semiconductors Product specification 48 × 84 dot matrix LCD driver NOTES OM6211 2002 Jan 17 47 Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. © Koninklijke Philips Electronics N.V. 2002 SCA74 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 403512/01/pp48 Date of release: 2002 Jan 17 Document order number: 9397 750 07744