OQ2541HP

INTEGRATED CIRCUITS DATA SHEET OQ2541HP; OQ2541U SDH/SONET data and clock recovery unit STM1/4/16 OC3/12/48 GE Product specification Supersedes data of 1999 Mar 19 File under Integrated Circuits, IC19 1999 May 27 Philips Semiconductors Product specification SDH/SONET data and clock recovery unit STM1/4/16 OC3/12/48 GE FEATURES • Data and clock recovery up to 2.5 Gbits/s • Multirate configurable (155, 622, 1250 or 2500 Mbits/s) • Differential data input with 2.5 mV (p-p) typical sensitivity • Differential Current-Mode Logic (CML) data and clock outputs with 50 Ω driving capability • Adjustable CML output level • Loop mode for system testing • Bit error rate related loss of signal detection • Few external components needed • Single supply voltage • Power dissipation 350 mW (typical value) • LQFP48 plastic package. ORDERING INFORMATION TYPE NUMBER OQ2541HP OQ2541U PACKAGE NAME LQFP48 − DESCRIPTION APPLICATIONS OQ2541HP; OQ2541U • Data and clock recovery in STM1/OC3, STM4/OC12 and STM16/OC48 transmission systems • Data and clock recovery in Gigabit Ethernet (GE) transmission systems. DESCRIPTION The OQ2541 is a data and clock recovery IC intended for use in Synchronous Digital Hierarchy (SDH) and Synchronous Optical Network (SONET) systems. The circuit recovers data and extracts the clock signal from an incoming bitstream up to 2.5 Gbits/s. It can be configured for use in STM1/OC3, STM4/OC12, STM16/OC48 and Gigabit Ethernet systems. VERSION SOT313-2 − plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm bare die; 2360 × 2360 × 380 µm 1999 May 27 2 Philips Semiconductors Product specification SDH/SONET data and clock recovery unit STM1/4/16 OC3/12/48 GE BLOCK DIAGRAM OQ2541HP; OQ2541U handbook, full pagewidth LOS 39 DOUT622 DOUT1250 DOUT155 27 28 30 AREF 48 ENL 1 FREQUENCY DIVIDER 1 1/2/4/16 42 43 45 DATA AND CLOCK OUTPUT 46 6 7 3 4 DOUT DOUTQ COUT COUTQ DLOOP DLOOPQ CLOOP CLOOPQ 33 DIN 34 DINQ ALEXANDER PHASE DETECTOR OQ2541 enable 21 22 FREQUENCY WINDOW DETECTOR (1000 ppm) CREF CREFQ + ∫ dt 130 pF proportional path VCRO 2.5 GHz integrating path 130 pF POWER CONTROL 37 i.c. 5 13, 18, 19, 36, 40 FREQUENCY DIVIDER 2 64/128 12 LOCK 9 DREF19 24 16 15 PC 17 2, 5, 8, 10, 11, 14, 17, 20, 23, 26, 29, 32, 35, 38, 41, 44, 47 25 VEE1 31 MBH972 GND DREF39 CAPDOQ CAPUPQ VEE2 Fig.1 Block diagram. 1999 May 27 3 Philips Semiconductors Product specification SDH/SONET data and clock recovery unit STM1/4/16 OC3/12/48 GE PINNING SYMBOL ENL GND CLOOP CLOOPQ GND DLOOP DLOOPQ GND DREF19 GND GND LOCK i.c. GND CAPUPQ CAPDOQ GND i.c. i.c. GND CREF CREFQ GND DREF39 VEE1 GND DOUT1250 DOUT622 GND DOUT155 VEE2 GND DIN DINQ GND i.c. PC GND LOS i.c. 1999 May 27 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 loop mode enable input (active LOW) ground; note 1 clock output in loop mode (differential) inverted clock output in loop mode (differential) ground; note 1 data output in loop mode (differential) inverted data output in loop mode (differential) ground; note 1 reference frequency select input 1 (see Table 2) ground; note 1 ground; note 1 phase lock detection output internally connected; note 2 ground; note 1 external loop filter capacitor connection external loop filter capacitor return connection ground; note 1 internally connected; note 2 internally connected; note 2 ground; note 1 reference clock input (differential) inverting reference clock input (differential) ground; note 1 reference frequency select input 2 (see Table 2) negative supply voltage (−3.3 V); note 3 ground; note 1 STM mode select input 1 (see Table 3) STM mode select input 2 (see Table 3) ground; note 1 STM mode select input 3 (see Table 3) negative supply voltage (−3.3 V); note 3 ground; note 1 data input (differential) inverting data input (differential) ground; note 1 internally connected; note 2 control output for negative power supply ground; note 1 loss of signal detection output internally connected; note 2 4 DESCRIPTION OQ2541HP; OQ2541U Philips Semiconductors Product specification SDH/SONET data and clock recovery unit STM1/4/16 OC3/12/48 GE SYMBOL GND DOUT DOUTQ GND COUT COUTQ GND AREF Notes PIN 41 42 43 44 45 46 47 48 ground; note 1 data output in normal mode (differential) inverted data output in normal mode (differential) ground; note 1 clock output in normal mode (differential) inverted clock output in normal mode (differential) ground; note 1 DESCRIPTION OQ2541HP; OQ2541U reference voltage input for controlling voltage swing on data and clock outputs 1. ALL GND pins or pads must be bonded; do not leave one single GND pin or pad unconnected. 2. ALL pins or pads denoted ‘i.c.’ should not be connected. Connections to these pins or pads degrade device performance. 3. ALL VEE pins or pads must be bonded; do not leave one single VEE pin or pad unconnected. 46 COUTQ 45 COUT 42 DOUT 48 AREF handbook, full pagewidth 43 DOUTQ 38 GND 41 GND 44 GND 47 GND 39 LOS 37 PC 40 i.c. ENL 1 36 i.c. 35 GND 34 DINQ 33 DIN 32 GND GND 2 CLOOP 3 CLOOPQ 4 GND 5 DLOOP 6 DLOOPQ 7 GND 8 DREF19 9 GND 10 GND 11 LOCK 12 OQ2541HP 31 VEE2 30 DOUT155 29 GND 28 DOUT622 27 DOUT1250 26 GND 25 VEE1 DREF39 24 CREF 21 CAPUPQ 15 CAPDOQ 16 CREFQ 22 i.c. 13 GND 14 GND 17 i.c. 18 i.c. 19 GND 20 GND 23 MBH971 Fig.2 Pin configuration. 1999 May 27 5 Philips Semiconductors Product specification SDH/SONET data and clock recovery unit STM1/4/16 OC3/12/48 GE FUNCTIONAL DESCRIPTION The OQ2541 recovers data and clock signals from an incoming high speed bitstream. The input signal on pins DIN and DINQ is buffered and amplified by the input circuitry (see Fig.1). The signal is then fed to the Alexander phase detector where the phase of the incoming data signal is compared with that of the internal clock. If the signals are out of phase, the phase detector generates correction pulses (up or down) that shift the phase of the Voltage Controlled Ring Oscillator (VCRO) output in discrete amounts (∆ϕ) until the clock and data signals are in phase. The technique used is based on principles first proposed by J.D.H. Alexander, hence the name of the phase detector. Data sampling The eye pattern of the incoming data is sampled at three instants A, T and B (see Fig.3). When clock and data signals are synchronized (locked): • A is the centre of the data bit • T is in the vicinity of the next transition • B is in the centre of the bit following the transition. If the same level is recorded at both A and B, a transition has not occurred and no action is taken regardless of the level T. However, if levels A and B are different a transition has occurred and the phase detector uses level T to determine whether the clock was too early or too late with respect to the data transition. If levels A and T are the same, but different from level B, the clock was too early and needs to be slowed down a little. The Alexander phase detector then generates a down pulse which stretches a single output pulse from the ring oscillator by approximately 0.25% which is 1 ps of the 400 ps bit period in the STM16/OC48 mode. This forces the VCRO to run at a slightly lower frequency for one bit period. The phase of the clock signal is thus shifted fractionally with respect to the data signal. OQ2541HP; OQ2541U If, on the other hand, levels B and T are the same but different from level A, the clock was too late and needs to be speeded up for synchronization. The phase detector generates an up pulse forcing the VCRO to run at a slightly higher frequency (+0.25%) for one bit period. The phase of the clock signal is shifted with respect to the data signal (as above, but in the opposite direction). Only the proportional path is active while these phase adjustments are being made. Because the instantaneous frequency of the VCRO can be changed only in one of two discrete steps (±0.25%), this type of loop is also known as a Bang/Bang Phase-Locked Loop (PLL). If not only the phase but also the frequency of the VCRO is incorrect, a long train of up or down pulses will be generated. This pulse train is integrated to generate a control voltage that is used to shift the centre frequency of the VCRO. Once the correct frequency has been established, only the phase will need to be adjusted for synchronization. The proportional path adjusts the phase of the clock signal, whereas the integrating path adjusts the centre frequency. Frequency window detector The frequency window detector checks the VCRO frequency which must be within a 1000 ppm (parts per million) window around the required frequency. It compares the output of frequency divider 2 with the reference frequency on pins CREF and CREFQ (19.44 or 38.88 MHz; see Table 2). If the VCRO frequency is found to be outside this window, the frequency window detector disables the Alexander phase detector and forces the VCRO output to a frequency within the window. The phase detector then starts acquiring lock again. Because of the loose coupling of 1000 ppm, the reference frequency does not need to be highly accurate or stable. Any crystal based oscillator that generates a reasonably accurate frequency (e.g. 100 ppm) will do. Since sampling point A is always in the centre of the eye pattern when the data and clock signals are in phase (locked), the values recorded at this point are taken as the retrieved data. The data and clock signals are available at the CML output buffers, which are capable of driving a 50 Ω load. RF data and clock input circuit The schematic of the input circuit is shown in Fig.4. handbook, halfpage DATA A CLOCK T B MGK143 RF data and clock output circuit Fig.3 Data sampling. The schematic of the output circuit is shown in Fig.5. 1999 May 27 6 Philips Semiconductors Product specification SDH/SONET data and clock recovery unit STM1/4/16 OC3/12/48 GE OQ2541HP; OQ2541U handbook, halfpage 100 Ω 50 Ω DIN, CREF 50 Ω DINQ, CREFQ 100 Ω DOUTQ, COUTQ DOUT, COUT VAREF VEE MGL669 MGL670 VEE Fig.4 RF data and clock input circuit. Fig.5 RF data and clock output circuit. Power supply and power control loop The OQ2541 contains an on-board voltage regulator. An external power transistor is needed to deliver the supply to this circuit. The required external circuit is straightforward, and can be built using a few components. A suitable circuit with a power supply of −4.5 V is illustrated in Fig.6. A different configuration could be used, as long as the power supply rejection ratio is greater than 60 dB for all frequencies. The inductor is a RF choke with an impedance greater than 50 Ω at frequencies higher than 2 MHz. Any transistor with a β > 100 and enough current sink capability can be used. The OQ2541 can also be used with a power supply of −5.0 or −5.2 V. The only adaptation to be made to the power control circuit is to change the emitter resistor R1 (see Table 1). Table 1 Value of resistor R1. RESISTOR R1 2.0 Ω 6.8 Ω 8.2 Ω −4.5 V −5.0 V −5.2 V Output amplitude reference The voltage swing at the CML compatible output stages (pins DOUT, DOUTQ, COUT, COUTQ, DLOOP, DLOOPQ, CLOOP and CLOOPQ) can be controlled by adjusting the voltage on pin AREF (see Fig.7). An internal voltage divider of 500 Ω and 16 kΩ connected between ground and VEE initially fixes this level. In most applications the outputs will be DC-coupled to a load of 50 Ω. The output level regulation circuit will maintain a 200 mV (p-p) single-ended swing across this load. The voltage on pin AREF is half the single-ended peak-to-peak value of the output signal (−100 mV). No adjustments are necessary with DC-coupling. If the outputs are AC-coupled, the voltage on pin AREF is half the single-ended peak-to-peak value of the output RL + Ro signal multiplied by a factor ------------------RL where RL is the external load and Ro is the output impedance of the OQ2541 (100 Ω). POWER SUPPLY 1999 May 27 7 Philips Semiconductors Product specification SDH/SONET data and clock recovery unit STM1/4/16 OC3/12/48 GE OQ2541HP; OQ2541U handbook, full pagewidth BAND GAP REFERENCE on chip VEE PC GND off chip 100 nF 2Ω β > 100 1 kΩ R1 2Ω 1 kΩ 3.3 nF 1 µF L1(1) −4.5 V MGL732 (1) L1 = RF choke type Murata BLM21 or equivalent. Fig.6 Schematic diagram of OQ2541 power control loop. If the outputs are AC-coupled, the formulae for calculating the required voltage on pin AREF and the value of the resistor connected between pins AREF and VEE as follows: RL + Ro V AREF = – ------------------- × 0.5V swing RL GND 500 Ω AREF 16 kΩ VEE on chip off chip MGL667 (1) handbook, halfpage and: VAREF RAREF R AREF  V EE  R1 ×  ---------------- – 1   V AREF  = -------------------------------------------------------------- R1  V EE  1 –  ------- ×  ---------------- – 1    R2  V AREF  (2) where R1 = 500 Ω, R2 = 16 kΩ and VEE = −3.3 V. To maintain a single-ended swing of 200 mV (p-p) across a 50 Ω AC-coupled load, the voltage on pin AREF must be ( 50 + 100 ) Ω – 100 mV × ---------------------------------- = – 300 mV 50 Ω This can be achieved by connecting a 7.3 kΩ resistor between pins AREF and VEE. Fig.7 Functionality of pin AREF. 1999 May 27 8 Philips Semiconductors Product specification SDH/SONET data and clock recovery unit STM1/4/16 OC3/12/48 GE External capacitor for loop filter The loop filter is an integrator with a built-in capacitance of 2 × 130 pF. An external capacitance of 200 nF must be connected between pins CAPUPQ and CAPDOQ to ensure loop stability while the frequency window detector is active. Loop mode enable The loop mode is provided for system testing (see Fig.8). The loop mode is enabled by applying a voltage lower than 0.8 V (TTL LOW-level) to pin ENL. This selects the loop mode: the outputs on pins DLOOP, DLOOPQ, CLOOP and CLOOPQ are switched on. If a voltage higher than 2.0 V (TTL HIGH-level) is applied to pin ENL, then pins DOUT, DOUTQ, COUT and COUTQ are switched on while pins DLOOP, DLOOPQ, CLOOP and CLOOPQ are disabled to minimize power consumption. If pin ENL is connected to VEE (−3.3 V), all outputs are enabled. OQ2541HP; OQ2541U Pin LOCK is an open-collector TTL output and should be pulled up with a 10 kΩ resistor to a positive supply voltage. If the VCO frequency is within a 1000 ppm window around the desired frequency, pin LOCK will remain at a HIGH-level. If no reference clock is present, or the VCO is outside the 1000 ppm window, pin LOCK will be at a LOW-level. The logic level on pin LOCK does not indicate locking of the PLL to the incoming data; this is indicated by the signal on pin LOS. Loss of signal detection The Loss Of Signal (LOS) function is closely related to the functionality of the Alexander phase detector; see Fig.3 for the meaning of A, B and T in this section. In the functional description it is described that the phase detector does not take any action if the value at sample points A and B are the same, because there has not been any transition. However, if levels A and B are the same but different from level T, this still means there has not been any transition, but level T has got the wrong level somehow. This is probably due to noise or bad signal integrity, which will lead to a bit error. Hence the occurrence of this particular situation is an indication for bit errors. If too many of these bit errors occur per time and the PLL is gradually losing lock, the LOS alarm is asserted. The LOS alarm assert level is around a Bit Error Rate (BER) for BER = 5 ⋅ 10−2 and the de-assert level is around BER = 1 ⋅ 10−3. The LOS function will only work properly if the input signal is larger than the input offset of the OQ2541; otherwise, the signal will be masked by the input offset and interpreted as consecutive bits of the same sign, thus obstructing a proper LOS detection. In practice an optical front-end device with a noise level (RMS value) larger than the specified offset of the OQ2541 will ensure a proper LOS indication. The LOS detection is BER related, but neither dependent on the data stream content, nor protocol. Therefore, an SDH/SONET data stream is no prerequisite for a proper LOS function. Since the LOS function of the OQ2541 is derived from digital signals, it is a good supplement to an analog, amplitude based, LOS indication. Pin LOS is an open-collector TTL compatible output. A pull-up resistor should be connected to a positive supply voltage. Pin LOS will be at a HIGH-level (TTL) if the data signal is absent on pins DIN and DINQ or if BER > 5 ⋅ 10−2; otherwise pin LOS will be at a LOW-level if BER < 1 ⋅ 10−3. handbook, halfpage off chip on chip ENL 36 kΩ GND DECODER LOGIC VEE MGL668 Fig.8 Input circuit of pin ENL. Lock detection Pin LOCK should be interpreted as an indication for the presence of the reference clock on pin CREF and for properly functioning of the acquisition aid (frequency window detector). 1999 May 27 9 Philips Semiconductors Product specification SDH/SONET data and clock recovery unit STM1/4/16 OC3/12/48 GE Reference frequency select A reference clock signal of 19.44 or 38.88 MHz must be connected to pins CREF and CREFQ. It should be noted that the reference frequency should be either 39.0625 MHz or 19.53125 MHz in a Gigabit Ethernet system. Pins DREF19 and DREF39 are used to select the appropriate output frequency at frequency divider 2 (see Table 2). To minimize the adverse influence of reference clock crosstalk, a differential signal with an amplitude from 75 to 150 mV (p-p) is advised. Since the reference clock is only used as an acquisition aid for the PLL of the frequency window detector, the quality of the reference clock (i.e. phase noise) is not important. There is no phase noise specification imposed on the reference clock generator and even frequency stability may be in the order of 100 ppm. In general, most inexpensive crystal based oscillators are suitable. When the OQ2541 is used in an application with a fixed reference clock frequency, it is best to connect the planes of pins DREF19 and DREF39 with a short trace or a via to the plane of pin GND or pin VEE. If a selectable reference clock frequency is required in the application, the pins can be controlled through low ohmic switching FETs, e.g. BSH103 or equivalent (low RDSon). Table 2 Reference frequency selection DIVISION FACTOR 64 128 LEVEL ON PIN DREF19 ground VEE DREF39 VEE VEE OQ2541HP; OQ2541U Due to the nature of the PLL, the very wide tuning range is a necessity for proper lock behaviour over the guaranteed temperature range, aging and batch to batch spread. Though it might seem that the OQ2541 is capable of recovering other bit rates than SDH/SONET and Gigabit Ethernet rates (STM1/OC3, STM4/OC12, STM16/OC48 and 1250 Mbits/s), the behaviour can not be guaranteed. The required SDH/SONET bit rate is selected by connecting pins DOUT155, DOUT622 and DOUT1250 to ground or to the supply voltage VEE (see Table 3): • For STM16/OC48 (2488.32 Mbits/s) operation: all three pins must be connected to ground • For Gigabit Ethernet (1250 Mbits/s) operation: pin DOUT1250 must be connected to VEE • For STM4/OC12 (622.08 Mbits/s) operation: pins DOUT1250 and DOUT622 must be connected to VEE (the dividers are daisy chained) • For STM1/OC3 (155,52 Mbits/s) operation: all three pins must be connected to VEE. The connections to VEE and ground carry a current of a few milliamperes and should have low resistance and inductance, so short printed-circuit board tracks are recommended. In some cases a decoupling capacitor near the selection pins can be necessary to provide a clean return path for RF signals. When the OQ2541 is used in an application with a fixed data rate, it is best to connect the planes of pins DOUT155, DOUT622 and DOUT1250 with a short trace or a via to the plane of pin GND or pin VEE. If a selectable reference clock frequency is required in the application, the pins can be controlled through low-ohmic switching FETs, e.g. BSH103 or equivalent (low RDSon). FREQUENC Y (MHz) 38.88 19.44 STM mode selection The VCRO has a very large tuning range. However, the performance of the OQ2541 is optimized for SDH/SONET bit rates. Table 3 STM mode select BIT RATE (Mbits/s) 155.52 622.08 1250.00 2488.32 DIVISION FACTOR 16 4 2 1 LEVEL ON PIN DOUT155 VEE ground ground ground DOUT622 VEE VEE ground ground DOUT1250 VEE VEE VEE ground MODE STM1/OC3 STM4/OC12 Gigabit Ethernet STM16/OC48 1999 May 27 10 Philips Semiconductors Product specification SDH/SONET data and clock recovery unit STM1/4/16 OC3/12/48 GE Application with positive supply voltage Due to the versatile design of the OQ2541 the device can also operate in a positive supply voltage application, although some pins have a different mode of operation. This section deals with these differences and supports the user with achieving a successful application of the OQ2541 in a +5 V environment. APPLICATION DIAGRAM A sample application diagram can be found in Fig.29. It should be noted that all pins GND are now connected to VCC and all pins VEE are connected to the regulated voltage from the power controller. OUTPUT SELECTION In a positive supply voltage application, the loop mode is the default RF output. Due to the decoding logic on pin ENL, it is only possible to select the loop mode outputs or enable all the outputs. If pin ENL is connected to VCC (+5 V), only the loop mode outputs are active (see Table 4). When pin ENL is connected to VEE (the voltage is approximately 3.3 V below VCC) all outputs become active. In the positive supply voltage application the normal mode outputs can not be selected, unless the voltage on pin ENL is 2 V above the positive supply voltage (VCC). MGL671 OQ2541HP; OQ2541U LOSS OF SIGNAL AND LOCK DETECTION In the negative supply application, pins LOS and LOCK are open-collector outputs that require pull-up resistors to a positive supply voltage. In the positive supply application, the pull-up voltage would need to be higher then the positive supply voltage and the signals on pins LOS and LOCK would not be TTL compatible any more. However, the internal circuit on pins LOS and LOCK can be used in a current mirror configuration (see Fig.9). This requires only an external PNP transistor (e.g. BC857 or equivalent) to mirror the current. A 10 kΩ pull-down resistor from the collector of the external transistor to ground yields a TTL compatible signal again, albeit inverted. Table 5 shows the meaning of the LOS and LOCK flag, when used in the positive supply application. handbook, halfpage on chip off chip GND +5 V BC857 LOS, LOCK signal out 10 kΩ CAUTION Do not to connect pin ENL to ground, because this will destroy the IC. Table 4 Fig.9 Signal out for LOS and LOCK indication in a positive supply voltage application. Output selection in a positive supply voltage application OUTPUT MODE Loop Loop and normal Normal Table 5 LEVEL ON PIN ENL VCC (+5 V) VEE (VCC − 3.3 V) VCC + 2 V DLOOP, DLOOPQ, CLOOP AND CLOOPQ active active − DOUT, DOUTQ, COUT AND COUTQ − active active LOS and LOCK indication in a positive supply voltage application DESCRIPTION loss of signal: BER > 5 ⋅ 10−2 10−3 no loss of signal: BER < 1 ⋅ LEVEL 0 V (ground) +5 V (VCC) 0 V (ground) +5 V (VCC) TTL LOW HIGH LOW HIGH SIGNAL LOS active LOS inactive LOCK active LOCK inactive 1999 May 27 reference clock present and VCRO inside 1000 ppm window no reference clock present or VCRO outside 1000 ppm window 11 Philips Semiconductors Product specification SDH/SONET data and clock recovery unit STM1/4/16 OC3/12/48 GE DIVIDER SETTINGS The reference frequency dividers and the STM mode selectors still operate the same in a positive supply voltage application. The only difference is that pins formerly connected to ground should now be connected to VCC (+5 V). Pins connected to VEE should still be connected to VEE because connecting these pins to ground (0 V) will damage the IC. RF INPUT AND OUTPUTS All RF inputs, outputs and internal signals of the OQ2541 are referenced to pins GND. In the positive supply voltage application, this means that all RF signals are referenced to VCC. Therefore a clean VCC rail is of ultimate importance for proper RF performance. The best performance is obtained when the transmission line reference plane is also decoupled to VCC. Careful design of VCC and good decoupling schemes should be taken into account. While designing the printed-circuit board, bear in mind that the VCC has become what was formerly ground. OQ2541HP; OQ2541U While laying out the application, the return path is the most important issue to be considered. It is always advised to examine carefully the current carrying loops in the design. Care should be taken that for all frequencies (both of interest and not of interest) low ohmic and low inductance return paths are available. These return paths should preferably have an enclosed area as small as possible, both horizontally and vertically (by means of through-holes or vias). The position of a decoupling capacitor is very important. A decoupling capacitor on an unfavourable position could do more damage than completely omitting the capacitor, while on the right location it can mean the difference between mediocre results and the ultimate achievement. 1999 May 27 12 Philips Semiconductors Product specification SDH/SONET data and clock recovery unit STM1/4/16 OC3/12/48 GE LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VEE Vn negative supply voltage DC voltage on pins PARAMETER OQ2541HP; OQ2541U MIN. −6 −1 MAX. +0.5 +0.5 V V V V V UNIT CLOOP, CLOOPQ, DLOOP, DLOOPQ, CREF, CREFQ, DIN, DINQ, DOUT, DOUTQ, COUT and COUTQ ENL, LOCK and LOS, CAPUPQ and CAPDOQ In input current on pins ENL CREF, CREFQ, DIN and DINQ Ptot Tamb Tj Tstg total power dissipation ambient temperature junction temperature storage temperature VEE − 0.5 +5.5 VEE + 0.5 −0.5 − −20 − −40 −40 −65 1 +10 700 +85 +110 +150 DREF19, DREF39, DOUT1250, DOUT622, DOUT155, PC and AREF VEE − 0.5 +0.5 mA mA mW °C °C °C HANDLING INSTRUCTIONS Precautions should be taken to avoid damage through electrostatic discharge. This is particularly important during assembly and handling of the bare die. Additional safety can be obtained by bonding the VEE and GND pads first, the remaining pads may then be bonded to their external connections in any order. THERMAL CHARACTERISTICS SYMBOL Rth(j-s) Rth(j-a) Note 1. Thermal resistance from junction to ambient is determined with the IC soldered on a standard single sided 57 × 57 × 1.6 mm FR4 epoxy PCB with 35 µm thick copper traces. The measurements are performed in still air. PARAMETER thermal resistance from junction to solder point thermal resistance from junction to ambient in free air; note 1 CONDITIONS VALUE 46 67 UNIT K/W K/W 1999 May 27 13 Philips Semiconductors Product specification SDH/SONET data and clock recovery unit STM1/4/16 OC3/12/48 GE OQ2541HP; OQ2541U CHARACTERISTICS VEE = −3.3 V; Tamb = −40 to +85 °C; typical values measured at Tamb = 25 °C; all voltages are measured with respect to GND. SYMBOL Supply VEE IEE Ptot Vi(p-p) Vi(sens)(p-p) VIO VI Zi Vo(p-p) negative supply voltage negative supply current total power dissipation 50 Ω measurement system; see Fig.10; notes 2 and 3 50 Ω measurement system; notes 2 and 4 50 Ω measurement system 50 Ω measurement system single-ended; see Fig.4; note 5 50 Ω measurement system; single-ended; see Fig.10 default adjustment; note 6 special adjustment; note 7 VO Zo tr(C) tf(C) tr(D) tf(D) td(D-C) VAREF output voltage output impedance clock output rise time clock output fall time data output rise time data output fall time data-to-clock delay single-ended differential; 20% to 80% differential; 20% to 80% differential; 20% to 80% differential; 20% to 80% see Fig.11; note 8 170 50 −600 − − − − − 250 −110 200 − − 100 54 54 116 116 280 −100 210 400 0 − − − − − 310 −90 mV mV mV Ω ps ps ps ps ps see Fig.12; note 1 open outputs; see Fig.13 −3.50 − − −3.30 105 350 −3.10 155 550 V mA mW PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Data and clock inputs: pins DIN, DINQ, CREF and CREFQ input voltage (peak-to-peak value) input sensitivity (peak-to-peak value) DC input offset voltage input voltage input impedance 7 − −3 −600 − 200 2.5 0 −200 50 450 7 +3 +250 − mV mV mV mV Ω Data and clock outputs: pins DOUT, DOUTQ, DLOOP, DLOOPQ, COUT, COUTQ, CLOOP and CLOOPQ output voltage swing (peak-to-peak value) Output amplitude adjustment: pin AREF output amplitude reference voltage floating pin mV Power control output: pin PC gm IO VIL VIH VOL VOH transconductance output current −84 1 − 2.0 −0.6 − −60 − − − − − −42 3.5 mA/V mA Loop mode enable input: pin ENL LOW-level input voltage HIGH-level input voltage 0.8 − − 3.3 V V Phase lock indicator: pin LOCK LOW-level output voltage HIGH-level output voltage note 9 note 9 V V 1999 May 27 14 Philips Semiconductors Product specification SDH/SONET data and clock recovery unit STM1/4/16 OC3/12/48 GE SYMBOL PARAMETER CONDITIONS OQ2541HP; OQ2541U MIN. −0.6 − − − − − − − 1.5 0.15 0.15 1.5 0.7 0.15 0.15 0.15 1.5 0.15 0.15 − − − − − − − − − − − TYP. MAX. − 3.3 − − UNIT Loss of signal indicator: pin LOS VOL VOH tas tdas BERas BERdas tacq Jtol(p-p) LOW-level output voltage HIGH-level output voltage assert time de-assert time assert bit error rate de-assert bit error rate note 9 note 9 note 10 note 10 note 10 note 10 V V µs µs BER BER µs µs UI UI UI UI UI UI UI UI UI UI UI UI UI UI UI UI UI UI UI UI 0.1 10 1⋅ 10−3 5 ⋅ 10−2 − − PLL characteristics acquisition time jitter tolerance (peak-to-peak value) CREF = 19.44 MHz CREF = 38.88 MHz STM1/OC3 mode; note 11 f = 6.5 kHz f = 65 kHz f = 1 MHz STM4/OC12 mode; note 11 f = 25 kHz f = 100 kHz f = 250 kHz f = 1 MHz f = 5 MHz STM16/OC48 mode; note 11 f = 100 kHz f = 1 MHz f = 10 MHz Jgen(p-p) jitter generation (peak-to-peak value) STM1/OC3 mode; note 12 f = 500 Hz to 1.3 MHz f = 12 kHz to 1.3 MHz f = 65 kHz to 1.3 MHz STM4/OC12 mode; note 12 f = 1 kHz to 5 MHz f = 12 kHz to 5 MHz f = 250 kHz to 5 MHz STM16/OC48 mode; note 12 f = 5 kHz to 20 MHz f = 12 kHz to 20 MHz f = 1 to 20 MHz 0.079 0.063 0.053 0.50 0.10 0.10 0.050 0.040 0.052 0.50 0.10 0.10 0.039 0.032 0.032 0.50 0.10 0.10 >10 1.1 0.23 − − − >10 3 1.3 0.50 0.35 − − − − − >10 1.3 0.8 − − − 100 50 200 200 1999 May 27 15 Philips Semiconductors Product specification SDH/SONET data and clock recovery unit STM1/4/16 OC3/12/48 GE SYMBOL Jgen(rms) PARAMETER jitter generation (RMS value) CONDITIONS STM1/OC3 mode; note 12 f = 500 Hz to 1.3 MHz f = 12 kHz to 1.3 MHz f = 65 kHz to 1.3 MHz STM4/OC12 mode; note 12 f = 1 kHz to 5 MHz f = 12 kHz to 5 MHz f = 250 kHz to 5 MHz STM16/OC48 mode; note 12 f = 5 kHz to 20 MHz f = 12 kHz to 20 MHz f = 1 to 20 MHz TDR Notes 1. Typical power supply voltage for the voltage regulator is −4.5 V (see Fig.6). transitionless data run note 13 OQ2541HP; OQ2541U MIN. − − − − − − − − − − TYP. 0.0060 0.0046 0.0041 0.0093 0.0079 0.0081 0.0143 0.0139 0.0079 2000 MAX. − − − − − − − − − − UNIT UI UI UI UI UI UI UI UI UI bits 2. It is assumed that both CML inputs carry a complementary signal with the specified peak-to-peak value (true differential excitation). 3. The specified input voltage range is the guaranteed and tested range for proper operation; BER < 1 ⋅ 10−10. 4. An input sensitivity of 7 mV (p-p) for BER < 1 ⋅ 10−10 is guaranteed. The typical input sensitivity for BER < 1 ⋅ 10−10 is 2.5 mV (p-p). 5. CML inputs are terminated internally using on-chip resistors of 50 Ω connected to ground. 6. Output voltage range with default reference voltage on pin AREF (floating). 7. Output voltage range with adjustment of voltage on pin AREF (see Section “Output amplitude reference”). 8. Measured with 1010 data pattern, single-ended output signals and rising edges of the signals on pins COUT to DOUT or pins CLOOP to DLOOP. It should be noted that small deviations of the specified value are possible if measured differentially. 9. External pull-up resistor of 10 kΩ connected to supply voltage of +3.3 V. 10. LOS assert or de-assert timing and BER level are for indication only. The values are neither production tested nor guaranteed. 11. Measured in accordance with ITU specification G.958. Measured on demoboard OM5801 for STM16/OC48 and demoboard OM5802 for STM1/OC3 and STM4/OC12. See for more information “Application note AN96051” and “Application note AN97065”. 12. Measured in accordance with ITU specification G.813 and 1 dB above the system input sensitivity power level. Measured on demoboard OM5801 for STM16/OC48 and on demoboard OM5802 for STM1/OC3 and STM4/OC12. 13. TDR is bit rate independent. 1999 May 27 16 Philips Semiconductors Product specification SDH/SONET data and clock recovery unit STM1/4/16 OC3/12/48 GE OQ2541HP; OQ2541U handbook, full pagewidth CML INPUT CML OUTPUT VI(max) GND VIQH VIH Vi(p-p) VIQL VIL VI(min) VIO VOQL VOL VO(min) VOO VO(max) VOQH VOH Vo(p-p) GND MGK144 Fig.10 Logic level symbol definitions for CML. handbook, full pagewidth COUT or CLOOP GND −200 mV td(D-C) GND DOUT or DLOOP MGL672 −200 mV Fig.11 Data-to-clock delay for CML outputs: COUT to DOUT or CLOOP to DLOOP. 1999 May 27 17 Philips Semiconductors Product specification SDH/SONET data and clock recovery unit STM1/4/16 OC3/12/48 GE TYPICAL PERFORMANCE CHARACTERISTICS OQ2541HP; OQ2541U handbook, halfpage −3.30 VEE (V) −3.35 MGL650 handbook, halfpage 160 MGL649 IEE (mA) 120 80 −3.40 40 −3.45 −40 0 40 80 T (°C) 120 0 −40 0 40 80 T (°C) 120 It should be noted that the voltage on pins VEE is regulated by the power controller. Fig.12 Supply voltage as a function of the temperature. Fig.13 Supply current as a function of the temperature. handbook, halfpage 80 MGL653 tr(C) (ps) handbook, halfpage 70 MGL652 tf(C) (ps) 76 66 72 62 68 58 64 54 60 −40 0 40 80 T (°C) 120 50 −40 0 40 80 T (°C) 120 Measured on single-ended output. Measured on single-ended output. Fig.14 Clock output rise time as a function of the temperature. Fig.15 Clock output fall time as a function of the temperature. 1999 May 27 18 Philips Semiconductors Product specification SDH/SONET data and clock recovery unit STM1/4/16 OC3/12/48 GE OQ2541HP; OQ2541U handbook, halfpage 170 MGL655 handbook, halfpage 110 MGL654 tr(D) (ps) 160 tf(D) (ps) 100 90 150 80 140 −40 0 40 80 T (°C) 120 70 −40 0 40 80 T (°C) 120 Measured on single-ended output. Measured on single-ended output. Fig.16 Data output rise time as a function of the temperature. Fig.17 Data output fall time as a function of the temperature. handbook, halfpage 300 td(D-C) (ps) 280 MGL651 260 240 220 200 −40 0 40 80 T (°C) 120 See Fig.11 for the definition of td. Fig.18 Data-to-clock delay time as a function of the temperature. 1999 May 27 19 Philips Semiconductors Product specification SDH/SONET data and clock recovery unit STM1/4/16 OC3/12/48 GE OQ2541HP; OQ2541U handbook, halfpage 1 MGL658 handbook, halfpage 1 MGL657 BER 10−1 BER 10−1 10−2 10−2 10−3 10−3 10−4 10−4 10−5 10−5 10−6 10−6 10−7 10−7 10−8 10−8 10−9 10−9 10−10 10−10 10−11 0 0.5 1 Vi(p-p) (mV) 1.5 10−11 0 0.5 1 Vi(p-p) (mV) 1.5 A complementary input signal of the indicated value is applied to pins DIN and DINQ. A complementary input signal of the indicated value is applied to pins DIN and DINQ. Fig.19 Bit error rate as a function of the input signal in STM1/OC3 mode (155.52 Mbits/s). Fig.20 Bit error rate as a function of the input signal in STM4/OC12 mode (622.08 Mbits/s). 1999 May 27 20 Philips Semiconductors Product specification SDH/SONET data and clock recovery unit STM1/4/16 OC3/12/48 GE OQ2541HP; OQ2541U handbook, halfpage 1 MGL656 BER 10−1 10−2 10−3 10−4 10−5 10−6 10−7 10−8 10−9 10−10 10−11 0 0.5 1 Vi(p-p) (mV) 1.5 A complementary input signal of the indicated value is applied to pins DIN and DINQ. Fig.21 Bit error rate as a function of the input signal in STM16/OC48 mode (2488.32 Mbits/s). 1999 May 27 21 Philips Semiconductors Product specification SDH/SONET data and clock recovery unit STM1/4/16 OC3/12/48 GE OQ2541HP; OQ2541U 103 handbook, full pagewidth Jtol(p-p) (UI) 102 MGL659 10 1 (1) (2) 10−1 1 10 102 103 f (kHz) 104 (1) Device performance measured on OM5802 demoboard. (2) ITU specification template. Fig.22 Jitter tolerance as a function of the jitter frequency in the STM1/OC3 mode (155.52 Mbits/s). 103 handbook, full pagewidth Jtol(p-p) (UI) 102 MGL660 (1) 10 1 (2) 10−1 1 10 102 103 f (kHz) 104 (1) Device performance measured on OM5802 demoboard. (2) ITU specification template. Fig.23 Jitter tolerance as a function of the jitter frequency in the STM4/OC12 mode (622.08 Mbits/s). 1999 May 27 22 Philips Semiconductors Product specification SDH/SONET data and clock recovery unit STM1/4/16 OC3/12/48 GE OQ2541HP; OQ2541U 103 handbook, full pagewidth Jtol(p-p) (UI) 102 MGL661 (1) 10 (2) 1 10−1 1 10 102 103 f (kHz) 104 (1) Device performance measured on OM5801 demoboard. (2) ITU specification template. Fig.24 Jitter tolerance as a function of the jitter frequency in the STM16/OC48 mode (2488.32 Mbits/s). 1999 May 27 23 Philips Semiconductors Product specification SDH/SONET data and clock recovery unit STM1/4/16 OC3/12/48 GE OQ2541HP; OQ2541U MGS228 handbook, full pagewidth 200 mV/div Measured single-ended. Fig.25 Data and clock output waveforms in the STM4/OC12 mode (622.08 Mbits/s). MGS229 handbook, full pagewidth 200 mV/div Measured single-ended. Fig.26 Data and clock output waveforms in the STM16/OC48 mode (2488.32 Mbits/s). 1999 May 27 24 Philips Semiconductors Product specification SDH/SONET data and clock recovery unit STM1/4/16 OC3/12/48 GE APPLICATION INFORMATION OQ2541HP; OQ2541U handbook, full pagewidth +3.3 V 10 kΩ CAPUPQ 15 100 nF 100 nF 16 CAPDOQ LOCK 12 39 +3.3 V 10 kΩ LOS DIN PREAMP DINQ 33 34 42 43 45 DOUT DOUTQ COUT COUTQ DLOOP DLOOPQ CLOOP CLOOPQ ENL AREF DOUT1250 DOUT622 output select loop output normal output OQ2541 46 6 CREF 39 MHz system clock 21 CREFQ 22 7 3 4 1 DREF19 DREF39 9 24 5 13, 18, 19, 36, 40 25 GND(1) 17 100 nF 2Ω 1 kΩ 2Ω 1 kΩ β > 100 31 37 PC VEE1 VEE2 48 27 28 30 i.c. DOUT155 3.3 nF 1 µF L1(2) MBH973 − 4.5 V (1) All pins GND must be connected directly to the PCB ground plane (pins 2, 5, 8, 10, 11, 14, 17, 20, 23, 26, 29, 32, 35, 38, 41, 44 and 47). (2) L1 = RF choke type Murata BLM21. Fig.27 Application diagram showing the OQ2541 configured for the STM16/OC48 mode (2488.32 Mbits/s). 1999 May 27 25 Philips Semiconductors Product specification SDH/SONET data and clock recovery unit STM1/4/16 OC3/12/48 GE OQ2541HP; OQ2541U handbook, full pagewidth +3.3 V 10 kΩ CAPUPQ 15 100 nF 100 nF 16 CAPDOQ LOCK 12 39 +3.3 V 10 kΩ LOS DIN PREAMP DINQ 33 34 42 43 45 DOUT DOUTQ COUT COUTQ DLOOP DLOOPQ CLOOP CLOOPQ ENL AREF DOUT1250 DOUT622 output select loop output normal output OQ2541 46 6 CREF 39 MHz system clock 21 CREFQ 22 7 3 4 1 DREF19 DREF39 9 24 5 13, 18, 19, 36, 40 25 GND(1) 17 100 nF 2Ω 1 kΩ 2Ω 1 kΩ β > 100 31 37 PC VEE1 VEE2 48 27 28 30 i.c. DOUT155 3.3 nF 1 µF L1(2) MGL662 − 4.5 V (1) All pins GND must be connected directly to the PCB ground plane (pins 2,5, 8, 10, 11, 14, 17, 20, 23, 26, 29, 32, 35, 38, 41, 44 and 47). (2) L1 = RF choke type Murata BLM21. Fig.28 Application diagram showing the OQ2541 configured for the STM4/OC12 mode (622.08 Mbits/s). 1999 May 27 26 Philips Semiconductors Product specification SDH/SONET data and clock recovery unit STM1/4/16 OC3/12/48 GE OQ2541HP; OQ2541U handbook, full pagewidth VCC CAPUPQ 15 39 LOS LOS 16 CAPDOQ 12 LOCK LOCK 10 kΩ DIN PREAMP DINQ 34 33 42 43 DOUT DOUTQ COUT COUTQ DLOOP DLOOPQ CLOOP CLOOPQ ENL AREF DOUT1250 DOUT622 i.c. 5 13, 18, 19, 36, 40 25 GND(1) 17 100 nF 2Ω 1 kΩ VCC VCC MGL663 100 nF 100 nF 10 kΩ VCC OQ2541 45 46 6 normal unused = output output CREF 39 MHz system clock 21 CREFQ 22 7 3 4 1 loop output = main output(3) VCC DREF19 DREF39 output select 9 24 48 27 28 31 37 PC 30 DOUT155 VCC VEE1 VEE2 β > 100 VCC 2Ω 1 kΩ 3.3 nF 1 µF L1(2) (1) (1) All pins GND must be connected directly to VCC on the PCB plane of +5 V (pins 2, 5, 8, 10, 11, 14, 17, 20, 23, 26, 29, 32, 35, 38, 41, 44 and 47). (2) L1 = RF choke type Murata BLM21. (3) The loop mode outputs are used as main outputs: pin ENL = HIGH-level selects loop mode outputs pin ENL = LOW-level selects loop mode and normal mode outputs simultaneously. Fig.29 Application diagram showing the OQ2541 configured for the STM16/OC48 mode (2488.32 Mbits/s) with a positive supply voltage application. 1999 May 27 27 Philips Semiconductors Product specification SDH/SONET data and clock recovery unit STM1/4/16 OC3/12/48 GE BONDING PADS OQ2541HP; OQ2541U COUTQ COUT DOUT AREF handbook, full pagewidth DOUTQ GND GND GND GND 38 LOS 48 ENL GND CLOOP CLOOPQ GND 2.360 mm DLOOP DLOOPQ GND DREF19 GND GND LOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 47 46 45 44 43 42 41 40 39 37 36 35 34 33 32 i.c. GND DINQ DIN GND VEE2 DOUT155 GND DOUT622 DOUT1250 GND VEE1 PC 31 30 29 28 27 26 25 24 DREF39 MGL664 x 0 0 y OQ2541U 14 15 16 17 18 19 20 21 i.c. 22 23 i.c. i.c. GND CAPUPQ CAPDOQ GND i.c. GND CREF CREFQ 2.360 mm Fig.30 Bonding pad locations of OQ2541U. 1999 May 27 28 GND Philips Semiconductors Product specification SDH/SONET data and clock recovery unit STM1/4/16 OC3/12/48 GE Table 6 Bonding pad locations. COORDINATES(1) SYMBOL ENL GND CLOOP CLOOPQ GND DLOOP DLOOPQ GND DREF19 GND GND LOCK i.c. GND CAPUPQ CAPDOQ GND i.c. i.c. GND CREF CREFQ GND DREF39 VEE1 GND DOUT1250 DOUT622 GND DOUT155 VEE2 GND DIN DINQ GND i.c. PC GND PAD x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 −1017.5 −1017.5 −1017.5 −1017.5 −1017.5 −1017.5 −1017.5 −1017.5 −1017.5 −1017.5 −1017.5 −1017.5 −852.5 −697.5 −542.5 −387.5 −232.5 −77.5 +77.5 +232.5 +387.5 +542.5 +697.5 +852.5 +1017.5 +1017.5 +1017.5 +1017.5 +1017.5 +1017.5 +1017.5 +1017.5 +1017.5 +1017.5 +1017.5 +1017.5 +852.5 +697.5 y +852.5 +697.5 +542.5 +387.5 +232.5 +77.5 −77.5 −232.5 −387.5 −542.5 −697.5 −852.5 −1017.5 −1017.5 −1017.5 −1017.5 −1017.5 −1017.5 −1017.5 −1017.5 −1017.5 −1017.5 −1017.5 −1017.5 −852.5 −697.5 −542.5 −387.5 −232.5 −77.5 +77.5 +232.5 +387.5 +542.5 +697.5 +852.5 +1017.5 +1017.5 SYMBOL LOS i.c. GND DOUT DOUTQ GND COUT COUTQ GND AREF Note OQ2541HP; OQ2541U COORDINATES(1) PAD x 39 40 41 42 43 44 45 46 47 48 +542.5 +387.5 +232.5 +77.5 −77.5 −232.5 −387.5 −542.5 −697.5 −852.5 y +1017.5 +1017.5 +1017.5 +1017.5 +1017.5 +1017.5 +1017.5 +1017.5 +1017.5 +1017.5 1. All x and y coordinates represent the position of the centre of the pad in µm with respect to the centre of the die (see Fig.30). 1999 May 27 29 Philips Semiconductors Product specification SDH/SONET data and clock recovery unit STM1/4/16 OC3/12/48 GE Table 7 Physical characteristics of bare die NAME Glass passivation Bonding pad dimension Metallization Thickness Size Backing Attache temperature Attache time Thermal considerations OQ2541HP; OQ2541U DESCRIPTION 0.8 µm silicon nitride on top of 0.9 µm PSG (PhosphoSilicate Glass) minimum dimension of exposed metallization is 90 × 90 µm (pad size = 100 × 100 µm) 1.8 µm AlCu (1% Cu) 380 µm nominal 2.360 × 2.360 mm (5.5696 mm2) silicon; electrically connected to VEE potential through substrate contacts