PCA5007

INTEGRATED CIRCUITS DATA SHEET PCA5007 Pager baseband controller Product specification File under Integrated Circuits, IC17 1998 Oct 07 Philips Semiconductors Product specification Pager baseband controller CONTENTS 1 2 3 4 5 6 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 6.14 6.15 6.16 6.17 6.18 6.19 6.20 6.21 6.22 7 7.1 8 9 10 11 12 13 FEATURES ORDERING INFORMATION GENERAL DESCRIPTION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION General CPU timing Overview on the different clocks used within the PCA5007 Memory organization Addressing I/O facilities Timer/event counters I2C-bus serial I/O Serial interface SIO0: UART 76.8 kHz oscillator Clock correction 6 MHz oscillator Real-time clock Wake-up counter Tone generator Watchdog timer 2 or 4-FSK demodulator, filter and clock recovery circuit AFC-DAC Interrupt system Idle and power-down operation Reset DC/DC converter INSTRUCTION SET Instruction Map LIMITING VALUES EXTERNAL COMPONENTS DC CHARACTERISTICS AC CHARACTERISTICS CHARACTERISTIC CURVES TEST AND APPLICATION INFORMATION 15.1 15.2 15.3 15.4 15.5 15.6 15.7 15.8 15.9 15.10 16 17 18 19 19.1 19.2 19.3 19.4 20 21 22 14 14.1 14.2 14.3 15 PCA5007 APPENDIX 1: SPECIAL MODES OF THE PCA5007 Overview OTP parallel programming mode Test modes APPENDIX 2: THE PARALLEL PROGRAMMING MODE Introduction General description Entering the parallel programming mode Address space Single byte programming Multiple byte programming High voltage timing OTP test modes Signature bytes Security APPENDIX 3: OS SHEET APPENDIX 4: BONDING PAD LOCATIONS PACKAGE OUTLINE SOLDERING Introduction Reflow soldering Wave soldering Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS 1998 Oct 07 2 Philips Semiconductors Product specification Pager baseband controller 1 FEATURES PCA5007 • Operating temperature from: −10 to +55 °C • Supply voltage range with on-chip DC/DC converter: 0.9 to 1.6 V • Low operating and standby current consumption • On-chip DC/DC converter generates the supply voltage for the PCA5007 and external circuitry from a single cell battery • Battery low detector • Low electromagnetic noise emission • Full static asynchronous 80C51 CPU (8-bit CPU) • Recovery from lowest power standby Idle mode to full speed operation within microseconds • 20 kbytes of One-Time Programmable (OTP) memory and 1-kbyte of RAM on-chip • 27 general purpose I/O port lines (4 ports with interrupt possibility) • 15 different interrupt sources with selectable priority • 2 standard timer/event counters T0 and T1 • I2C-bus serial port (single 100 kHz master transmitter and receiver) • Subset of standard UART serial port (8 and 9-bit transmission at 4800/9600 bits/s) • 76.8 kHz crystal oscillator reference with digital clock correction for real time and paging protocol • Real-Time Clock (RTC) • Receiver and synthesizer control – Receiver control by software through general purpose I/Os – Synthesizer control by software through general purpose I/Os – 6-bit DAC for AFC to the receiver local oscillator – Dedicated protocol timer. 2 ORDERING INFORMATION TYPE NUMBER(1) PACKAGE PRODUCT TYPE NAME LQFP48 DESCRIPTION plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm VERSION SOT313-2 • Decoding of paging data – POCSAG or APOC phase 1, advanced high speed paging protocols are also supported – Supported data rates: 1200, 1600, 2400 and 3200 symbols/s using a 76.8 kHz crystal oscillator – Demodulation of Zero-IF I and Q 4 or 2 level FSK input or direct data input – Noise filtering of data input and symbol clock reconstruction – De-interleaving, error checking and correction, sync word detection address recognition, buffering and more is done in software – All user functions (keypad interface, alerter control, display, etc.) are implemented in software. • Musical tone generator for beeper, controlled by the microcontroller • Watchdog timer • 48-pin LQFP package. PCA5007H/XXX pre-programmed OTP Note 1. Please refer to the Order Entry Form (OEF) for this device for the full type number to use when ordering. This type number will also specify the required OTP code. 1998 Oct 07 3 Philips Semiconductors Product specification Pager baseband controller 3 GENERAL DESCRIPTION PCA5007 The instruction set of the PCA5007 is based on that of the 80C51. The PCA5007 also functions as an arithmetic processor having facilities for both binary and BCD arithmetic plus bit-handling capabilities. The instruction set consists of over 100 instructions: 49 one-byte, 46 two-byte, and 16 three-byte. This data sheet details the properties of the PCA5007. For details of the I2C-bus functions see “The I2C-bus and how to use it”. For details on the basic 80C51 properties and features see “Data Handbook IC20”. The PCA5007 pager baseband controller is manufactured in an advanced CMOS/OTP technology. The PCA5007 is an 8-bit microcontroller especially suited for pagers. For this purpose, features such as a 4 or 2 level FSK demodulator, filter, clock recovery, protocol timer, DC/DC converter optimized for small paging systems and RTC are integrated on-chip. The device is optimized for low power consumption. The PCA5007 has several software selectable modes for power reduction: Idle and power-down mode of the microcontroller, and standby and off mode of the DC/DC converter. 1998 Oct 07 4 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... andbook, full pagewidth 1998 Oct 07 I(D1), Q(D0) 2 AFCOUT DAC WATCHDOG AT TONE GENERATOR 4 Philips Semiconductors Pager baseband controller BLOCK DIAGRAM DIGITAL FILTER ZERO-IF 4L DEMODULATOR SYMBOL SAMPLING CLOCK RECOVERY VPP PORT CONTROL 8 P0 RAM OTP/ROM P0 P2 PROCESSOR 80C51 8 P2 6 MHz OSCILLATOR P3 4 P3 (T0, T1, INT0, INT1) P1 (SDA, SCL, RXD, TXD) 5 VIND VDD(DC) VSS(DC) VBAT 2 VDD VSS 2 RESETIN RESOUT TIMER 0 DC/DC CONVERTER INTERRUPT CONTROL TIMER 1 P1 7 UART SIO various clocks POWER CONTROLLER I2C SIO MODE AND TEST CONTROL WAKE-UP RTC CLOCK GENERATOR CLOCK CORRECTION 76.8 kHz OSCILLATOR XTL2 Product specification XTL1 supplied by VBAT 3 ALE, PSEN, EA TCLK MGR107 PCA5007 Fig.1 Block diagram. Philips Semiconductors Product specification Pager baseband controller 5 PINNING SYMBOL P3.4 and P3.5 PIN 1 and 2 TYPE I/O DESCRIPTION PCA5007 Port 3: P3.4 and P3.5 are configured as push-pull output only (option 3R; see Section 6.6). Using the software input commands or the secondary port function is possible by driving the port 3 output lines accordingly: P3.4 secondary function: T0 (counter input for T0) P3.5 secondary function: T1 (counter input for T1) AT P2.0 to P2.7 3 4 to 11 O I/O Beeper high volume control output. Used to drive external bipolar transistor. Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups (option 1S; see Section 6.6.3). As inputs, port 2 pins that are externally pulled LOW will source current because of the internal pull-ups. (see Chapter “DC characteristics”: Ipu). Port 2 emits the high-order address byte during fetches from external program memory. In this application, it uses strong internal pull-ups when emitting logic 1s. Port 2 is also used to control the parallel programming mode of the on-chip OTP. Port 0: Port 0 is a bidirectional I/O port with internal pull-ups (option 1S; see Section 6.6.3). Port 0 pins that have logic 1s written to them are pulled HIGH by the internal pull-ups and can be used as inputs. Port 0 is also the multiplexed low-order address and data bus during access to external program and data memory. In this application, it uses strong internal pull-ups when emitting 1s. Port 0 also outputs the code bytes during OTP programming verification. supply voltage for the analog parts of the PCA5007 and the receiver/synthesizer control signals (Port 0 pins) Buffered analog output of DAC for automatic receiver frequency control. A voltage proportional to the offset of the receiver frequency can be generated. Can be enabled/disabled by software. input from receiver: may be demodulated NRZ signal or Zero-IF. In phase limited signal input from receiver: may be demodulated NRZ signal or Zero-IF, Quadrature limited signal. ground signal reference (for the analog parts) (connected to substrate) Port 0: Port 0 is a bidirectional I/O port with internal pull-ups (option 1R,1R and 1S; see Section 6.6.3). Port 0 pins that have logic 1s written to them are pulled HIGH by the internal pull-ups and can be used as inputs. Port 0 is also the multiplexed low-order address and data bus during access to external program and data memory. In this application, it uses strong internal pull-ups when emitting 1s. Port 0 also outputs the code bytes during OTP programming verification. Port 1: Port 1 is an 8-bit quasi bidirectional I/O port with internal pull-ups. Port 1 pins that have logic 1s written to them are pulled HIGH by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled LOW will source current because of the internal pull-ups (see Chapter “DC characteristics”: Ipu). P1.0 to P1.2 have external interrupts INT2 to INT4 assigned. If the UART is disabled (ENS1 in S1CON.4 = 0) then P1.3 can be used as general purpose P1 port pin. If the UART function is required, then a logic 1 must be written to P1.3. This I/O then becomes the RXD/data line of the UART. P0.0 to P0.4 12 to 16 I/O VDDA AFCOUT 17 18 S O I(D1) Q(D0) VSSA P0.5 to P0.7 19 20 21 22 to 24 I I S I/O P1.0 to P1.2 25 to 27 I/O P1.3 28 I/O 1998 Oct 07 6 Philips Semiconductors Product specification Pager baseband controller PCA5007 SYMBOL P1.4 PIN 29 TYPE I/O DESCRIPTION If the UART is disabled (ENS1 in S1CON.4 = 0) then P1.4 can be used as general purpose P1 port pin. If the UART function is required, then a logic 1 must be written to P1.4. This I/O then becomes the TXD/clock line of the UART. P1.4 has external interrupt INT6 (X6) assigned. ground (connected to substrate) supply voltage for the core logic and most peripheral drivers of the PCA5007 (see VDDA) Address Latch Enable: output pulse for latching the low byte of the address during an access to external memory. Program Store Enable: the read strobe to external program memory. When the device is executing code from the external program memory, PSEN is activated for each code byte fetch. External Access Enable: EA must be externally held LOW to enable the device to fetch code from external program memory locations 0000H to 4FFFH. If EA is held HIGH, the device executes from internal program memory unless the program counter contains an address greater the 4FFFH (20 kbytes). clock input for use as timing reference in external access mode and emulation Programming voltage (12.5 V) for the OTP. Is connected to VSS in the application. If the I2C-bus is disabled (ENS1 in S1CON.6 = 0) then P1.6 can be used as general purpose P1 port pin. If the I2C-bus function is required, then a logic 1 must be written to P1.6. This I/O then becomes the clock line of the I2C-bus. P1.6 is equipped with an open-drain output buffer. The pin has no clamp diode to VDD. If the I2C-bus is disabled (ENS1 in S1CON.6 = 0) then P1.7 can be used as general purpose P1 port pin. If the I2C-bus function is required, then a logic 1 must be written to P1.7. This I/O then becomes the data line of the I2C-bus. P1.7 is equipped with an open-drain output buffer. The pin has no clamp diode to VDD. output from the current source oscillator amplifier input to the inverting oscillator amplifier and time reference for pager decoder, real-time clock and timers Supply terminal from battery. Is used for supplying parts of the chip that need to operate at all times. Supply voltage output of the DC/DC converter. An external capacitor is required. Current input for the DC/DC converter. The booster inductor needs to be connected externally. ground (connected to substrate) OTP Schmitt trigger reset input for the PCA5007. External R and C need to be connected to the battery supply. All internal storage elements (except microcontroller RAM) are initialized when this input is activated. VSS VDD ALE PSEN 30 31 32 33 S S I/O I/O EA 34 I/O TCLK VPP P1.6(SCL) 35 36 37 I S I/O P1.7(SDA) 38 I/O XTL2 XTL1 VBAT VDD(DC) VIND VSS(DC) RESETIN 39 40 41 42 43 44 45 O I S O I S I 1998 Oct 07 7 Philips Semiconductors Product specification Pager baseband controller PCA5007 SYMBOL RESOUT PIN 46 TYPE O DESCRIPTION Monitor output for the emulation system. Is active (LOW) whenever a reset is applied to the microcontroller. (a reset can be forced by RESETIN, watchdog or wake-up from DC/DC converter in off mode). A reset to the microcontroller initializes all SFRs and port pins; it has no impact on the blocks operating from VBAT. Port 3: P3.2 and P3.3 are configured as push-pull output only (option 3R; see Section 6.6). Using the software input commands or the secondary port function is possible by driving the port 3 output lines accordingly: P3.2 secondary function: INT0 (external interrupt 0) P3.3 secondary function: INT1 (external interrupt 1) P3.2 to P3.3 47 and 48 I/O 45 RESETIN 42 VDD(DC) 46 RESOUT 44 VSS(DC) handbook, full pagewidth 41 VBAT 40 XTL1 39 XTL2 43 VIND 38 P1.7 48 P3.3 37 P1.6 47 P3.2 P3.4 1 36 VPP 35 TCLK 34 EA 33 PSEN 32 ALE P3.5 2 AT 3 P2.0 4 P2.1 5 P2.2 6 P2.3 7 P2.4 8 P2.5 9 P2.6 10 P2.7 11 P0.0 12 PCA5007H 31 VDD 30 VSS 29 P1.4 28 P1.3 27 P1.2 26 P1.1 25 P1.0 VSSA 21 P0.2 14 VDDA 17 AFCOUT 18 I(D1) 19 Q(D0) 20 P0.5 22 P0.7 24 P0.1 13 P0.3 15 P0.4 16 P0.6 23 MGR108 Fig.2 Pin configuration. 1998 Oct 07 8 Philips Semiconductors Product specification Pager baseband controller 6 6.1 FUNCTIONAL DESCRIPTION General PCA5007 TANGRAM is a high level programming language which allows the description of parallel and sequential processes that can be compiled into logic on silicon. The CPU has the following features: • No clock is needed. Every function within the CPU is self timed and always runs at the maximum speed that a given silicon die under the current operating conditions (supply voltage and temperature) allows. • The CPU fetches opcodes with maximum speed until a special mode (e.g. Idle) is entered that stops this sequence. • Only bytes that are required are fetched from the program memory. The dummy read cycles which exist in the standard 80C51 have been omitted to save power. • To further speed up the execution of a program, the next sequential byte is always fetched from the code memory during the execution of the current command. In the event of jumps the prefetched byte is discarded. • Since no clocks are required, the operating power consumption is essentially lower compared to conventional architectures and Idle power consumption is reduced to nearly zero (leakage only). • Clocks are only required as timing references for timers/counters and for generating the timing to the off-chip world. 6.2.2 EXECUTION OF PROGRAMS FROM INTERNAL CODE MEMORY The PCA5007 contains a high-performance CMOS microcontroller and the required peripheral circuitry to implement high-speed pagers for the modern paging protocols. For this purpose, features such as FSK demodulator, protocol timer, real-time clock and DC/DC converter have been integrated on-chip. The microcontroller embedded within the PCA5007 implements the standard 80C51 architecture and supports the complete instruction set of the 80C51 with all addressing modes. The PCA5007 contains 20 kbytes of OTP program memory; 1-kbyte of static read/write data memory, 27 I/O lines, two 16-bit timer/event counters, a fifteen-source two priority-level, nested interrupt structure and on-chip oscillator and timing circuit. The PCA5007 devices have several software selectable modes of reduced activity for power reduction; Idle for the CPU and standby or off for the DC/DC converter. The Idle mode freezes the CPU while allowing the RAM, timers, serial I/O and interrupt system to continue functioning. The standby mode for the DC/DC converter allows a high efficiency of the latter at low currents and the off mode reduces the supply voltage to the battery level. In the off mode the RAM contents are preserved, the real-time clock and protocol timer are operating, but all other chip functions are inoperative. Two serial interfaces are provided on-chip; a UART serial interface and an I2C-bus serial interface. The I2C-bus serial interface has byte oriented master functions allowing communication with a whole family of I2C-bus compatible slave devices. 6.2 CPU timing When code is executed in internal access mode (EA = 1), the opcodes are fetched from the on-chip OTP. The OTP is a self timed block which delivers data at maximum speed. This is the preferred operating mode of the PCA5007. 6.2.3 EXECUTION OF PROGRAMS FROM EXTERNAL CODE MEMORY The internal CPU timing of the PCA5007 is completely different to other implementations of this core. The CPU is realized in asynchronous handshaking technology, which results in extremely low power consumption and low EMC noise generation. 6.2.1 BASICS The implementation of the CPU of the PCA5007 as a block in handshake technology has become possible through the TANGRAM tool set, developed in the Philips Natlab in Eindhoven. When code is executed in external access mode (EA = 0), the opcodes are fetched from an off-chip memory using the standard signals ALE, PSEN and P0, P2 for multiplexed data and address information. In this mode the identical hardware configurations as for a standard 80C51 system can be used, even if the timing for ALE and PSEN is slightly different because it is generated from an internal oscillator. 1998 Oct 07 9 Philips Semiconductors Product specification Pager baseband controller 6.3 Overview on the different clocks used within the PCA5007 PCA5007 Figure 3 gives an overview on the clocks available within the PCA5007 for the different functions. handbook, full pagewidth 76.8 kHz TONE GENERATOR (both clock edges are used) UART (both clock edges are used) TIMER 1 (both clock edges are used) DEMODULATOR/ CLOCK RECOVERY 76.8 kHz 76.8 kHz OSCILLATOR 76.8 kHz 76.8 kHz CORR CLOCK CORRECTION CCON.7 38.4 kHz ÷150 DIVIDER ÷9600 FOR THE DIFFERENT ÷2400 FREQUENCIES ÷4 256 Hz TIMER 0 4 Hz REAL-TIME CLOCK 16 Hz WATCHDOG 9.6 kHz 76.8 kHz 6 MHz WAKE-UP COUNTER DC/DC CONVERTER 6 MHz OSCILLATOR OS6CON.7 DIVIDER OS6CON.7 400 kHz I2C-BUS MICROCONTROLLER OUTPUT AND EXTERNAL ACCESS MGR109 6 MHz Fig.3 Overview on the clocks used within the PCA5007. 1998 Oct 07 10 Philips Semiconductors Product specification Pager baseband controller 6.4 Memory organization 6.4.2 DATA MEMORY PCA5007 The PCA5007 has a program memory (OTP) plus data memory (RAM) on-chip. The device has separate address spaces for program and data memory (see Fig.4). If ports P0 and P2 are not used as I/O signals these pins can be used to address up to 64 kbytes of external program memory. In this case, the CPU generates the latch signal (ALE) for an external address latch and the read strobe (PSEN) for external program memory. External data memory is not supported. 6.4.1 PROGRAM MEMORY After reset the CPU begins execution of the program memory at location 0000H. The program memory can be implemented in either internal OTP or external memory. If the EA pin is strapped to VDD, then program memory fetches are directed to the internal program memory. If the EA pin is strapped to VSS, then program memory fetches are directed to external memory. Programming the on-chip OTP is detailed in Chapter 15. Usually Philips will deliver programmed parts to a customer. Supply of blank engineering samples is possible, but then Philips cannot give any guarantee on the programmability and retention of the program memory. The PCA5007 contains 1024 bytes of internal RAM (consisting of 256 bytes standard RAM and 768 bytes AUX-RAM) and Special Function Registers (SFRs). Figure 4 shows the internal data memory space divided into the lower 128 bytes the upper 128 bytes and the SFR space and 768 bytes auxiliary RAM. Internal RAM locations 0 to 127 are directly and indirectly addressable. Internal RAM locations 128 to 255 are only indirectly addressable. The SFR locations 128 to 255 are only directly addressable and the auxiliary RAM is indirectly addressable as external RAM (MOVX). External Data Memory (EDM) is not supported. 6.4.3 SPECIAL FUNCTION REGISTERS The second 128 bytes are the address locations of the special function registers. Table 1 shows the special function registers space. The SFRs include the port latches, timers, peripheral control, serial I/O registers, etc. These registers can only be accessed by direct addressing. There are 128 bit addressable locations in the SFR address space (those SFRs whose addresses are divisible by eight). FFFFH handbook, full pagewidth EXTERNAL 2FFH INDIRECT ADDRESSING WITH DPTR 100H 0FFH 4FFFH FFH DIRECT INDIRECT ADDRESSING ADDRESSING EXTERNAL (EAN = 0) 0 Internal RAM PROGRAM MEMORY SFR space 80H 7FH INDIRECT AND DIRECT ADDRESSING INTERNAL (EAN = 1) 00H INDIRECT ADDRESSING WITH Ri, DPTR Internal XRAM 000H External XRAM is not supported MGR110 DATA MEMORY Fig.4 Memory map. 1998 Oct 07 11 Philips Semiconductors Product specification Pager baseband controller 6.5 Addressing PCA5007 • Special function registers through Direct • Program memory Look-Up Tables (LUTs) through Base-Register plus Index-Register-Indirect. The PCA5007 is classified as an 8-bit device since the internal ROM, RAM, Special Function Registers (SFRs), Arithmetic Logic Unit (ALU) and external data bus are all 8 bits wide. It performs operations on bit, nibble, byte and double-byte data types. Facilities are available for byte transfer, logic and integer arithmetic operations. Data transfer, logic and conditional branch operations can be performed directly on Boolean variables to provide excellent bit handling. While the PCA5007 is executing code from the internal memory, ALE and PSEN pins are inactive with ALE = LOW and PSEN = HIGH. External XRAM is not supported for this device, since P3.7 (RD) and P3.6 (WR) pins are not available. If the external XRAM is accessed accidentally, no PSEN or ALE cycle is done and actual P0 values are read. Internal XRAM access is not visible from outside the chip (no ALE, PSEN, P0 and P2 activity). The PCA5007 has five methods for addressing source operands: • Register • Direct • Register-Indirect • Immediate • Base-Register plus Index-Register-Indirect. The first three methods can be used for addressing destination operands. Most instructions have a ‘destination/source’ field that specifies the data type, addressing methods and operands involved. For operations other than MOVs, the destination operand is also a source operand. Access to memory addressing is as follows: • Registers in one of the four 8-register banks through Register-Direct or Register-Indirect • Maximum 1024 bytes of internal data RAM through Direct or Register-Indirect – Bytes 0 to 127 of internal RAM may be addressed directly/indirectly. Bytes 128 to 255 of internal RAM share their address location with the SFRs and so may only be addressed Register-Indirect as data RAM. – Bytes 0 to 768 of AUX-RAM can only be addressed indirectly via MOVX. Bytes 256 to 768 can only be addressed using indirect addressing with the data pointer, while bytes 0 to 255 may be also addressed using R0 or R1. 1998 Oct 07 12 Philips Semiconductors Product specification Pager baseband controller Table 1 ADDR (HEX) 80 81 82 83 87 88 89 8A 8B 8C 8D 90 92 93 94 95 96 98 99 9E A0 A5 A8 B0 B8 C0 CD CE D0 D1 D2 D3 D4 D8 D9 DA E0 E8 E9 Special Function Registers Overview; note 1 NAME P0 SP DPL DPH PCON TCON TMOD TL0 TL1 TH0 TH1 P1 TGCON TG0 WUCON WUC0 WUC1 S0CON S0BUF AFCON P2 WDCON IEN0/IE P3 IP/IP0 IRQ1 RTCON RTC0 PSW DCCON0 DCCON1 OS6CON OS6M0 S1CON S1STA S1DAT ACC IEN1 IX1 EMIN IL9 EWD IL8 EDC IL7 EX6 IL6 ESC IL5 13 EX4 IL4 EX3 IL3 EX2 IL2 − SC4 ENS1 SC3 STA SC2 STO SC1 SI SC0 AA 0 − 0 − 0 CY OFF ENB AC SBY − F0 RXE SF4 RS1 SBLI SF3 RS0 − − SF2 OV − − SF1 STB(3) − SF0 P(3) − − IQ9 MIN PWU IQ8 − PS1 IQ7 − PS0 IQ6 − PT1 IQ5 − PX1 IQ4 W/R PT0 IQ3 LOAD PX0 IQ2 SET COND EA WD3 EWU WD2 ES1 WD1 ES0 WD0 ET1 − EX1 − ET0 LD EX0 ENB − AFC5 AFC4 AFC3 AFC2 AFC1 SM0 SM1 − REN TB8 RB8 TI RI RUN WUP TEST CPL Z1 Z0 LOAD SET ENB CLK2 − − − − − − SMOD TF1 GATE XRE TR1 C/T ENIS TF0 M1 − TR0 M0 GF1 IE1 GATE GF0 IT1 C/T PD IE0 M1 IDL IT0 M0 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W AFC0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R R/W R/W R/W R/W BLI(3) R/W MFR R/W RESET VALUE 9FH 07H 00H 00H 00H 00H 00H 00H 00H 00H 00H FFH 00H 00H 00H 00H 00H 00H 00H 00H FFH 00H 00H C3H 00H 00H 00H 00H 00H 03H 00H 00H 00H 00H 78H 00H 00H 00H 00H PCA5007 COMMENT bit addressable bit addressable bit addressable note 2 note 2 note 2 bit addressable bit addressable bit addressable bit addressable bit addressable bit addressable note 2 note 2 bit addressable VBG1 VBG0 VLO1 VLO0 bit addressable bit addressable bit addressable 1998 Oct 07 Philips Semiconductors Product specification Pager baseband controller PCA5007 ADDR (HEX) EC ED EE EF F0 F8 FC FD FE Notes NAME DMD0 DMD1 DMD2 DMD3 B IP1 CCON CC0 CC1 7 ENB ENA ENC 6 M − 5 − BF 4 RES − 3 LEV TEST 2 BD2 B2 1 BD1 AVG1 B1 0 BD0 AVG0 B0 R/W R/W R R/W R/W R/W RESET VALUE 00H 00H 00H 00H 00H 00H 00H 00H 00H COMMENT AVG6 AVG5 AVG4 AVG3 AVG2 ENA is RW bit addressable bit addressable PMIN ENB CIV7 PWD CIV6 PDC CIV5 PX6 CIV4 PSC CIV3 PX4 − CIV2 PX3 BYPAS CIV1 CIV9 PX2 SET R/W R/W PLUS TEST CIV17 CIV16 CIV0 R/W CIV8 R/W CIV15 CIV14 CIV13 CIV12 CIV11 CIV10 1. An empty field in this map indicates a bit that can be read from or written to by software. 2. Value only reset with RESETIN and not or only partly with an off-restart sequence. 3. This bit cannot be changed by writing to it. handbook, halfpage 7FH 30H 2FH bit-addressable space (bit addresses 0 to 7F) R7 R0 R7 R0 R7 R0 R7 R0 20H 1FH 18H 17H 10H 0FH 08H 07H 0 4 banks of 8 registers (R0 to R7) MLA560 - 1 Fig.5 The lower 128 bytes of internal data memory. 1998 Oct 07 14 Philips Semiconductors Product specification Pager baseband controller 6.6 6.6.1 I/O facilities PORTS PCA5007 Port 3 Pins are configured as strong push-pull outputs (see Table 5 for configuration details). The following alternative Port 3 functions are available, but to avoid short-circuiting of the port pins, the input signals cannot be applied externally to the Port 3 pins. The alternative function can only be stimulated via the respective port output function: • External interrupt request inputs INT0/P3.2 and INT1/P3.3 • Counter inputs T0/P3.4 and T1/P3.5. To enable a port pin alternative function, the port bit latch in its SFR must contain a logic 1. Each port consists of a latch (SFRs P0 to P3), an output driver and input buffer. Standard ports have internal pull-ups. Figure 6a shows that the strong transistor p1 is turned on for only a short time after a LOW-to-HIGH transition in the port latch. When on, it turns on p3 (a weak pull-up) through the inverter IN1. This inverter and p3 form a latch which holds the logic 1. 6.6.2 PORT I/O CONFIGURATION (OPTIONS) The PCA5007 has 27 I/O lines treated as 27 individually addressable bits or as four parallel 8-bit addressable ports. Ports 0 and 2 are complete, Port 1 has only 7 and Port 3 has only 4 pins externally available. Ports 0, 1, 2 and 3 perform the following alternative functions: Port 0 Is also used for external access, parallel OTP programming mode and emulation (see Table 2 for configuration details): • Provides the multiplexed low-order address and data bus for expanding the device with standard memories and peripherals • Provides access to the OTP data I/O lines in OTP parallel programming mode. Port 1 Used for a number of alternative functions (see Table 3 for configuration details): • Provides the inputs for the external interrupts INT2/P1.0 to INT4/P1.2 and INT6/P1.4 • SCL/P1.6 and SDA/P1.7 for the I2C-bus interface are real open-drain outputs; no other port configurations are available • RXD/P1.3 and TXD/P1.4 for the UART data input and output. Port 2 Is also used for external access, parallel OTP programming mode and emulation (see Table 4 for configuration details): • Provides the high-order address bus when expanding the device with external program memory • Allows control of the on-chip OTP parallel programming mode. I/O port output configurations are determined on-chip according to one of the options illustrated in Fig.6. They cannot be changed by software. 1998 Oct 07 15 Philips Semiconductors Product specification Pager baseband controller PCA5007 handbook, full pagewidth VDD weak pull-up delay >50 ns strong pull-up p1 p2 hold pull-up p3 I/O pin Q from port latch n IN1 VSS VSS MGR111 input data a. Standard/quasi-bidirectional (option 1). handbook, full pagewidth VDD strong pull-up p1 Q from port latch I/O pin n VSS VDD VSS input data MGR112 b. Push-pull (option 3). handbook, full pagewidth VDD external I/O pin Q from port latch SLEW RATE CONTROL external pull-up n VSS VSS LOW-PASS FILTER input data MGR113 c. Open-drain (only SDA/P1.7, SCL/P1.6; option 2). Fig.6 Port configuration options. 1998 Oct 07 16 Philips Semiconductors Product specification Pager baseband controller 6.6.3 PORT I/O CONFIGURATION PCA5007 Tables 2 to 6 show the hardwired configuration for the different I/Os of the PCA5007. Table 2 Port 0 configuration; notes 1 and 2 CONFIGURATION quasi bidirectional I/O (option 1S) quasi bidirectional I/O (option 1S) quasi bidirectional I/O (option 1S) quasi bidirectional I/O (option 1S) quasi bidirectional I/O (option 1S) quasi bidirectional I/O (option 1R) quasi bidirectional I/O (option 1R) quasi bidirectional I/O (option 1S) PULL-UP INPUT RESET yes yes yes yes yes yes yes yes hys hys hys hys hys hys hys hys HIGH HIGH HIGH HIGH HIGH LOW LOW HIGH DRIVE 0.75 mA 0.75 mA 0.75 mA 0.75 mA 0.75 mA 0.75 mA 0.75 mA 0.75 mA POSSIBLE APPLICATION IN A PAGER LCD_enable (O) SPI_enable (O) SPI_clock (O) SPI_data (O) SPI_data (I) RXE (O) ROE (O) bandwidth (O)/RSSI (I) PORT PIN P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 Notes 1. Option 1S means port configuration option 1 with post-reset set to HIGH; option 1R means post-reset state will be LOW. 2. ‘hys’ means input stage with hysteresis. Table 3 Port 1 configuration CONFIGURATION quasi bidirectional I/O (option 1S) quasi bidirectional I/O (option 1S) quasi bidirectional I/O (option 1S) quasi bidirectional I/O (option 1S) quasi bidirectional I/O (option 1S) not available I2C-bus open-drain I/O (option 2S) (slew rate limited) I2C-bus open-drain I/O (option 2S) (slew rate limited) Port 2 configuration CONFIGURATION quasi bidirectional I/O (option 1S) quasi bidirectional I/O (option 1S) quasi bidirectional I/O (option 1S) quasi bidirectional I/O (option 1S) PULL-UP INPUT RESET yes yes yes yes hys hys hys hys HIGH HIGH HIGH HIGH DRIVE 0.75 mA 0.75 mA 0.75 mA 0.75 mA POSSIBLE APPLICATION IN A PAGER LCD_Data LCD_Data LCD_Data LCD_Data no no hys hys HIGH HIGH 2.25 mA 2.25 mA SCL SDA PULL-UP INPUT RESET yes yes yes yes yes hys hys hys hys hys HIGH HIGH HIGH HIGH HIGH DRIVE 0.75 mA 0.75 mA 0.75 mA 0.75 mA 0.75 mA POSSIBLE APPLICATION IN A PAGER Key Key Key RXD TXD PORT PIN P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 Table 4 PORT PIN P2.0 P2.1 P2.2 P2.3 1998 Oct 07 17 Philips Semiconductors Product specification Pager baseband controller PCA5007 PORT PIN P2.4 P2.5 P2.6 P2.7 Table 5 CONFIGURATION quasi bidirectional I/O (option 1S) quasi bidirectional I/O (option 1S) quasi bidirectional I/O (option 1S) quasi bidirectional I/O (option 1S) PULL-UP INPUT RESET yes yes yes yes hys hys hys hys HIGH HIGH HIGH HIGH DRIVE 0.75 mA 0.75 mA 0.75 mA 0.75 mA POSSIBLE APPLICATION IN A PAGER LCD_Data LCD_Data LCD_Data LCD_Data Port 3 configuration CONFIGURATION not available not available push-pull output (option 3R) push-pull output (option 3R) push-pull output (option 3R) push-pull output (option 3R) not available not available no no no no hys hys hys hys LOW LOW LOW LOW 3 mA 3 mA 3 mA 3 mA call LED vibrator backlight LCD R/W/RXD Enable PULLUP INPUT RESET DRIVE POSSIBLE APPLICATION IN A PAGER PORT PIN P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 The port configuration is fixed and cannot be reconfigured by software or ROM code. Table 6 Other pins CONFIGURATION push-pull output digital input digital input digital input digital input push-pull output analog input/output (10 pF) analog input/output (10 pF) analog output quasi bidirectional I/O quasi bidirectional I/O 3-state I/O with bus keeper PULL-UP INPUT RESET no no no no no no no no no yes yes hold hys hys buffer HIGH HIGH HIGH 1.5 mA 0.75 mA 0.75 mA hys hys hys hys hys LOW 1.5 mA reset input reset output to crystal quartz to crystal quartz LOW DRIVE 3 mA POSSIBLE APPLICATION IN A PAGER tone generator output PORT PIN AT I(D1) Q(D0) TCLK RESETIN RESOUT XTL1 XTL2 AFCOUT ALE PSEN EA 1998 Oct 07 18 Philips Semiconductors Product specification Pager baseband controller 6.7 Timer/event counters PCA5007 In the timer mode the timers count events on the XTL1 input. Timer 0 counts through a prescaler at a rate of 256 Hz and Timer 1 counts directly on both edges of the XTL1 signal at a rate of 153.6 kHz. The nominal frequency of the XTL1 signal is 76.8 kHz. In the counter mode, the register is incremented in response to a HIGH-to-LOW transition at P3.4 (T0) and P3.5 (T1). Besides the different input frequencies and the non-availability of Mode 3, both Timer 0 and Timer 1 behave identically to the standard 80C51 Timer 0 and Timer 1. The PCA5007 contains two 16-bit timer/event counters, Timer 0 and Timer 1, which can perform the following functions: • Measure time intervals and pulse durations • Count events • Generate interrupt requests • Generate output on comparator match • Generate a Pulse Width Modulated (PWM) output signal. Timer 0 and Timer 1 can be programmed independently to operate in four modes: Mode 0: 8-bit timer or 8-bit counter each with divide-by-32 prescaler Mode 1: 16-bit time interval or event counter Mode 2: 8-bit time interval or event counter with automatic reload upon overflow Mode 3: this mode of the standard 80C51 is not available. handbook, full pagewidth XTL1 T0 ÷ 300 256 Hz C/T = 0 TL0 C/T = 1 TR0 TH0 Gate INT0 XTL1 T1 153.6 kHz C/T = 0 TL1 C/T = 1 MGR114 TH1 TR1 Gate INT1 Detailed configuration of the 4 available modes is found in the 80C51 family hardware description (“Philips Semiconductors IC20 Data Handbook”). Fig.7 Timer/counter 0 and 1: clock sources and control logic. 1998 Oct 07 19 Philips Semiconductors Product specification Pager baseband controller 6.8 I2C-bus serial I/O 6.8.1 PCA5007 DIFFERENCES TO A STANDARD I2C-BUS INTERFACE The serial port supports the 2-line I2C-bus which consists of a data line (SDA) and a clock line (SCL). These lines also function as the I/O port lines P1.7 and P1.6 respectively. The system is unique because data transport, clock generation, address recognition and bus control arbitration are all controlled by hardware. The I2C-bus serial I/O has complete autonomy in byte handling. The implementation in the PCA5007 operates in single master mode as: • Master transmitter • Master receiver. These functions are controlled by the S1CON register. S1STA is the status register whose contents may also be used as a vector to various service routines. S1DAT is the data shift register. The block diagram of the I2C-bus serial I/O is shown in Fig.8. The I2C-bus interface of the PCA5007 implements the standard for master receiver and transmitter as defined in e.g. P83CL781/782 with the following restrictions: • The baud rate is fixed to 100 kHz derived from the on-chip 6 MHz oscillator. Therefore bits CR0, CR1 and CR2 in the S1CON SFR are not available. • Only single master functions are implemented. – Slave address (S1ADR) is not available – Status register (S1STA) reports only status defined for the MST/TRX and MST/REC modes – Multimaster operation is not supported. handbook, full pagewidth SDA SHIFT REGISTER INTERNAL BUS MGL449 S1DAT ARBITRATION LOGIC SCL BUS CLOCK GENERATOR 7 S1CON 6 5 4 3 2 1 0 7 S1STA 6 5 4 3 2 1 0 Fig.8 Block diagram of I2C-bus serial I/O. 1998 Oct 07 20 Philips Semiconductors Product specification Pager baseband controller 6.8.2 Table 7 7 − Table 8 BIT S1CON.7 S1CON.6 SERIAL CONTROL REGISTER (S1CON) Serial Control Register (S1CON, SFR address D8H) 6 ENS1 5 STA 4 STO 3 SI 2 AA 1 − PCA5007 0 − Description of the S1CON bits SYMBOL − ENS1 CR2 is not available. Enable Serial I/O. When ENS1 = 0, the serial I/O is disabled. SDA and SCL outputs are in the high-impedance state; P1.6 and P1.7 function as open-drain ports. When ENS1 = 1, the serial I/O is enabled. Output port latches P1.6 and P1.7 must be set to logic 1. START flag. If STA is set while the SIO is in master mode, SIO will generate a repeated START condition. STOP flag. With this bit set while in master mode a STOP condition is generated. When a STOP condition is detected on the I2C-bus, the SIO hardware clears the STO flag. SIO interrupt flag. This flag is set, and an interrupt is generated, after any of the following events occur: • A START condition is generated in master mode • A data byte has been received or transmitted in master mode (even if arbitration is lost). If this flag is set, the I2C-bus is halted (by pulling down SCL). Received data is only valid until this flag is reset. FUNCTION S1CON.5 S1CON.4 S1CON.3 STA STO SI S1CON.2 AA Assert Acknowledge. When this bit is set, an acknowledge (LOW level to SDA) is returned during the acknowledge clock pulse on the SCL line when: • A data byte is received while the device is programmed to be a master receiver. When this bit is reset, no acknowledge is returned. S1CON.1 S1CON.0 6.8.3 − − CR1 and CR0 are not available. DATA SHIFT REGISTER (S1DAT) S1DAT contains the serial data to be transmitted or data which has just been received. Bit 7 is transmitted or received first; i.e. data shifted from left to right. Table 9 7 D7 6.8.4 Data Shift Register (S1DAT, SFR address DAH) 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 ADDRESS REGISTER (S1ADR) The slave address register is not available since slave mode is not supported. 6.8.5 SERIAL STATUS REGISTER (S1STA) The contents of this register may be used as a vector to a service routine. This optimizes the response time of the software and consequently that of the I2C-bus. S1STA is a read-only register. The status codes for all available modes of a single master I2C-bus interface are given in Tables 12 to 14. 1998 Oct 07 21 Philips Semiconductors Product specification Pager baseband controller Table 10 Serial Status Register (S1STA and SFR address D9H) 7 SC4 6 SC3 5 SC2 4 SC1 3 SC0 2 0 1 0 PCA5007 0 0 Table 11 Description of the S1STA bits BIT S1STA.3 to S1STA.7 S1STA.0 to S1STA.2 Table 12 MST/TRX mode S1STA VALUE 08H 10H 18H 20H 28H 30H Table 13 MST/REC mode S1STA VALUE 40H 48H 50H 58H Table 14 Miscellaneous S1STA VALUE 78H DESCRIPTION no information available (reset value); the serial interrupt flag SI, is not yet set DESCRIPTION SLA and R have been transmitted, ACK received SLA and R have been transmitted, ACK received DATA has been received, ACK returned DATA has been received, ACK returned DESCRIPTION a START condition has been transmitted a repeated START condition has been transmitted SLA and W have been transmitted, ACK has been received SLA and W have been transmitted, ACK received DATA of S1DAT has been transmitted, ACK received DATA of S1DAT has been transmitted, ACK received SYMBOL SC4 to SC0 − 5-bit status code these 3 bits are held LOW FUNCTION Table 15 Symbols used in Tables 12 to 14 SYMBOL SLA R W ACK ACK DATA MST SLV TRX REC 7-bit slave address read bit write bit acknowledgement (acknowledge bit = logic 0) no acknowledgement (acknowledge bit = logic 1) 8-bit data byte to or from I2C-bus master slave transmitter receiver DESCRIPTION 1998 Oct 07 22 Philips Semiconductors Product specification Pager baseband controller 6.9 Serial interface SIO0: UART The serial port can operate in 2 modes: PCA5007 The UART interface of the PCA5007 implements a subset of the complete standard as defined in e.g. the P80CL580. 6.9.1 DIFFERENCES TO THE STANDARD 80C51 UART The following deviations from the standard exist: • If [SM1 and SM0] = 10 then Mode 1 (8-bit data transmission) is selected, with a fixed baud rate (4800/9600 bits/s) • If [SM1 and SM0] = 01 then Mode 2 (9-bit data transmission) is selected, with a fixed baud rate (4800/9600 bits/s) • Modes 0 and 3 and the variable baud rate selection using Timer 1 overflow is not available • The SM2 bit has no function • The time reference for Modes 1 and 2 is taken from the f OSC 76.8 kHz oscillator, instead of the original ---------12 6.9.2 UART MODES Mode 1 10 bits are transmitted (through TXD) or received (through RXD): a START bit (0), 8 data bits (LSB first) and a STOP bit (1). On receive, the stop bit goes into RB8 in special function register S0CON (see Figs 9 and 10). Mode 2 11 bits are transmitted (through TXD) or received (through RXD): a START bit (0), 8 data bits (LSB first), a programmable 9th data bit and a STOP bit (1). On transmit, the 9th data bit (TB8 in S0CON) can be assigned the value of 0 or 1. Or, for example, the parity bit (P, in the PSW) could be moved into TB8. On receive, the 9th data bit goes into RB8 in S0CON, while the STOP bit is ignored (see Figs 9 and 11). In both modes the baud rate can be selected to either 4800 or 9600 depending on the SMOD bit in the PCON SFR. If SMOD = 0 the baud rate is 4800, if SMOD = 1 the baud rate is 9600 with a 76.8 kHz quartz crystal. In both modes, transmission is initiated by any instruction that uses S0BUF as a destination register. Reception is initiated by the incoming start bit if REN = 1. 6.9.3 SERIAL PORT CONTROL REGISTER (S0CON) This serial port is full duplex which means that it can transmit and receive simultaneously. It is also receive-buffered and can commence reception of a second byte before a previously received byte has been read from the register. However, if the first byte has not been read by the time the reception of the second byte is complete, the second byte will be lost. The serial port receive and transmit registers are both accessed via the special function register S0BUF. Writing to S0BUF loads the transmit register and reading from S0BUF accesses a physically separate receive register. The serial port control and status register is the special function register S0CON (see Table 16). The register contains not only the mode selection bits, but also the 9th data bit for transmit and receive (TB8 and RB8), and the serial port interrupt bits (TI and RI). Table 16 Serial Port Control Register (S0CON, SFR address 98H) 7 SM0 6 SM1 5 − 4 REN 3 TB8 2 RB8 1 TI 0 RI 1998 Oct 07 23 Philips Semiconductors Product specification Pager baseband controller Table 17 Description of the S0CON bits BIT S0CON.7 S0CON.6 S0CON.5 S0CON.4 S0CON.3 S0CON.2 S0CON.1 SYMBOL SM0 SM1 − REN TB8 RB8 TI FUNCTION PCA5007 this bit together with the SM1 bit, is used to select the serial port mode; see Table 18 this bit together with the SM0 bit, is used to select the serial port mode; see Table 18 SM2 is not available this bit enables serial reception and is set by software to enable reception, and cleared by software to disable reception this bit is the 9th data bit that will be transmitted in Mode 2; set or cleared by software as desired in Mode 2, this bit is the 9th data bit received; in Mode 1 it is the stop bit that was received The transmit interrupt flag; Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit time in the other modes, in any serial transmission; must be cleared by software. The receive interrupt flag; Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the other modes, in any serial transmission (for exception see SM2); must be cleared by software. S0CON.0 RI Table 18 Selection of the serial port modes SM0 0 1 6.9.4 SM1 1 0 MODE 1 2 DESCRIPTION 8-bit UART 9-bit UART BAUD RATE 1⁄ f 16 osc 1⁄ f 16 osc or 1⁄8fosc or 1⁄8fosc UART DATA REGISTER (S0BUF) The UART data register (S0BUF) contains the serial data to be transmitted or data which has just been received. Bit 0 is transmitted or received first. Table 19 Data Shift Register (S0BUF, SFR address 99H) 7 D7 6.9.5 6 D6 BAUD RATES SMOD 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 The baud rate in Modes 1 and 2 depends on the value of the SMOD bit in SFR PCON and may be calculated as: 2 Baud rate = ---------------- × f osc 16 • If SMOD = 0, (which is the value on reset), the baud rate is 1⁄16fosc • If SMOD = 1, the baud rate is 1⁄8fosc. 1998 Oct 07 24 Philips Semiconductors Product specification Pager baseband controller PCA5007 handbook, full pagewidth INTERNAL BUS TB8 write to SBUF XTL1 DS CL Q S0 BUFFER TXD 2 0 CSMOD at PCON.7 1 SHIFT ZERO DETECTOR STOP BIT START 8 TX CLOCK TX CONTROL T1 SHIFT DATA SEND serial port interrupt 8 sample HIGH-TO-LOW TRANSITION DETECTOR RX CLOCK START R1 LOAD SBUF SHIFT RX CONTROL BIT DETECTOR RXD LOAD SBUF INPUT SHIFT REGISTER (9-BITS) SHIFT S0 BUFFER READ SBUF INTERNAL BUS MGL452 Fig.9 Serial port Mode 1and Mode 2. 1998 Oct 07 25 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1998 Oct 07 TX CLOCK WRITE TO SBUF SEND DATA SHIFT TXD START BIT TI ÷8 RESET D0 D1 D2 D3 D4 D5 D6 D7 STOP BIT T R A N S M I T handbook, full pagewidth Philips Semiconductors Pager baseband controller 26 R E C E I V E RX CLOCK START BIT RXD D0 D1 D2 D3 D4 D5 D6 D7 STOP BIT BIT DETECTOR SAMPLE TIME SHIFT RI MGL451 Product specification PCA5007 Fig.10 Serial port Mode 1 timing. This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1998 Oct 07 TX CLOCK WRITE TO SBUF SEND DATA SHIFT TXD START BIT TI STOP BIT GEN ÷8 RESET RX CLOCK R E C E I V E START BIT RXD D0 D1 D2 D3 D4 D5 D6 D7 RB8 STOP BIT D0 D1 D2 D3 D4 D5 D6 D7 TB8 STOP BIT T R A N S M I T handbook, full pagewidth Philips Semiconductors Pager baseband controller 27 BIT DETECTOR SAMPLE TIME SHIFT RI MGL450 Product specification PCA5007 Fig.11 Serial port Mode 2 timing. Philips Semiconductors Product specification Pager baseband controller 6.10 6.10.1 76.8 kHz oscillator FUNCTION PCA5007 The whole circuit operates directly at the battery supply. The 76.8 kHz oscillator cannot be disabled. It also continues its operation during DC/DC converter off or 8051 stop mode. The simplest application configuration is shown in Fig.12a. C1 and C2 can be added to operate a crystal at its optimum load condition. The resulting capacitance of the series connection of C1 and C2 must be smaller than 5 pF for a guaranteed start-up of the oscillator. The oscillator produces a reference frequency of 76.8 kHz. The frequency offset is compensated for by a separate digital clock correction block. The oscillator operates directly on VBAT and is always enabled. 6.10.2 OSCILLATOR CIRCUITRY The on-chip inverting oscillator amplifier is a single NMOS transistor supplied with a constant current. The amplitude visible at terminals XTL1 and XTL2 is therefore not a full rail swing with a very high impedance. To reduce the power consumption, the input Schmitt trigger buffer is limited to approximately 100 kHz maximum frequency. handbook, full pagewidth 76.8 kHz 76.8 kHz 76.8 kHz 10 pF 10 pF 10 pF 10 pF 10 pF 10 pF XTL1 76.8 kHz 2 MΩ XTL2 XTL1 76.8 kHz XTL2 XTL1 VP = VBAT XTL2 2 MΩ C1 C2 fmax = 100 kHz MGR115 (a) (b) (c) Fig.12 Oscillator circuit. 1998 Oct 07 28 Philips Semiconductors Product specification Pager baseband controller 6.11 Clock correction 6.11.1 FUNCTION PCA5007 Crystal offset correction can be performed with a resolution of 5 ppm. This block also generates the timing reference signals for other functional blocks such as the RTC (4 Hz), watchdog (16 Hz), Timer 0 (256 Hz), wake-up counter (9600 Hz) and the demodulator/clock recovery block. The generation of these timing references is always active and cannot be disabled. The clock correction block is connected to the 76.8 kHz oscillator. It operates directly from VBAT. By means of the clock correction circuit a digital adjustment of the 76.8 kHz oscillator signal is implemented. An 18-bit interval counter inserts or deletes one pulse from the 76.8 kHz clock each time its count has expired. The interval is stored by the processor to the 18-bit interval register CIV. Addition or deletion is performed by hardware. handbook, full pagewidth VDD supply RESET with each OFF cycle SFR to microcontroller SET ENB PLUS BYPASS TEST CIV0 to CIV17 1 D internal set flag INTERVAL LATCH (18-BIT) Q STORE RESET only on RESETIN reload data Q D R 76.8 kHz & INTERVAL COUNTER (18-BIT) (RELOAD ON CARRY) CARRY corrected 38.4 kHz ÷2 VBAT supply ADD/DELETE ONE PULSE ON CARRY MGR116 Fig.13 Block diagram for clock compensation. 1998 Oct 07 29 Philips Semiconductors Product specification Pager baseband controller 6.11.2 CLOCK CORRECTION CONTROL REGISTER (CCON) PCA5007 The CCON special function register is used to control the clock correction by software. Table 20 Clock Correction Control Register (CCON, SFR address FCH) 7 ENB 6 PLUS 5 TEST 4 CIV17 3 CIV16 2 − 1 BYPASS 0 SET Table 21 Description of the CCON bits BIT CCON.7 CCON.6 CCON.5 SYMBOL ENB PLUS TEST FUNCTION Enable clock correction. If ENB = 1 has been set, then correction is enabled and will stay enabled even when the DC/DC converter is shut down and restarted. ± sign for value. If PLUS = 1 then clock pulses are inserted, or else deleted. Test signal, must always be logic 0 in normal mode. It is s used during test to bypass the first 9 FFs in the timing generator divider chain. If TEST = 1 the clock rate of the signals 9600 Hz and 256 Hz is doubled and the frequency on 16 Hz and 4 Hz is multiplied by 300. bit 17 of interval value, is used as extension of CC0 and CC1 bit 16 of interval value, is used as extension of CC0 and CC1 unused. Test signal, must always be logic 0 in normal mode. It is used during test to generate 76.8 kHz on all outputs of the timing generator (4 Hz, 16 Hz, 256 Hz and 9600 Hz). A load signal to the interval register. After a logic 0 to logic 1 transition of this bit the value of ENB, PLUS, TEST, BYPASS and CIV are copied into the local latches with the next 76.8 kHz clock pulse. The duration of one MOV instruction is long enough for the set operation to complete. The SFR values must remain stable for at least one oscillator period because the actual transfer happens synchronized with the local clock (see Figs 14 and 16). CCON.4 CCON.3 CCON.2 CCON.1 CCON.0 CIV17 CIV16 − BYPASS SET 6.11.3 CLOCK CORRECTION INTERVAL REGISTERS (CC0 AND CC1) The CC0 and CC1 special function registers (together with CCON.3 and CCON.4) are used to define the interval between subsequent clock correction actions. Table 22 Clock Correction Interval Register (CC0, SFR address FDH) 7 CIV7 6 CIV6 5 CIV5 4 CIV4 3 CIV3 2 CIV2 1 CIV1 0 CIV0 Table 23 Clock Correction Interval Register (CC1, SFR address FEH) 7 CIV15 6 CIV14 5 CIV13 4 CIV12 3 CIV11 2 CIV10 1 CIV9 0 CIV8 1998 Oct 07 30 Philips Semiconductors Product specification Pager baseband controller 6.11.4 EXAMPLE SEQUENCE TO SET ANOTHER CLOCK CORRECTION INTERVAL PCA5007 handbook, full pagewidth PLUS, ENB and CIV valid value in SFR must stay valid for one period of 76.8 kHz SET MGR117 Fig.14 Sequence for setting the clock compensation. MOV CC0, #(CIV7 to CIV0). MOV CC1, #(CIV8 to CIV15). MOV CCON, #D4H. MOV CCON, #D5H. 6.11.5 TIMING Figures 15 and 16 illustrate how the clock correction works and how the access of the microcontroller is synchronized to the local operation. handbook, full pagewidth [CIV] − 1 [CIV] − 2 [CIV] − 3 [CIV] − 4 [CIV] − 5 [CIV] − 1 [CIV] − 2 [CIV] − 3 [CIV] − 4 [CIV] 76.8 kHz 38.4 kHz CORR for clock recovery corrected 38.4 kHz with PLUS = 1 corrected 38.4 kHz with PLUS = 0 [CIV] Interval counter 6 5 4 3 2 1 0 MGR118 After (CIV) clock ticks of 76.8 kHz or 38.4 kHz one correction is made. Fig.15 Operation of clock compensation. 1998 Oct 07 31 [CIV] − 5 7 6 5 4 3 2 1 0 Philips Semiconductors Product specification Pager baseband controller PCA5007 SET (SFR) handbook, full pagewidth SET flag (local) 76.8 kHz store (local) data (SFR) K data (local) reload from local data counter I I−1 I−2 I−3 I−4 1 0 K K K−1 K−2 MGR119 Fig.16 Synchronization of local counter operation and access from the microcontroller. 6.12 6.12.1 6 MHz oscillator FUNCTION The DC/DC converter does not need the 6 MHz clock when set in the standby mode. If the 6 MHz output is required as a frequency source for other blocks (e.g. I2C-bus) the software needs to enable it explicitly by setting ENB = 1. Besides the DC/DC converter the following functions require the operation of the 6 MHz oscillator: • I2C-bus block as basic time reference • Port output logic. Software commands that write to the ports need this clock to complete the operation (if a program ‘hangs’, this could be the problem). • Code fetching from external memories needs the clock for the ALE/PSEN timing (e.g. LJMP 5000H needs this clock for completion). When the ENB bit has been set by software, the clock will be available internally after the start-up time of this oscillator. The start-up time is 2 to 3 periods of the 76.8 kHz reference frequency. The 6 MHz oscillator provides the clock for the DC/DC converter, the I2C-bus interface, the port I/Os and for the external memory access timing (ALE/PSEN). The 6 MHz oscillator is a 5 inverter stage current controlled ring oscillator. The oscillator is optimized for low operating current consumption. The actual frequency of the oscillator can be measured by activating the MFR signal. An 8-bit counter will then be reset and will start counting at the first rising edge of the 76.8 kHz signal and will stop counting at the next rising edge of the 76.8 kHz signal. The processor then can read the contents of the MFR counter. The processor can adjust the oscillator frequency using the F0 to F4 signals (control of source current for ring oscillator). The 6 MHz oscillator is enabled by hardware only during the start-up phase and whenever the DC/DC converter needs the 6 MHz clock. In all other cases the 6 MHz oscillator is switched off by hardware. 1998 Oct 07 32 Philips Semiconductors Product specification Pager baseband controller 6.12.2 6 MHZ OSCILLATOR CONTROL REGISTER (OS6CON) PCA5007 The OS6CON special function register is used to control the operation of the on-chip 6 MHz oscillator. The 6 MHz oscillator can be controlled as follows: • It can be enabled or disabled. Disabling this oscillator when the DC/DC converter is in standby mode and no port I/O nor I2C-bus activity is required saves current. • The frequency of the oscillator can be adjusted by setting the SFx bits accordingly • The actual frequency of the oscillator can be measured by writing the MFR bit to logic 1. Table 24 6 MHz Oscillator Control Register (OS6CON, SFR address D3H) 7 ENB 6 − 5 SF4 4 SF3 3 SF2 2 SF1 1 SF0 0 MFR Table 25 Description of the OS6CON bits BIT OS6CON.7 SYMBOL ENB FUNCTION Enable oscillator. If ENB = 1 then the function is enabled. The enable bit is only cleared when the processor writes the bit to logic 0, or if the DC/DC converter is put into ‘OFF’ state and a reset is generated during the following power-up sequence. unused Set frequency. This 5-bit value adjusts the current of the ring oscillator and thus the frequency. Writing a small value decreases the frequency. The nominal frequency of 6 MHz is assigned to code (SF4, SF3, SF2, SF1 SF0) = 00000. The resolution of the frequency adjustment is 200 kHz per step, the range is approximately 3 to 9 MHz. In order to start with the nominal frequency the MSB bit is inverted in this SFR. Measure frequency. If a positive pulse is issued on this SFR-bit a frequency measurement cycle is executed. The duration of this cycle is one period of 76.8 kHz. The count of 6 MHz periods during the measurement cycle is reported back in OS6M0. The bit must be reset by software. OS6CON.6 OS6CON.5 OS6CON.4 OS6CON.3 OS6CON.2 OS6CON.1 OS6CON.0 − SF4 SF3 SF2 SF1 SF0 MFR 6.12.3 6 MHZ OSCILLATOR MEASURED FREQUENCY REGISTER (OS6M0) The actual frequency of the 6 MHz on-chip oscillator can be calculated from the value in the OS6M0 special function register, after a Measure Frequency operation (MFR). Table 26 6 MHz Oscillator Measured Frequency Register (OS6M0, SFR address D4H) 7 MF7 6 MF6 5 MF5 4 MF4 3 MF3 2 MF2 1 MF1 0 MF0 The value stored in this SFR is the counted number of 6 MHz cycles during one 76.8 kHz period. The frequency of the 6 MHz oscillator is therefore f = MF × 76800 Hz with a resolution of 76800 Hz. 1998 Oct 07 33 Philips Semiconductors Product specification Pager baseband controller 6.12.4 ENABLING OF THE 6 MHZ OSCILLATOR PCA5007 handbook, full pagewidth S0CON, S0BUF I2C-BUS SERIAL INTERFACE PX PORT I/O EXTERNAL ACCESS & MICROCONTROLLER OS6CON, ENB 6 MHz OSCILLATOR ≥1 ENB DC/DC CONVERTER MGR120 ENB F6M Fig.17 Relationship between 6 MHz oscillator, DC/DC converter and microcontroller. 6.13 6.13.1 Real-time clock FUNCTION The Real-Time Clock (RTC) consists of an 8-bit counter that is active at all times. To save power it is operated directly on VBAT. It counts up on every 4 Hz clock pulse (corrected clock). The RTC can be read from and written to by the processor. When it reaches 239, the signal MINUTE is activated. This signal resets the counter to 0 (at the next clock pulse), and generates a MIN-interrupt for the processor. The microcontroller ‘sees’ the minute interrupt as if it was an X9 interrupt. It can be enabled and disabled and must be cleared as an X9 interrupt (CLR IQ9). If the DC/DC converter is not active when this happens, the DC/DC converter is started first, and a power-up/restart sequence of the microcontroller follows. The MIN bit remains set during this procedure. 6.13.2 REAL-TIME CLOCK CONTROL REGISTER (RTCON) The RTCCON special function register is used to control the operation of the on-chip real-time clock function. 1998 Oct 07 34 Philips Semiconductors Product specification Pager baseband controller Table 27 RTC Control Register (RTCCON, SFR address CDH) 7 MIN 6 − 5 − 4 − 3 − 2 W/R 1 LOAD PCA5007 0 SET Table 28 Description of the RTCON bits BIT RTCON.7 SYMBOL MIN FUNCTION MIN is activated when the counter reaches 239. MIN is used to generate the interrupt request signal MINUTE. In order to complete the interrupt cycle and reset the interrupt source, the processor has to clear MIN. This must be done in a 2 step operation writing MIN and then applying a positive edge to SET. unused unused unused unused Before the RTC time can be set by software, the updating of the SFR by the RTC must be disabled. This is done by writing the W/R bit to logic 1. The W/R bit is cleared by hardware after the next 4 Hz clock, when the RTC has been loaded with its next value. Load RTC with contents of RTC0. LOAD is sampled with the positive edge of the set flag SET. If LOAD is not HIGH during a SET operation, only the MIN flag is (re)set by the command. Latch signal for the real-time clock. With the pulse on SET the content of MIN is copied into the ‘real’ MIN latch. This is necessary because the RTC has to be active at all times independant of the microcontroller. RTCON.6 RTCON.5 RTCON.4 RTCON.3 RTCON.2 − − − − W/R RTCON.1 LOAD RTCON.0 SET 6.13.3 REAL-TIME CLOCK DATA REGISTER (RTC0) Table 29 RTC Data Register (RTC0, SFR address CEH) 7 QSECS7 6 QSECS6 5 QSECS5 4 QSECS4 3 QSECS3 2 QSECS2 1 QSECS1 0 QSECS0 The value stored in this SFR is the actual 4 Hz count since the last MINUTE interrupt. The contents of this counter can be read from and written to by software. The contents of this counter are only initialized when RESETIN is activated. During an OFF sequence, the RTC continues its operation. The value of the RTC data register is only updated while the STB flag in the DCCON0 SFR is HIGH, i.e. the DC/DC converter is able to sustain the VDD supply voltage. If the STB flag is at logic 0 the real-time clock continues its operation, the MINUTE interrupt occurs regularly, but the SFR is not updated. 1998 Oct 07 35 Philips Semiconductors Product specification Pager baseband controller 6.13.4 EXAMPLE SEQUENCE FOR PROGRAMMING THE RTC: PCA5007 Sequence to clear an interrupt of the RTC: CLR IQ9; Interrupt request flag is IQ9 MOV RTCON, #00H; clear also MIN flag in the SFR MOV RTCON, #01H; now set the data valid flag (SET) in the SFR. 6.13.5 TIMING Sequence to set another value into the RTC: MOV RTCON, #06H; set LOAD, W/R bits MOV RTC0, #(new value); load new RTC value into SFR MOV RTCON, #07H; now set the data valid flag (SET) in the SFR. The interface between 2 and 1 V regions is implemented similar to the clock correction block. The sequence for writing values is identical (see Fig.13). handbook, full pagewidth 4 Hz update by hardware data (RTC0) i i+1 MOV RTC0 #m m data must be valid until here update by hardware m+1 W/R (RTCON) MOV RTCON #... LOAD (RTCON) cleared by hardware SET (RTCON) internal SET flag internal store internal write RTC value i i+1 m m+1 MGR121 Fig.18 Operation of RTC to microcontroller interface. 1998 Oct 07 36 Philips Semiconductors Product specification Pager baseband controller 6.14 6.14.1 Wake-up counter FUNCTION PCA5007 The counter is implemented as a 16-bit ripple-down counter. It can be loaded from the wake-up reload latch by a signal from the processor. When the counter is loaded it automatically starts if the RUN signal is active. When the counter reaches zero the wake-up signal becomes active and may generate an interrupt. The wake-up signal automatically reloads the counter (modulo N counter). The counter is stopped when the RUN signal is written to logic 0. Auto reloading of the counter is also possible, when the DC/DC converter is not operating (i.e. VDD is below 1.8 V). The contents of the wake-up counter cannot be read by the processor. Reading WUC0 and WUC1 reflects the contents of the 16-bit wake-up register (set by the microcontroller). The interface between the 2 and 1 V regions is implemented similar to the clock correction block. The sequence for writing values is identical (see Fig.14). The wake-up counter is intended to be used as a protocol timer. It can be programmed to wake-up the processor when the protocol needs an action. Amongst others this may be: • Switching on the DC/DC converter at time 0 • Enabling the receiver at time 1 • Enabling the demodulator and clock recovery function at time 2 before relevant data is expected. The time to wake-up is defined as a 16-bit value containing the number of 9600 Hz ticks. The maximum time interval that can be spawn with one cycle then equals 6.8 s. The wake-up counter and its reload latch are supplied by VBAT and operate independent of the 2 V supply. A reset to the microcontroller does not clear the wake-up counter control flags or the reload latch, but clears the reload register (see Fig.19). handbook, full pagewidth Interrupt ≥1 VDD supply SFR to microcontroller SET CPL RUN LOAD WUP TEST Z1 Z0 WU0 to WU15 RESET with each OFF cycle wake-up DC/DC converter 1 D internal SET FLAG WU RELOAD LATCH (16-BIT) Q STORE reload RESET only on RESETIN R ≥1 reload data Q D 9600 Hz & WU COUNTER (16-BIT) CARRY VBAT supply MGR122 Fig.19 Block diagram of the wake-up counter. 1998 Oct 07 37 Philips Semiconductors Product specification Pager baseband controller 6.14.2 WAKE-UP COUNTER CONTROL REGISTER (WUCON) PCA5007 The WUCON special function register is used to control the operation of the wake-up counter by software. Table 30 Wake-up Counter Control Register (WUCON, SFR address 94H) 7 RUN 6 WUP 5 TEST 4 CPL 3 Z1 2 Z0 1 LOAD 0 SET Table 31 Description of the WUCON bits BIT WUCON.7 WUCON.6 SYMBOL RUN WUP Control signal from the processor. Latched Wake-Up signal. The bit is set by hardware (or software) and generates a wake-up interrupt if enabled and the DC/DC STB bit is set. The bit needs to be cleared by software (SFR and 1 V bits). A SET sequence is required to clear the flag on the 1 V side. Attention: reading the bit reads the contents of the ‘real’ wake-up flag on the 1 V side, (read/modify/write commands will fail on this bit). Test control signal (uses 76.8 kHz as clock input for high and low counter). Set operation completed. Bit set by hardware when the last operation is completed and the SFRs are again ready to accept new settings. The bit generates a wake-up interrupt if enabled. The bit needs to be cleared by software. 2 bits that are only reset by a primary RESETIN. The bits can be written to and read from by the software. The bits are not cleared when the DC/DC converter is switched off. Same procedure for setting the bits as WU0 to WU15 (reading these bits returns the ‘real’ flags on the 1 V side; read/modify/write commands will fail on this bit). Load wake-up counter with contents of reload latch (see Fig.19). Is sampled on the positive edge of SET. Clock signal for writing to RUN or wake-up SFR (on 1 V level). FUNCTION WUCON.5 WUCON.4 TEST CPL WUCON.3 WUCON.2 Z1 Z0 WUCON.1 WUCON.0 6.14.3 LOAD SET WAKE-UP DATA REGISTERS (WUC0, WUC1) The WUC0 and WUC1 special function registers are used to define the interval to the next wake-up interrupt. Table 32 Low Wake-UP Register (WUC0, SFR address 95H) 7 WU7 6 WU6 5 WU5 4 WU4 3 WU3 2 WU2 1 WU1 0 WU0 Table 33 High Wake-UP Register (WUC1, SFR address 96H) 7 WU15 6 WU14 5 WU13 4 WU12 3 WU11 2 WU10 1 WU9 0 WU8 1998 Oct 07 38 Philips Semiconductors Product specification Pager baseband controller WU0 to WU15 is a 16-bit register that is loaded by the processor. The contents of this register will be loaded into a 16-bit reload latch with a positive pulse on SET and into the 16-bit ripple-down counter with a positive pulse on LOAD. The value stored in the wake-up counter cannot be read by software. The contents of this counter are only initialized when RESETIN is activated. During an off sequence, the wake-up counter continues its operation. The wake-up interrupt can only occur while the STB flag in the DCCON0 SFR is HIGH, i.e. the DC/DC converter is able to sustain the VDD supply voltage. If the STB flag is at logic 0 the wake-up counter continues its operation, the WUP flag is set when expired (but can still be checked by software) but an interrupt is not generated. 6.14.5 TIMING 6.14.4 PCA5007 EXAMPLE SEQUENCE FOR CONTROLLING THE WAKE-UP COUNTER Sequence to set another reload value: MOV WUC1, #(high VALUE) MOV WUC0, #(low VALUE) MOV WUCON, #82H; set RUN and LOAD bit MOV WUCON, #83H; activate SET flag MOV PCON, #01H; >>> IDLE, WAIT FOR CPL INTERRUPT. handbook, full pagewidth 9600 Hz transfer to 1 V registers completed, data may change again data in SFR m LOAD SET bit in SFR internal SET flag internal STORE internal data m counter value i i−1 m m−1 CPL bit in WUCON (generates interrupt if enabled) set by hardware cleared by software MGR123 Fig.20 Operation of wake-up counter to microcontroller interface. 1998 Oct 07 39 Philips Semiconductors Product specification Pager baseband controller PCA5007 handbook, full pagewidth 9600 Hz LOAD only WUCON data to be transferred, no reload for WUC0, WUC1 SET bit in SFR SET to transfer modified WUP to 1 V side internal SET flag counter value 0 m m−1 WUP remains HIGH if not cleared WUP flag on 1 V side generates DC/DC wake-up if required set by hardware SFR and 1 V WUP are different WUP in WUCON SFR (generates interrupt if enabled) set by hardware cleared by software CPL in WUCON SFR (generates interrupt if enabled) set by hardware cleared by software MGR124 Fig.21 Wake-up interrupt sequence. 6.15 6.15.1 Tone generator FUNCTION The tone generator is implemented by a programmable divider from 76.8 kHz. An 8-bit value is used to define the cycle of a modulo N counter. The output of the modulo N counter is divided-by-2 to produce a symmetrical output signal. The counter is running when enabled. 76.8 kHz The output frequency at the pin AT is defined as: f AT = ---------------------- if TFREQ ≥ 1. If TFREQ = 0 then fAT = 76.8 kHz. TFREQ A secondary clock signal can be used as clock input to the modulo N counter. This input is required to generate the accurate resonance frequency of certain acoustic alerters (e.g. 512, 687, 1024, 1365, 2048, 2730, 4096). The tone volume can be controlled by setting the frequency on or off alerter resonance. 6.15.2 INTERFACES BIT 7 ENB TFREQ7 BIT 6 CLK2 TFREQ6 BIT 5 − TFREQ5 BIT 4 − TFREQ4 BIT 3 − TFREQ3 BIT 2 − TFREQ2 BIT 1 − TFREQ1 BIT 0 − TFREQ0 SFR ADDRESS TGCON (92H) TG0 (93H) 1998 Oct 07 40 Philips Semiconductors Product specification Pager baseband controller SFR: • TFREQ0 to TFREQ7: 8-bit register containing the divisor of the tone. Loaded by the processor. • ENB: Enable frequency generator. Control signal from processor. • CLK2: Use secondary clock input for tone generation. If set a 32768 Hz clock signal is generated from the primary 76800 Hz clock signal and used as a timing reference for the tone generator. Inputs: • 76.8 kHz: Input to the tone counter. Outputs: • AT: Output for alerter. Is logic 0 when disabled: 76.8 kHz f AT = ---------------------TFREQ 6.15.3 GENERATION OF THE 32768 HZ REFERENCE 6.16 6.16.1 Watchdog timer FUNCTION PCA5007 The watchdog timer consists of an 8-bit down counter. The binary number defined with WD3 to WD0 defines the expiry time of the watchdog timer between 1 to 16 s. Once enabled this counter is running continuously. Once expired the timer produces firstly an interrupt and finally a reset. The software must reload the watchdog in regular intervals to avoid expiry. A positive edge on the LD SFR bit (re)loads the counter with the value of WD3 to WD0, sets the LOW bits to logic 1 and activates this counter if it is not yet running. However, to prepare the (re)loading a positive edge must be applied to the COND bit in WDCON. In this way at least two locations in software must be passed before the counter can be reloaded. After reset the counter is not running. Only after the first LD it is clocked continuously by a clock pulse of 16 Hz until the DC/DC converter is switched off or an external reset is applied. If the next LD signal is not given within the defined expiry interval an overflow occurs and the processor will be reset (signal WDR). A WDI interrupt is issued one clock cycle before the reset is applied. This gives the opportunity to avoid the reset if required. The maximum watchdog expiry time is thus 254 × 16 Hz ticks to the WD interrupt and 255 × 16 Hz ticks to the reset. If the DC/DC converter is in the off mode, the watchdog timer is suspended. The 32768 Hz reference is generated from 76800 Hz according to the following algorithm: forever do begin for 10 times do { from 7 clocks on 76.8 kHz generate 3 pulses on 32 kHz } from 5 clocks on 76.8 kHz generate 2 pulses on 32 kHz end 6.16.2 WATCHDOG TIMER CONTROL REGISTER (WDCON) The WDCON special function register is used to control the operation of the on-chip watchdog timer. Table 34 Watchdog Control Register (WDCON, SFR address A5H) 7 COND 6 WD3 5 WD2 4 WD1 3 WD0 2 − 1 − 0 LD 1998 Oct 07 41 Philips Semiconductors Product specification Pager baseband controller Table 35 Description of the WDCON bits BIT WDCON.7 WDCON.6 WDCON.5 WDCON.4 WDCON.3 WDCON.2 WDCON.1 WDCON.0 6.16.3 SYMBOL COND WD3 WD2 WD1 WD0 − − LD unused unused FUNCTION Load condition. Control signal from processor. PCA5007 WD0 to WD3 is the preset value for the high nibble of the watchdog timer. The value is the number of seconds to expiry of the watchdog. Load watchdog timer with WD0 to WD3. Control signal from processor. The offset coding is given in Table 37. Both the filter and direct modes are intended for applications with an external demodulator. In this case, at the I and Q pins, there are fed NRZ data. In the 4-FSK situation the MSB is at pin I and the LSB is at pin Q. In the 2-FSK situation, only pin I is used; pin Q must be connected to VSS. In these two modes, the offset calculation and compensation cannot be performed. In the filter mode (M = 1 and BF = 0), the data is filtered and then sent to the clock recovery. In the direct mode (M = 1 and BF = 1), no function of the demodulator is performed. Consequently there is no filtering on the data which is sent directly to the clock recovery. Table 36 Modulation coding FREQUENCY (Hz) +4800 2-FSK D1 1 1 0 0 D0 X X X X D1 1 1 0 0 4-FSK D0 0 1 1 0 SAMPLE SEQUENCE TO RELOAD THE WATCHDOG The sequence to reload the watchdog with 1 s is: MOV WDCON, #80H; prepare condition. MOV WDCON, #01H; reload the timer. 6.17 6.17.1 2 or 4-FSK demodulator, filter and clock recovery circuit FUNCTION The aim of the demodulator and clock recovery circuitry is to take the signal from the receiver, to format it into symbols and to transfer it to the processor. The two blocks use the 76.8 kHz clock. The demodulator decodes the incoming signal and generates a sequence of NRZ data. This data is fed to the clock recovery block which regenerates the synchronization clock. This clock is used to sample and to shift the symbols into register DMD3. 6.17.1.1 Demodulator and filter +1600 −1600 −4800 The demodulator can operate both with 2-FSK and 4-FSK (selected by the LEV bit). For both types of input signals the so called demodulator, filter and direct modes are allowed. The operational mode is selected on the basis of the M bit and BF bit. In the demodulator mode (M = 0 and BF = X) the I and Q signals are decoded according to Table 36. Operating in this mode, an offset compensation can be performed and the calculated offset value is stored into register DMD1, in the field AVG. The offset value can be used by the processor to adjust the analog AFC output voltage. 1998 Oct 07 42 Philips Semiconductors Product specification Pager baseband controller Table 37 Offset coding (two’s compliment) OFFSET (Hz) −9450 −9300 ... −300 −150 0 150 300 ... 9300 9450 MAGNITUDE (AVG6 TO AVG0) 0111111 0111110 ... 0000010 0000001 0000000 1111111 1111110 ... 1000001 1000000 6.17.2 PCA5007 The recovered clock is used to sample and shift to left into an internal register one bit each symbol period in 2-FSK and two bits in 4-FSK. The symbol period is determined by bits BD2 to BD0. On the basis of BD bits the demodulator filter length is also set. In the clock recovery, a pulse (SYMCLK) is generated each N-bit, where ‘N’ is defined by means of bits B2 to B0. This pulse is used to update the DMD3 register. Moreover, it can be used as an interrupt to the processor through the IRQ1.3 (symbol interrupt). The interrupt informs the controller that ‘N’ bits are available in the DMD3 register. DEMODULATOR CONTROL REGISTER (DMD0) The demodulator control register DMD0 contains the control bits for enabling the demodulator function and setting its mode and data rate. 6.17.1.2 Clock recovery The clock recovery regenerates the synchronization clock using the edges of the incoming NRZ data. When the NRZ data have no edges for a long time, the synchronization is maintained by means of the correction information from the clock correction block. Table 38 Demodulator Control Register (DMD0, SFR address ECH) 7 ENB 6 M 5 − 4 RES 3 LEV 2 BD2 1 BD1 0 BD0 Table 39 Description of the DMD0 bits BIT DMD0.7 DMD0.6 DMD0.5 DMD0.4 DMD0.3 DMD0.2 DMD0.1 DMD0.0 SYMBOL ENB M − RES LEV BD2 BD1 BD0 enable demodulator function mode selection: logic 0 = I/Q from zero-IF receiver, logic 1 = NRZ data not used reserved for future implementation if set to logic 0 2-FSK demodulation, if set to logic 1 4-FSK demodulation baud rate setting; see Table 40 FUNCTION 1998 Oct 07 43 Philips Semiconductors Product specification Pager baseband controller Table 40 Baud rate for bits BD2, BD1 and BD0 BITS PCA5007 BAUD RATE BD2 0 0 0 0 1 1 1 1 6.17.3 BD1 0 0 1 1 0 0 1 1 BD0 0 1 0 1 0 1 0 1 1200 symbols/s 2400 symbols/s 1600 symbols/s 3200 symbols/s undefined undefined undefined undefined DEMODULATOR AVERAGING REGISTER (DMD1) The demodulator averaging register DMD1 contains the control bit for enabling the averaging function, used for the offset compensation during demodulation and the coded average (offset) value. Table 41 Demodulator Averaging Register (DMD1, SFR address EDH) 7 ENA 6 AVG6 5 AVG5 4 AVG4 3 AVG3 2 AVG2 1 AVG1 0 AVG0 Table 42 Description of the DMD1 bits BIT DMD1.7 DMD1.6 DMD1.5 DMD1.4 DMD1.3 DMD1.2 DMD1.1 DMD1.0 SYMBOL ENA AVG6 AVG5 AVG4 AVG3 AVG2 AVG1 AVG0 FUNCTION enable averaging function/offset calculation 7-bit value indicating the offset value of the demodulator. This is an indication of the LO offset frequency and will be used to determine the AFC output voltage. For coding see Table 37. 1998 Oct 07 44 Philips Semiconductors Product specification Pager baseband controller 6.17.4 CLOCK RECOVERY CONTROL REGISTER (DMD2) PCA5007 The clock recovery control register DMD2 contains the control bits for enabling the clock recovery function and setting its mode. Whenever the clock recovery function is enabled (DMD2.7 = 1) the positive edge of the synchronized SYMCLK signal will force a SymClk interrupt through the IRQ1.3 request flag after [B2, B1 and B0] received bits (see Section 6.19 Table 50). Table 43 Clock Recovery Control Register (DMD2, SFR address EEH) 7 ENC 6 − 5 BF 4 − 3 TEST 2 B2 1 B1 0 B0 Table 44 Description of the DMD2 bits BIT DMD2.7 DMD2.6 DMD2.5 DMD2.4 DMD2.3 DMD2.2 DMD2.1 DMD2.0 6.17.5 SYMBOL ENC − BF − TEST B2 B1 B0 enable clock recovery function not used bypass demodulator filter not used reserved, should always beat logic 0 Select number of bits per interrupt: If LEV = 0 then 000 = 1-bit, 001 = 2-bit to 111 = 8-bit If LEV = 1 then 00X = 2-bit, 01X = 4-bit, 10X = 6-bit and 11X = 8-bit. FUNCTION DEMODULATOR DATA REGISTER (DMD3) The demodulator data register DMD3 contains the (demodulated) recovered received symbols. Table 45 Demodulator Data Register (DMD3, SFR address EFH) 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 Table 46 Description of the DMD3 bits BIT DMD3.7 DMD3.6 DMD3.5 DMD3.4 DMD3.3 DMD3.2 DMD3.1 DMD3.0 SYMBOL D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION Recovered symbols. The number of relevant bits are set with DMD2[2 to 0]. 1998 Oct 07 45 Philips Semiconductors Product specification Pager baseband controller 6.18 6.18.1 AFC-DAC FUNCTION PCA5007 The AFC digital-to-analog converter provides an analog signal to the receiver to reduce its frequency offset. The analog signal is available at pin 18 (AFCOUT). For low noise sensitivity the DAC output is buffered and can drive a load impedance of 10 kΩ (max.). The output swing is from rail-to-rail VDD. When the enable signal ENB is at logic 1 a linear binary conversion is performed according to Table 47. Below 0.2 V the linearity at the output voltage is not ideal. When ENB is at logic 0 the AFCOUT pin is tied to VSS and all currents are switched off. Table 47 Coding of the AFC-DAC CODE 000000 000001 ... N ... 111111 6.18.2 AFC-DAC CONTROL/DATA REGISTER (AFCON) 63 × N× OUTPUT VOLTAGE 0 1 × 1⁄64VDD ... 1⁄ V 64 DD ... 1⁄ V 64 DD The AFC-DAC Control/Data register AFCON contains the control bit for enabling the AFC-DAC and the data bits for setting the output voltage. Table 48 AFC-DAC Control/Data Register (AFCON, SFR address 9EH) 7 ENB 6 − 5 AFC5 4 AFC4 3 AFC3 2 AFC2 1 AFC1 0 AFC0 Table 49 Description of the AFCON bits BIT AFCON.7 AFCON.6 AFCON.5 AFCON.4 AFCON.3 AFCON.2 AFCON.1 AFCON.0 SYMBOL ENB − AFC5 AFC4 AFC3 AFC2 AFC1 AFC0 enable DAC output not used. 6-bit value for DAC output according to Table 47 FUNCTION 1998 Oct 07 46 Philips Semiconductors Product specification Pager baseband controller 6.19 Interrupt system 6.19.1 OVERVIEW PCA5007 External events and the real-time-driven on-chip peripherals require service by the CPU asynchronously to the execution of any particular section of code. To tie the asynchronous activities of these functions to normal program execution a multiple-source, two-priority-level, nested interrupt system is provided. The interrupt system is shown in Fig.27. The PCA5007 acknowledges interrupt requests from fifteen sources as follows: • INT0 to INT4 and INT6 • Timer 0 and Timer 1 • Wake-up counter • I2C-bus serial I/O • UART transmitter and receiver • Demodulator • DC/DC converter • Watchdog timer • Real-time clock (MINUTE). Each interrupt vectors to a separate location in program memory for its service routine. Each source can be individually enabled or disabled by its corresponding bit in the Interrupt Enable Registers (IEN0 and IEN1). The priority level is selected via the Interrupt Priority Registers (IP0 and IP1). All enabled sources can be globally disabled or enabled. The interrupt controller implemented in the PCA5007 has 15 interrupt sources, of which some are level sensitive and some are edge sensitive. The interrupt controller samples all active sources during one instruction cycle; evaluation of the interrupts is then performed. A priority decoder decides which interrupt is serviced. Each interrupt has its own vector pointing to an 8 bytes long program segment. A low priority interrupt can be interrupted by a high priority interrupt, but not by another low priority interrupt i.e. only two interrupt levels are possible. Between the RETI instruction (Return from Interrupt) and the LCALL to a next interrupt, there is at least one instruction of the lower program level executed (see Fig.22). An interrupt is performed with a long subroutine call (LCALL) to vector address, which is determined by the respective interrupt. During LCALL the PC is pushed onto the stack. Returning from interrupt with RETI, the PC is popped from the stack. handbook, full pagewidth Level 21 RETI Level 20 RETI Interrupt level 2x RETI Interrupt level 1 IP = 1 IP = 0 IP = 1 Program level 0 one instruction MGR125 Fig.22 Interrupt hierarchy. 1998 Oct 07 47 Philips Semiconductors Product specification Pager baseband controller 6.19.2 INTERRUPT PROCESS PCA5007 Clearing the flags: During the forced LCALL the interrupt flag of the relevant interrupt is cleared by hardware, if applicable, otherwise by software. Emulation: During emulation the interrupts may be disabled. This is performed during break mode. With INTD asserted, all the interrupts are disabled. Idle or power-down: When Idle (PCON.0) or power-down (PCON.1) is set, the interrupt controller waits for the according WUI signal. Because the interrupt controller is waiting for WUI, all activity in the circuit will be stopped, thus no handshake can be completed. The WUI signal for Idle is the OR of all the interrupt request bits and the reset. For power-down the WUI signal is built only with the Port 1 interrupt request flags and the reset. 6.19.3 INTERRUPT CONTROLLER RELATED SFRS Sample the interrupt lines: The interrupt lines are latched at the beginning of each instruction cycle. Analyse the requests: The sampled interrupt lines will be analysed with respect to the relevant Interrupt Enable register (IEx) and Interrupt Priority register (IPx). The process will deliver the vector of the highest interrupt request and the priority information. Depending on the interrupt level and the priority of the interrupt in progress, an interrupt request to the core is performed. The vector address will be passed to the core process. Interrupt request to core: Level 0: The interrupt request to the core is performed, when at least one instruction is performed since the RETI from Level 1. Level 1: The interrupt request is performed, when at least one instruction is performed since the RETI from Level 21 and the request has high priority. Level 20: No request is performed. Level 21: No request is performed. Emulation: In break mode no interrupt request is performed. Update the interrupt level: Level 0: In the event of a high priority interrupt the new level will be Level 20. If it is a low priority interrupt, the new level will be Level 1. Level 1: In the event of a high priority interrupt, the new level will be Level 21. A low priority interrupt is not performed, the level is unchanged. On RETI the new level will be Level 0. Level 20: On RETI, the new level is Level 0. Level 21: On RETI, the new level is Level 1. Level 1: On RETI, the new level is Level 0. Level 0: The new level is Level 0. The implementation of the interrupt controller related SFRs for enabling and disabling interrupts is identical to a standard 80C51, but the interrupt sources have been changed according to Table 50. 1998 Oct 07 48 Philips Semiconductors Product specification Pager baseband controller PCA5007 Table 50 Interrupt controller related SFRs: IEN0 (A8H), IEN1 (E8H), IP0 (B8H), IP1 (F8H), IRQ1 (C0H), TCON (88H), WUCON (94H) and RTCON (CDH) BITS CONV. NAME SOURCE NOTES IEN0 address A8H: interrupt enable for X0, X1, T0, T1, T2, S0, S1 and global interrupt enable (note 1) 0 1 2 3 4 5 6 7 EX0 ET0 EX1 ET1 ES0 ES1 ET2 EA P3.2 TIMER 0 P3.3 TIMER 1 UART I2C Enables or disables EXTERNAL0 interrupt. If EX0 = 0, the external interrupt 0 is disabled. Enables or disables the TIMER 0 overflow interrupt. If ET0 = 0, the Timer 0 interrupt is disabled. Enables or disables the EXTERNAL1 interrupt. If EX1 = 0, external interrupt 1 is disabled. Enables or disables TIMER 1 overflow interrupt. If ET1 = 0, the Timer 1 interrupt is disabled. Enables or disables the UART interrupt. If ES0 = 0, the UART interrupt is disabled. Enables or disables the I2C-bus interrupt. If ES1 = 0, the I2C-bus interrupt is disabled. WAKE-UP Enables or disables the WAKE-UP interrupt. If ET2 = 0, the wake-up interrupt is disabled. / Disables all interrupts. If EA = 0, no interrupt will be acknowledged. If EA = 1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit. IEN1 address E8H: interrupt enable for X2 to X9 (note 1) 0 1 2 3 4 5 6 7 EX2 EX3 EX4 EX5 EX6 EX7 EX8 EX9 P1.0 P1.1 P1.2 SYMBOL P1.4 DC/DC WDI MIN Enables or disables interrupts on P1.0. If EX2 = 0, the corresponding interrupt is disabled. Enables or disables interrupts on P1.1. If EX3 = 0, the corresponding interrupt is disabled. Enables or disables interrupts on P1.2. If EX4 = 0, the corresponding interrupt is disabled. Enables or disables the SYMBOL interrupt. If EX5 = 0, the SYMBOL interrupt is disabled. Enables or disables interrupts on P1.4. If EX6 = 0, the corresponding interrupt is disabled. Enables or disables the DC/DC CONVERTER interrupt. If EX7 = 0, the DC/DC converter interrupt is disabled. Enables or disables interrupts on the WATCHDOG. If EX8 = 0, the WDINT interrupt is disabled. Enables or disables REAL-TIME CLOCK interrupt. If EX9 = 0, the MINUTE interrupt is disabled. IP0 address B8H: interrupt priority for X0, X1, T0, T1, T2, S0 and S1 (note 2) 0 1 2 3 PX0 PT0 PX1 PT1 P3.2 TIMER 0 P3.3 TIMER 1 Defines the EXTERNAL0 interrupt 0 priority level. PX0 = 1 programs it to the higher priority level. Enables or disables the TIMER 0 interrupt priority level. PT0 = 1 programs it to the higher priority level. Defines the EXTERNAL1 interrupt priority level. PX1 = 1 programs it to the higher priority level. Defines the TIMER 1 interrupt priority level. PT1 = 1 programs it to the higher priority level. 49 1998 Oct 07 Philips Semiconductors Product specification Pager baseband controller PCA5007 BITS 4 5 6 7 CONV. NAME PS0 PS1 PT2 − SOURCE UART I2C NOTES Defines the UART interrupt priority level. PS0 = 1 programs it to the higher priority level. Defines the I2C-bus interrupt priority level. PS1 = 1 programs it to the higher priority level. WAKE-UP Defines the WAKE-UP interrupt priority level. PT2 = 1 programs it to the higher priority level. / unused IP1 address F8H: interrupt priority for X2 to X9 (note 2) 0 1 2 3 4 5 6 7 PX2 PX3 PX4 PX5 PX6 PX7 PX8 PX9 P1.0 P1.1 P1.2 SYMBOL P1.4 DC/DC WDI MIN Defines the EXTERNAL2 interrupt priority level 1. PX2 = 1 programs it to the higher priority level. Defines the EXTERNAL3 interrupt priority level 1. PX3 = 1 programs it to the higher priority level. Defines the EXTERNAL4 interrupt priority level 1. PX4 = 1 programs it to the higher priority level. Defines the SYMBOL interrupt priority level 1. PX5 = 1 programs it to the higher priority level. Defines the EXTERNAL6 interrupt priority level 1. PX6 = 1 programs it to the higher priority level. Defines the DC/DC CONVERTER interrupt priority level 1. PX7 = 1 programs it to the higher priority level. Defines the WATCHDOG interrupt priority level 1. PX8 = 1 programs it to the higher priority level. Defines the REAL-TIME CLOCK interrupt priority level 1. PX9 = 1 programs it to the higher priority level. TCON address 88H: timer/counter mode control register 0 1 2 3 4 5 6 7 IT0 IE0 IT1 IE1 TR0 TF0 TR1 TF1 P3.2 P3.2 P3.3 P3.3 TIMER 0 TIMER 0 TIMER 1 TIMER 1 EXTERNAL0 interrupt type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupt. EXTERNAL0 interrupt flag. Set by hardware when external Interrupt detected. Cleared by hardware. EXTERNAL1 interrupt type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupt. EXTERNAL1 interrupt flag. Set by hardware when external Interrupt detected. Cleared by hardware. Timer 0 run control bit. Set/cleared by software to turn timer on/off. Timer 0 overflow flag. Set by hardware on timer/counter overflow. Cleared by hardware or software. Timer 1 run control bit. Set/cleared by software to turn timer on/off. Timer 1 overflow flag. Set by hardware on timer/counter overflow. Cleared by hardware or software. IRQ1 address C0H: interrupt request register for X2 to X9 0 1 IQ2 IQ3 P1.0 P1.1 Interrupt request flag from P1.0. Interrupt request flag from P1.1. 1998 Oct 07 50 Philips Semiconductors Product specification Pager baseband controller PCA5007 BITS 2 3 4 5 6 7 CONV. NAME IQ4 IQ5 IQ6 IQ7 IQ8 IQ9 SOURCE P1.2 SYMBOL P1.4 DC/DC WDI MIN Interrupt request flag from P1.2. NOTES Interrupt request flag from clock recovery circuit. Set by hardware or software. Cleared by software. Interrupt request flag from P1.4. Interrupt request flag from DC/DC CONVERTER. Set by hardware or software. Cleared by software. Interrupt request flag from watchdog timer. Set by hardware or software. Cleared by software. Interrupt request flag from real-time clock interrupt. Set by hardware or software. Cleared by software. WUCON address 94H: wake-up counter control register 0 1 2 3 4 5 6 7 SET LOAD Z0 Z1 CPL unused WUP RUN − − − − − − − − − − − − − Interrupt request flag from RTC. Set by hardware or software. Cleared by software. WUP interrupt flag from wake-up counter timer. Set by hardware or software. Cleared by software. RUN bit for wake-up counter. Complete interrupt flag from wake-up counter timer. Set by hardware or software. Cleared by software. Latch signal to copy content of WUC to peripheral register. Parallel load signal for wake-up counter. RTCON address CDH: real-time clock control register 0 1 2 3 to 6 7 Notes 1. IEN0 and IEN1: These are two 8-bit registers that control the enabling of the 15 interrupt sources individually as well as a global enable/disable for all of the sources. 2. IP0 and IP1: These are two 8-bit registers that set priority for each interrupt source. IP0 actually contains only 7 bits as IP.7 is not implemented. This bit will always read as logic 0. SET LOAD W/R unused MIN Latch signal to copy content of WUC to peripheral register. Load RTC0 value from SFR to RTC. Disable write back to SFR. 1998 Oct 07 51 Philips Semiconductors Product specification Pager baseband controller 6.19.4 PORT 3 INTERRUPTS: P3.2 AND P3.3 6.19.5 WAKE-UP INTERRUPT PCA5007 INT0 and INT1 are level or edge sensitive. The programming is performed with TCON. Since P3.2 and P3.3 are configured as push-pull outputs, these interrupts can only be triggered by output commands to these ports and not by external events. TCON.0 (IT0): Interrupt 0 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupt (see Fig.23). TCON.1 (IE0): Interrupt 0 flag. Set by hardware when an external interrupt is detected. Cleared by hardware when the service routine is called. TCON.2 (IT1): Interrupt 1 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupt. TCON.3 (IE1): Interrupt 0 flag. Set by hardware when an external interrupt is detected. Cleared by hardware when the service routine is called. The wake-up interrupt (T2) is the level sensitive OR function of the WUP bit or CPL bit in the WUCON SFR. The wake-up interrupt is mapped to the T2 vector (see Fig.24). These flags are set by hardware and need to be cleared by software. For more information see Section 6.14. WUCON.6 (WUP): WUP interrupt flag. Attention: writing and reading this SFR bit does not access the same flag. The flag is set by hardware and needs to be cleared by software. WUCON.4 (CPL): Complete flag. The previous set instruction is completed. The settings of the SFR have been copied to the peripheral block. The flag is set by hardware and needs to be cleared by software. handbook, full pagewidth Pad Port 3.2 INT0 0 IE0 1 IT0 (interrupt edge flag) MGR126 X0 Fig.23 External interrupt Port 3.2 and Port 3.3 (INT0 and INT1). handbook, full pagewidth WUP WAKE-UP COUNTER CPL MGR1127 ≥1 T2 Fig.24 Wake-up interrupt. 1998 Oct 07 52 Philips Semiconductors Product specification Pager baseband controller 6.19.6 PORT 1 INTERRUPTS: PORT 1.0 TO PORT 1.4 (INT2 TO INT6) PCA5007 The IRQ bits are not set if the corresponding enable is not set. IRQ1.3: (symbol interrupt); this interrupt request flag, if enabled, is set if the demodulator (clock recovery) has data ready, that should be read by the microcontroller. The event is called symbol clock or SymClk, because in one mode of operation one symbol is delivered per interrupt. The flag is set by hardware and needs to be cleared by software. IRQ1.5: (DC/DC converter interrupt); this interrupt request flag, if enabled, is set if the DC/DC converter is not able to deliver the required current (STB flag cleared). The flag is set by hardware and needs to be cleared by software. IRQ1.6: (watchdog interrupt); this interrupt request flag, if enabled, is set if the watchdog timer will expire within 1⁄ s. The flag is set by hardware and needs to be 16 cleared by software. IRQ1.7: (minute interrupt); this interrupt request flag, if enabled, is set once each minute by the real-time clock. The flag is set by hardware and needs to be cleared by software. Four Port 1 lines can be used as external interrupt inputs (see Fig.25). When enabled (IEN1 SFR), each of these lines can wake-up the device from power-down. Using the IX1 register, each of these port lines may be set active to either HIGH or LOW. IRQ1 is the interrupt request flag register. Each flag, if the interrupt is enabled, will send an interrupt request, but must be cleared by software, i.e. via the interrupt software. The Port 1 interrupt request flags can only be set if the corresponding interrupt enable bit is set. 6.19.7 MORE INTERRUPTS: SYMCLK, DC/DC CONVERTER, WATCHDOG AND MINUTE The decoder blocks generate events that can force an interrupt when enabled (IEN0 and IEN1 SFR). These interrupts are mapped to the corresponding P1 interrupt request flag register bits (see Fig.26). Each flag, if the interrupt is enabled, will send an interrupt request and must be cleared by software, i.e. via the interrupt service routine. handbook, full pagewidth Pad Port 1.0 INT2 0 IRQ1.0 1 IX1.0 IEN1.0 wake-up.0 MGR128 X2 Fig.25 Interrupt Port 1.0. handbook, full pagewidth CLOCK RECOVERY BLOCK SymClk IEN1.3 IRQ1.3 X5 MGR129 Fig.26 SymClk (as an example for any of the 4 mentioned interrupts). 1998 Oct 07 53 Philips Semiconductors Product specification Pager baseband controller 6.19.8 INTERRUPT HANDLING PCA5007 Figure 27 shows the conventions for interrupt assignments and priorities. Arbitration of several simultaneous interrupts can be seen from Fig.27. The sampled interrupt with the highest priority will be handled first (assuming that the interrupt priority is default). Setting of interrupt request flags for X2 to X9 is masked by the corresponding interrupt enable bit (IEN1). cleared handbook, vector full pagewidth by 03 2B 53 0B 33 5B 13 3B 63 1B 43 6B 23 4B 73 HW SW SW HW SW SW HW SW SW HW SW SW SW SW SW function Port Name Flag IEN0/1 IP0/1 0.0 0.5 1.3 0.1 0.6 1.4 0.2 1.0 1.5 0.3 1.1 1.6 0.4 1.2 1.7 0.7 global enable PRIORITY high low INT0 I2C-bus SymClk Timer 0 Wake-up INT6 INT1 INT2 DC/DC Timer 1 INT3 WDINT UART INT4 MINUTE P3.2 X0 S1 X5 T0 T2 IE0 SI SYM TF0 WUP IQ6 IE1 IQ2 DC TF1 IQ3 WDI TI/RI IQ4 MIN TCON.1 S1CON.3 IRQ1.3 TCON.5 WUCON.6 IRQ1.4 TCON.3 IRQ.0 IRQ1.5 TCON.7 IRQ1.1 IRQ1.6 S0CON.0/1 IRQ1.2 RTCON.7 0.0 0.5 1.3 0.1 0.6 1.4 0.2 1.0 1.5 0.3 1.1 1.6 0.4 1.2 1.7 P1.4 P3.3 P1.0 X6 X1 X2 X7 T1 decreasing priority within same level P1.1 X3 X8 S0 P1.2 X4 X9 MGR130 The signal level applied to the EAN pin defines whether the interrupt vector code is fetched from external or internal ROM. Fig.27 Interrupt assignment and priorities. 1998 Oct 07 54 Philips Semiconductors Product specification Pager baseband controller 6.20 Idle and power-down operation 6.20.2 POWER-DOWN MODE PCA5007 Idle and power-down are power saving modes of the microcontroller that can be activated when no CPU activity is required. Both modes do not stop the 76.8 kHz oscillator nor disable any peripheral function. The following functions remain active during the Idle mode. • Timer 0 and Timer 1 • Wake-up counter • Watchdog counter • Real-time clock • Demodulator and clock recovery • UART • I2C-bus • External interrupt. 6.20.1 IDLE MODE The instruction that sets PCON.1 is the last instruction executed in the normal operating mode before the power-down mode is activated. Once in the power-down mode, the CPU status is preserved together with the stack pointer, program counter, program status word and accumulator. The RAM and all other registers maintain their data during power-down mode. The status of the external pins during power-down mode is shown in Table 51. There are two ways to terminate the power-down mode: 1. Activation of an enabled external interrupt (INT2 to INT9) will cause PCON.1 to be cleared by hardware thus terminating the power-down mode. The interrupt is serviced, and following the RETI instruction, the next instruction to be executed will be the one following the instruction that put the device in the power-down mode. 2. The second way of terminating the power-down mode is with an internal or external hardware reset. Reset redefines all SFRs but does not affect the on-chip RAM. Possible sources of an internal reset are a) Watchdog reset if the watchdog had expired b) OFF-ON reset if the DC/DC converter is restarted from the off mode (wake-up counter or P1 pins). The power-down mode is not especially useful. It has been implemented for compatibility only. The Idle mode has the same power saving capability and allows much more flexible wake-up. 6.20.3 OFF MODE The instruction that sets PCON.0 is the last instruction executed in the normal operating mode before the Idle mode is activated. Once in the Idle mode, the CPU status is preserved together with the stack pointer, program counter, program status word and accumulator. The RAM and all other registers maintain their data during Idle mode. The status of the external pins during Idle mode is shown in Table 51. There are two ways to terminate the Idle mode: 1. Activation of any enabled interrupt will cause PCON.0 to be cleared by hardware thus terminating the Idle mode. The interrupt is serviced, and following the RETI instruction, the next instruction to be executed will be the one following the instruction that put the device into the Idle mode. The flag bits GF0 and GF1 may be used to determine whether the interrupt was received during normal execution or during the Idle mode. For example, the instruction that writes to PCON.0 can also set or clear one or both flag bits. When the Idle mode is terminated by an interrupt, the service routine can examine the status of the flag bits. 2. The second way of terminating the Idle mode is with an internal or external hardware reset. Reset redefines all SFRs but does not affect the on-chip RAM. Possible sources of an internal reset are: a) Watchdog reset if the watchdog had expired b) Off/on reset if the DC/DC converter is restarted from the off mode (wake-up counter, RTC or P1 pins). The off mode has been designed as the power saving mode of the PCA5007. Shortly after entering this mode the DC/DC converter is switched off and VDD is reduced to VBAT. Directly after activating the off mode, the CPU must be set in Idle mode. The off mode is entered by: 1. ORL DCCON0, #80H 2. ORL PCON, #01H. The off mode can be exited by one of the following events: • RTC minute event • Wake-up counter event • Event on any P1 pin • RESETIN active HIGH. 1998 Oct 07 55 Philips Semiconductors Product specification Pager baseband controller Each of these events first starts the DC/DC converter to ramp up VDD to 2.2 V. After an initial reset, generated by the DC/DC converter when VDD is again at normal level, all 2 V blocks will restart their operation. The first instruction will be fetched from address 0. The edge sensitive interrupts (minute and wake-up) from the internal sources will have been lost during restart and must be polled from their SFRs. Events from P1 pins can be served after enabling the interrupts, since they are level sensitive. Table 51 Status of external pins during normal, Idle and power-down modes MODE Normal Idle Power-down MEMORY internal internal external internal external 6.20.5 ALE 0 1 1 0 0 PSEN 1 1 1 0 0 PORT 0 port data port data pull-up HIGH pull-up HIGH pull-up HIGH PORT 1 port data port data port data port data port data PORT 2 port data port data address port data address 6.20.4 STATUS OF EXTERNAL PINS PCA5007 The status of the external pins during Idle and power-down mode is shown in Table 51. PORT 3 port data port data port data port data port data POWER CONTROL REGISTER (PCON) The reduced power modes are activated by software using this special function register. PCON is not bit addressable. Table 52 Power Control Register (PCON and SFR address 87H) 7 SMOD 6 XRE 5 ENIS 4 − 3 GF1 2 GF0 1 PD 0 IDL Table 53 Power Control Register (PCON, SFR address 87H) BIT PCON.7 PCON.6 SYMBOL SMOD XRE FUNCTION Control bit to double data rate of UART, when set to logic 1. If set to logic 1 enables external XRAM from address 0 on, if set to logic 0 the first 768 XRAM bytes are in internal XRAM, the higher addresses come from external XRAM; see note 2. Enable ISYNC. If bit is set, ISYNC can be monitored at pin EA in internal access mode. The binary value of ISYNC changes each time a new instruction is fetched from memory. This bit must not be set to logic 1 by user program! reserved General purpose flag bit. General purpose flag bit. Power-down bit. Setting this bit activates the power-down mode; see note 1. Idle mode bit. Setting this bit activates the Idle mode; see note 1. PCON.5 ENIS PCON.4 PCON.3 PCON.2 PCON.1 PCON.0 Notes − GF1 GF0 PD IDL 1. If logic 1s are written to PD and IDL at the same time, PD takes precedence. The reset value of PCON is (00000000). 2. This device does not support external XRAM access. Therefore the XRE bit is meaningless and should never be written to logic 1. 1998 Oct 07 56 Philips Semiconductors Product specification Pager baseband controller 6.21 Reset 6.21.2 PCA5007 EXTERNAL POWER-ON RESET USING THE RESETIN PIN To initialize the PCA5007 a reset is performed by using either of the 2 following methods: • Applying an external reset signal to the RESETIN pin • Via the on-chip watchdog timer. The reset state of the output pins is given in separate tables (Tables 2 to 6). The reset state of the SFRs is given in a separate overview (see Table 1). While a reset is applied to the device the output RESOUT is driven LOW. The internal RAM is not affected by reset. When VDD is turned on, the RAM contents are indeterminate. 6.21.1 EXTERNAL RESET USING THE RESETIN PIN An automatic reset can be obtained by connecting the RESETIN pin to VBAT via a capacitor and to VSS via a resistor. At power-on, the voltage on the RESETIN pin is equal to VBAT and decreases from VBAT as the capacitor charges through the resistor to VSS. VRESETIN must remain higher than the threshold of the Schmitt trigger for a duration of tRESETIN (see Chapter “AC characteristics”). The reset configuration is shown in Fig.28. 6.21.3 INTERNAL RESET The watchdog which is available in the PCA5007 (see Section 6.16) will force a reset if it is enabled and expires. A reset is also forced, when the DC/DC converter restarts operation from the off mode (see Section 6.22.3). All resets to the microcontroller can be observed as negative pulses at the output RESOUT. The external reset input for the PCA5007 is the RESETIN pin. A Schmitt trigger is used at the input for noise rejection. Immediately after pin RESETIN goes HIGH, an internal reset is executed. As a consequence the SFRs and port pins adopt their reset state, ALE and PSEN are held HIGH. As long as the RESETIN pin stays HIGH, the reset state is maintained. When RESETIN goes LOW, the device start-up sequence is executed (see Section 6.22). handbook, full pagewidth PCA5007 VBAT 10 µF RESETIN RESOUT RESET AND POWER CONTROLLER VBAT 10 kΩ watchdog restart DC/DC converter VSS internal reset for microcontroller MGR131 Fig.28 Application diagram for external power-on reset configuration. 1998 Oct 07 57 Philips Semiconductors Product specification Pager baseband controller 6.22 6.22.1 DC/DC converter FUNCTION PCA5007 For a certain current load (IL) the controller settles to a stable voltage VDD (IL) between 2.15 to 2.25 V. Increasing the load decreases VDD (IL) by a small amount. When VDD (IL) drops below 2.15 V the DC/DC converter calculates a new set of coefficients and VDD (IL) settles again between 2.15 and 2.25 V (see Fig.38). The DC/DC converter converts the voltage from a single primary cell (0.9 to 1.6 V) to a nominal 2.2 V supply voltage for on-chip and off-chip use. For EMC reasons a special technique is used to minimize coil current ripples under all load conditions. The voltage generated by the DC/DC converter is available at pin VDD(DC). The supply for all functions of the chip is taken from the VDD and VDDA pins. The user has to connect VDD(DC) to the other VDD pins. The supply used for the reference and comparators is taken from VDDA. A typical circuit configuration is shown in Fig.29. handbook, full pagewidth L VBAT 0.9 to 1.6 V 470 µH Ci 4.7 µF VBAT VIND D1 VDD(DC) VDD Co 4.7 µF VDD VDDA PCA5007 BLI 2.25 V C1 RESETIN DIGITAL CONTROL 2.15 V 6 MHz BAND GAP R1 MICROCONTROLLER VSS, VSSA MGR132 Fig.29 Typical operating circuit. 1998 Oct 07 58 Philips Semiconductors Product specification Pager baseband controller 6.22.2 TYPICAL OPERATING CHARACTERISTICS PCA5007 The efficiency is determined by the series resistance RS and the current consumption of the converter itself. RS is the sum of the battery resistance RBAT, the DC resistance SRL of the coil, the on resistance of the MOSFET RDS,on and the ESR of the output capacitor Co. Figure 32a shows the efficiency when using a 470 µH coil with a SRL of 5 Ω and a load capacitor of 4.7 µF with an ESR of 0.5 Ω. In Fig.32b the efficiency for the same configuration is shown but with a SRL of only 0.1 Ω. To increase efficiency for extremely low output currents, the converter should be set into standby mode (see Fig.33). The maximum power delivered by the DC/DC converter is given by equation (1). ( V Bat ) P o(max) ≤ ------------------4 × Rs 2 (1) Rs is the total series resistance which is the sum of RBAT + Rind + Rsw + ESR(Co). In Figs 30 and 31 the maximum available output current (IL) is shown as a function of VBAT and Rs. handbook, full pagewidth 8 Rs (Ω) 7 30 15 MGR345 20 6 35 25 40 5 30 35 4 25 40 45 20 50 30 35 55 60 3 40 45 50 70 55 60 75 65 70 75 80 90 100 2 0.8 1 1.2 1.4 VBAT (V) 1.6 VDD = 2.2 V; RS = RBAT + Rind + Rsw Fig.30 Maximum available output current (mA) in normal mode. 1998 Oct 07 59 Philips Semiconductors Product specification Pager baseband controller PCA5007 handbook, full pagewidth 8 Rs (Ω) 25 5 MGR346 7 1 30 7.5 12.5 35 3.5 10 6 2 15 30 40 20 25 5 1 35 45 5 12.5 7.5 4 2 15 40 50 3.5 10 20 30 55 35 50 45 60 3 65 70 80 2 0.8 VDD = 2.2 V; Rs = RBAT + Rind + Rsw 1 1.2 1.4 VBAT (V) 1.6 Fig.31 Maximum available output current (mA) in standby mode. MGR134 handbook, halfpage 100 η handbook, halfpage 100 MGR135 η (%) 80 (1) (%) 80 (3) (2) (1) (2) (3) 60 60 40 40 20 20 0 0 4 8 12 16 IL (mA) 20 0 0 4 8 12 16 IL (mA) 20 a. Rs = 6 Ω. (1) VBAT = 1.5 V. (2) VBAT = 1.2 V. (3) VBAT = 0.9 V. b. Rs = 1 Ω. Fig.32 Efficiency in normal mode as a function of load current. 1998 Oct 07 60 Philips Semiconductors Product specification Pager baseband controller PCA5007 MGR136 handbook, halfpage 100 η (%) 80 (3) (2) (1) 60 40 20 0 0 1 2 3 IL (mA) 4 (1) VBAT = 1.5 V. (2) VBAT = 1.2 V. (3) VBAT = 0.9 V. Fig.33 Efficiency in standby mode as a function of load current. 6.22.3 START-UP DESCRIPTION 6.22.3.1 Start-up from reset An external RC network together with an on-chip Schmitt trigger is used to generate a reset pulse after the insertion of a new battery (see Section 6.21). A reset pulse at the RESETIN pin resets the SFRs and the internal registers of the DC/DC converter to the factory programmed values and the start-up sequence shown in Fig.34 is started. The reset pulse must be essentially longer then the rise time of VBAT. The start-up sequence is divided into several steps: 1. Start-up 76.8 kHz crystal oscillator (256 clocks). 2. Boost up of VDD to approximately 1.7 V using the 76.8 kHz clock. During this phase, the p-channel MOSFET is switched off and the charge is transferred via the external Schottky diode. 1 3. Start of the 6 MHz clock  2 × ----------------------  ;  76.8 kHz  (see Section 6.12). 4. Boost up VDD to 2.2 V using the internal 6 MHz clock and the p-channel MOSFET. As soon as VDD ≥ 2.15 V, the stable flag is set to indicate that the system is powered-up successfully and the microcontroller starts operating. The DC/DC converter now stays in the normal mode of the normal operating mode. If a reset pulse is generated during normal operation, the DC/DC converter immediately resets the whole system and enters the start-up sequence. 6.22.3.2 Start-up from off mode Start-up from off mode behaves exactly as start-up from external reset (see Fig.34) except that: • The internal registers of the DC/DC converter are not reset; however the DC/DC converter SFRs are reset. off mode is exited when one of the following events occur: • Key pressed • Minute interrupt • Wake-up interrupt. 1998 Oct 07 61 Philips Semiconductors Product specification Pager baseband controller PCA5007 handbook, full pagewidth DC/DC converter microcontroller RESETIN reset internal register VDD OK = 0 STABLE = 0 Delay = 256T start DC/DC using 76.8 kHz clock Wait until VDD > 1.7 V (up to some ms) RESTART = INIT Z_R active RESOUT active VDD OK = 1 Delay = 2T DC/DC uses 6 MHz Wait until VDD > 2.2 V (