PCA9530

INTEGRATED CIRCUITS PCA9530 2-bit I2C LED dimmer Preliminary data 2002 Dec 12 Philips Semiconductors Philips Semiconductors Preliminary data 2-bit I2C LED dimmer PCA9530 the duty cycle to vary the amount of time the LED is on and thus the average current through the LED. The initial setup sequence programs the two blink rates/duty cycles for each individual PWM. From then on, only one command from the bus master is required to turn individual LEDs ON, OFF, BLINK RATE 1 or BLINK RATE 2. Based on the programmed frequency and duty cycle, BLINK RATE 1 and BLINK RATE 2 will cause the LEDs to appear at a different brightness or blink at periods up to 1.6 second. The open drain outputs directly drive the LEDs with maximum output sink current of 25 mA per bit and 50 mA per package. To blink LEDs at periods greater than 1.6 second the bus master (MCU, MPU, DSP, chipset, etc.) must send repeated commands to turn the LED on and off as is currently done when using normal I/O Expanders like the Philips PCF8574 or PCA9554. Any bits not used for controlling the LEDs can be used for General Purpose Parallel Input/Output (GPIO) expansion which provides a simple solution when additional I/O is needed for ACPI power switches, sensors, pushbuttons, alarm monitoring, fans, etc. The active low hardware reset pin (RESET) and Power On Reset (POR) initialize the registers to their default state causing the bits to be set high (LED off). One hardware address pin on the PCA9530 allows two devices to operate on the same bus. FEATURES • 2 LED drivers (on, off, flashing at a programmable rate) • 2 selectable, fully programmable blink rates (frequency and duty • 256 brightness steps • Input/output not used as LED drivers can be used as regular • Internal oscillator requires no external components • I2C interface logic compatible with SMBus • Internal power-on reset • Noise filter on SCL/SDA inputs • Active low reset input • 2 open drain outputs directly drive LEDs to 25 mA • Edge rate control on outputs • No glitch on power-up • Supports hot insertion • Low stand-by current • Operating power supply voltage range of 2.3 V to 5.5 V • 0 to 400 kHz clock frequency • ESD protection exceeds 2000 V HBM per JESD22-A114, • Latch-up testing is done to JESDEC Standard JESD78 which • Package offer: SO8, TSSOP8, VSSOP8 DESCRIPTION The PCA9530 is a 2-bit I@C and SMBus I/O expander optimized for dimming LEDs in 256 discrete steps for Red/Green/Blue (RGB) color mixing and back light applications. The PCA9530 contains an internal oscillator with two user programmable blink rates and duty cycles coupled to the output PWM. The LED brightness is controlled by setting the blink rate high enough (> 100 Hz) that the blinking can not be seen and then using exceeds 100 mA 150 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101 GPIOs cycle) between 0.625 and 160 Hz (1.6 seconds and 6.25 milliseconds) A0 1 LED0 LED1 VSS 2 3 4 8 7 6 5 VDD SDA SCL RESET SW00926 Figure 1. Pin configuration PIN DESCRIPTION PIN NUMBER 1 2 3 4 5 6 7 8 SYMBOL A0 LED0 LED1 VSS RESET SCL SDA VDD FUNCTION Address input 0 LED driver 0 LED driver 1 Supply ground Active low reset input Serial clock line Serial data line Supply voltage ORDERING INFORMATION PACKAGES 8-Pin Plastic SO 8-Pin Plastic TSSOP TEMPERATURE RANGE -40 to +85 °C -40 to +85 °C ORDER CODE PCA9530D PCA9530DP TOPSIDE MARK PCA9530 9530 DRAWING NUMBER SOT96-1 SOT505-1 Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging. I2C is a trademark of Philips Semiconductors Corporation. 2002 Dec 12 2 Philips Semiconductors Preliminary data 2-bit I2C LED dimmer PCA9530 BLOCK DIAGRAM A0 PCA9530 INPUT REGISTER SCL INPUT FILTERS SDA I2C-BUS CONTROL LED SELECT (LSx) REGISTER 0 1 LEDx VDD RESET POWER-ON RESET PRESCALER 0 REGISTER OSCILLATOR PRESCALER 1 REGISTER PWM0 REGISTER PWM1 REGISTER BLINK0 BLINK1 VSS NOTE: ONLY ONE I/O SHOWN FOR CLARITY SW02042 Figure 2. Block diagram 2002 Dec 12 3 Philips Semiconductors Preliminary data 2-bit I2C LED dimmer PCA9530 DEVICE ADDRESSING Following a START condition the bus master must output the address of the slave it is accessing. The address of the PCA9530 is shown in Figure 3. To conserve power, no internal pullup resistor is incorporated on the hardware selectable address pin and it must be pulled HIGH or LOW. SLAVE ADDRESS Unused bits must be programmed with zeroes. INPUT — INPUT REGISTER bit Default 7 0 6 0 5 0 4 0 3 0 2 0 1 X 0 X The INPUT register reflects the state of the device pins. Writes to this register will be acknowledged but will have no effect. PSC0 — FREQUENCY PRESCALER 0 bit default 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 1 1 0 0 0 0 A0 R/W FIXED HARDWARE SELECTABLE SW00928 PSC0 is used to program the period of the PWM output. (PSC0 ) 1) 152 PWM0 — PWM REGISTER 0 The period of BLINK0 + bit default 7 1 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Figure 3. Slave address The last bit of the address byte defines the operation to be performed. When set to logic 1 a read is selected while a logic 0 selects a write operation. CONTROL REGISTER Following the successful acknowledgement of the slave address, the bus master will send a byte to the PCA9530 which will be stored in the Control Register. 0 0 0 AI 0 B2 B1 B0 The PWM0 register determines the duty cycle of BLINK0. The outputs are LOW (LED on) when the count is less than the value in PWM0 and HIGH (LED off) when it is greater. If PWM0 is programmed with 00h, then the PWM0 output is always HIGH (LED off) . The duty cycle of BLINK0 is: PWM0 256 PSC1 — FREQUENCY PRESCALER 1 bit 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 default REGISTER ADDRESS RESET STATE: 00h AUTO-INCREMENT FLAG SW01034 PSC1 is used to program the period of PWM output. (PSC1 ) 1) 152 PWM1 — PWM REGISTER 1 The period of BLINK1 + Figure 4. Control register CONTROL REGISTER DEFINITION B2 0 0 0 0 1 1 B1 0 0 1 1 0 0 B0 0 1 0 1 0 1 REGISTER NAME INPUT PSC0 PWM0 PSC1 PWM1 LS0 TYPE READ READ/ WRITE READ/ WRITE READ/ WRITE READ/ WRITE READ/ WRITE REGISTER FUNCTION INPUT REGISTER FREQUENCY PRESCALER 0 PWM REGISTER 0 FREQUENCY PRESCALER 1 PWM REGISTER 1 bit default 7 1 6 0 5 0 4 0 3 0 2 0 1 0 0 0 The PWM1 register determines the duty cycle of BLINK1. The outputs are LOW (LED on) when the count is less than the value in PWM1 and HIGH (LED off) when it is greater. If PWM1 is programmed with 00h, then the PWM1 output is always HIGH (LED off). The duty cycle of BLINK1 is: PWM1 256 LS0 — LED SELECTOR LED 1 bit 7 1 6 1 5 1 4 1 3 0 2 0 default LED 0 1 0 0 0 LED SELECTOR REGISTER DESCRIPTION The lowest 3 bits are used as a pointer to determine which register will be accessed. If the auto-increment flag is set, the three low order bits of the Control Register are automatically incremented after a read or write. This allows the user to program the registers sequentially. The contents of these bits will rollover to ‘000’ after the last register is accessed. When auto-increment flag is set (AI = 1) and a read sequence is initiated, the sequence must start by reading a register different from the input register (B2 B1 B0 0 0 0 0). Only the 3 least significant bits are affected by the AI flag. The LSx LED select registers determine the source of the LED data. 00 = Output is set low Hi-Z (LED off - default) 01 = Output is set low (LED on) 10 = Output blinks at PWM0 rate 11 = Output blinks at PWM1 rate 2002 Dec 12 4 Philips Semiconductors Preliminary data 2-bit I2C LED dimmer PCA9530 POWER-ON RESET When power is applied to VDD, an internal Power On Reset holds the PCA9530 in a reset state until VDD has reached VPOR. At this point, the reset condition is released and the PCA9530 registers are initialized to their default states, all the outputs in the off state. SDA EXTERNAL RESET A reset can be accomplished by holding the RESET pin low for a minimum of tW. The PCA9530 registers and I2C state machine will be held in their default state until the RESET input is once again high. This input requires a pull-up resistor to VDD. SCL data line stable; data valid change of data allowed SW00363 Figure 5. Bit transfer Start and stop conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P) (see Figure 6). CHARACTERISTICS OF THE I2C-BUS The is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. I2C-bus System configuration A device generating a message is a transmitter: a device receiving is the receiver. The device that controls the message is the master and the devices which are controlled by the master are the slaves (see Figure 7). Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 5). SDA SDA SCL S START condition P STOP condition SCL SW00365 Figure 6. Definition of start and stop conditions SDA SCL MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER I2C MULTIPLEXER SLAVE SW00366 Figure 7. System configuration 2002 Dec 12 5 Philips Semiconductors Preliminary data 2-bit I2C LED dimmer PCA9530 Acknowledge The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse, set-up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition. DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER S START condition 1 2 8 9 clock pulse for acknowledgement SW00368 Figure 8. Acknowledgement on the I2C-bus 2002 Dec 12 6 Philips Semiconductors Preliminary data 2-bit I2C LED dimmer PCA9530 Bus transactions SCL 1 2 3 4 5 6 7 8 9 command byte data to register slave address SDA S 1 1 0 0 0 0 A0 0 R/W A 0 0 0 AI 0 B2 B1 B0 A acknowledge from slave DATA 1 A acknowledge from slave start condition acknowledge from slave WRITE TO REGISTER DATA OUT FROM PORT tpv DATA 1 VALID SW01014 Figure 9. WRITE to register slave address acknowledge from slave acknowledge from slave slave address acknowledge from slave data from register acknowledge from master S 1 1 0 0 0 0 A0 0 R/W A 0 0 0 AI 0 B2 B1 B0 A S 1 1 0 0 0 0 A0 1 R/W A DATA first byte A at this moment master-transmitter becomes master-receiver and slave-receiver becomes slave-transmitter data from register auto-increment register address if AI = 1 no acknowledge from master DATA last byte NA P SW01098 Figure 10. READ from register slave address data from port data from port SDA S 1 1 0 0 0 0 A0 1 R/W A acknowledge from slave DATA 1 A acknowledge from master DATA 4 NA P stop condition start condition no acknowledge from master READ FROM PORT DATA INTO PORT DATA 1 tph DATA 2 DATA 3 tps DATA 4 SW01095 NOTES: 1. This figure assumes the command byte has previously been programmed with 00h. Figure 11. READ input port register 2002 Dec 12 7 Philips Semiconductors Preliminary data 2-bit I2C LED dimmer PCA9530 APPLICATION DATA 5V 3.3 V VDD SDA SCL SDA SCL RESET LED0 LED1 I2C/SMBus MASTER A0 VSS PCA9530 Figure 12. Typical application SW02043 Minimizing IDD when the I/O is used to control LEDs When the I/Os are used to control LEDs, they are normally connected to VDD through a resistor as shown in Figure 12. Since the LED acts as a diode, when the LED is off the I/O VIN is about 1.2 V less than VDD. The supply current , IDD, increases as VIN becomes lower than VDD and is specified as ∆IDD in the DC characteristics table. Designs needing to minimize current consumption, such as battery power applications, should consider maintaining the I/O pins greater than or equal to VDD when the LED is off. Figure 13 shows a high value resistor in parallel with the LED. Figure 14 shows VDD less than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O VIN at or above VDD and prevents additional supply current consumption when the LED is off. VDD 3.3 V 5V LED VDD 100 k VDD LED LEDx LEDx SW02086 SW02087 Figure 13. High value resistor in parallel with the LED Figure 14. Device supplied by a lower voltage 2002 Dec 12 8 Philips Semiconductors Preliminary data 2-bit I2C LED dimmer PCA9530 Programming example The following example will show how to set LED0 to blink at 1 Hz at a 50% duty cycle. LED1 will be set to be dimmed at 25% of their maximum brightness (duty cycle = 25%). Table 1. I2C-bus Start PCA9530 address with A0 = low PSC0 subaddress + auto-increment Set prescaler PSC0 to achieve a period of 1 second: Blink period + 1 + PSC0 ) 1 152 PSC0 = 151 Set PWM0 duty cycle to 50%: PWM0 + 0.5 256 PWM0 = 128 Set prescaler PCS1 to dim at maximum frequency. Blink period + maximum PSC1 = 0 Set PWM1 output duty cycle to 25%: PWM1 + 0.25 256 PWM1 = 64 Set LED0 to PWM0 and set LED1 to blink at PWM1 Stop OEh P 40h S COh 11h 97h 80h 00h 2002 Dec 12 9 Philips Semiconductors Preliminary data 2-bit I2C LED dimmer PCA9530 ABSOLUTE MAXIMUM RATINGS In accordance with the Absolute Maximum Rating System (IEC 134) SYMBOL VDD VI/O II/O ISS Ptot Tstg Tamb Supply voltage DC voltage on an I/O DC output current on an I/O Supply current Total power dissipation Storage temperature range Operating ambient temperature PARAMETER CONDITIONS MIN -0.5 VSS - 0.5 — — — -65 -40 MAX 6.0 5.5 +25 50 400 +150 +85 UNIT V V mA mA mW °C °C HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take precautions appropriate to handling MOS devices. Advice can be found in Data Handbook IC24 under ”Handling MOS devices”. DC CHARACTERISTICS VDD = 2.3 to 5.5 V; VSS = 0 V; Tamb = -40 to +85 °C; unless otherwise specified. TYP at 3.3 V and 25 °C. SYMBOL Supplies VDD IDD Istb ∆IDD VPOR VIL VIH IOL IL CI I/Os VIL VIH LOW level input voltage HIGH level input voltage VOL = 0.4 V; VDD = 2.3 V; Note 1 VOL = 0.4 V; VDD = 3.0 V; Note 1 IOL LOW level output current VOL = 0.4 V; VDD = 5.0 V; Note 1 VOL = 0.7 V; VDD = 2.3 V; Note 1 VOL = 0.7 V; VDD = 3.0 V; Note 1 VOL = 0.7 V; VDD = 5.0 V; Note 1 IL CIO VIL VIH ILI CI Input leakage current Input/output capacitance LOW level input voltage HIGH level input voltage Input leakage current Input capacitance VI = VSS VDD = 3.6 V; VI = 0 or VDD -0.5 2.0 9 12 15 15 20 25 -1 — -0.5 2.0 -1 — — — — — — — — — — 2.1 — — — 2.3 0.8 5.5 — — — — — — 1 5 0.8 5.5 1 5 V V mA mA mA mA mA mA µA pF V V µA pF Supply voltage Supply current Standby current Additional standby current Power-on reset voltage LOW level input voltage HIGH level input voltage LOW level output current Leakage current Input capacitance VOL = 0.4V VI = VDD = VSS VI = VSS Operating mode; VDD = 5.5 V; no load; VI = VDD or VSS; fSCL = 100 kHz Standby mode; VDD = 5.5 V; no load; VI = VDD or VSS; fSCL = 0 kHz Standby mode; VDD = 5.5 V; Every LED I/O at VIN = 4.3 V; fSCL = 0 kHz No load; VI = VDD or VSS 2.3 — — — 1.4 -0.5 0.7 VDD 3 -1 — — 350 1.9 — 1.7 — — — — 3.7 2.2 0.3 VDD 5.5 — +1 5 5.5 500 3.0 V µA µA µA V V V mA µA pF PARAMETER CONDITIONS MIN TYP MAX UNIT Input SCL; input/output SDA Select Inputs A0 / RESET NOTE: 1. The maximum current sink for any single I/O must be externally limited to 25mA. 2002 Dec 12 10 Philips Semiconductors Preliminary data 2-bit I2C LED dimmer PCA9530 AC SPECIFICATIONS SYMBOL fSCL tBUF tHD;STA tSU;STA tSU;STO tHD;DAT tVD;ACK tVD;DAT (L) tVD;DAT (H) tSU;DAT tLOW tHIGH tF tR tSP Port Timing tPV tPS tPH Reset tW tREC tRESET4,5 Reset pulse width Reset recovery time Time to reset 6 0 400 — — — 6 0 400 — — — ns ns ns Output data valid Input data setup time Input data hold time — 100 1 200 — — — 100 1 200 — — ns ns µs PARAMETER Operating frequency Bus free time between STOP and START conditions Hold time after (repeated) START condition Repeated START condition setup time Setup time for STOP condition Data in hold time Valid time for ACK condition2 Data out valid time3 Data out valid time3 Data setup time Clock LOW period Clock HIGH period Clock/Data fall time Clock/Data rise time Pulse width of spikes that must be suppressed by the input filters STANDARD MODE I2C BUS MIN 0 4.7 4.0 4.7 4.0 0 — — — 250 4.7 4.0 — — — MAX 100 — — — — — 600 600 1500 — — — 300 1000 50 FAST MODE I2C BUS MIN 0 1.3 0.6 0.6 0.6 0 — — — 100 1.3 0.6 20 + 0.1 Cb — 1 UNITS kHz µs µs µs µs ns ns ns ns ns µs µs ns ns ns MAX 400 — — — — — 600 600 600 — — — 300 300 50 20 + 0.1 Cb1 NOTES: 1. Cb = total capacitance of one bus line in pF. 2. tVD;ACK = time for Acknowledgement signal from SCL low to SDA (out) low. 3. tVD;DAT = minimum time for SDA data out to be valid following SCL low. 4. Resetting the device while actively communicating on the bus may cause glitches or errant STOP conditions. 5. Upon reset, the full delay will be the sum of tRESET and the RC time constant of the SDA bus. 2002 Dec 12 11 Philips Semiconductors Preliminary data 2-bit I2C LED dimmer PCA9530 +20% MAX +10% 0% PERCENT VARIATION AVG -10% -20% -30% MIN -40% -40 0 +25 TEMPERATURE (°C) +70 +85 SW01085 Figure 15. Typical frequency variation over process at VDD = 2.3 V to 3.0 V +20% MAX +10% 0% PERCENT VARIATION AVG -10% -20% -30% MIN -40% -40 0 +25 TEMPERATURE (°C) +70 +85 SW01086 Figure 16. Typical frequency variation over process at VDD = 3.0 V to 5.5 V 2002 Dec 12 12 Philips Semiconductors Preliminary data 2-bit I2C LED dimmer PCA9530 START SCL ACK OR READ CYCLE SDA 30% tREC RESET 50% tREC tW tREC LEDx 50% LED OFF 50% 50% SW01087 Figure 17. Definition of RESET timing SDA tBUF tLOW tR tF tHD;STA tSP SCL tHD;STA P S tHD;DAT tHIGH tSU;DAT Sr tSU;STA tSU;STO P SU00645 Figure 18. Definition of timing 2002 Dec 12 13 Philips Semiconductors Preliminary data 2-bit I2C LED dimmer PCA9530 SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 2002 Dec 12 14 Philips Semiconductors Preliminary data 2-bit I2C LED dimmer PCA9530 TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1 2002 Dec 12 15 Philips Semiconductors Preliminary data 2-bit I2C LED dimmer PCA9530 Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips. This specification can be ordered using the code 9398 393 40011. Data sheet status Level I Data sheet status[1] Objective data Product status[2] [3] Development Definitions This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). II Preliminary data Qualification III Product data Production [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825  Koninklijke Philips Electronics N.V. 2002 All rights reserved. Printed in U.S.A. Date of release: 12-02 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. Document order number: Philips Semiconductors 2002 Dec 12 16