PCA9564U

INTEGRATED CIRCUITS PCA9564 Parallel bus to I2C-bus controller Product data sheet Supersedes data of 2004 Jun 25 2006 Sep 01 Philips Semiconductors Philips Semiconductors Product data sheet Parallel bus to I2C-bus controller PCA9564 DESCRIPTION The PCA9564 is an integrated circuit designed in CMOS technology that serves as an interface between most standard parallel-bus microcontrollers/microprocessors and the serial I2C-bus and allows the parallel bus system to communicate bi-directionally with the I2C-bus. The PCA9564 can operate as a master or a slave and can be a transmitter or receiver. Communication with the I2C-bus is carried out on a byte-wise basis using interrupt or polled handshake. The PCA9564 controls all the I2C-bus specific sequences, protocol, arbitration and timing with no external timing element required. FEATURES • Parallel-bus to I2C-bus protocol converter and interface • Both master and slave functions • Multi-master capability • Internal oscillator reduces external components • Operating supply voltage 2.3 V to 3.6 V • 5 V tolerant I/Os • Standard and fast mode I2C capable and compatible with SMBus • ESD protection exceeds 2000 V HEM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101 The PCA9564 is similar to the PCF8584 but operates at lower voltages and higher I@C frequencies. Other enhancements requested by design engineers have also been incorporated. Characteristic Voltage range Maximum master mode I2C frequency Maximum slave mode I2C frequency Clock source PCA9564 2.3–3.6 V 360 kHz PCF8584 4.5–5.5 V 90 kHz Comments PCA9564 is 5 V tolerant Faster I2C interface 400 kHz 100 kHz Faster I2C interface • Latch-up testing is done to JEDEC Standard JESD78 which exceed 100 mA. Internal External Less expensive and more flexible with internal oscillator Compatible with faster processors • Packages offered: DIP20, SO20, TSSOP20, HVQFN20 APPLICATIONS Parallel interface Fast 50 MHz Slow • Add I2C-bus port to controllers/processors that do not have one • Add additional I2C-bus ports to controllers/processors that need multiple I2C-bus ports • Higher frequency, lower voltage migration path for the PCF8584 • Converts 8 bits of parallel data to serial data stream to prevent having to run a large number of traces across the entire PC board While the PCF8584 supported most parallel-bus microcontrollers/ microprocessors including the Intel 8049/8051, Motorola 6800/68000 and the Zilog Z80, the PCA9564 has been designed to be very similar to the Philips standard 80C51 microcontroller I2C hardware so the devices are not code compatible. Additionally, the PCA9564 does not support the bus monitor “Snoop” mode nor the long distance mode and is not footprint compatible with the PCF8584. ORDERING INFORMATION PACKAGES 20-Pin Plastic DIP 20-Pin Plastic SO 20-Pin Plastic TSSOP 20-Pin Plastic HVQFN whole wafer TEMPERATURE RANGE –40 °C to +85 °C –40 °C to +85 °C –40 °C to +85 °C –40 °C to +85 °C –40 °C to +85 °C ORDER CODE PCA9564N PCA9564D PCA9564PW PCA9564BS PCA9564U TOPSIDE MARK PCA9564N PCA9564D PCA9564 9564 n/a DRAWING NUMBER SOT146-1 SOT163-1 SOT360-1 SOT662-1 n/a Standard packing quantities and other packaging data are available at www.standardics.philips.com/packaging. 2006 Sep 01 2 Philips Semiconductors Product data sheet Parallel bus to I2C-bus controller PCA9564 PIN CONFIGURATION — DIP, SO, TSSOP D0 D1 D2 D3 D4 D5 D6 D7 DNU 1 2 3 4 5 6 7 8 9 20 VDD 19 SDA 18 SCL 17 RESET 16 INT 15 A1 PIN CONFIGURATION — HVQFN 16 SDA 15 SCL 14 RESET 13 INT 12 A1 11 A0 CE 10 6 7 8 WR 9 RD 17 VDD 20 D2 19 D1 VSS 18 D0 D3 D4 D5 D6 1 2 3 4 5 TOP VIEW 14 A0 13 CE 12 RD 11 WR D7 VSS 10 DNU SW02260 SW02261 PIN DESCRIPTION PIN NUMBER DIP, SO, TSSOP 1, 2, 3, 4, 5, 6, 7, 8 9 10 11 HVQFN 1, 2, 3, 4, 5, 18, 19, 20 6 71 8 SYMBOL D0–D7 DNU VSS WR Pwr I PIN TYPE I/O NAME AND FUNCTION Data Bus: Bi-directional 3-State data bus used to transfer commands, data and status between the controller and the CPU. D0 is the least significant bit. Do not use: must be left floating (pulled LOW internally) Ground Write Strobe: When LOW and CE is also LOW, the contents of the data bus is loaded into the addressed register. The transfer occurs on the rising edge of the signal. Read Strobe: When LOW and CE is also LOW, causes the contents of the addressed register to be presented on the data bus. The read cycle begins on the falling edge of RD. Chip Enable: Active-LOW input signal. When LOW, data transfers between the CPU and the controller are enabled on D0–D7 as controlled by the WR, RD and A0–A1 inputs. When HIGH, places the D0–D7 lines in the 3-State condition. Address Inputs: Selects the controller internal registers and ports for read/write operations. Interrupt Request: Active-LOW, open-drain, output. This pin requires a pull-up device. Reset: A LOW level clears internal registers resets the I2C state machine. I2C-bus serial clock input/output (open-drain). I2C-bus serial data input/output (open-drain). Power Supply: 2.3 to 3.6 V 12 9 RD I 13 10 CE I 14, 15 16 17 18 19 20 11, 12 13 14 15 16 17 A0, A1 INT RESET SCL SDA VDD I O I I/O I/O Pwr NOTES: 1. HVQFN package die supply ground is connected to both VSS pin and exposed center pad. VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the PCB in the thermal pad region. 2006 Sep 01 3 Philips Semiconductors Product data sheet Parallel bus to I2C-bus controller PCA9564 DATA D7 D6 D5 D4 D3 D2 D1 D0 PCA9564 SDA FILTER BUS BUFFER A1 SDA CONTROL SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 0 I2CDAT – DATA REGISTER – READ/WRITE A0 1 TE AA ENSIO STA STO SI TO6 TO5 TO4 TO3 TO2 TO1 TO0 0 0 I2CTO – TIMEOUT REGISTER – WRITE ONLY SCL FILTER BIT7 SCL CONTROL BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 1 0 I2CADR – OWN ADDRESS – READ/WRITE ST7 ST6 ST5 ST4 ST3 ST2 ST1 ST0 0 0 I2CSTA – STATUS REGISTER – READ ONLY ENSIO STA STO SI AA ENSIO STA STO SI CR2 CR1 CR0 1 1 I2CCON – CONTROL REGISTER – READ/WRITE CLOCK SELECTOR OSCILLATOR CR0 CR1 CR2 CONTROL BLOCK INTERRUPT CONTROL POWER–ON RESET CE WR RD INT RESET A1 A0 VDD CONTROL SIGNALS SW02262 Figure 1. Block diagram 2006 Sep 01 4 Philips Semiconductors Product data sheet Parallel bus to I2C-bus controller PCA9564 FUNCTIONAL DESCRIPTION General The PCA9564 acts as an interface device between standard high-speed parallel buses and the serial I2C-bus. On the I2C-bus, it can act either as master or slave. Bidirectional data transfer between the I2C-bus and the parallel-bus microcontroller is carried out on a byte-wise basis, using either an interrupt or polled handshake. The Address Register, I2CADR: I2CADR is not affected by the SIO hardware. The contents of this register are irrelevant when SIO is in a master mode. In the slave modes, the seven most significant bits must be loaded with the microcontroller’s own slave address. 7 I2CADR BIT7 6 BIT6 5 BIT5 4 BIT4 3 BIT3 2 BIT2 1 BIT1 0 0 own slave address Internal Oscillator The PCA9564 contains an internal 9 MHz oscillator which is used for all I2C timing. The oscillator requires up to 500 µs to start-up after ENSIO bit is set to “1”. The most significant bit corresponds to the first bit received from the I2C-bus after a start condition. A logic 1 in I2CADR corresponds to a HIGH level on the I2C-bus, and a logic 0 corresponds to a LOW level on the bus. The least significant bit is not used but should be programmed with a ‘0’. The Data Register, I2CDAT: I2CDAT contains a byte of serial data to be transmitted or a byte which has just been received. In master mode, this includes the slave address that the master wants to send out on the I2C-bus, with the most significant bit of the slave address in the SD7 bit position and the Read/Write bit in the SD0 bit position. The CPU can read from and write to this 8-bit register while it is not in the process of shifting a byte. This occurs when SIO is in a defined state and the serial interrupt flag is set. Data in I2CDAT remains stable as long as SI is set. Whenever the SIO generates an interrupt, the I2CDAT registers contain the data byte that was just transferred on the I2C-bus. NOTE: The I2CDAT register will capture the serial address as data when addressed via the serial bus. Also, the data register will continue to capture data from the serial bus during 38H so the I2CDAT register will need to be reloaded when the bus becomes free. 7 6 SD6 5 SD5 4 SD4 3 SD3 2 SD2 1 SD1 0 SD0 I2CDAT SD7 Registers The PCA9564 contains four registers which are used to configure the operation of the device as well as to send and receive serial data. The registers are selected by setting pins A0 and A1 to the appropriate logic levels before a read or write operation is executed. CAUTION: Do not write to I2C registers while the I2C-bus is busy and the SIO is in master or addressed slave mode. REGISTER NAME I2CSTA I2CTO I2CDAT I2CADR I2CCON REGISTER FUNCTION Status Time-out Data Own address Control A1 0 0 0 1 1 A0 0 0 1 0 1 READ/ WRITE R W R/W R/W R/W DEFAULT F8h FFh 00h 00h 00h The Time-out Register, I2CTO: The time-out register is used to determine the maximum time that SCL is allowed to be LOW before the I2C state machine is reset. When the I2C interface is operating, I2CTO is loaded in the time-out counter at every SCL transition. 7 I2CTO TE 6 TO6 5 TO5 4 TO4 3 TO3 2 TO2 1 TO1 0 TO0 • SD7 - SD0: Eight bits to be transmitted or just received. A logic 1 in I2CDAT corresponds to a HIGH level on the I2C-bus, and a logic 0 corresponds to a LOW level on the bus. The Control Register, I2CCON: The microcontroller can read from and write to this 8-bit register. Two bits are affected by the SIO hardware: the SI bit is set when a serial interrupt is requested, and the STO bit is cleared when a STOP condition is present on the I2C-bus. A write to the I2CCON register clears the SI bit and causes the Serial Interrupt line to be de–asserted and the next clock pulse on the SCL line to be generated. Since none of the registers should be written to via the parallel interface once the Serial Interrupt line has been de-asserted, all the other registers that need to be modified should be written to before the content of the I2CCON register is modified. 7 I2CCON AA 6 ENSIO 5 STA 4 STO 3 SI 2 CR2 1 CR1 0 CR0 Time-out value The most significant bit of I2CTO (TE) is used as a time-out enable/disable. A “1” will enable the time-out function. The time-out period = (I2CTO[6:0] + 1) × 113.7 µs. The time-out value may vary some and is an approximate value. The time-out register can be used in the following cases: 1. When the SIO, in the master mode, wants to send a START condition and the SCL line is held LOW by some other device. The SIO waits a time period equivalent to the time-out value for the SCL to be released. In case it is not released, the SIO concludes that there is a bus error, loads 90H in the I2CSTA register, generates an interrupt signal and releases the SCL and SDA lines. After the microcontroller reads the status register, it needs to send an external reset in order to reset the SIO. 2. In the master mode, the time-out feature starts every time the SCL goes LOW. If SCL stays LOW for a time period equal to or greater than the time-out value, the SIO concludes there is a bus error and behaves in the manner described above. 3. In case of a forced access to the I2C-bus. (See more details on page 15.) • ENSIO, THE SIO ENABLE BIT ENSIO = “0”: When ENSIO is “0”, the SDA and SCL outputs are in a high impedance state. SDA and SCL input signals are ignored, SIO is in the “not addressed” slave state. ENSIO = “1”: When ENSIO is “1”, SIO is enabled. After the ENSIO bit is set, it takes 500 µs for the internal oscillator to start up, therefore, the PCA9564 will enter either the master or the slave mode after this time. ENSIO should not be used to temporarily 2006 Sep 01 5 Philips Semiconductors Product data sheet Parallel bus to I2C-bus controller PCA9564 release the PCA9564 from the I2C-bus since, when ENSIO is reset, the I2C-bus status is lost. The AA flag should be used instead (see description of the AA flag in the following text). – A data byte has been received while SIO is in the addressed slave receiver mode – “Own slave address” has been received When SIO is in the addressed slave transmitter mode, state C8H will be entered after the last serial is transmitted (see Figure 5). When SI is cleared, enters the not addressed slave receiver mode, and the SDA line remains at a HIGH level. In state C8H, the AA flag can be set again for future address recognition. When SIO is in the not addressed slave mode, its own slave address is ignored. Consequently, no acknowledge is returned, and a serial interrupt is not requested. Thus, SIO can be temporarily released from the I2C-bus while the bus status is monitored. While SIO is released from the bus, START and STOP conditions are detected, and serial data is shifted in. Address recognition can be resumed at any time by setting the AA flag. • STA, THE START FLAG In the following text, it is assumed that ENSIO = “1”. STA = “1”: When the STA bit is set to enter a master mode, the SIO hardware checks the status of the I2C-bus and generates a START condition if the bus is free. If the bus is not free, then SIO waits for a STOP condition (which will free the bus) and generates a START condition after the minimum buffer time (tBUF) has elapsed. If STA is set while SIO is already in a master mode and one or more bytes are transmitted or received, SIO transmits a repeated START condition. STA may be set at any time. STA may also be set when SIO is an addressed slave. STA = “0”: When the STA bit is reset, no START condition or repeated START condition will be generated. • STO, THE STOP FLAG • THE CLOCK RATE BITS, CR2, CR1, AND CR0 STO = “1”: When the STO bit is set while SIO is in a master mode, a STOP condition is transmitted to the I2C-bus. When the STOP condition is detected on the bus, the SIO hardware clears the STO flag. If the STA and STO bits are both set, then a STOP condition is transmitted to the I2C-bus if SIO is in a master mode. SIO then transmits a START condition. STO = “0”: When the STO bit is reset, no STOP condition will be generated. Three bits determine the serial clock frequency when SIO is in master mode. The various serial rates are shown in Table 1. The clock frequencies only take the HIGH and LOW times into consideration. The rise and fall time will cause the actual measured frequency to be lower than expected. The frequencies shown in Table 1 are unimportant when SIO is in a slave mode. In the slave modes, SIO will automatically synchronize with any clock frequency up to 400 kHz. Table 1. Serial Clock Rates CR2 CR1 CR0 SERIAL CLOCK FREQUENCY (kHz) • SI, THE SERIAL INTERRUPT FLAG SI = “1”: When the SI flag is set, then, if the ENSIO bit is also set, a serial interrupt is requested. SI is set by hardware when one of 24 of the 25 possible SIO states is entered. The only state that does not cause SI to be set is state F8H, which indicates that no relevant state information is available. While SI is set, the LOW period of the serial clock on the SCL line is stretched, and the serial transfer is suspended. A HIGH level on the SCL line is unaffected by the serial interrupt flag. SI must be reset by writing “0” to the SI bit. The SI bit cannot be set by the user. SI = “0”: When the SI flag is reset, no serial interrupt is requested, and there is no stretching of the serial clock on the SCL line. • AA, THE ASSERT ACKNOWLEDGE FLAG AA = “1”: If the AA flag is set, an acknowledge (LOW level to SDA) will be returned during the acknowledge clock pulse on the SCL line when: – The “own slave address” has been received – A data byte has been received while SIO is in the master receiver mode – A data byte has been received while SIO is in the addressed slave receiver mode AA = “0”: if the AA flag is reset, a not acknowledge (HIGH level to SDA) will be returned during the acknowledge clock pulse on SCL when: – A data byte has been received while SIO is in the master receiver mode 0 0 0 330 0 0 1 288 0 1 0 217 0 1 1 146 1 0 0 881 1 0 1 59 1 1 0 44 1 1 1 36 NOTE: 1. The clock frequency values are approximate and may vary with temperature, supply voltage, process, and SCL output loading. If normal mode I2C parameters must be strictly followed (SCL < 100kHz), it is recommended not to use CR[2:0] = 100 (SCL = 88kHz) since the clock frequency might be slightly higher than 100 kHz under certain temperature, voltage, and process conditions and use CR[2:0] = 101 (SCL = 59 kHz) instead. The Status Register, I2CSTA: I2CSTA is an 8-bit read-only register. The three least significant bits are always zero. The five most significant bits contain the status code. There are 25 possible status codes. When I2CSTA contains F8H, no relevant state information is available and no serial interrupt is requested. All other I2CSTA values correspond to defined SIO states. When each of these states is entered, a serial interrupt is requested (SI = “1”). 2006 Sep 01 6 Philips Semiconductors Product data sheet Parallel bus to I2C-bus controller PCA9564 More Information on SIO Operating Modes The four operating modes are: – Master Transmitter – Master Receiver – Slave Receiver – Slave Transmitter Data transfers in each mode of operation are shown in Figures 2–5. These figures contain the following abbreviations: Abbreviation S SLA R W A A Data P Explanation Start condition 7-bit slave address Read bit (HIGH level at SDA) Write bit (LOW level at SDA) Acknowledge bit (LOW level at SDA) Not acknowledge bit (HIGH level at SDA) 8-bit data byte Stop condition Master Receiver Mode: In the master receiver mode, a number of data bytes are received from a slave transmitter (see Figure 3). The transfer is initialized as in the master transmitter mode. When the start condition has been transmitted, the interrupt service routine must load I2CDAT with the 7-bit slave address and the data direction bit (SLA+R). The SI bit in I2CCON must then be cleared before the serial transfer can continue. When the slave address and the data direction bit have been transmitted and an acknowledgment bit has been received, the serial interrupt flag (SI) is set again, and a number of status codes in I2CSTA are possible. These are 40H, 48H, or 38H for the master mode and also 68H, or B0H if the slave mode was enabled (AA = logic 1). The appropriate action to be taken for each of these status codes is detailed in Table 3. ENSIO is not affected by the serial transfer and are not referred to in Table 3. After a repeated start condition (state 10H), SIO may switch to the master transmitter mode by loading I2CDAT with SLA+W. Note that a master should not transmit its own slave address. Slave Receiver Mode: In the slave receiver mode, a number of data bytes are received from a master transmitter (see Figure 4). To initiate the slave receiver mode, I2CADR and I2CCON must be loaded as follows: 7 I2CADR BIT7 6 BIT6 5 BIT5 4 BIT4 3 BIT3 2 BIT2 1 BIT1 0 0 In Figures 2-5, circles are used to indicate when the serial interrupt flag is set. A serial interrupt is not generated when I2CSTA = F8H. This happens on a stop condition. The numbers in the circles show the status code held in the I2CSTA register. At these points, a service routine must be executed to continue or complete the serial transfer. These service routines are not critical since the serial transfer is suspended until the serial interrupt flag is cleared by software. When a serial interrupt routine is entered, the status code in I2CSTA is used to branch to the appropriate service routine. For each status code, the required software action and details of the following serial transfer are given in Tables 2-6. Master Transmitter Mode: In the master transmitter mode, a number of data bytes are transmitted to a slave receiver (see Figure 2). Before the master transmitter mode can be entered, I2CCON must be initialized as follows: 7 I2CCON AA X 6 ENSIO 1 5 STA 0 4 STO 0 3 SI 0 2 CR2 1 CR1 0 CR0 own slave address The upper 7 bits are the address to which SIO will respond when addressed by a master. 7 I2CCON AA 1 6 ENSIO 1 5 STA 0 4 STO 0 3 SI 0 2 CR2 X 1 CR1 X 0 CR0 X bit rate ENSIO must be set to logic 1 to enable SIO. If the AA bit is reset, SIO will not acknowledge its own slave address in the event of another device becoming master of the bus. In other words, if AA is reset, SIO cannot enter a slave mode. STA, STO, and SI must be reset. The master transmitter mode may now be entered by setting the STA bit. The SIO logic will now test the I2C-bus and generate a start condition as soon as the bus becomes free. When a START condition is transmitted, the serial interrupt flag (SI) is set, and the status code in the status register (I2CSTA) will be 08H. This status code must be used to vector to an interrupt service routine that loads I2CDAT with the slave address and the data direction bit (SLA+W). The SI bit in I2CCON must then be reset before the serial transfer can continue. When the slave address and the direction bit have been transmitted and an acknowledgment bit has been received, the serial interrupt flag (SI) is set again, and a number of status codes in I2CSTA are possible. There are 18H, 20H, or 38H for the master mode and also 68H, or B0H if the slave mode was enabled (AA = logic 1). The appropriate action to be taken for each of these status codes is detailed in Table 2. After a repeated start condition (state 10H). SIO may switch to the master receiver mode by loading I2CDAT with SLA+R). Note that a master should never transmit its own slave address. 2006 Sep 01 7 ENSIO must be set to logic 1 to enable SIO. The AA bit must be set to enable SIO to acknowledge its own slave address, STA, STO, and SI must be reset. When I2CADR and I2CCON have been initialized, SIO waits until it is addressed by its own slave address followed by the data direction bit which must be “0” (W) for SIO to operate in the slave receiver mode. After its own slave address and the W bit have been received, the serial interrupt flag (I) is set and a valid status code can be read from I2CSTA. This status code is used to vector to an interrupt service routine, and the appropriate action to be taken for each of these status codes is detailed in Table 4. The slave receiver mode may also be entered if arbitration is lost while SIO is in the master mode (see status 68H). If the AA bit is reset during a transfer, SIO will return a not acknowledge (logic 1) to SDA after the next received data byte. While AA is reset, SIO does not respond to its own slave address. However, the I2C-bus is still monitored and address recognition may be resumed at any time by setting AA. This means that the AA bit may be used to temporarily isolate SIO from the I2C-bus. Philips Semiconductors Product data sheet Parallel bus to I2C-bus controller PCA9564 MT SUCCESSFUL TRANSMISSION TO A SLAVE RECEIVER NEXT TRANSFER STARTED WITH A REPEATED START CONDITION NOT ACKNOWLEDGE RECEIVED AFTER THE SLAVE ADDRESS NOT ACKNOWLEDGE RECEIVED AFTER A DATA BYTE ARBITRATION LOST IN SLAVE ADDRESS OR DATA BYTE ARBITRATION LOST AND ADDRESSED AS SLAVE FROM MASTER TO SLAVE FROM SLAVE TO MASTER Data A ANY NUMBER OF DATA BYTES AND THEIR ASSOCIATED ACKNOWLEDGE BITS n THIS NUMBER (CONTAINED IN I2CSTA) CORRESPONDS TO A DEFINED STATE OF THE I2C BUS. SEE TABLE 2. NOTE: THE MASTER SHOULD NEVER TRANSMIT ITS OWN SLAVE ADDRESS Figure 2. Format and states in the master transmitter mode 2006 Sep 01 ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇ ÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇÇÇÇ Ç ÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇÇÇÇ Ç S SLA W A DATA A P 08H 18H 28H F8 S SLA W 10H A P R 20H F8H A P 30H F8H A or A OTHER MST CONTINUES A or A OTHER MST CONTINUES 38H 38H A OTHER MST CONTINUES 68H TO CORRESPONDING STATES IN SLAVE RECEIVER MODE TO CORRESPONDING STATES IN SLAVE TRANSMITTER MODE B0H TO MST/REC MODE ENTRY = MR ÇÇÇÇ Ç ÇÇÇÇ Ç ÇÇÇÇ ÇÇÇÇ Ç ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ SW00816 8 Philips Semiconductors Product data sheet Parallel bus to I2C-bus controller PCA9564 MR SUCCESSFUL RECEPTION FROM A SLAVE TRANSMITTER NEXT TRANSFER STARTED WITH A REPEATED START CONDITION NOT ACKNOWLEDGE RECEIVED AFTER THE SLAVE ADDRESS ARBITRATION LOST IN SLAVE ADDRESS OR ACKNOWLEDGE BIT ARBITRATION LOST AND ADDRESSED AS SLAVE FROM MASTER TO SLAVE FROM SLAVE TO MASTER DATA A ANY NUMBER OF DATA BYTES AND THEIR ASSOCIATED ACKNOWLEDGE BITS n THIS NUMBER (CONTAINED IN I2CSTA) CORRESPONDS TO A DEFINED STATE OF THE I2C BUS. SEE TABLE 3. 2006 Sep 01 ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇ ÇÇ Ç ÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇ ÇÇ Ç ÇÇÇÇÇÇÇÇ S SLA R A DATA A DATA A P 08H 40H 50H 58H F8H S SLA R 10H A P W 48H F8H TO MST/TRX MODE ENTRY = MT A or A OTHER MST CONTINUES 38H A OTHER MST CONTINUES 68H TO CORRESPONDING STATES IN SLAVE RECEIVER MODE TO CORRESPONDING STATES IN SLAVE TRANSMITTER MODE B0H Figure 3. Format and states in the master receiver mode 9 ÇÇÇ ÇÇÇ ÇÇÇ A 38H OTHER MST CONTINUES ÇÇ ÇÇÇÇ ÇÇÇÇÇ Ç ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ SW00817 Philips Semiconductors Product data sheet Parallel bus to I2C-bus controller PCA9564 RECEPTION OF THE OWN SLAVE ADDRESS AND ONE OR MORE DATA BYTES ALL ARE ACKNOWLEDGED. LAST DATA BYTE RECEIVED IS NOT ACKNOWLEDGED ARBITRATION LOST AS MST AND ADDRESSED AS SLAVE FROM MASTER TO SLAVE FROM SLAVE TO MASTER Data A ANY NUMBER OF DATA BYTES AND THEIR ASSOCIATED ACKNOWLEDGE BITS n THIS NUMBER (CONTAINED IN I2CSTA) CORRESPONDS TO A DEFINED STATE OF THE I2C BUS. SEE TABLE 4. RECEPTION OF THE OWN SLAVE ADDRESS AND TRANSMISSION OF ONE OR MORE DATA BYTES S SLA ARBITRATION LOST AS MST AND ADDRESSED AS SLAVE FROM MASTER TO SLAVE B0H LAST DATA BYTE TRANSMITTED. SWITCHED TO NOT ADDRESSED SLAVE (AA BIT IN I2CCON = “0”) A All “1”s FROM SLAVE TO MASTER C8H DATA A ANY NUMBER OF DATA BYTES AND THEIR ASSOCIATED ACKNOWLEDGE BITS n THIS NUMBER (CONTAINED IN I2CSTA) CORRESPONDS TO A DEFINED STATE OF THE I2C BUS. SEE TABLE 5. Figure 5. Format and states of the slave transmitter mode 2006 Sep 01 10 ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇÇ Ç ÇÇÇ ÇÇÇ ÇÇÇÇÇÇ ÇÇÇÇÇÇÇ ÇÇÇ ÇÇÇÇÇÇÇ S SLA W A DATA A DATA SLA A P or S 60H 80H 80H A0H A P or S 88H F8H ON STOP A Figure 4. Format and states in the slave receiver mode R A DATA A8H A ÇÇÇÇÇÇÇÇÇÇ ÇÇ Ç ÇÇÇÇÇÇÇÇÇÇ ÇÇ Ç ÇÇÇÇÇÇÇÇÇÇ ÇÇ Ç ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ P or S F8 A B8H 68H ÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇ ÇÇ ÇÇ ÇÇÇÇÇ Ç ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ Ç ÇÇÇÇ ÇÇÇÇ Ç ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ ON STOP SW00814 DATA A P or S C0H F8H ON STOP P or S F8H ON STOP SW00815 Philips Semiconductors Product data sheet Parallel bus to I2C-bus controller PCA9564 Table 2. STATUS CODE (I2CSTA) 08H 10H Master Transmitter Mode STATUS OF THE OF THE I2C BUS AND SIO HARDWARE HARDWARE A START condition has been transmitted A repeated START condition h b diti has been transmitted SLA+W has been transmitted; ACK has been received b id APPLICATION SOFTWARE RESPONSE TO/FROM I2CDAT I2CDAT STA Load SLA+W Load SLA+W or Load SLA+R Load data byte or no I2CDAT action or no I2CDAT action or no I2CDAT action X X X 0 1 0 1 TO I2CCON STO X X X 0 0 1 1 SI 0 0 0 0 0 0 0 AA X X X X X X X SLA+W will be transmitted; ACK bit will be received As above SLA+R will be transmitted; SIO will be switched to MST/REC mode Data byte will be transmitted; ACK bit will be received Repeated START will be transmitted; STOP condition will be transmitted; STO flag will be reset STOP condition followed by a START condition will be transmitted; STO flag will be reset Data byte will be transmitted; ACK bit will be received Repeated START will be transmitted; STOP condition will be transmitted; STO flag will be reset STOP condition followed by a START condition will be transmitted; STO flag will be reset Data byte will be transmitted; ACK bit will be received Repeated START will be transmitted; STOP condition will be transmitted; STO flag will be reset STOP condition followed by a START condition will be transmitted; STO flag will be reset Data byte will be transmitted; ACK bit will be received Repeated START will be transmitted; STOP condition will be transmitted; STO flag will be reset STOP condition followed by a START condition will be transmitted; STO flag will be reset I2C-bus will be released; not addressed slave will be entered A START condition will be transmitted when the bus becomes free (STOP or SCL and SDA high) NEXT ACTION TAKEN BY SIO HARDWARE 18H 20H SLA+W has been transmitted; NOT ACK hb id has been received Load data byte or no I2CDAT action or no I2CDAT action or no I2CDAT action 0 1 0 1 0 0 1 1 0 0 0 0 X X X X 28H Data byte in I2CDAT has been transmitted; ACK h b id has been received Load data byte or no I2CDAT action or no I2CDAT action or no I2CDAT action 0 1 0 1 0 0 1 1 0 0 0 0 X X X X 30H Data byte in I2CDAT has been transmitted; NOT ACK h b has been received received Load data byte or no I2CDAT action or no I2CDAT action or no I2CDAT action 0 1 0 1 0 0 1 1 0 0 0 0 X X X X 38H Arbitration lost in SLA+W or D Data b bytes No I2CDAT action or No I2CDAT action 0 1 0 0 0 0 X X 2006 Sep 01 11 Philips Semiconductors Product data sheet Parallel bus to I2C-bus controller PCA9564 Table 3. STATUS CODE (I2CSTA) 08H 10H Master Receiver Mode STATUS OF THE OF THE I2C BUS AND SIO HARDWARE SIO HARDWARE A START condition has been transmitted A repeated START condition h b diti has been transmitted Arbitration lost in NOT ACK bit APPLICATION SOFTWARE RESPONSE TO/FROM I2CDAT I2CDAT STA Load SLA+R Load SLA+R or Load SLA+W No I2CDAT action or No I2CDAT action X X X 0 1 0 0 1 0 1 TO I2CCON STO X X X 0 0 0 0 0 1 1 SI 0 0 0 0 0 0 0 0 0 0 AA X X X X X 0 1 X X X SLA+R will be transmitted; ACK bit will be received As above SLA+W will be transmitted; SIO will be switched to MST/TRX mode I2C-bus will be released; SIO will enter a slave mode A START condition will be transmitted when the bus becomes free Data byte will be received; NOT ACK bit will be returned Data byte will be received; ACK bit will be returned Repeated START condition will be transmitted STOP condition will be transmitted; STO flag will be reset STOP condition followed by a START condition will be transmitted; STO flag will be reset Data byte will be received; NOT ACK bit will be returned Data byte will be received; ACK bit will be returned Repeated START condition will be transmitted STOP condition will be transmitted; STO flag will be reset STOP condition followed by a START condition will be transmitted; STO flag will be reset I2C-bus will be released; not addressed slave will be entered A START condition will be transmitted when the bus becomes free NEXT ACTION TAKEN BY SIO HARDWARE 38H 40H SLA+R has been transmitted; ACK has b id been received SLA+R has been transmitted; NOT ACK t itt d has been received No I2CDAT action or no I2CDAT action No I2CDAT action or no I2CDAT action or no I2CDAT action 48H 50H Data byte has been received; ACK has been d returned Data byte has been received; NOT ACK h id has been returned Read data byte or read data byte Read data byte or read data byte or read data byte 0 0 1 0 1 0 0 0 1 1 0 0 0 0 0 0 1 X X X 58H 38H Arbitration lost in SLA+R No I2CDAT action or No I2CDAT action 0 1 0 0 0 0 X X 2006 Sep 01 12 Philips Semiconductors Product data sheet Parallel bus to I2C-bus controller PCA9564 Table 4. STATUS CODE (I2CSTA) 60H Slave Receiver Mode STATUS OF THE OF THE I2C BUS AND SIO HARDWARE HARDWARE Own SLA+W has been received; ACK hb d has been returned Arbitration lost in SLA+R/W as master; Own SLA+W has been received, ACK returned Previously addressed with own SLV address; DATA has been received; ACK has been returned Previously addressed with own SLA; DATA b hb byte has been received; NOT ACK been returned has been returned APPLICATION SOFTWARE RESPONSE TO/FROM I2CDAT I2CDAT STA No I2CDAT action or no I2CDAT action No I2CDAT action or no I2CDAT action Read data byte or X X X TO I2CCON STO X X X SI 0 0 0 AA 0 1 0 Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned Switched to not addressed SLV mode; no recognition of own SLA Switched to not addressed SLV mode; Own SLA will be recognized Switched to not addressed SLV mode; no recognition of own SLA. A START condition will be transmitted when the bus becomes free Switched to not addressed SLV mode; Own SLA will be recognized. A START condition will be transmitted when the bus becomes free. Switched to not addressed SLV mode; no recognition of own SLA Switched to not addressed SLV mode; Own SLA will be recognized Switched to not addressed SLV mode; no recognition of own SLA. A START condition will be transmitted when the bus becomes free Switched to not addressed SLV mode; Own SLA will be recognized. A START condition will be transmitted when the bus becomes free. NEXT ACTION TAKEN BY SIO HARDWARE 68H X X X X 0 0 1 0 80H read data byte Read data byte or read data byte or read data byte or X 0 0 1 X X X X 0 0 0 0 1 0 1 0 88H read data byte 1 X 0 1 A0H A STOP condition or repeated START condition h b di i has been received while still addressed as as SLV/REC No I2CDAT action or No I2CDAT action or No I2CDAT action or No I2CDAT action 0 0 1 X X X 0 0 0 0 1 0 1 X 0 1 2006 Sep 01 13 Philips Semiconductors Product data sheet Parallel bus to I2C-bus controller PCA9564 Table 5. STATUS CODE (I2CSTA) A8H Slave Transmitter Mode STATUS OF THE OF THE I2C BUS AND SIO HARDWARE HARDWARE Own SLA+R has been received; ACK hb d has been returned Arbitration lost in SLA+R/W as master; Own SLA+R has Own SLA+R has been received, ACK has been returned Data byte in I2CDAT has been transmitted; ACK h b has been received Data byte in I2CDAT has been transmitted; NOT ACK h b has been received APPLICATION SOFTWARE RESPONSE TO/FROM I2CDAT I2CDAT STA Load data byte or load data byte Load data byte or load data byte Load data byte or load data byte No I2CDAT action or no I2CDAT action or no I2CDAT action or X X X X X X 0 0 1 TO I2CCON STO X X X X X X X X X SI 0 0 0 0 0 0 0 0 0 AA 0 1 0 1 0 1 0 1 0 Last data byte will be transmitted and ACK bit will be received Data byte will be transmitted; ACK will be received Last data byte will be transmitted and ACK bit will be received Data byte will be transmitted; ACK bit will be received Last data byte will be transmitted and ACK bit will be received Data byte will be transmitted; ACK bit will be received Switched to not addressed SLV mode; no recognition of own SLA Switched to not addressed SLV mode; Own SLA will be recognized Switched to not addressed SLV mode; no recognition of own SLA. A START condition will be transmitted when the bus becomes free Switched to not addressed SLV mode; Own SLA will be recognized. A START condition will be transmitted when the bus becomes free. Switched to not addressed SLV mode; no recognition of own SLA Switched to not addressed SLV mode; Own SLA will be recognized Switched to not addressed SLV mode; no recognition of own SLA. A START condition will be transmitted when the bus becomes free Switched to not addressed SLV mode; Own SLA will be recognized. A START condition will be transmitted when the bus becomes free. NEXT ACTION TAKEN BY SIO HARDWARE B0H B8H C0H no I2CDAT action 1 X 0 1 C8H Last data byte in I2CDAT has been id 0) transmitted (AA = 0); ACK has been received received No I2CDAT action or no I2CDAT action or no I2CDAT action or 0 0 1 X X X 0 0 0 0 1 0 no I2CDAT action 1 X 0 1 Table 6. STATUS CODE (I2CSTA) F8H Miscellaneous States STATUS OF THE OF THE I2C BUS AND SIO HARDWARE HARDWARE On reset or STOP APPLICATION SOFTWARE RESPONSE TO/FROM I2CDAT I2CDAT STA No I2CDAT action No I2CDAT action No I2CDAT action 1 0 0 TO I2CCON STO X X X SI 0 0 0 AA X 0 1 Go into master mode; send START No recognition of own SLA Will recognize own SLA Reset SIO (Requires reset to return to state F8H) Reset SIO (Requires reset to return to state F8H) Reset SIO (Requires reset to return to state F8H) NEXT ACTION TAKEN BY SIO HARDWARE 70H 90H 00H Bus error SDA stuck LOW Bus error SCL stuck LOW Bus error during master or slave mode, due to illegal START or STOP condition 2006 Sep 01 14 Philips Semiconductors Product data sheet Parallel bus to I2C-bus controller PCA9564 Slave Transmitter Mode: In the slave transmitter mode, a number of data bytes are transmitted to a master receiver (see Figure 5). Data transfer is initialized as in the slave receiver mode. When I2CADR and I2CCON have been initialized, SIO waits until it is addressed by its own slave address followed by the data direction bit which must be “1” (R) for SIO to operate in the slave transmitter mode. After its own slave address and the R bit have been received, the serial interrupt flag (SI) is set and a valid status code can be read from I2CSTA. This status code is used to vector to an interrupt service routine, and the appropriate action to be taken for each of these status codes is detailed in Table 5. The slave transmitter mode may also be entered if arbitration is lost while SIO is in the master mode (see state B0H). If the AA bit is reset during a transfer, SIO will transmit the last byte of the transfer and enter state C8H. SIO is switched to the not addressed slave mode and will ignore the master receiver if it continues the transfer. Thus the master receiver receives all 1s as serial data. While AA is reset, SIO does not respond to its own slave address. However, the I2C-bus is still monitored, and address recognition may be resumed at any time by setting AA. This means that the AA bit may be used to temporarily isolate SIO from the I2C-bus. Miscellaneous States: There are four I2CSTA codes that do not correspond to a defined SIO hardware state (see Table 6). These are discussed below. I2CSTA = F8H: This status code indicates that no relevant information is available because the serial interrupt flag, SI, is not yet set. This occurs on a STOP condition and when SIO is not involved in a serial transfer. I2CSTA = 00H: This status code indicates that a bus error has occurred during an SIO serial transfer. A bus error is caused when a START or STOP condition occurs at an illegal position in the format frame. Examples of such illegal positions are during the serial transfer of an address byte, a data byte, or an acknowledge bit. A bus error may also be caused when external interference disturbs the internal SIO signals. When a bus error occurs, SI is set. To recover from a bus error, the microcontroller must send an external reset signal to reset the SIO. I2CSTA = 70H: This status code indicates that the SDA line is stuck LOW when the SIO, in master mode, is trying to send a START condition. I2CSTA = 90H: This status code indicates that the SCL line is stuck LOW. Some Special Cases: The SIO hardware has facilities to handle the following special cases that may occur during a serial transfer: • SIMULTANEOUS REPEATED START CONDITIONS FROM TWO MASTERS A repeated START condition may be generated in the master transmitter or master receiver modes. A special case occurs if another master simultaneously generates a repeated START condition (see Figure 6). Until this occurs, arbitration is not lost by either master since they were both transmitting the same data. If the SIO hardware detects a repeated START condition on the I2C-bus before generating a repeated START condition itself, it will use the repeated START as its own and continue with the sending of the slave address. • DATA TRANSFER AFTER LOSS OF ARBITRATION Arbitration may be lost in the master transmitter and master receiver modes. Loss of arbitration is indicated by the following states in I2CSTA; 38H, 68H, and B0H (see Figures 2 and 3). NOTE: In order to exit state 38H, a Timeout, Reset, or external Stop are required. If the STA flag in I2CCON is set by the routines which service these states, then, if the bus is free again, a START condition (state 08H) is transmitted without intervention by the CPU, and a retry of the total serial transfer can commence. • FORCED ACCESS TO THE I2C BUS In some applications, it may be possible for an uncontrolled source to cause a bus hang-up. In such situations, the problem may be caused by interference, temporary interruption of the bus or a temporary short-circuit between SDA and SCL. If an uncontrolled source generates a superfluous START or masks a STOP condition, then the I2C-bus stays busy indefinitely. If the STA flag is set and bus access is not obtained within a reasonable amount of time, then a forced access to the I2C-bus is possible. If the I2C-bus stays idle for a time period equal to the time out period, then the ’64 concludes that no other master is using the bus and sends a START condition. S SLA W A DATA A S BOTH MASTERS CONTINUE WITH SLA TRANSMISSION 08H 18H 28H OTHER MASTER SENDS REPEATED START CONDITION EARLIER SU00975 Figure 6. Simultaneous repeated START conditions from 2 masters 2006 Sep 01 15 Philips Semiconductors Product data sheet Parallel bus to I2C-bus controller PCA9564 TIME OUT STA FLAG SDA LINE SCL LINE START CONDITION SU00976 Figure 7. Forced access to a busy I2C-bus • I2C BUS OBSTRUCTED BY A LOW LEVEL ON SCL OR SDA hang-up occurs if SDA or SCL is pulled LOW by an An uncontrolled source. If the SCL line is obstructed (pulled LOW) by a device on the bus, no further serial transfer is possible, and the SIO hardware cannot resolve this type of problem. When this occurs, the problem must be resolved by the device that is pulling the SCL bus line LOW. When the SCL line stays LOW for a period equal to the time-out value, the ’64 concludes that this is a bus error and behaves in a manner described on page 5 under “Time-out Register”. If the SDA line is obstructed by another device on the bus (e.g., a slave device out of bit synchronization), the problem can be solved by transmitting additional clock pulses on the SCL line (see Figure 8). The SIO hardware sends out nine clock pulses followed by the STOP condition. If the SDA line is released by the slave pulling it LOW, a normal START condition is transmitted by the SIO, state 08H is entered and the serial transfer continues. If the SDA line is not released by the slave pulling it LOW, then the SIO concludes that there is a bus error, loads 70H in I2CSTA, generates an interrupt signal, and releases the SCL and SDA lines. After the I2C-bus microcontroller reads the status register, it needs to send an external reset signal in order to reset the SIO. If a forced bus access occurs or a repeated START condition is transmitted while SDA is obstructed (pulled LOW), the SIO hardware performs the same action as described above. In each case, state 08H is entered after a successful START condition is transmitted and normal serial transfer continues. Note that the CPU is not involved in solving these bus hang-up problems. • BUS ERROR A bus error occurs when a START or STOP condition is present at an illegal position in the format frame. Examples of illegal positions are during the serial transfer of an address byte, a data or an acknowledge bit. The SIO hardware only reacts to a bus error when it is involved in a serial transfer either as a master or an addressed slave. When a bus error is detected, SIO releases the SDA and SCL lines, sets the interrupt flag, and loads the status register with 00H. This status code may be used to vector to a service routine which either attempts the aborted serial transfer again or simply recovers from the error condition as shown in Table 6. The microcontroller must send an external reset signal to reset the SIO. STA FLAG SDA LINE 1 SCL LINE 2 3 4 5 6 7 8 9 STOP CONDITION START CONDITION su01663 Figure 8. Recovering from a bus obstruction caused by a LOW level on SDA 2006 Sep 01 16 Philips Semiconductors Product data sheet Parallel bus to I2C-bus controller PCA9564 I2C-BUS TIMING DIAGRAMS The diagrams (Figures 9 to 12) illustrate typical timing diagrams for the PCA9564 in master/slave functions. SCL SDA INT 7-bit address R/W = 0 START condition from slave receiver Master PCA9564 writes data to slave transmitter. ACK interrupt first-byte ACK interrupt nbyte ACK interrupt STOP condition su01490 Figure 9. Bus timing diagram; master transmitter mode SCL SDA INT 7-bit address R/W = 1 START condition ACK interrupt first-byte ACK interrupt nbyte no ACK STOP condition from slave Master PCA9564 reads data from slave transmitter. from master receiver su01491 Figure 10. Bus timing diagram; master receiver mode 2006 Sep 01 17 Philips Semiconductors Product data sheet Parallel bus to I2C-bus controller PCA9564 SCL SDA INT 7-bit address R/W = 1 START condition ACK interrupt first-byte ACK interrupt nbyte no ACK interrupt STOP condition from slave PCA9564 from master receiver External master receiver reads data from PCA9564. su01492 Figure 11. Bus timing diagram; slave transmitter mode SCL SDA INT 7-bit address R/W = 0 START condition ACK interrupt first-byte ACK interrupt nbyte ACK interrupt interrupt (after STOP) STOP condition from slave PCA9564 Slave PCA9564 is written to by external master transmitter. su01493 Figure 12. Bus timing diagram; slave receiver mode 2006 Sep 01 18 Philips Semiconductors Product data sheet Parallel bus to I2C-bus controller PCA9564 VDD ADDRESS BUS VDD VDD A0 A1 DECODER ALE PCA9564 CE SCL 8 D[0:7] RD WR VDD SDA SLAVE INT RESET 80C51 INT RESET VSS VDD VSS SD00705 Figure 13. Application diagram using the 80C51 2006 Sep 01 19 Philips Semiconductors Product data sheet Parallel bus to I2C-bus controller PCA9564 SPECIFIC APPLICATIONS The PCA9564 is a parallel bus to I2C bus controller that is designed to allow “smart” devices to interface with I2C or SMBus components, where the “smart” device does not have an integrated I2C port and the designer does not want to “bit-bang” the I2C port. The PCA9564 can also be used to add more I2C ports to “smart” devices, provide a higher frequency, lower voltage migration path for the PCF8584 and convert 8 bits of parallel data to a serial bus to avoid running multiple traces across the PC board. PCA8584 MIGRATION PATH The PCA9564 does the same type of parallel to serial conversion as the PCF8584. Although not footprint or code compatible, the PCA9564 provides improvements such as: 1. Operating at 3.3 V and 2.5 V voltage nodes with 5 V tolerant I/Os 2. Allows interface with I2C or SMBus components at speeds up to 400 kHz. 3. Built-in oscillator provides a cost effective solution since the external clock input is no longer required. 4. Parallel data can be exchanged at speeds up to 50 MHz allowing the use of faster processors. ADD I2C-BUS PORT As shown in Figure 14, the PCA9564 converts 8-bits of parallel data into a multiple master capable I2C port for microcontrollers, microprocessors, custom ASICs, DSPs, etc., that need to interface with I2C or SMBus components. SUPPLY VOLTAGE 2.3 – 3.6 V CONTROL SIGNALS MICROCONTROLLER, MICROPROCESSOR, OR ASIC 8-BITS SDA PCA9564 SCL 4.5 – 5.5 V FREQUENCY < 400 kHz PCA9564 OSCILLATOR SDA SCL < 100 kHz PCF8584 SDA SCL SW02108 Figure 14. Adding I2C-bus Port Application CLOCK INPUT SW02110 Figure 16. PCF8584 Migration Path ADD ADDITIONAL I2C-BUS PORTS CONVERT 8 BITS OF PARALLEL DATA INTO I2C-BUS SERIAL DATA STREAM Functioning as a slave transmitter, the PCA9564 can convert 8-bit parallel data into a two-wire I2C data stream as is shown in Figure 17. This would prevent having to run 8 traces across the entire width of the PC board. The PCA9564 can be used to convert 8-bit parallel data into additional multiple master capable I2C port as shown in Figure 15. It is used if the microcontroller, microprocessor, custom ASIC, DSP, etc., already have an I2C port but need one or more additional I2C ports to interface with more I2C or SMBus components or components that cannot be located on the same bus (e.g., 100 kHz and 400 kHz slaves on different buses so that each bus can operate at its maximum potential). SDA SCL MICROCONTROLLER, MICROPROCESSOR, OR ASIC MICROCONTROLLER, MICROPROCESSOR, OR ASIC CONTROL SIGNALS SDA PCA9564 8-BITS SCL CONTROL SIGNALS PCA9564 SDA MASTER SCL 8-BITS SW02111 Figure 17. Converting Parallel to Serial Data Application SW02109 Figure 15. Adding Additional I2C-bus Ports Application 2006 Sep 01 20 Philips Semiconductors Product data sheet Parallel bus to I2C-bus controller PCA9564 ABSOLUTE MAXIMUM RATINGS In accordance with the Absolute Maximum Rating System (IEC 134) SYMBOL VDD VI II IO Ptot PO Tamb Supply voltage Voltage range (any input) DC input current (any input) DC output current (any output) Total power dissipation Power dissipation per output Operating ambient temperature PARAMETER CONDITIONS MIN –0.3 –0.8 –10 –10 — — –40 MAX 4.6 6.01 10 10 300 50 +85 UNIT V V mA mA mW mW °C Tstg Storage temperature –65 +150 °C NOTE: 1. 5.5 V steady state voltage tolerance on inputs and outputs is valid only when the supply voltage is present. 4.6 V steady state voltage tolerance on inputs and outputs when no supply voltage is present. HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take precautions appropriate to handling MOS devices. Advice can be found in Data Handbook IC24 under ”Handling MOS devices”. DC CHARACTERISTICS SYMBOL Supplies VDD IDD VPOR VIL VIH IL CI VIL VIH IOH IOL IL CIO VIL VIH IL IOL CIO Outputs INT IOL IL CO Supply voltage Supply current current VDD = 2.3 V to 3.6 V; Tamb = –40 to +85 °C; unless otherwise specified. PARAMETER CONDITIONS MIN 2.3 standby operating – no load — — — 0 2.0 Input; VI = 0 V or 5.5 V VI = VSS or VDD –1 — 0 2.0 VOH = VDD – 0.4 V VOL = 0.4 V Input; VI = 0 V or 5.5 V VI = VSS or VDD –4.0 4.0 –1 — 0 0.7 VDD Input/output; VI = 0 V or 3.6 V Input/output; VI = 5.5 V VOL = 0.4 V VI = VSS or VDD VOL = 0.4 V VO = 0 or 3.6 V VI = VSS or VDD –1 –1 5.0 — 3.0 –1 — TYP — 0.1 — 1.8 — — — 1.7 — — –7.0 8.0 — 2.4 — — — — 8.5 2.5 — — 2.1 MAX 3.6 3.0 6.0 2.2 0.8 5.51 1 3 0.8 5.51 — — 1 4 0.3 VDD 5.51 1 10 — 4 — 1 4 UNIT V µA mA V V V µA pF V V mA mA µA pF V V µA mA pF mA µA pF Power-on Reset voltage LOW-level input voltage HIGH-level input voltage Leakage current Input capacitance LOW-level input voltage HIGH-level input voltage HIGH-level output current LOW-level output current Leakage current Input/output capacitance LOW-level input voltage HIGH-level input voltage Leakage current current LOW-level output current Input/output capacitance LOW-level output current Leakage current Output capacitance Inputs WR, RD, A0, A1, CE, RESET Inputs/outputs D0 to D7 SDA and SCL NOTE: 1. 5.5 V steady state voltage tolerance on inputs and outputs is valid only when the supply voltage is present. 4.6 V steady state voltage tolerance on inputs and outputs when no supply voltage is present. 2006 Sep 01 21 Philips Semiconductors Product data sheet Parallel bus to I2C-bus controller PCA9564 SDA tF tLOW tR tSU;DAT tF tHD;STA tSP tR tBUF SCL S tHD;STA tHD;DAT tHIGH tSU;STA SR tSU;STO P S SU01755 Figure 18. Definition of timing I2C-BUS TIMING SPECIFICATIONS All the timing limits are valid within the operating supply voltage and ambient temperature range; VDD = 2.5 V ± 0.2 V and 3.3 V ± 0.3 V, Tamb = –40 to +85 °C; and refer to VIL and VIH with an input voltage of VSS to VDD. SYMBOL fSCL tBUF tHD;STA tSU;STA tSU;STO tHD;DAT tVD;ACK tVD;DAT(L) tVD;DAT(H) tSU;DAT tLOW tHIGH tF tR tSP Operating frequency Bus free time between STOP and START conditions Hold time after (repeated) START condition Repeated START condition setup time Setup time for STOP condition Data in hold time Valid time for ACK condition Data out valid time LOW Data out valid time HIGH Data setup time Clock LOW period Clock HIGH period Clock/Data fall time Clock/Data rise time Pulse width of spikes that must be suppressed by the input filters PARAMETER STANDARD-MODE I2C-BUS MIN 0 4.7 4.0 4.7 4.0 0 — — — 250 4.7 4.0 — — — MAX 100 — — — — — 0.6 0.6 0.6 — — — 0.3 1 50 FAST-MODE I2C-BUS MIN 0 1.3 0.6 0.6 0.6 0 — — — 100 1.3 0.6 — — — MAX 400 — — — — — 0.6 0.6 0.6 — — — 0.3 0.3 50 kHz µs µs µs µs ns µs µs µs ns µs µs µs µs ns UNITS 2006 Sep 01 22 Philips Semiconductors Product data sheet Parallel bus to I2C-bus controller PCA9564 START SCL ACK OR READ CYCLE SDA 30% tRES RESET 50% tREC tWRES tRES Dn 50% LED OFF 50% 50% SW02107 Figure 19. Reset timing A0–A1 tAS tAH CE tCS tRW RD tCH tRWD tDD D0–D7 (READ) NOT VALID tDF FLOAT VALID FLOAT tRWD WR tDS tDH D0–D7 (WRITE) VALID SD00711 Figure 20. Bus timing 2006 Sep 01 23 Philips Semiconductors Product data sheet Parallel bus to I2C-bus controller PCA9564 AC CHARACTERISTICS (3.3 VOLT) 1, 2, 3 ÁÁÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁ Á Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁ Á Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ Á Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á LIMITS SYMBOL PARAMETER Min 10 0 0 7 0 0 7 Max — — — — — — — — UNIT Reset Timing (See Figure 19) tWRES tREC tAS tRES 4,5 VCC = 3.3 V ± 0.3 V, Tamb = –40 °C to +85 °C, unless otherwise specified. (See page 25 for 2.5 V.) Reset pulse width Time to reset ns ns ns ns ns ns ns ns ns ns ns ns ns 250 Reset recovery time Bus Timing (See Figure 20, 21) tAH tCS A0–A1 setup time to RD, WR LOW CE setup time to RD, WR LOW WR, RD pulse width (Low time) A0–A1 hold time from RD, WR LOW CE Hold time from RD, WR LOW Data valid after RD and CE LOW tCH tDD tDF tDS tRW — — 7 0 17 17 — — — Data bus floating after RD or CE HIGH Data hold time after WR HIGH Data bus setup time before WR or CE HIGH (write cycle) High time between read and/or write cycles tDH tRWD 12 NOTES: 1. Parameters are valid over specified temperature and voltage range. 2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0 V and 3.0 V with a transition time of 5 ns maximum. All time measurements are referenced at input voltages of 1.5 V and output voltages shown in Figures 20–21. 3. Test conditions for outputs: CL = 50 pF, RL = 500 Ω, except open drain outputs. Test conditions for open drain outputs: CL = 50 pF, RL = 1 kΩ pullup to VDD. 4. Resetting the device while actively communicating on the bus may cause glitches or an errant STOP condition. 5. Upon reset, the full delay will be the sum of tRES and the RC time constant of the SDA and SCL bus. 2006 Sep 01 24 Philips Semiconductors Product data sheet Parallel bus to I2C-bus controller PCA9564 AC CHARACTERISTICS (2.5 VOLT) 1, 2, 3 ÁÁÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁ Á Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁ Á Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ Á Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á LIMITS SYMBOL PARAMETER Min 10 0 0 9 0 0 9 Max — — — — — — — — UNIT Reset Timing (See Figure 19) tWRES tREC tAS tRES 4,5 VCC = 2.5 V ± 0.2 V, Tamb = –40 to +85 °C, unless otherwise specified. (See page 24 for 3.3 V.) Reset pulse width Time to reset ns ns ns ns ns ns ns ns ns ns ns ns ns 250 Reset recovery time Bus Timing (See Figure 20, 21) tAH tCS A0–A1 setup time to RD, WR LOW CE setup time to RD, WR LOW WR, RD pulse width (low time) A0–A hold time from RD, WR LOW CE Hold time from RD, WR LOW Data valid after RD and CE LOW tCH tDD tDF tDS tRW — — 8 0 22 17 — — — Data bus floating after RD or CE HIGH Data hold time after WR HIGH Data bus setup time before WR or CE HIGH (write cycle) High time between read and/or write cycles tDH tRWD 12 NOTES: 1. Parameters are valid over specified temperature and voltage range. 2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0 V and 3.0 V with a transition time of 5 ns maximum. All time measurements are referenced at input voltages of 1.5 V and output voltages shown in Figures 20–21. 3. Test conditions for outputs: CL = 50 pF, RL = 500 Ω, except open drain outputs. Test conditions for open drain outputs: CL = 50 pF, RL = 1 kΩ pullup to VDD. 4. Resetting the device while actively communicating on the bus may cause glitches or an errant STOP condition. 5. Upon reset, the full delay will be the sum of tRES and the RC time constant of the SDA and SCL bus. 2006 Sep 01 25 Philips Semiconductors Product data sheet Parallel bus to I2C-bus controller PCA9564 RD, CE INPUT VI VM GND tDF(LZ) tDD(ZL) VCC VM VOL tDF(HZ) VX tDD(ZH) VY VM GND OUTPUTS ENABLED OUTPUTS FLOATING OUTPUTS ENABLED VM Dn OUTPUT LOW-TO-FLOAT FLOAT-TO-LOW Dn OUTPUT HIGH-TO-FLOAT FLOAT-TO-HIGH VOH VM = 1.5 V VX = VOL + 0.3 V VY = VOH – 0.3 V VOL AND VOH ARE TYPICAL OUTPUT VOLTAGE DROPS THAT OCCUR WITH THE OUTPUT LOAD. SW02113 Figure 21. tDD and tDF times VCC 6.0 V Open RL = 500 Ω PULSE GENERATOR VI D.U.T. RT VO CL 50 pF RL = 500 Ω TEST tPLZ/tPZL tPLH/tPHL S1 6V Open DEFINITIONS RL = Load resistor. CL = Load capacitance includes jig and probe capacitance RT = Termination resistance should be equal to the output impedance ZO of the pulse generators. SW02114 Figure 22. Test circuitry for switching times 2006 Sep 01 26 Philips Semiconductors Product data sheet Parallel bus to I2C-bus controller PCA9564 DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1 2006 Sep 01 27 Philips Semiconductors Product data sheet Parallel bus to I2C-bus controller PCA9564 SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 2006 Sep 01 28 Philips Semiconductors Product data sheet Parallel bus to I2C-bus controller PCA9564 TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 2006 Sep 01 29 Philips Semiconductors Product data sheet Parallel bus to I2C-bus controller PCA9564 HVQFN20: plastic thermal enhanced very thin quad flat package; no leads; 20 terminals; body 5 x 5 x 0.85 mm SOT662-1 2006 Sep 01 30 Philips Semiconductors Product data sheet Parallel bus to I2C-bus controller PCA9564 REVISION HISTORY Rev _4 Date 20060901 Description Product data sheet. Supersedes data of 2004 Jun 25 (9397 750 13272). • Ordering information table on page 2: added whole wafer package option (PCA9564U). • Pin description table on page 3: added table note 1 and its reference at HVQFN pin 7 (VSS). • Section “The Control Register, I2CCON” on page 5: 3rd sentence re-written. _3 _2 _1 20040625 20030402 20030226 Product data sheet (9397 750 13272). Supersedes data of 2003 Apr 02 (9397 750 11353). Product data (9397 750 11353). ECN 853-2419 29715 Dated 24 March 2003. Supersedes Objective data of 2003 Feb 26 (9397 750 11153). Objective data (9397 750 11153). 2006 Sep 01 31 Philips Semiconductors Product data sheet Parallel bus to I2C-bus controller PCA9564 Legal Information Data sheet status Document status [1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet Product status [3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this data sheet was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.semiconductors.philips.com. Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Philips Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Philips Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. inclusion and/or use of Philips Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — Philips Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.semiconductors.philips.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by Philips Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. 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Suitability for use — Philips Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a Philips Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Philips Semiconductors accepts no liability for Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of Koninklijke Philips Electronics N.V. Contact information For additional information please visit: http://www.semiconductors.philips.com For sales office addresses, send an e-mail to: sales.addresses@www.semiconductors.philips.com. Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. For more information, please visit http://www.semiconductors.philips.com. For sales office addresses, email to: sales.addresses@www.semiconductors.philips.com. Date of release: 20060901 Document identifier: PCA9564_4 yyyy mmm dd 32