PCF8576DT

INTEGRATED CIRCUITS DATA SHEET PCF8576D Universal LCD driver for low multiplex rates Product specification Supersedes data of 2004 Oct 07 2004 Dec 22 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates CONTENTS 1 2 3 4 5 6 6.1 6.2 6.3 6.3.1 6.4 6.4.1 6.4.2 6.4.3 6.4.4 6.5 6.5.1 6.5.2 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 6.14 6.15 7 7.1 7.2 7.3 FEATURES GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Power-on reset LCD bias generator LCD voltage selector LCD bias formulae LCD drive mode waveforms Static drive mode 1 : 2 multiplex drive mode 1 : 3 multiplex drive mode 1 : 4 multiplex drive mode Oscillator Internal clock External clock Timing Display register Segment outputs Backplane outputs Display RAM Data pointer Subaddress counter Output bank selector Input bank selector Blinker CHARACTERISTICS OF THE I2C-BUS Bit transfer Start and stop conditions System configuration 7.4 7.5 7.6 7.7 7.8 7.9 7.10 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 16.5 17 18 19 20 PCF8576D Acknowledge PCF8576D I2C-bus controller Input filters I2C-bus protocol Command decoder Display controller Cascaded operation LIMITING VALUES HANDLING DC CHARACTERISTICS AC CHARACTERISTICS BONDING PAD INFORMATION DEVICE PROTECTION TRAY INFORMATION PACKAGE OUTLINE SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS PURCHASE OF PHILIPS I2C COMPONENTS 2004 Dec 22 2 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 1 FEATURES PCF8576D • Single-chip LCD controller/driver • Selectable backplane drive configuration: static or 2/3/4 backplane multiplexing • Selectable display bias configuration: static, 1/2 and 1/3 • Internal LCD bias generation with voltage-follower buffers • 40 segment drives: up to twenty 8-segment numeric characters; up to ten 15-segment alphanumeric characters; or any graphics of up to 160 elements • 40 × 4-bit RAM for display data storage • Auto-incremental display data loading across device subaddress boundaries • Display memory bank switching in static and duplex drive modes • Versatile blinking modes • Independent supplies possible for LCD and logic voltages • Wide power supply range: from 1.8 to 5.5 V • Wide logic LCD supply range: from 2.5 V for low-threshold LCDs and up to 6.5 V for guest-host LCDs and high-threshold (automobile) twisted nematic LCDs • Low power consumption • 400 kHz I2C-bus interface • TTL/CMOS compatible 3 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME PCF8576DH PCF8576DT PCF8576DU/DA PCF8576DH/2(1) PCF8576DT/2(1) PCF8576DU/DA/2(1) PCF8576DU/2DA/2(1) Note 1. These types have improved EMC immunity. TQFP64 TSSOP56 − TQFP64 TSSOP56 − − DESCRIPTION plastic thin shrink small outline package; 56 leads; body width 6.1 mm chips in tray plastic thin shrink small outline package; 56 leads; body width 6.1 mm chips in tray chip with bumps in tray VERSION SOT364-1 − SOT364-1 − − plastic thin quad flat package; 64 leads; body 10 × 10 × 1.0 mm SOT357-1 • Compatible with 4, 8 or 16-bit microprocessors or microcontrollers • May be cascaded for large LCD applications (up to 2560 elements possible) • No external components • Compatible with chip-on-glass technology • Manufactured in silicon gate CMOS process. 2 GENERAL DESCRIPTION The PCF8576D is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD) with low multiplex rates. It generates the drive signals for any static or multiplexed LCD containing up to four backplanes and up to 40 segments and can easily be cascaded for larger LCD applications. The PCF8576D is compatible with most microprocessors/microcontrollers and communicates via a two-line bidirectional I2C-bus. Communication overheads are minimized by a display RAM with auto-incremental addressing, by hardware subaddressing and by display memory switching (static and duplex drive modes). plastic thin quad flat package; 64 leads; body 10 × 10 × 1.0 mm SOT357-1 2004 Dec 22 3 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2004 Dec 22 handbook, full pagewidth 4 Philips Semiconductors Universal LCD driver for low multiplex rates BLOCK DIAGRAM BP0 BP2 BP1 BP3 25 26 27 28 S0 to S39 29 to 32, 34 to 47, 49 to 64, 2 to 7 DISPLAY SEGMENT OUTPUTS VLCD 21 BACKPLANE OUTPUTS LCD VOLTAGE SELECTOR DISPLAY CONTROLLER DISPLAY REGISTER VSS 20 LCD BIAS GENERATOR OUTPUT BANK SELECT AND BLINK CONTROL 4 CLK SYNC 13 CLOCK SELECT 12 AND TIMING BLINKER TIMEBASE PCF8576DH DISPLAY RAM 40 × 4 BIT OSC VDD SCL SDA 15 14 11 10 OSCILLATOR POWER-ON RESET COMMAND DECODER WRITE DATA CONTROL DATA POINTER AND AUTO INCREMENT INPUT FILTERS I2C-BUS CONTROLLER 19 SA0 1, 8, 9, 22 to 24, 33, 48 SUB-ADDRESS COUNTER 16 A0 A1 17 A2 18 MDB075 n.c. Product specification PCF8576D Fig.1 Block diagram for version PCF8576DH. This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2004 Dec 22 BP0 BP2 BP1 BP3 56 VLCD 55 1 2 3 S0 to S39 4 to 43 BACKPLANE OUTPUTS DISPLAY SEGMENT OUTPUTS LCD VOLTAGE SELECTOR DISPLAY CONTROLLER DISPLAY REGISTER VSS 54 LCD BIAS GENERATOR OUTPUT BANK SELECT AND BLINK CONTROL Philips Semiconductors Universal LCD driver for low multiplex rates 5 CLK SYNC 47 CLOCK SELECT 46 AND TIMING BLINKER TIMEBASE PCF8576DT DISPLAY RAM 40 × 4 BIT OSC VDD SCL SDA 49 48 45 44 OSCILLATOR POWER-ON RESET COMMAND DECODER WRITE DATA CONTROL DATA POINTER AND AUTO INCREMENT INPUT FILTERS I2C-BUS CONTROLLER 53 SA0 SUB-ADDRESS COUNTER 50 A0 A1 51 A2 52 Product specification 001aab131 PCF8576D Fig.2 Block diagram for version PCF8576DT. Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 5 PINNING PIN SYMBOL PCF8576DH SDA SCL CLK VDD SYNC OSC A0 to A2 SA0 VSS VLCD BP0, BP2, BP1, BP3 S0 to S39 n.c. 10 11 13 14 12 15 16 to 18 19 20 21 25 to 28 44 45 47 48 46 49 50 to 52 53 54 55 56, 1, 2, 3 PCF8576DT PCF8576DU 1, 58 and 59 2 and 3 5 6 4 7 8 to 10 11 12 13 14 to 17 18 to 57 − PAD PCF8576D DESCRIPTION I2C-bus serial data input/output I2C-bus serial clock input external clock input/output supply voltage cascade synchronization input/output internal oscillator enable input subaddress inputs I2C-bus slave address input; bit 0 logic ground LCD supply voltage LCD backplane outputs LCD segment outputs not connected 29 to 32, 34 to 47, 4 to 43 49 to 64, 2 to 7 1, 8, 9, 22 to 24, 33 and 48 − 2004 Dec 22 6 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8576D 64 S33 63 S32 62 S31 61 S30 60 S29 59 S28 58 S27 57 S26 56 S25 55 S24 54 S23 53 S22 52 S21 51 S20 50 S19 n.c. S34 S35 S36 S37 S38 S39 n.c. n.c. 49 S18 48 n.c. 47 S17 46 S16 45 S15 44 S14 43 S13 42 S12 41 S11 40 S10 39 S9 38 S8 37 S7 36 S6 35 S5 34 S4 33 n.c. S3 32 MDB073 handbook, full pagewidth 1 2 3 4 5 6 7 8 PCF8576DH 9 SDA 10 SCL 11 SYNC 12 CLK 13 VDD 14 OSC 15 A0 16 A1 17 A2 18 SA0 19 VSS 20 VLCD 21 n.c. 22 n.c. 23 n.c. 24 BP0 25 BP2 26 BP1 27 BP3 28 S0 29 S1 30 S2 31 Fig.3 Pin configuration (TQFP64). 2004 Dec 22 7 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8576D BP2 BP1 BP3 S0 S1 S2 S3 S4 S5 1 2 3 4 5 6 7 8 9 56 BP0 55 VLCD 54 VSS 53 SA0 52 A2 51 A1 50 A0 49 OSC 48 VDD 47 CLK 46 SYNC 45 SCL 44 SDA 43 S39 42 S38 41 S37 40 S36 39 S35 38 S34 37 S33 36 S32 35 S31 34 S30 33 S29 32 S28 31 S27 30 S26 29 S25 001aab132 S6 10 S7 11 S8 12 S9 13 S10 14 S11 15 S12 16 S13 17 S14 18 S15 19 S16 20 S17 21 S18 22 S19 23 S20 24 S21 25 S22 26 S23 27 S24 28 PCF8576DT Fig.4 Pin configuration (TSSOP56). 2004 Dec 22 8 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 6 FUNCTIONAL DESCRIPTION PCF8576D The host microprocessor/microcontroller maintains the 2-line I2C-bus communication channel with the PCF8576D. The internal oscillator is enabled by connecting pin OSC to pin VSS. The appropriate biasing voltages for the multiplexed LCD waveforms are generated internally. The only other connections required to complete the system are to the power supplies (VDD, VSS and VLCD) and the LCD panel chosen for the application. The PCF8576D is a versatile peripheral device designed to interface any microprocessor/microcontroller with a wide variety of LCDs. It can directly drive any static or multiplexed LCD containing up to four backplanes and up to 40 segments. The display configurations possible with the PCF8576D depend on the number of active backplane outputs required. A selection of display configurations is shown in Table 1; all of these configurations can be implemented in the typical system shown in Fig.5. Table 1 Selection of display configurations NUMBER OF BACKPLANES 4 3 2 1 SEGMENTS 160 120 80 40 20 15 10 5 7-SEGMENTS NUMERIC DIGITS INDICATOR SYMBOLS 20 15 10 5 14-SEGMENTS ALPHANUMERIC DOT MATRIX CHARACTERS 10 8 5 2 INDICATOR SYMBOLS 20 8 10 12 160 dots (4 × 40) 120 dots (3 × 40) 80 dots (2 × 40) 40 dots (1 × 40) VDD R≤ tr 2CB VDD 6 SDA 1, 58, 59 SCL OSC 2, 3 7 8 A0 9 A1 10 A2 VLCD 13 40 segment drives HOST MICROPROCESSOR/ MICROCONTROLLER LCD PANEL (up to 160 elements) PCF8576DU 4 backplanes 11 12 mdb079 SA0 VSS VSS The resistance of the power supply lines must be kept to a minimum. For chip-on-glass applications, due to Indium Tin Oxide (ITO) track resistance, each supply line must be routed separately between the chip and the connector. Fig.5 Typical system configuration. 2004 Dec 22 9 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 6.1 Power-on reset 6.3.1 LCD BIAS FORMULAE 1 Bias is calculated by the formula -----------1+a For 1⁄2 bias, a = 1; for 1⁄3 bias, a = 2. PCF8576D At power-on the PCF8576D resets to the following starting conditions: • All backplane outputs are set to VLCD • All segment outputs are set to VLCD • Drive mode ‘1 : 4 multiplex with 1⁄3 bias’ is selected • Blinking is switched off • Input and output bank selectors are reset (as defined in Table 4) • The I2C-bus interface is initialized • The data pointer and the subaddress counter are cleared • Display is disabled. Data transfers on the I2C-bus should be avoided for 1 ms following power-on to allow completion of the reset action. 6.2 LCD bias generator The LCD on voltage (Von) is calculated by the formula V op 2 1 1 - --- + ( N – 1 ) ⋅  ------------ 1 + a N -----------------------------------------------------------N The LCD off voltage (Voff) is calculated by the formula V op a – ( 2a + N ) --------------------------------2 N ⋅ (1 + a) 2 where Vop is the resultant voltage at the LCD segment; N is the LCD drive mode: 1 = static, 2 = 1 : 2, 3 = 1 : 3, 4 = 1 : 4. Discrimination is the ratio of Von to Voff, and is determined Fractional LCD biasing voltages are obtained from an internal voltage divider comprising three resistors connected in series between VLCD and VSS. The middle resistor can be bypassed to provide a 1⁄2 bias voltage level for the 1 : 2 multiplex configuration. The LCD voltage can be temperature compensated externally via the supply to pin VLCD. 6.3 LCD voltage selector V on by the formula --------- = V off (a + 1) + (N – 1) -------------------------------------------2 (a – 1) + (N – 1) 2 Using the above formula, the discrimination for an LCD drive mode of 1 : 3 with 1⁄2 bias is 21 is ---------- = 1.528. 3 The advantage of these LCD drive modes is a reduction of the LCD full-scale voltage VLCD as follows: 1 : 3 multiplex (1⁄2 bias): VLCD = 6 × V off(rms) = 2.449 Voff(rms) 3 = 1.732, and the discrimination for an LCD drive mode of 1 : 4 with 1⁄2 bias The LCD voltage selector co-ordinates the multiplexing of the LCD in accordance with the selected LCD drive configuration. The operation of the voltage selector is controlled by MODE SET commands from the command decoder. The biasing configurations that apply to the preferred modes of operation, together with the biasing characteristics as functions of VLCD and the resulting Discrimination ratios (D), are given in Table 2. A practical value for VLCD is determined by equating Voff(rms) with a defined LCD threshold voltage (Vth), typically when the LCD exhibits approximately 10% contrast. In the static drive mode a suitable choice is VLCD > 3Vth. Multiplex drive modes of 1 : 3 and 1 : 4 with 1⁄2 bias are possible but the discrimination and hence the contrast ratios are smaller. 1 : 4 multiplex (1⁄2 bias): VLCD = (4 × 3) --------------------3 = 2.309 Voff(rms) These compare with VLCD = 3 Voff(rms) when 1⁄3 bias is used. 2004 Dec 22 10 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates Table 2 Discrimination ratios NUMBER OF LCD DRIVE MODE BACKPLANES static 1 : 2 multiplex 1 : 2 multiplex 1 : 3 multiplex 1 : 4 multiplex 6.4 6.4.1 1 2 2 3 4 LEVELS 2 3 4 4 4 LCD BIAS CONFIGURATION static 1⁄ 1⁄ 1⁄ 1⁄ 2 3 3 3 PCF8576D V off(rms) -------------------V lcd 0 0.354 0.333 0.333 0.333 V on(rms) -------------------V lcd 1 0.791 0.745 0.638 0.577 V on(rms) D = -------------------V off(rms) ∞ 2.236 2.236 1.915 1.732 LCD drive mode waveforms STATIC DRIVE MODE The static LCD drive mode is used when a single backplane is provided in the LCD. The backplane (BPn) and segment drive (Sn) waveforms for this mode are shown in Fig.4. handbook, full pagewidth Tframe VLCD BP0 VSS VLCD Sn VSS VLCD Sn + 1 VSS VLCD (a) Waveforms at driver. state 1 (on) state 2 (off) LCD segments state 1 0V −VLCD VLCD state 2 0V −VLCD (b) Resultant waveforms at LCD segment. MGL745 V on(rms) = V LCD V state2(t) = V S n+1 (t) – V BP0(t) V off(rms) = 0 V Fig.6 Static drive mode waveforms. 2004 Dec 22 11 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 6.4.2 1 : 2 MULTIPLEX DRIVE MODE PCF8576D The 1 : 2 multiplex drive mode is used when two backplanes are provided in the LCD. This mode allows fractional LCD bias voltages of 1⁄2 bias or 1⁄3 bias as shown in Figs 7 and 8. handbook, full pagewidth Tframe VLCD BP0 VLCD/2 VSS state 1 VLCD BP1 VLCD/2 VSS VLCD Sn VSS VLCD Sn + 1 VSS (a) Waveforms at driver. VLCD VLCD/2 state 1 0V −VLCD/2 −VLCD VLCD VLCD/2 state 2 0V −VLCD/2 −VLCD (b) Resultant waveforms at LCD segment. MGL746 LCD segments state 2 V state1(t) = V S (t) – V BP0(t) n V on(rms) = 0.791V LCD V state2(t) = V S (t) – V BP1(t) n V off(rms) = 0.354V LCD Fig.7 Waveforms for the 1 : 2 multiplex drive mode with 1⁄2 bias. 2004 Dec 22 12 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8576D handbook, full pagewidth Tframe VLCD 2VLCD/3 VLCD/3 VSS VLCD BP1 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS (a) Waveforms at driver. VLCD 2VLCD/3 VLCD/3 state 1 0V −VLCD/3 −2VLCD/3 −VLCD VLCD 2VLCD/3 VLCD/3 state 2 0V −VLCD/3 −2VLCD/3 −VLCD (b) Resultant waveforms at LCD segment. MGL747 LCD segments BP0 state 1 state 2 Sn Sn + 1 V state1(t) = V S (t) – V BP0(t) n V on(rms) = 0.745V LCD V state2(t) = V S (t) – V BP1(t) n V off(rms) = 0.333V LCD Fig.8 Waveforms for the 1 : 2 multiplex drive mode with 1⁄3 bias. 2004 Dec 22 13 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 6.4.3 1 : 3 MULTIPLEX DRIVE MODE PCF8576D When three backplanes are provided in the LCD, the 1 : 3 multiplex drive mode applies (see Fig.9). handbook, full pagewidth Tframe VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS (a) Waveforms at driver. VLCD 2VLCD/3 VLCD/3 0V −VLCD/3 −2VLCD/3 −VLCD VLCD 2VLCD/3 VLCD/3 state 2 0V −VLCD/3 −2VLCD/3 −VLCD (b) Resultant waveforms at LCD segment. state 1 state 2 LCD segments BP0 BP1 BP2 Sn Sn + 1 Sn + 2 state 1 MGL748 V state1(t) = V S (t) – V BP0(t) n V on(rms) = 0.638V LCD V state2(t) = V S (t) – V BP1(t) n V off(rms) = 0.333V LCD Fig.9 Waveforms for the 1 : 3 multiplex drive mode. 2004 Dec 22 14 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 6.4.4 1 : 4 MULTIPLEX DRIVE MODE PCF8576D When four backplanes are provided in the LCD, the 1 : 4 multiplex drive mode applies (see Fig.10). handbook, full pagewidth Tframe VLCD 2VLCD/3 VLCD/3 VSS VLCD state 1 state 2 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS (a) Waveforms at driver. VLCD 2VLCD/3 VLCD/3 0V −VLCD/3 −2VLCD/3 −VLCD VLCD 2VLCD/3 VLCD/3 LCD segments BP0 BP1 BP2 BP3 Sn Sn + 1 Sn + 2 Sn + 3 state 1 V state1(t) = V S (t) – V BP0(t) n V on(rms) = 0.577V LCD V state2(t) = V S (t) – V BP1(t) n state 2 0V −VLCD/3 −2VLCD/3 −VLCD (b) Resultant waveforms at LCD segment. V off(rms) = 0.333V LCD MGL749 Fig.10 Waveforms for the 1 : 4 multiplex drive mode. 2004 Dec 22 15 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 6.5 6.5.1 Oscillator INTERNAL CLOCK 6.9 Backplane outputs PCF8576D The internal logic of the PCF8576D and its LCD drive signals are timed either by its internal oscillator or by an external clock. The internal oscillator is enabled by connecting pin OSC to pin VSS. If the internal oscillator is used, the output from pin CLK can be used as the clock signal for several PCF8576Ds in the system that are connected in cascade. After power-up, pin SDA must be HIGH to guarantee that the clock starts. 6.5.2 EXTERNAL CLOCK Pin CLK is enabled as an external clock input by connecting pin OSC to VDD. The LCD frame signal frequency is determined by the clock frequency (fCLK). A clock signal must always be supplied to the device; removing the clock may freeze the LCD in a DC state. 6.6 Timing The LCD drive section includes four backplane outputs BP0 to BP3 which should be connected directly to the LCD. The backplane output signals are generated in accordance with the selected LCD drive mode. If less than four backplane outputs are required, the unused outputs can be left open-circuit. In the 1 : 3 multiplex drive mode, BP3 carries the same signal as BP1, therefore these two adjacent outputs can be tied together to give enhanced drive capabilities. In the 1 : 2 multiplex drive mode, BP0 and BP2, BP1 and BP3 respectively carry the same signals and may also be paired to increase the drive capabilities. In the static drive mode the same signal is carried by all four backplane outputs and they can be connected in parallel for very high drive requirements. 6.10 Display RAM The PCF8576D timing controls the internal data flow of the device. This includes the transfer of display data from the display RAM to the display segment outputs. In cascaded applications, the correct timing relationship between each PCF8576D in the system is maintained by the synchronization signal at pin SYNC. The timing also generates the LCD frame signal whose frequency is derived from the clock frequency. The frame signal frequency is a fixed division of the clock frequency from either the internal or an external clock. f CLK Frame frequency = --------24 6.7 Display register The display RAM is a static 40 × 4-bit RAM which stores LCD data. A logic 1 in the RAM bit-map indicates the on-state of the corresponding LCD segment; similarly, a logic 0 indicates the off-state. There is a one-to-one correspondence between the RAM addresses and the segment outputs, and between the individual bits of a RAM word and the backplane outputs. The first RAM column corresponds to the 40 segments operated with respect to backplane BP0 (see Fig.11). In multiplexed LCD applications the segment data of the second, third and fourth column of the display RAM are time-multiplexed with BP1, BP2 and BP3 respectively. When display data is transmitted to the PCF8576D, the display bytes received are stored in the display RAM in accordance with the selected LCD drive mode. The data is stored as it arrives and does not wait for an acknowledge cycle as with the commands. Depending on the current multiplex drive mode, data is stored singularly, in pairs, triplets or quadruplets. For example, in the 1 : 2 mode, the RAM data is stored every second bit. To illustrate the filling order, an example of a 7-segment numeric display showing all drive modes is given in Fig.12; the RAM filling organization depicted applies equally to other LCD types. With reference to Fig.12, in the static drive mode, the eight transmitted data bits are placed in bit 0 of eight successive display RAM addresses. In the 1 : 2 mode, the eight transmitted data bits are placed in bits 0 and 1 of four successive display RAM addresses. In the 1 : 3 mode, these bits are placed in bits 0, 1 and 2 of three successive addresses, with bit 2 of the third address left unchanged. This last bit may, if necessary, be controlled by an additional transfer to this address but care should be taken to avoid overriding adjacent data because full bytes are always transmitted. 16 The display latch holds the display data while the corresponding multiplex signals are generated. There is a one-to-one relationship between the data in the display latch, the LCD segment outputs and each column of the display RAM. 6.8 Segment outputs The LCD drive section includes 40 segment outputs S0 to S39 which should be connected directly to the LCD. The segment output signals are generated in accordance with the multiplexed backplane signals and with data residing in the display latch. When less than 40 segment outputs are required, the unused segment outputs should be left open-circuit. 2004 Dec 22 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates In the 1 : 4 mode, the eight transmitted data bits are placed in bits 0, 1, 2 and 3 of two successive display RAM addresses. 6.11 Data pointer PCF8576D arriving data byte is stored at the display RAM address indicated by the data pointer in accordance with the filling order shown in Fig.12. After each byte is stored, the contents of the data pointer are automatically incremented by a value dependent on the selected LCD drive mode: eight (static drive mode), four (1 : 2 mode), three (1 : 3 mode) or two (1 : 4 mode). If an I2C-bus data access is terminated early then the state of the data pointer will be unknown. The data pointer should be re-written prior to further RAM accesses. The addressing mechanism for the display RAM is realized using the data pointer. This allows the loading of an individual display data byte, or a series of display data bytes, into any location of the display RAM. The sequence commences with the initialization of the data pointer by the LOAD DATA POINTER command. Following this, an display RAM addresses (rows) / segment outputs (S) 0 0 display RAM bits 1 (columns) / backplane outputs 2 (BP) 3 MBE525 1 2 3 4 35 36 37 38 39 Fig.11 Display RAM bit-map showing direct relationship between display RAM addresses and segment outputs, and between bits in a RAM word and backplane outputs. 6.12 Subaddress counter 6.13 Output bank selector The storage of display data is determined by the contents of the subaddress counter. Storage is allowed to take place only when the contents of the subaddress counter agree with the hardware subaddress applied to A0, A1 and A2. The subaddress counter value is defined by the DEVICE SELECT command. If the contents of the subaddress counter and the hardware subaddress do not agree then data storage is inhibited but the data pointer is incremented as if data storage had taken place. The subaddress counter is also incremented when the data pointer overflows. The storage arrangements described lead to extremely efficient data loading in cascaded applications. When a series of display bytes are sent to the display RAM, automatic wrap-over to the next PCF8576D occurs when the last RAM address is exceeded. Subaddressing across device boundaries is successful even if the change to the next device in the cascade occurs within a transmitted character (such as during the 14th display data byte transmitted in 1 : 3 mode). The hardware subaddress should not be changed whilst the device is being accessed on the I2C-bus interface. The output bank selector selects one of the four bits per display RAM address for transfer to the display latch. The actual bit chosen depends on the selected LCD drive mode and on the instant in the multiplex sequence. In 1 : 4 mode, all RAM addresses of bit 0 are selected, these are followed by the contents of bit 1, bit 2 and then bit 3. Similarly in 1 : 3 mode, bits 0, 1 and 2 are selected sequentially. In 1 : 2 mode, bits 0 and 1 are selected and, in static mode, bit 0 is selected. Signal SYNC will reset these sequences to the following starting points; bit 3 for 1 : 4 mode, bit 2 for 1 : 3 mode, bit 1 for 1 : 2 mode and bit 0 for static mode. The PCF8576D includes a RAM bank switching feature in the static and 1 : 2 drive modes. In the static drive mode, the BANK SELECT command may request the contents of bit 2 to be selected for display instead of the contents of bit 0. In 1 : 2 mode, the contents of bits 2 and 3 may be selected instead of bits 0 and 1. This allows display information to be prepared in an alternative bank and then selected for display when it is assembled. 2004 Dec 22 17 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 6.14 Input bank selector PCF8576D An additional feature allows an arbitrary selection of LCD segments to be blinked in the static and 1 : 2 drive modes. This is implemented without any communication overheads by the output bank selector which alternates the displayed data between the data in the display RAM bank and the data in an alternative RAM bank at the blink frequency. This mode can also be implemented by the BLINK command. In the 1 : 3 and 1 : 4 drive modes, where no alternative RAM bank is available, groups of LCD segments can be blinked by selectively changing the display RAM data at fixed time intervals. The entire display can be blinked at a frequency other than the nominal blink frequency by sequentially resetting and setting the display enable bit E at the required rate using the MODE SET command. The input bank selector loads display data into the display RAM in accordance with the selected LCD drive configuration. The BANK SELECT command can be used to load display data in bit 2 in static drive mode or in bits 2 and 3 in 1 : 2 mode. The input bank selector functions are independent of the output bank selector. 6.15 Blinker The PCF8576D has a very versatile display blinking capability. The whole display can blink at a frequency selected by the BLINK command. Each blink frequency is a multiple integer value of the clock frequency; the ratio between the clock frequency and blink frequency depends on the blink mode selected, as shown in Table 3. Table 3 Blinking frequencies BLINK MODE NORMAL OPERATING MODE RATIO − f CLK ---------768 f CLK -----------1536 f CLK -----------3072 NOMINAL BLINK FREQUENCY blinking off 2 Hz 1 Hz 0.5 Hz Off 2 Hz 1 Hz 0.5 Hz Note 1. Blink modes 0.5, 1 and 2 Hz, and nominal blink frequencies 0.5, 1 and 2 Hz correspond to an oscillator frequency (fCLK) of 1536 Hz at pin CLK. The oscillator frequency range is given in Chapter 11. 2004 Dec 22 18 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2004 Dec 22 drive mode LCD segments a f g e d Sn 6 c b Sn Sn Sn 7 DP 1 BP0 Philips Semiconductors Universal LCD driver for low multiplex rates LCD backplanes display RAM filling order transmitted display byte Sn Sn Sn 2 3 4 5 n bit/ BP 0 1 2 3 c x x x n1 b x x x n2 a x x x n3 f x x x n4 g x x x n5 e x x x n6 d x x x n7 MSB DP x x x cbaf LSB g e d DP static Sn Sn BP0 a f g b n bit/ BP BP1 c n1 f g x x n2 e c x x n3 d DP x x MSB abf LSB g e c d DP 1:2 Sn 1 multiplex Sn Sn Sn 2 3 e d DP 0 1 2 3 a b x x handbook, full pagewidth 19 1:3 multiplex 1:4 multiplex 1 2 f a b g e d c DP Sn BP0 n bit/ BP BP1 BP2 n1 a d g x n2 f e x x MSB b DP c a d g f LSB e Sn 0 1 2 3 b DP c x Sn f a b g e c d DP BP1 BP3 BP0 BP2 n bit/ BP 0 1 2 3 a c b DP n1 f e g d MSB a c b DP f LSB egd Sn 1 Product specification PCF8576D MGL751 x = data bit unchanged. Fig.12 Relationships between LCD layout, drive mode, display RAM filling order and display data transmitted over the I2C-bus. Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 7 CHARACTERISTICS OF THE I2C-BUS PCF8576D acknowledge clock pulse so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition (see Fig.16). 7.5 PCF8576D I2C-bus controller The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. In chip-on-glass applications where the track resistance from the SDA pad to the system SDA line can be significant, a potential divider is generated by the bus pull-up resistor and the Indium Tin Oxide (ITO) track resistance. It is therefore necessary to minimize the track resistance from the SDA pad to the system SDA line to guarantee a valid LOW-level during the acknowledge cycle. 7.1 Bit transfer The PCF8576D acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or transmit data to an I2C-bus master receiver. The only data output from the PCF8576D are the acknowledge signals of the selected devices. Device selection depends on the I2C-bus slave address, on the transferred command data and on the hardware subaddress. In single device applications, the hardware subaddress inputs A0, A1 and A2 are normally tied to VSS which defines the hardware subaddress 0. In multiple device applications A0, A1 and A2 are tied to VSS or VDD in accordance with a binary coding scheme such that no two devices with a common I2C-bus slave address have the same hardware subaddress. 7.6 Input filters One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal (see Fig.13). 7.2 Start and stop conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P), (see Fig.14). 7.3 System configuration To enhance noise immunity in electrically adverse environments, RC low-pass filters are provided on the SDA and SCL lines. 7.7 I2C-bus protocol A device generating a message is a ‘transmitter’, a device receiving a message is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’, (see Fig.15). 7.4 Acknowledge The number of data bytes that can be transferred from transmitter to receiver between the START and STOP conditions is unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH-level signal on the bus that is asserted by the transmitter during which time the master generates an extra acknowledge related clock pulse. An addressed slave receiver must generate an acknowledge after receiving each byte. Also a master receiver must generate an acknowledge after receiving each byte that has been clocked out of the slave transmitter. The acknowledging device must pull-down the SDA line during the Two I2C-bus slave addresses (01110000 and 01110010) are reserved for the PCF8576D. The least significant bit of the slave address that a PCF8576D will respond to is defined by the level tied to its SA0 input. The PCF8576D is a write-only device and will not respond to a read access. Having two reserved slave addresses allows the following on the same I2C-bus: • Up to 16 PCF8576Ds for very large LCD applications • The use of two types of LCD multiplex drive. The I2C-bus protocol is shown in Fig.17. The sequence is initiated with a START condition (S) from the I2C-bus master which is followed by one of two possible PCF8576D slave addresses available. All PCF8576Ds whose SA0 inputs correspond to bit 0 of the slave address respond by asserting an acknowledge in parallel. This I2C-bus transfer is ignored by all PCF8576Ds whose SA0 inputs are set to the alternative level. 20 2004 Dec 22 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates After an acknowledgement, one or more command bytes follow that define the status of each addressed PCF8576D. The last command byte sent is identified by resetting its most significant bit, continuation bit C, (see Fig.18). The command bytes are also acknowledged by all addressed PCF8576Ds on the bus. After the last command byte, one or more display data bytes may follow. Display data bytes are stored in the display RAM at the address specified by the data pointer and the subaddress counter. Both data pointer and subaddress counter are automatically updated and the data directed to the intended PCF8576D device. An acknowledgement after each byte is asserted only by the PCF8576Ds that are addressed via address lines A0, PCF8576D A1 and A2. After the last display byte, the I2C-bus master asserts a STOP condition (P). Alternately a START may be asserted to RESTART an I2C-bus access. 7.8 Command decoder The command decoder identifies command bytes that arrive on the I2C-bus. All available commands carry a continuation bit C in their most significant bit position as shown in Fig.18. When this bit is set, it indicates that the next byte of the transfer to arrive will also represent a command. If this bit is reset, it indicates that the command byte is the last in the transfer. Further bytes will be regarded as display data. The five commands available to the PCF8576D are defined in Table 4. SDA SCL data line stable; data valid change of data allowed MBA607 Fig.13 Bit transfer. handbook, full pagewidth SDA SDA SCL S START condition P STOP condition SCL MBC622 Fig.14 Definition of START and STOP conditions. 2004 Dec 22 21 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8576D MASTER TRANSMITTER/ RECEIVER SDA SCL SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER MGA807 Fig.15 System configuration. handbook, full pagewidth DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER S START condition clock pulse for acknowledgement MBC602 1 2 8 9 Fig.16 Acknowledgement on the I2C-bus. k, full pagewidth R/W slave address S acknowledge by all addressed PCF8576Ds acknowledge by A0, A1 and A2 selected PCF8576D only S 011100A0AC 0 1 byte COMMAND A DISPLAY DATA A P n ≥ 1 byte(s) n ≥ 0 byte(s) update data pointers and if necessary, subaddress counter MDB078 Fig.17 I2C-bus protocol. 2004 Dec 22 22 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8576D MSB C REST OF OPCODE LSB MSA833 C = 0 = last command. C = 1 = commands continue. Fig.18 Format of command byte. Table 4 Definition of PCF8576D commands OPCODE C 1 0 (1) COMMAND MODE SET OPTIONS B M1 M0 Table 5 Table 6 Table 7 DESCRIPTION Defines LCD drive mode. Defines LCD bias configuration. Defines display status; the possibility to disable the display allows implementation of blinking under external control. Six bits of immediate data, bits P5 to P0, are transferred to the data pointer to define one of forty display RAM addresses. Three bits of immediate data, bits A0 to A2, are transferred to the subaddress counter to define one of eight hardware subaddresses. Defines input bank selection (storage of arriving display data). Defines output bank selection (retrieval of LCD display data); the BANK SELECT command has no effect in 1 : 3 and 1 : 4 multiplex drive modes. Defines the blink frequency. Selects the blink mode; normal operation with frequency set by BF1, BF0 or blinking by alternating display RAM banks; alternating RAM bank blinking does not apply in 1 : 3 and 1 : 4 multiplex drive modes. E LOAD DATA C POINTER 0 P5 P4 P3 P2 P1 P0 Table 8 DEVICE SELECT C 1 1 0 0 A2 A1 A0 Table 9 BANK SELECT C 1 1 1 1 0 I O Table 10 Table 11 BLINK C 1 1 1 0 A BF1 BF0 Table 12 Table 13 Note 1. Not used. 2004 Dec 22 23 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates Table 5 Mode set option 1 LCD DRIVE MODE DRIVE MODE Static 1:2 1:3 1:4 Table 6 1⁄ 1⁄ PCF8576D Table 12 Blink option 1 BITS BLINK FREQUENCY BITS M0 Off 0 0 1 1 1 0 1 0 Table 13 Blink option 2 BLINK MODE BIT B Normal blinking Alternate RAM bank blinking Note 1. Normal blinking is assumed when LCD multiplex drive modes 1 : 3 or 1 : 4 are selected. 7.9 Display controller 0 1 BIT A 2 Hz 1 Hz 0.5 Hz BF1 0 1 0 1 BF0 BACKPLANE BP0 BP0, BP1 BP0, BP1, BP2 BP0, BP1, BP2, BP3 0 1 1 0 M1 Mode set option 2 LCD BIAS 3 bias 0 1 Mode set option 3 DISPLAY STATUS BIT E 0 1 Load data pointer option 1 BITS 2 bias Table 7 Disabled (blank) Enabled Table 8 DESCRIPTION The display controller executes the commands identified by the command decoder. It contains the device’s status registers and co-ordinates their effects. The display controller is also responsible for loading display data into the display RAM in the correct filling order. 7.10 Cascaded operation 6 bit binary value of 0 to 39 P5 P4 P3 P2 P1 P0 Table 9 Device select option 1 BITS A2 A1 A0 In large display configurations, up to 16 PCF8576Ds can be differentiated on the same I2C-bus by using the 3-bit hardware subaddresses (A0, A1 and A2) and the programmable I2C-bus slave address (SA0). PCF8576Ds connected in cascade are synchronized to allow the backplane signals from only one device in the cascade to be shared. This arrangement is cost-effective in large LCD applications since the backplane outputs of only one device need to be through-plated to the backplane electrodes of the display. The other cascaded PCF8576Ds contribute additional segment outputs but their backplane outputs are left open-circuit (see Fig.19). DESCRIPTION 3 bit binary value of 0 to 7 Table 10 Bank select option 1 (input) MODE BIT I STATIC RAM bit 0 RAM bit 2 1:2 RAM bits 0 and 1 0 RAM bits 2 and 3 1 Table 11 Bank select option 2 (output) MODE BIT O STATIC RAM bit 0 RAM bit 2 1:2 RAM bits 0 and 1 0 RAM bits 2 and 3 1 2004 Dec 22 24 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates All PCF8576Ds connected in cascade are correctly synchronized by the SYNC signal. This synchronization is guaranteed after the Power-on reset. The only time that SYNC is likely to be needed is if synchronization is lost accidentally, for example, by noise in adverse electrical environments, or if the LCD multiplex drive mode is changed in an application using several cascaded PCF8576Ds, as the drive mode cannot be changed on all of the cascaded devices simultaneously. SYNC can be either an input or an output signal; a SYNC output is implemented as an open-drain driver with an internal pull-up resistor. A PCF8576D asserts SYNC at the start of its last active backplane signal, and monitors the SYNC line at all other times. If cascade synchronization is lost, it will be restored by the first PCF8576D to assert SYNC. The timing relationship between the backplane waveforms and the SYNC signal for each LCD drive mode is shown in Fig.20. Table 14 SYNC contact resistance NUMBER OF DEVICES 2 3 to 5 6 to 10 10 to 16 PCF8576D MAXIMUM CONTACT RESISTANCE 6000 Ω 2200 Ω 1200 Ω 700 Ω The contact resistance between the SYNC input/output on each cascaded device must be controlled. If the resistance is too high, the device will not be able to synchronize properly; this is particularly applicable to chip-on-glass applications. The maximum SYNC contact resistance allowed for the number of devices in cascade is given in Table 14. handbook, full pagewidth VDD 6 SDA 1, 58, 59 SCL 2, 3 SYNC CLK 4 VLCD 13 40 segment drives LCD PANEL (up to 2560 elements) PCF8576DU BP0 to BP3 (open-circuit) 5 OSC 7 8 A0 VLCD VDD R≤ tr 2CB 9 10 11 12 A1 A2 SA0 VSS V DD V LCD 40 segment drives HOST MICROPROCESSOR/ MICROCONTROLLER 6 13 SDA 1, 58, 59 SCL 2, 3 SYNC 4 PCF8576DU CLK 5 OSC 7 8 9 A1 10 A2 11 12 4 backplanes BP0 to BP3 MDB077 VSS A0 SA0 VSS Fig.19 Cascaded PCF8576D configuration. 2004 Dec 22 25 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8576D handbook, full pagewidth 1 Tframe = f frame BP0 SYNC (a) static drive mode. BP1 (1/2 bias) BP1 (1/3 bias) SYNC (b) 1 : 2 multiplex drive mode. BP2 SYNC (c) 1 : 3 multiplex drive mode. BP3 SYNC MGL755 (d) 1 : 4 multiplex drive mode. Fig.20 Synchronization of the cascade for the various PCF8576D drive modes. 2004 Dec 22 26 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 8 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VDD VLCD Vi1 Vi2 VO II IO IDD ISS ILCD Ptot PO Tstg 9 supply voltage LCD supply voltage input voltage CLK, SYNC, SA0, OSC, A0 to A2 input voltage SCL and SDA output voltage S0 to S39, BP0 to BP3 DC input current DC output current VDD current VSS current VLCD current total power dissipation power dissipation per output storage temperature PARAMETER MIN. −0.5 VSS − 0.5 VSS − 0.5 VSS − 0.5 VSS − 0.5 −10 −10 −50 −50 −50 − − −65 PCF8576D MAX. +6.5 +7.5 VDD + 0.5 +6.5 VDD + 0.5 +10 +10 +50 +50 +50 400 100 +150 V V V V V UNIT mA mA mA mA mA mW mW °C HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices (see “Handling MOS Devices” ). 2004 Dec 22 27 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8576D 10 DC CHARACTERISTICS VDD = 1.8 to 5.5 V; VSS = 0 V; VLCD = 2.5 to 6.5 V; Tamb = −40 to +85 °C; unless otherwise specified. SYMBOL Supplies VDD VLCD IDD ILCD Logic VIL VIH VIL2 VIH2 IOL1 IOH1 IOL2 IL1 IL2 VPOR CI VBP VS RBP RS Notes 1. VLCD > 3 V for 1⁄3 bias. 2. LCD outputs are open-circuit; inputs at VSS or VDD; external clock with 50% duty factor; I2C-bus inactive. 3. When tested, I2C pins SCL and SDA have no diode to VDD and may be driven according to the Vi2 limiting values given in Chapter 8. Also see Fig.24. 4. Periodically sampled, not 100% tested. 5. Outputs measured one at a time. LOW-level input voltage CLK, SYNC, OSC, A0 to A2 and SA0 HIGH-level input voltage CLK, SYNC, OSC, A0 to A2 and SA0 LOW-level input voltage SCL, SDA HIGH-level input voltage SCL, SDA HIGH-level output current CLK LOW-level output current SDA leakage current CLK, SCL, SDA, A0 to A2 and SA0 leakage current OSC power-on reset voltage level input capacitance note 4 note 3 VOH = 4.6 V; VDD = 5 V VOL = 0.4 V; VDD = 5 V VI = VDD or VSS VI = VDD LOW-level output current CLK, SYNC VOL = 0.4 V; VDD = 5 V VSS 0.7VDD VSS 0.7VDD 1 −1 3 −1 −1 1.0 − −100 −100 note 5; VLCD = 5 V note 5; VLCD = 5 V − − − − − − − − − − − 1.3 − − − 1.5 6.0 0.3VDD VDD 0.3VDD VDD − − − +1 +1 1.6 7 V V V V mA mA mA µA µA V pF supply voltage LCD supply voltage supply current LCD supply current note 1 note 2; fCLK = 1536 Hz note 2; fCLK = 1536 Hz 1.8 2.5 − − − − 8 24 5.5 6.5 20 60 V V µA µA PARAMETER CONDITIONS MIN. TYP. MAX. UNIT LCD outputs DC voltage tolerance BP0 to BP3 DC voltage tolerance S0 to S39 output resistance BP0 to BP3 output resistance S0 to S39 +100 +100 − − mV mV kΩ kΩ 2004 Dec 22 28 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8576D 11 AC CHARACTERISTICS VDD = 1.8 to 5.5 V; VSS = 0 V; VLCD = 2.5 to 6.5 V; Tamb = −40 to +85 °C; unless otherwise specified. SYMBOL fCLK tCLKH tCLKL tPD(SYNC) tSYNCL tPD(LCD) PARAMETER oscillator frequency input CLK HIGH time input CLK LOW time SYNC propagation delay SYNC LOW time driver delays with test loads VLCD = 5 V; note 2 CONDITIONS note 1 MIN. 960 60 60 − 1 − − 1.3 0.6 0.6 1.3 0.6 fSCL = 400 kHz fSCL < 125 kHz tf CB tSU;DAT tHD;DAT tSU;STO tSW Notes 1. Typical output duty factor: 50% measured at the CLK output pin. 2. Not tested in production. 3. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD. SCL and SDA fall time capacitive bus line load data set-up time data hold time set-up time for STOP condition tolerable spike width on bus − − − − 100 0 0.6 − TYP. 1890 − − 30 − − − − − − − − − − − − − − − − MAX. 2640 − − − − 30 UNIT Hz µs µs ns µs µs Timing characteristics: I2C-bus; note 3 fSCL tBUF tHD;STA tSU;STA tLOW tHIGH tr SCL clock frequency bus free time between a STOP and START START condition hold time set-up time for a repeated START condition SCL LOW time SCL HIGH time SCL and SDA rise time 400 − − − − − 0.3 1.0 0.3 400 − − − 50 kHz µs µs µs µs µs µs µs µs pF ns ns µs ns handbook, full pagewidth SYNC 6.8 Ω (2%) 3.3 k Ω (2%) VDD CLK 0.5VDD SDA, SCL 1.5 k Ω (2%) VDD BP0 to BP3, and S0 to S39 1 nF VSS MCE439 Fig.21 Test loads. 2004 Dec 22 29 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8576D handbook, full pagewidth 1/fCLK tCLKH tCLKL 0.7VDD 0.3VDD CLK SYNC 0.7VDD 0.3VDD tPD(SYNC) tSYNCL tPD(SYNC) BP0 to BP3, and S0 to S39 0.5 V (VDD = 5 V) 0.5 V tPD(LCD) MCE424 Fig.22 Driver timing waveforms. handbook, full pagewidth SDA t BUF t LOW tf SCL t HD;STA tr t HD;DAT t HIGH t SU;DAT SDA t SU;STA MGA728 t SU;STO Fig.23 I2C-bus timing waveforms. 2004 Dec 22 30 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 12 BONDING PAD INFORMATION Table 15 Bonding pad locations All x/y coordinates represent the position of the centre of each pad (in µm) with respect to the centre (x/y = 0) of the chip (see Fig.23). COORDINATES SYMBOL SDA SCL SCL SYNC CLK VDD OSC A0 A1 A2 SA0 VSS VLCD BP0 BP2 BP1 BP3 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 2004 Dec 22 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 PAD x −34.38 +109.53 +181.53 +365.58 +469.08 +577.08 +740.88 +835.83 +1005.48 +1005.48 +1005.48 +1005.48 1005.48 1005.48 1005.48 1005.48 1005.48 1005.48 1005.48 1005.48 1005.48 347.22 263.97 180.72 97.47 14.22 −69.03 −152.28 −235.53 −318.78 −402.03 −485.28 −568.53 −651.78 −735.03 y −876.6 −876.6 −876.6 −876.6 −876.6 −876.6 −876.6 −876.6 −630.9 −513.9 −396.9 −221.4 10.71 156.51 232.74 308.97 385.2 493.2 565.2 637.2 709.2 876.6 876.6 876.6 876.6 876.6 +876.6 +876.6 +876.6 +876.6 +876.6 +876.6 +876.6 +876.6 +876.6 31 SYMBOL S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39 SDA SDA 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 PAD x −1005.5 −1005.5 −1005.5 −1005.5 −1005.5 −1005.5 −1005.5 −1005.5 −1005.5 −1005.5 −1005.5 −1005.5 −1005.5 −1005.5 −1005.5 −1005.5 −735.03 −663.03 −591.03 −519.03 −447.03 −375.03 −196.38 −106.38 +930.42 −829.98 PCF8576D COORDINATES y +625.59 +541.62 +458.19 +374.76 +291.33 +207.9 +124.47 +41.04 −42.39 −125.8 −209.3 −292.7 −376.1 −459.5 −543 −625.6 −876.6 −876.6 −876.6 −876.6 −876.6 −876.6 −876.6 −876.6 −870.3 −870.3 Alignment marks C1 C2 Table 16 Gold bump dimension PCF8576DU/2DA/2 DESCRIPTION Gold bump dimension Gold bump tolerance 3 µm DIMENSION 52 µm × 80 µm × 15 µm Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8576D S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 23 35 34 33 32 31 30 29 28 27 26 25 24 22 S4 handbook, full pagewidth 21 S3 S2 S1 S0 BP3 BP1 BP2 BP0 VLCD S18 S19 S20 S21 S22 S23 S24 S25 2.01 mm S26 S27 S28 S29 S30 S31 S32 S33 36 37 38 39 40 41 42 43 44 45 46 47 48 20 19 18 17 16 15 14 x 0 0 y 13 12 VSS 11 49 50 51 SA0 A2 A1 PCF8576DU 10 9 C2 52 53 54 55 56 57 58 59 1 2 3 4 5 6 7 8 C1 SDA SDA SDA S34 S35 S36 S37 S38 S39 SCL SCL SYNC CLK OSC 2.26 mm VDD A0 MDB074 Chip dimensions: approximately 2.26 × 2.01 mm. Bump dimensions (except pad 1): 52 × 80 × 17.5 (height) µm. Bump dimensions (pad 1): 52 × 76 × 17.5 (height) µm. Alignment marks: diameter = 72 µm. Fig.23 Bonding pad locations. 2004 Dec 22 32 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 13 DEVICE PROTECTION PCF8576D handbook, full pagewidth VDD SA0 VDD VSS VDD CLK VSS SCL VSS VDD VSS OSC VSS VDD SYNC SDA VSS VDD A0, A1 A2 VSS VSS VLCD BP0, BP1, BP2, BP3 VSS VLCD S0 to S39 VSS MDB076 VLCD VSS Fig.24 Device protection diagram. 2004 Dec 22 33 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 14 TRAY INFORMATION PCF8576D handbook, full pagewidth x G H 1,1 2,1 A C y x,1 D 1,2 B F 1,y x,y E MCE404 For dimensions, see Table 17. Fig.25 Tray details. Table 17 Tray dimensions (see Fig.25) SYMBOL A B C D E F G H x y DESCRIPTION pocket pitch, in x direction pocket pitch, in y direction pocket width, in x direction pocket width, in y direction tray width, in x direction tray width, in y direction cut corner to pocket 1,1 centre cut corner to pocket 1,1 centre number of pockets in x direction number of pockets in y direction VALUE 5.59 mm 6.35 mm 3.16 mm 3.16 mm 50.8 mm 50.8 mm 5.83 mm 6.35 mm 8 7 MDB080 handbook, halfpage PC8576DU The orientation of the IC in a pocket is indicated by the position of the IC type name on the die surface with respect to the chamfer on the upper left corner of the tray. Fig.26 Tray alignment. 2004 Dec 22 34 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 15 PACKAGE OUTLINES TQFP64: plastic thin quad flat package; 64 leads; body 10 x 10 x 1.0 mm PCF8576D SOT357-1 c y X A 48 49 33 32 ZE e E HE A wM pin 1 index bp 17 1 16 ZD bp D HD wM B vM B vM A detail X Lp L A2 A 1 (A 3) θ 64 e 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.2 A1 0.15 0.05 A2 1.05 0.95 A3 0.25 bp 0.27 0.17 c 0.18 0.12 D (1) 10.1 9.9 E (1) 10.1 9.9 e 0.5 HD HE L 1 Lp 0.75 0.45 v 0.2 w 0.08 y 0.1 Z D(1) Z E(1) 1.45 1.05 1.45 1.05 θ 7 o 0 o 12.15 12.15 11.85 11.85 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT357-1 REFERENCES IEC 137E10 JEDEC MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 00-01-19 02-03-14 2004 Dec 22 35 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8576D TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1 D E A X c y HE vMA Z 56 29 Q A2 A1 pin 1 index Lp L (A 3) A θ 1 e bp wM 28 detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions). UNIT mm A max. 1.2 A1 0.15 0.05 A2 1.05 0.85 A3 0.25 bp 0.28 0.17 c 0.2 0.1 D (1) 14.1 13.9 E (2) 6.2 6.0 e 0.5 HE 8.3 7.9 L 1 Lp 0.8 0.4 Q 0.50 0.35 v 0.25 w 0.08 y 0.1 Z 0.5 0.1 θ 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT364-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 2004 Dec 22 36 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 16 SOLDERING 16.1 Introduction to soldering surface mount packages PCF8576D To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C or 265 °C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 16.4 Manual soldering This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 16.2 Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 °C to 270 °C depending on solder paste material. The top-surface temperature of the packages should preferably be kept: • below 225 °C (SnPb process) or below 245 °C (Pb-free process) – for all BGA, HTSSON..T and SSOP..T packages – for packages with a thickness ≥ 2.5 mm – for packages with a thickness < 2.5 mm and a volume ≥ 350 mm3 so called thick/large packages. • below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times. 16.3 Wave soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 °C and 320 °C. Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. 2004 Dec 22 37 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 16.5 Suitability of surface mount IC packages for wave and reflow soldering methods PACKAGE(1) BGA, HTSSON..T(3), LBGA, LFBGA, SQFP, SSOP..T(3), TFBGA, VFBGA, XSON DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC(5), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP CWQCCN..L(8), PMFP(9), WQCCN..L(8) Notes not suitable not suitable(4) suitable not not recommended(5)(6) recommended(7) PCF8576D SOLDERING METHOD WAVE REFLOW(2) suitable suitable suitable suitable suitable not suitable not suitable 1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 3. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. 4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 5. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 6. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 7. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 8. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. 9. Hot bar soldering or manual soldering is suitable for PMFP packages. 2004 Dec 22 38 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 17 DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development DEFINITION PCF8576D This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). II Preliminary data Qualification III Product data Production Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 18 DEFINITIONS Short-form specification  The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition  Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information  Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 19 DISCLAIMERS Life support applications  These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes  Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 2004 Dec 22 39 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8576D Bare die  All die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a period of ninety (90) days from the date of Philips' delivery. If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post packing tests performed on individual die or wafer. Philips Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, Philips Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify their application in which the die is used. 20 PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 2004 Dec 22 40 Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. © Koninklijke Philips Electronics N.V. 2004 SCA76 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands R15/05/pp41 Date of release: 2004 Dec 22 Document order number: 9397 750 14492