INTEGRATED CIRCUITS
DATA SHEET
PCF8578 LCD row/column driver for dot matrix graphic displays
Product specification Supersedes data of 1998 Sep 08 2003 Apr 14
Philips Semiconductors
Product specification
LCD row/column driver for dot matrix graphic displays
CONTENTS 1 2 3 4 5 6 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 8 8.1 9 9.1 9.2 9.3 9.4 10 11 12 13 14 15 16 17 FEATURES APPLICATIONS GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Mixed mode Row mode Multiplexed LCD bias generation Power-on reset Internal clock External clock Timing generator Row/column drivers Display mode controller Display RAM Data pointer Subaddress counter I2C-bus controller Input filters RAM access Display control TEST pin I2C-BUS PROTOCOL Command decoder CHARACTERISTICS OF THE I2C-BUS Bit transfer Start and stop conditions System configuration Acknowledge LIMITING VALUES HANDLING DC CHARACTERISTICS AC CHARACTERISTICS APPLICATION INFORMATION CHIP DIMENSIONS AND BONDING PAD LOCATIONS CHIP-ON-GLASS INFORMATION PACKAGE OUTLINES 18 18.1 18.2 18.3 18.4 18.5 19 20 21 22 SOLDERING
PCF8578
Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS PURCHASE OF PHILIPS I2C COMPONENTS
2003 Apr 14
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Philips Semiconductors
Product specification
LCD row/column driver for dot matrix graphic displays
1 FEATURES
PCF8578
• Single chip LCD controller/driver • Stand-alone or may be used with up to 32 PCF8579s (40960 dots possible) • 40 driver outputs, configurable as 32⁄8, 24⁄16, 16⁄24 or 8⁄ rows/columns 32 • Selectable multiplex rates; 1 : 8, 1 : 16, 1 : 24 or 1 : 32 • Externally selectable bias configuration, 5 or 6 levels • 1280-bit RAM for display data storage and scratch pad • Display memory bank switching • Auto-incremented data loading across hardware subaddress boundaries (with PCF8579) • Provides display synchronization for PCF8579 • On-chip oscillator, requires only 1 external resistor • Power-on reset blanks display • Logic voltage supply range 2.5 to 6 V • Maximum LCD supply voltage 9 V • Low power consumption • I2C-bus interface • TTL/CMOS compatible • Compatible with most microcontrollers • Optimized pinning for single plane wiring in multiple device applications (with PCF8579) • Space saving 56-lead plastic mini-pack and 64 pin quad flat pack • Compatible with chip-on-glass technology. 3 GENERAL DESCRIPTION The PCF8578 is a low power CMOS LCD row/column driver, designed to drive dot matrix graphic displays at multiplex rates of 1 : 8, 1 : 16, 1 : 24 or 1 : 32. The device has 40 outputs, of which 24 are programmable, configurable as 32⁄8, 24⁄16, 16⁄24 or 8⁄32 rows/columns. The PCF8578 can function as a stand-alone LCD controller/driver for use in small systems, or for larger systems can be used in conjunction with up to 32 PCF8579s for which it has been optimized. Together these two devices form a general purpose LCD dot matrix driver chip set, capable of driving displays of up to 40960 dots. The PCF8578 is compatible with most microcontrollers and communicates via a two-line bidirectional bus (I2C-bus). Communication overheads are minimized by a display RAM with auto-incremented addressing and display bank switching.
2
APPLICATIONS
• Automotive information systems • Telecommunication systems • Point-of-sale terminals • Computer terminals • Instrumentation.
4
ORDERING INFORMATION PACKAGE
TYPE NUMBER NAME PCF8578T PCF8578U/2 PCF8578H VSO56 − LQFP64 chip with bumps in tray plastic low profile quad flat package; 64 leads; body 10 × 10 × 1.4 mm DESCRIPTION plastic very small outline package; 56 leads VERSION SOT190-1 − SOT314-2
2003 Apr 14
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Philips Semiconductors
Product specification
LCD row/column driver for dot matrix graphic displays
5 BLOCK DIAGRAM
PCF8578
C39 - C32 R31/C31 - R8/C8 R7 - R0 17 - 56 (29 to 35, 37, 38 to 46 48 to 62, 63, 64, 1 to 6)
VDD V2 V3 V4 V5 VLCD TEST
9 (20) 10 (21) 11 (22) 12 (23) 13 (24) 14 (25) 6 (12) DISPLAY MODE CONTROLLER
ROW/COLUMN DRIVERS
(1)
PCF8578
OUTPUT CONTROLLER
Y DECODER AND SENSING AMPLIFIERS
32 x 40-BIT DISPLAY RAM
DISPLAY DECODER
X DECODER
(9) 3 POWER-ON RESET SUBADDRESS COUNTER RAM DATA POINTER Y X TIMING GENERATOR SYNC (10) 4 CLK
SCL SDA
2 (8) 1 (7) INPUT FILTERS (14, 15, 17 to 19 26 to 28 36, 47) n.c.
(16) 8 I 2 C-BUS CONTROLLER COMMAND DECODER OSCILLATOR
OSC R OSC
(11) 5 7 (13)
MSA842
15, 16 n.c.
VSS
SA0
(1) Operates at LCD voltage levels, all other blocks operate at logic levels. The pin numbers given in parenthesis refer to the LQFP64 package.
Fig.1 Block diagram.
2003 Apr 14
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Philips Semiconductors
Product specification
LCD row/column driver for dot matrix graphic displays
6 PINNING PIN SYMBOL VSO56 SDA SCL SYNC CLK VSS TEST SA0 OSC VDD V2 to V5 VLCD n.c. C39 to C32 R31/C31 to R8/C8 R7 to R0 1 2 3 4 5 6 7 8 9 10 to 13 14 15, 16 17 to 24 25 to 48 49 to 56 LQFP64 7 8 9 10 11 12 13 16 20 21 to 24 25 14, 15, 17 to 19, 26 to 28, 36, 47 29 to 35, 37 63, 64, 1 to 6 I2C-bus serial data input/output I2C-bus serial clock input cascade synchronization output external clock input/output ground (logic) test pin (connect to VSS) I2C-bus slave address input (bit 0) oscillator input positive supply voltage LCD bias voltage inputs LCD supply voltage not connected LCD column driver outputs LCD row driver outputs DESCRIPTION
PCF8578
38 to 46, 48 to 62 LCD row/column driver outputs
2003 Apr 14
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Philips Semiconductors
Product specification
LCD row/column driver for dot matrix graphic displays
PCF8578
SDA SCL SYNC CLK VSS TEST SA0 OSC VDD
1 2 3 4 5 6 7 8 9
56
R0
55 R1 54 53 52 51 50 49 48 47 46 R2 R3 R4 R5 R6 R7 R8/C8 R9/C9 R10/C10
V2 10 V3 11 V4 12 V5 13 VLCD 14
45 R11/C11 44 R12/C12 43 R13/C13
PCF8578T
n.c. 15 n.c. 16 C39 17 C38 18 C37 C36 C35 C34 C33 C32 R31/C31 R30/C30 R29/C29 R28/C28 19 20 21 22 23 24 25 26 27 28
MSA839
42 R14/C14 41 R15/C15 40 R16/C16 39 R17/C17 38 R18/C18 37 R19/C19 36 R20/C20 35 R21/C21 34 R22/C22 33 R23/C23 32 R24/C24 31 R25/C25 30 R26/C26 29 R27/C27
Fig.2 Pin configuration (VSO56).
2003 Apr 14
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Philips Semiconductors
Product specification
LCD row/column driver for dot matrix graphic displays
PCF8578
60 R10/C10
59 R11/C11
58 R12/C12
57 R13/C13
56 R14/C14
55 R15/C15
54 R16/C16
53 R17/C17
52 R18/C18
51 R19/C19
50 R20/C20
62 R8/C8
R5 R4 R3 R2 R1 R0 SDA SCL SYNC
1 2 3 4 5 6 7 8
61 R9/C9
handbook, full pagewidth
49 R21/C21 48 R22/C22 47 n.c. 46 R23/C23 45 R24/C24 44 R25/C25 43 R26/C26 42 R27/C27 41 R28/C28 40 R29/C29 39 R30/C30 38 R31/C31 37 C32 36 n.c. 35 C33 34 C34 33 C35 C36 32
MBH588
64 R6
63 R7
PCF8578H
9 CLK 10 VSS 11 TEST 12 SA0 13 n.c. 14 n.c. 15 OSC 16 n.c. 17 n.c. 18 n.c. 19 VDD 20 V2 21 V3 22 V4 23 V5 24 VLCD 25 n.c. 26 n.c. 27 n.c. 28 C39 29 C38 30 C37 31
Fig.3 Pin configuration (LQFP64).
2003 Apr 14
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Philips Semiconductors
Product specification
LCD row/column driver for dot matrix graphic displays
7 FUNCTIONAL DESCRIPTION
PCF8578
Timing signals are derived from the on-chip oscillator, whose frequency is determined by the value of the resistor connected between OSC and VSS. Commands sent on the I2C-bus from the host microcontroller set the mode (row or mixed), configuration (multiplex rate and number of rows and columns) and control the operation of the device. The device may have one of two slave addresses. The only difference between these slave addresses is the least significant bit, which is set by the logic level applied to SA0. The PCF8578 and PCF8579 also have subaddresses. The subaddress of the PCF8578 is only defined in mixed mode and is fixed at 0. The RAM may only be accessed in mixed mode and data is loaded as described for the PCF8579. Bias levels may be generated by an external potential divider with appropriate decoupling capacitors. For large displays, bias sources with high drive capability should be used. A typical mixed mode system operating with up to 15 PCF8579s is shown in Fig.5 (a stand-alone system would be identical but without the PCF8579s).
The PCF8578 row/column driver is designed for use in one of three ways: • Stand-alone row/column driver for small displays (mixed mode) • Row/column driver with cascaded PCF8579s (mixed mode) • Row driver with cascaded PCF8579s (mixed mode). 7.1 Mixed mode
In mixed mode, the device functions as both a row and column driver. It can be used in small stand-alone applications, or for larger displays with up to 15 PCF8579s (31 PCF8579s when two slave addresses are used). See Table 1 for common display configurations. 7.2 Row mode
In row mode, the device functions as a row driver with up to 32 row outputs and provides the clock and synchronization signals for the PCF8579. Up to 16 PCF8579s can normally be cascaded (32 when two slave addresses are used). Table 1 Possible displays configurations MULTIPLEX RATE 1:8 1 : 16 1 : 24 1 : 32 With PCF8579 1:8 1 : 16 1 : 24 1 : 32 Notes 1. Using 15 PCF8579s. 2. Using 16 PCF8579s. MIXED MODE ROWS 8 16 24 32 8(1) 16(1) 24(1) 32(1) COLUMNS 32 24 16 8 632(1) 624(1) 616(1) 608(1)
ROW MODE TYPICAL APPLICATIONS ROWS − − − − 8× 4(2) 2(2) 16 × COLUMNS − − − − 640(2) 640(2) 640(2) 640(2) alphanumeric displays and dot matrix graphic displays small digital or alphanumerical displays
APPLICATION Stand alone
24(2) 24(2)
2003 Apr 14
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Philips Semiconductors
Product specification
LCD row/column driver for dot matrix graphic displays
7.3 Multiplexed LCD bias generation 7.4 Power-on reset
PCF8578
The bias levels required to produce maximum contrast depend on the multiplex rate and the LCD threshold voltage (Vth). Vth is typically defined as the RMS voltage at which the LCD exhibits 10% contrast. Table 2 shows the optimum voltage bias levels for the PCF8578 as functions of Vop (Vop = VDD − VLCD), together with the discrimination ratios (D) for the different multiplex rates. A practical value for Vop is obtained by equating Voff(rms) with Vth. Figure 4 shows the first 4 rows of Table 2 as graphs. Table 3 shows the relative values of the resistors required in the configuration of Fig.5 to produce the standard multiplex rates. Table 2 Optimum LCD voltages MULTIPLEX RATE PARAMETER 1:8 V2 -------V op V3 -------V op V4 -------V op V5 -------V op V off ( rms ) --------------------V op V on ( rms ) -------------------V op V on ( rms ) D = --------------------V off ( rms ) V op -------V th Table 3 0.739 1 : 16 0.800 1 : 24 0.830 1 : 32
At power-on the PCF8578 resets to a defined starting condition as follows: 1. Display blank 2. 1 : 32 multiplex rate, row mode 3. Start bank, 0 selected 4. Data pointer is set to X, Y address 0, 0 5. Character mode 6. Subaddress counter is set to 0 7. I2C-bus interface is initialized. Data transfers on the I2C-bus should be avoided for 1 ms following power-on, to allow completion of the reset action.
1.0
MSA838
0.850
V bias Vop 0.8 V2
0.522
0.600
0.661
0.700
0.6
V3
0.478
0.400
0.339
0.300
0.4 V4 0.2 V5
0.261
0.200
0.170
0.150
0.297
0.245
0.214
0.193
0 1:8 1:16 1:24 1:32 multiplex rate
0.430
0.316
0.263
0.230
Vbias = V2, V3, V4, V5. See Table 2.
1.447
1.291
1.230
1.196
Fig.4
Vbias/Vop as a function of the multiplex rate.
3.370
4.080
4.680
5.190
Multiplex rates and resistor values for Fig.5 MULTIPLEX RATE (n)
RESISTORS n=8 R1 R2 R3 R ( n – 2)R (3 – n)R n = 16, 24, 32 R R ( n – 3)R
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LCD DISPLAY n rows V DD C R1 V2 C R2 V3 HOST MICROCONTROLLER C R3 V4 C R2 V5 C R1 V LCD SA0 VSS / V DD V DD V DD VLCD VSS SA0 SDA SCL CLK SYNC V4 A0 A1 subaddress 1 VSS / V DD V DD 40 columns 40 n columns
Philips Semiconductors
LCD row/column driver for dot matrix graphic displays
PCF8578
VLCD VSS VSS / V DD
PCF8579
10
SCL SDA
A2 A3 V3
VSS VSS VLCD OSC R OSC
SDA SCL CLK SYNC
Product specification
MSA843
PCF8578
Fig.5 Typical mixed mode configuration.
Philips Semiconductors
Product specification
LCD row/column driver for dot matrix graphic displays
PCF8578
T frame 0 VDD V2 V3 V4 V5 V LCD VDD V2 V3 V4 V5 V LCD SYNC 0 VDD V2 V3 V4 V5 V LCD VDD V2 V3 V4 V5 V LCD SYNC 0 VDD V2 V3 V4 V5 V LCD VDD V2 V3 V4 V5 V LCD SYNC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 VDD V2 V3 V4 V5 V LCD VDD V2 V3 V4 V5 V LCD SYNC
MSA841
ON 4 5 6 7 OFF
1
2
3
ROW 0
1:8
COLUMN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
ROW 0
1:16
COLUMN
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
ROW 0
1:24
COLUMN
ROW 0
1:32
COLUMN
column display
Fig.6 LCD row/column waveforms.
2003 Apr 14
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Philips Semiconductors
Product specification
LCD row/column driver for dot matrix graphic displays
PCF8578
T frame VDD V2 V3 V4 V5 V LCD VDD V2 V3 V4 V5 V LCD VDD V2 V3 V4 V5 V LCD VDD V2 V3 V4 V5 V LCD V op 0.261 Vop V state 1 (t) 0V 0.261 Vop
state 1 (OFF) state 2 (ON)
ROW 1 R1 (t)
ROW 2 R2 (t)
dot matrix 1:8 multiplex rate
COL 1 C1 (t)
COL 2 C2 (t)
V op V op 0.478 Vop 0.261 Vop V state 2 (t) 0V 0.261 Vop 0.478 Vop V op
MSA840
V state 1 (t) = C1(t)
R1(t): 8 8( 8 1 1) = 0.430
general relationship (n = multiplex rate)
Von(rms) V op
=
1 8
Von(rms) V op
=
1 n
n1 n ( n 1)
V state 2 (t) = C2(t)
R2(t):
Voff(rms) V op
=
2 ( 8 1) = 0.297 8 ( 8 1) 2
Voff(rms) = V op
2 ( n 1) n ( n 1) 2
Fig.7 LCD drive mode waveforms for 1 : 8 multiplex rate.
2003 Apr 14
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Philips Semiconductors
Product specification
LCD row/column driver for dot matrix graphic displays
PCF8578
T frame VDD V2 V3 V4 V5 V LCD VDD V2 V3 V4 V5 V LCD VDD V2 V3 V4 V5 V LCD VDD V2 V3 V4 V5 V LCD V op
state 1 (OFF) state 2 (ON)
ROW 1 R1 (t)
ROW 2 R2 (t)
COL 1 C1 (t)
dot matrix 1:16 multiplex rate
COL 2 C2 (t)
0.2 Vop V state 1 (t) 0V 0.2 Vop
V op V op 0.6 Vop V state 2 (t) 0.2 Vop 0V 0.2 Vop 0.6 Vop V op
MSA836
V state 1 (t) = C1(t)
R1(t):
general relationship (n = multiplex rate)
Von(rms) V op
=
1 16 1 = 0.316 16 16 ( 16 1 ) R2(t):
Von(rms) V op
=
1 n
n1 n ( n 1)
V state 2 (t) = C2(t)
V off(rms) V op
=
2 ( 16 1) = 0.254 16 ( 16 1 ) 2
Voff(rms) = V op
2 ( n 1) n ( n 1) 2
Fig.8 LCD drive mode waveforms for 1 : 16 multiplex rate.
2003 Apr 14
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Philips Semiconductors
Product specification
LCD row/column driver for dot matrix graphic displays
7.5 Internal clock 7.6 External clock
PCF8578
The clock signal for the system may be generated by the internal oscillator and prescaler. The frequency is determined by the value of the resistor ROSC, see Fig.9. For normal use a value of 330 kΩ is recommended. The clock signal, for cascaded PCF8579s, is output at CLK and has a frequency 1⁄6 (multiplex rate 1 : 8, 1 : 16 and 1 : 32) or 1⁄8 (multiplex rate 1 : 24) of the oscillator frequency.
If an external clock is used, OSC must be connected to VDD and the external clock signal to CLK. Table 4 summarizes the nominal CLK and SYNC frequencies. 7.7 Timing generator
10 3 f OSC (kHz) 10 2
MSA837
The timing generator of the PCF8578 organizes the internal data flow of the device and generates the LCD frame synchronization pulse SYNC, whose period is an integer multiple of the clock period. In cascaded applications, this signal maintains the correct timing relationship between the PCF8578 and PCF8579s in the system. 7.8 Row/column drivers
10
1 10
102
103
104 R OSC (kΩ )
Outputs R0 to R7 and C32 to C39 are fixed as row and column drivers respectively. The remaining 24 outputs R8/C8 to R31/C31 are programmable and may be configured (in blocks of 8) to be either row or column drivers. The row select signal is produced sequentially at each output from R0 up to the number defined by the multiplex rate (see Table 1). In mixed mode the remaining outputs are configured as columns. In row mode all programmable outputs (R8/C8 to R31/C31) are defined as row drivers and the outputs C32 to C39 should be left open-circuit. Using a 1 : 16 multiplex rate, two sets of row outputs are driven, thus facilitating split-screen configurations, i.e. a row select pulse appears simultaneously at R0 and R16/C16, R1 and R17/C17 etc. Similarly, using a multiplex rate of 1 : 8, four sets of row outputs are driven simultaneously. Driver outputs must be connected directly to the LCD. Unused outputs should be left open-circuit. In 1 : 8 R0 to R7 are rows; in 1 : 16 R0 to R15/C15 are rows; in 1 : 24 R0 to R23/C23 are rows; in 1 : 32 R0 to R31/C31 are rows.
To avoid capacitive coupling, which could adversely affect oscillator stability, ROSC should be placed as closely as possible to the OSC pin. If this proves to be a problem, a filtering capacitor may be connected in parallel to ROSC.
Fig.9
Oscillator frequency as a function of external oscillator resistor, ROSC.
Table 4
Signal frequencies required for nominal 64 Hz frame frequency; note 1. FRAME FREQUENCY fSYNC (Hz) 64 64 MULTIPLEX RATE (n) 1 : 8, 1 : 16, 1 : 32 1 : 24 DIVISION RATIO 6 8 CLOCK FREQUENCY fCLK (Hz) 2048 1536
OSCILLATOR FREQUENCY fOSC(2) (Hz) 12288 12288 Notes
1. A clock signal must always be present, otherwise the LCD may be frozen in a DC state. 2. ROSC = 330 kΩ.
2003 Apr 14
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Philips Semiconductors
Product specification
LCD row/column driver for dot matrix graphic displays
7.9 Display mode controller 7.15 RAM access
PCF8578
The configuration of the outputs (row or column) and the selection of the appropriate driver waveforms are controlled by the display mode controller. 7.10 Display RAM
RAM operations are only possible when the PCF8578 is in mixed mode. In this event its hardware subaddress is internally fixed at 0000 and the hardware subaddresses of any PCF8579 used in conjunction with the PCF8578 must start at 0001. There are three RAM ACCESS modes: • Character • Half-graphic • Full-graphic. These modes are specified by bits G1 to G0 of the RAM ACCESS command. The RAM ACCESS command controls the order in which data is written to or read from the RAM (see Fig.10). To store RAM data, the user specifies the location into which the first byte will be loaded (see Fig.11): • Device subaddress (specified by the DEVICE SELECT command) • RAM X-address (specified by the LOAD X-ADDRESS command) • RAM bank (specified by bits Y1 and Y0 of the RAM ACCESS command). Subsequent data bytes will be written or read according to the chosen RAM ACCESS mode. Device subaddresses are automatically incremented between devices until the last device is reached. If the last device has subaddress 15, further display data transfers will lead to a wrap-around of the subaddress to 0. 7.16 Display control
The PCF8578 contains a 32 × 40-bit static RAM which stores the display data. The RAM is divided into 4 banks of 40 bytes (4 × 8 × 40 bits). During RAM access, data is transferred to/from the RAM via the I2C-bus. The first eight columns of data (0 to 7) cannot be displayed but are available for general data storage and provide compatibility with the PCF8579. There is a direct correspondence between X-address and column output number. 7.11 Data pointer
The addressing mechanism for the display RAM is realized using the data pointer. This allows an individual data byte or a series of data bytes to be written into, or read from, the display RAM, controlled by commands sent on the I2C-bus. 7.12 Subaddress counter
The storage and retrieval of display data is dependent on the content of the subaddress counter. Storage takes place only when the contents of the subaddress counter agree with the hardware subaddress. The hardware subaddress of the PCF8578, valid in mixed mode only, is fixed at 0000. 7.13 I2C-bus controller
The I2C-bus controller detects the I2C-bus protocol, slave address, commands and display data bytes. It performs the conversion of the data input (serial-to-parallel) and the data output (parallel-to-serial). The PCF8578 acts as an I2C-bus slave transmitter/receiver in mixed mode, and as a slave receiver in row mode. A slave device cannot control bus communication. 7.14 Input filters
The display is generated by continuously shifting rows of RAM data to the dot matrix LCD via the column outputs. The number of rows scanned depends on the multiplex rate set by bits M1 and M0 of the SET MODE command. The display status (all dots on/off and normal/inverse video) is set by bits E1 and E0 of the SET MODE command. For bank switching, the RAM bank corresponding to the top of the display is set by bits B1 and B0 of the SET START BANK command. This is shown in Fig.12. This feature is useful when scrolling in alphanumeric applications. 7.17 TEST pin
To enhance noise immunity in electrically adverse environments, RC low-pass filters are provided on the SDA and SCL lines.
The TEST pin must be connected to VSS.
2003 Apr 14
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RAM 4 bytes 1 byte 0 1
Philips Semiconductors
LCD row/column driver for dot matrix graphic displays
PCF8578/PCF8579
driver 1
PCF8579
driver 2 driver k
bank 0 bank 1 bank 2 bank 3 PCF8578/PCF8579 system RAM 1 k 16 LSB
40-bits
2
3
4
5
6
7
8
9 10 11 character mode
16
0 2 bytes 1 3 5 7 9 11 13 15 17 19 21 23 half-graphic mode 2 4 6 8 10 12 14 16 18 20 22 0 1 4 bytes 2 3 6 10 14 18 22 26 30 34 38 42 46 4 5 8 12 16 20 24 28 32 36 40 44 9 13 17 21 25 29 33 37 41 45 7 11 15 19 23 27 31 35 39 43 47 RAM data bytes are written or read as indicated above full-graphic mode
MSA849
MSB
Product specification
PCF8578
Fig.10 RAM ACCESS mode.
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DEVICE SELECT: subaddress 12 RAM ACCESS: character mode bank 1 RAM bank 0 bank 1 bank 2 bank 3 LOAD X-ADDRESS: X-address = 8 R/ W slave address
Philips Semiconductors
LCD row/column driver for dot matrix graphic displays
17
R/W slave address DEVICE SELECT LOAD X-ADDRESS RAM ACCESS
READ
S
S 011110A1A
0
DATA
A
S
S 011110A0A11101100A10001000A01110001A 0
last command
WRITE
DATA
A
DATA
A
MSA835
Product specification
PCF8578
Fig.11 Example of commands specifying initial data byte RAM locations.
Philips Semiconductors
Product specification
LCD row/column driver for dot matrix graphic displays
PCF8578
RAM
bank 0 top of LCD
bank 1
LCD
bank 2
bank 3
MSA851
Fig.12 Relationship between display and SET START BANK; 1 : 32 multiplex rate and start bank = 2.
2003 Apr 14
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Philips Semiconductors
Product specification
LCD row/column driver for dot matrix graphic displays
8 I2C-BUS PROTOCOL
PCF8578
In READ mode, indicated by setting the read/write bit HIGH, data bytes may be read from the RAM following the slave address acknowledgement. After this acknowledgement the master transmitter becomes a master receiver and the PCF8578 becomes a slave transmitter. The master receiver must acknowledge the reception of each byte in turn. The master receiver must signal an end of data to the slave transmitter, by not generating an acknowledge on the last byte clocked out of the slave. The slave transmitter then leaves the data line HIGH, enabling the master to generate a stop condition (P). Display bytes are written into, or read from, the RAM at the address specified by the data pointer and subaddress counter. Both the data pointer and subaddress counter are automatically incremented, enabling a stream of data to be transferred either to, or from, the intended devices. In multiple device applications, the hardware subaddress pins of the PCF8579s (A0 to A3) are connected to VSS or VDD to represent the desired hardware subaddress code. If two or more devices share the same slave address, then each device must be allocated a unique hardware subaddress.
Two 7-bit slave addresses (0111100 and 0111101) are reserved for both the PCF8578 and PCF8579. The least significant bit of the slave address is set by connecting input SA0 to either 0 (VSS) or 1 (VDD). Therefore, two types of PCF8578 or PCF8579 can be distinguished on the same I2C-bus which allows: 1. One PCF8578 to operate with up to 32 PCF8579s on the same I2C-bus for very large applications 2. The use of two types of LCD multiplex schemes on the same I2C-bus. In most applications the PCF8578 will have the same slave address as the PCF8579. The I2C-bus protocol is shown in Fig.13. All communications are initiated with a start condition (S) from the I2C-bus master, which is followed by the desired slave address and read/write bit. All devices with this slave address acknowledge in parallel. All other devices ignore the bus transfer. In WRITE mode (indicated by setting the read/write bit LOW) one or more commands follow the slave address acknowledgement. The commands are also acknowledged by all addressed devices on the bus. The last command must clear the continuation bit C. After the last command a series of data bytes may follow. The acknowledgement after each byte is made only by the (A0, A1, A2 and A3) addressed PCF8579 or PCF8578 with its implicit subaddress 0. After the last data byte has been acknowledged, the I2C-bus master issues a stop condition (P).
2003 Apr 14
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Philips Semiconductors
Product specification
LCD row/column driver for dot matrix graphic displays
PCF8578
R/ W slave address S
acknowledge by all addressed PCF8578s / PCF8579s
acknowledge by A0, A1, A2 and A3 selected PCF8578s / PCF8579s only
S 0 1 1 1 1 0A 0AC
0 1 byte n
COMMAND
A
DISPLAY DATA
A
P
0 byte(s)
n
0 byte(s) update data pointers and if necessary, subaddress counter
(a)
MSA830
acknowledge by all addressed PCF8578s / PCF8579s slave address S 0 1 1 1 1 0A0 AC 0 slave address S COMMAND A acknowledge from master no acknowledge from master
S
S 011110A1A
0
DATA
A
DATA
1
P
n R/ W
1 byte R/W at this moment master transmitter becomes a master receiver and PCF8578/PCF8579 slave receiver becomes a slave transmitter
n bytes
last byte
update data pointers and if necessary subaddress counter
MSA832
(b)
acknowledge by all addressed PCF8578s / PCF8579s slave address S
acknowledge from master
no acknowledge from master
S 011110A1A
0
MSA831
DATA
A
DATA
1
P
R/ W
n bytes
last byte update data pointers and if necessary, subaddress counter
(c)
Fig.13 (a) Master transmits to slave receiver (WRITE mode); (b) Master reads after sending command string (WRITE commands; READ data); (c) Master reads slave immediately after sending slave address (READ mode).
2003 Apr 14
20
Philips Semiconductors
Product specification
LCD row/column driver for dot matrix graphic displays
8.1 Command decoder
MSB C REST OF OPCODE
PCF8578
The command decoder identifies command bytes that arrive on the I2C-bus. The most-significant bit of a command is the continuation bit C (see Fig.14). When this bit is set, it indicates that the next byte to be transferred will also be a command. If the bit is reset, it indicates the conclusion of the command transfer. Further bytes will be regarded as display data. Commands are transferred in WRITE mode only. The five commands available to the PCF8578 are defined in Tables 5 and 6. Table 5 Summary of commands OPCODE(1) C C C C C 1 1 1 1 0 0 1 1 1 D D 1 0 1 D D 1 D D D D 1 D D D D D D D D
LSB
MSA833
C = 0; last command. C = 1; commands continue.
Fig.14 General information of command byte.
COMMAND SET MODE SET START BANK DEVICE SELECT RAM ACCESS LOAD X-ADDRESS Note
DESCRIPTION D D D D D multiplex rate, display status, system type defines bank at top of LCD defines device subaddress graphic mode, bank select (D D D D ≥ 12 is not allowed; see SET START BANK opcode) 0 to 39
1. C = command continuation bit. D = may be a logic 1 or 0.
2003 Apr 14
21
Philips Semiconductors
Product specification
LCD row/column driver for dot matrix graphic displays
Table 6 Definition of PCF8578/PCF8579 commands OPCODE C 1 0 T OPTIONS see Table 8 see Table 9 SET START BANK C 1 1 1 1 1 B1 B0 see Table 10
PCF8578
COMMAND SET MODE
DESCRIPTION defines LCD drive mode defines display status defines system type defines pointer to RAM bank corresponding to the top of the LCD; useful for scrolling, pseudo-motion and background preparation of new display four bits of immediate data, bits A0 to A3, are transferred to the subaddress counter to define one of sixteen hardware subaddresses defines the auto-increment behaviour of the address for RAM access two bits of immediate data, bits Y0 to Y1, are transferred to the X-address pointer to define one of forty display RAM columns six bits of immediate data, bits X0 to X5, are transferred to the X-address pointer to define one of forty display RAM columns
E1 E0 M1 M0 see Table 7
DEVICE SELECT
C
1
1
0
A3 A2 A1 A0 see Table 11
RAM ACCESS
C
1
1
1
G1 G0 Y1 Y0 see Table 12 see Table 13
LOAD X-ADDRESS
C
0
X5 X4 X3 X2 X1 X0 see Table 14
2003 Apr 14
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Philips Semiconductors
Product specification
LCD row/column driver for dot matrix graphic displays
Table 7 Set mode option 1 BITS LCD DRIVE MODE M1 1:8 1 : 16 1 : 24 1 : 32 Table 8 MUX (8 rows) MUX (16 rows) MUX (24 rows) MUX (32 rows) Set mode option 2 BITS DISPLAY STATUS E1 Blank Normal All segments on Inverse video Table 9 Set mode option 3 BIT T 0 1 Table 14 Device select option 1 DESCRIPTION Decimal value 0 to 39 BITS START BANK POINTER B1 Bank 0 Bank 1 Bank 2 Bank 3 0 0 1 1 B0 0 1 0 1 0 0 1 1 E0 0 1 0 1 Table 13 Device select option 1 DESCRIPTION Decimal value 0 to 3 Y1 SYSTEM TYPE PCF8578 row only PCF8578 mixed mode Table 10 Set start bank option 1 0 1 1 0 M0 1 0 1 0 Character Half-graphic Full-graphic Not allowed (note 1) Note Table 11 Device select option 1 DESCRIPTION Decimal value 0 to 15 Table 12 RAM access option 1 A3
PCF8578
BITS A2 A1 A0
BITS RAM ACCESS MODE G1 0 0 1 1 G0 0 1 0 1
1. See opcode for SET START BANK in Table 6.
BITS Y0
BITS X5 X4 X3 X2 X1 X0
2003 Apr 14
23
Philips Semiconductors
Product specification
LCD row/column driver for dot matrix graphic displays
9 CHARACTERISTICS OF THE I2C-BUS 9.4 Acknowledge
PCF8578
The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL) which must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy. 9.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this moment will be interpreted as control signals. 9.2 Start and stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH, is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH, is defined as the STOP condition (P). 9.3 System configuration
The number of data bytes transferred between the start and stop conditions from transmitter to receiver is unlimited. Each data byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal the end of a data transmission to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a stop condition.
A device transmitting a message is a 'transmitter', a device receiving a message is the 'receiver'. The device that controls the message flow is the 'master' and the devices which are controlled by the master are the 'slaves'.
SDA
SCL data line stable; data valid change of data allowed
MBA607
Fig.15 Bit transfer.
2003 Apr 14
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Philips Semiconductors
Product specification
LCD row/column driver for dot matrix graphic displays
PCF8578
SDA
SDA
SCL S START condition P STOP condition
SCL
MBA608
Fig.16 Definition of start and stop condition.
SDA SCL MASTER TRANSMITTER / RECEIVER SLAVE TRANSMITTER / RECEIVER MASTER TRANSMITTER / RECEIVER
MBA605
SLAVE RECEIVER
MASTER TRANSMITTER
Fig.17 System configuration.
handbook, full pagewidth
START condition SCL FROM MASTER 1 2 8
clock pulse for acknowledgement 9
DATA OUTPUT BY TRANSMITTER S DATA OUTPUT BY RECEIVER
MBA606 - 1
The general characteristics and detailed specification of the I2C-bus are available on request.
Fig.18 Acknowledgement on the I2C-bus.
2003 Apr 14
25
Philips Semiconductors
Product specification
LCD row/column driver for dot matrix graphic displays
10 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VDD VLCD VI1 VI2 Vo1 Vo2 II IO IDD, ISS, ILCD Ptot Po Tstg 11 HANDLING supply voltage LCD supply voltage input voltage SDA, SCL, CLK, TEST, SA0 and OSC input voltage V2 to V5 output voltage SYNC and CLK output voltage R0 to R7, R8/C8 to R31/C31 and C32 to C39 DC input current DC output current VDD, VSS or VLCD current total power dissipation per package power dissipation per output storage temperature PARAMETER MIN. −0.5 VDD − 11 VSS − 0.5 VSS − 0.5 −10 −10 −50 − − −65
PCF8578
MAX. +8.0 VDD VDD + 0.5 VDD + 0.5 +10 +10 +50 400 100 +150 V V V V V V
UNIT
VLCD − 0.5 VDD + 0.5 VLCD − 0.5 VDD + 0.5
mA mA mA mW mW °C
Inputs and outputs are protected against electrostatic discharge in normal handling. However it is good practice to take normal precautions appropriate to handling MOS devices (see “Handling MOS devices” ).
2003 Apr 14
26
Philips Semiconductors
Product specification
LCD row/column driver for dot matrix graphic displays
PCF8578
12 DC CHARACTERISTICS VDD = 2.5 to 6 V; VSS = 0 V; VLCD = VDD − 3.5 V to VDD − 9 V; Tamb = −40 to +85 °C; unless otherwise specified. SYMBOL Supplies VDD VLCD IDD1 IDD2 VPOR Logic VIL VIH IOL1 IOH1 IOL2 IL1 IL2 Ci IL3 VDC LOW level input voltage HIGH level input voltage LOW level output current at SYNC and CLK HIGH level output current at SYNC and CLK LOW level output current at SDA VOL = 1 V; VDD = 5 V VOH = 4 V; VDD = 5 V VOL = 0.4 V; VDD = 5 V VSS 0.7VDD 1 − 3 − − − −2 − − − − − − − − − − ±20 0.3VDD VDD − −1 − +1 +1 5 +2 − V V mA mA mA mA µA pF µA mV supply voltage LCD supply voltage supply current external clock supply current internal clock power-on reset level fCLK = 2 kHz; note 1 ROSC = 330 kΩ note 2 2.5 VDD − 9 − − 0.8 − − 6 20 1.3 6.0 15 50 1.8 V µA µA V VDD − 3.5 V PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
leakage current at SDA, SCL, SYNC, Vi = VDD or VSS CLK, TEST and SA0 leakage current at OSC input capacitance at SCL and SDA Vi = VDD note 3
LCD outputs leakage current at V2 to V5 DC component of LCD drivers R0 to R7, R8/C8 to R31/C31 and C32 to C39 output resistance R0 to R7 and R8/C8 to R31/C31 output resistance R8/C8 to R31/C31 and C32 to C39 row mode; note 4 column mode; note 4 Vi = VDD or VLCD
RROW RCOL Notes
− −
1.5 3
3 6
kΩ kΩ
1. Outputs are open; inputs at VDD or VSS; I2C-bus inactive; external clock with 50% duty factor. 2. Resets all logic when VDD < VPOR. 3. Periodically sampled; not 100% tested. 4. Resistance measured between output terminal (R0 to R7, R8/C8 to R31/C31 and C32 to C39) and bias input (V2 to V5, VDD and VLCD) when the specified current flows through one output under the following conditions (see Table 2): a) Vop = VDD − VLCD = 9 V. b) Row mode, R0 to R7 and R8/C8 to R31/C31: V2 − VLCD ≥ 6.65 V; V5 − VLCD ≤ 2.35 V; ILOAD = 150 µA. c) Column mode, R8/C8 to R31/C31 and C32 to C39: V3 − VLCD ≥ 4.70 V; V4 − VLCD ≤ 4.30 V; ILOAD = 100 µA.
2003 Apr 14
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Philips Semiconductors
Product specification
LCD row/column driver for dot matrix graphic displays
PCF8578
13 AC CHARACTERISTICS All timing values are referenced to VIH and VIL levels with an input voltage swing of VSS to VDD. VDD = 2.5 to 6 V; VSS = 0 V; VLCD = VDD − 3.5 V to VDD − 9 V; Tamb = −40 to +85 °C; unless otherwise specified. SYMBOL fCLK1 fCLK2 tPSYNC tPLCD I2C-bus fSCL tSW tBUF tSU;STA tHD;STA tLOW tHIGH tr tf tSU;DAT tHD;DAT tSU;STO SCL clock frequency tolerable spike width on bus bus free time start condition set-up time start condition hold time SCL LOW time SCL HIGH time SCL and SDA rise time SCL and SDA fall time data set-up time data hold time stop condition set-up time repeated start codes only − − 4.7 4.7 4.0 4.7 4.0 − − 250 0 4.0 − − − − 4.0 − − − − − − − 100 100 − − − − − 1 0.3 − − − kHz ns µs µs µs µs µs µs µs ns ns µs PARAMETER CONDITIONS MIN. 1.2 0.9 − VDD − VLCD = 9 V; with test loads − TYP. 2.1 1.6 − − MAX. 3.3 2.5 500 100 UNIT kHz kHz ns µs clock frequency at multiplex rates of 1 : 8, ROSC = 330 kΩ; VDD = 6 V 1 : 16 and 1 : 32 clock frequency at multiplex rates of 1 : 24 SYNC propagation delay driver delays ROSC = 330 kΩ; VDD = 6 V
handbook, full pagewidth
3.3 kΩ SYNC, CLK 0.5 VDD SDA
1.5 kΩ VDD
MSA829
C39 to C32, R31/C31 to R8/C8 and R7 to R0
1 nF
Fig.19 AC test loads.
2003 Apr 14
28
Philips Semiconductors
Product specification
LCD row/column driver for dot matrix graphic displays
PCF8578
1/ f CLK 0.7 VDD 0.3 V DD
CLK
SYNC
0.7 VDD 0.3 V DD t PSYNC t PSYNC 0.5 V (V DD V LCD = 9 V) 0.5 V t PLCD
MSA834
C39 to C32, R31/C31 to R8/C8 and R7 to R0
Fig.20 Driver timing waveforms.
handbook, full pagewidth
SDA
t BUF
t LOW
tf
SCL
t
HD;STA
tr
t HD;DAT
t HIGH
t SU;DAT
SDA t SU;STA
MGA728
t SU;STO
Fig.21 I2C-bus timing waveforms.
2003 Apr 14
29
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LCD DISPLAY R0 R1 R2 R3 R4 R5 R6 R7 R8/ R9/ R10/ R11/ R12/ R13/ R14/ R15/ R16/ R17/ R18/ R19/ R20/ R21/ R22/ R23/ R24/ R25/ R26/ R27/ C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 PCF8578
14
Philips Semiconductors
LCD row/column driver for dot matrix graphic displays
APPLICATION INFORMATION
30
SDA SCL SYNC CLK VSS TEST SA0 OSC V DD V2 V3 V4 R31/ R30/ R29/ R28/ V5 VLCD n.c. n.c. C39 C38 C37 C36 C35 C34 C33 C32 C31 C30 C29 C28 R OSC
MSA844
Product specification
PCF8578
Fig.22 Stand-alone application using 8 rows and 32 columns.
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R0
f e g c d dp a b
Philips Semiconductors
LCD row/column driver for dot matrix graphic displays
PCF8578: Segment Driver Application one line of 24 digits 7 segment one line of 12 digits star-burst (mux 1:16) Total: 384 segments
R7 R8
LCD
R15 1 12
(Using 1:16 mux, the first character data must be loaded in bank 0 and 1 starting at byte number 16) 0
C16
C17
C39
FR
DISPLAY RAM PCF8578
,,, , ,, ,, ,,
16 17 1-byte
ALTERNATE DISPLAY BANK ALTERNATE DISPLAY BANK
(1)
,, ,,,, ,,
39 Bank 0 1 2 3
EE
R
AM
a LSB b f g c e d dp MSB
31
MLB423
Product specification
PCF8578
(1) Can be used for creating blinking characters.
Fig.23 Segment driver application for up to 384 segments.
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V DD V DD C C C C C R V2 R V3 (4 2 3)R V4 R V5 R VLCD PCF8578 (ROW MODE) 8 unused columns 40 columns subaddress 0 40 columns subaddress 1 40 columns subaddress k 1 32 rows
Philips Semiconductors
LCD row/column driver for dot matrix graphic displays
LCD DISPLAY
1:32 multiplex rate 32 x 40 x k dots (k (20480 dots max.)
16)
SA0
VSS
V DD
V DD VLCD 1 PCF8579
A0 A1 A2
V DD
V DD VLCD V3 2 PCF8579
A0 A1 A2
V DD
V DD VLCD V3 V4 k PCF8579
A0 A1 A2 A3
VLCD VSS
VSS
OSC R OSC VSS
V3
32
V DD SCL SDA
SDA SCL CLK SYNC
A3 V4 VSS SYNC CLK SCL SDA SA0 VSS VSS
A3 V4 VSS SYNC CLK SCL SDA SA0 VSS VSS
VSS SYNC CLK SCL SDA SA0 VSS VSS
MSA845
Product specification
PCF8578
Fig.24 Typical LCD driver system with 1 : 32 multiplex rate.
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V DD VSS V DD VSS V DD VSS SA0 SDA SCL CLK SYNC VSS A3 V3 A2 k V4 PCF8579 A1 V LCD A0 40 columns V DD V DD subaddress 1 SA0 SDA SCL CLK SYNC VSS A3 V3 A2 V4 2 PCF8579 A1 VLCD A0 40 columns 1:16 multiplex rate 16 x 40 x k dots (k (10240 dots max.) 1:16 multiplex rate 16 x 40 x k dots (k (10240 dots max.) 40 columns V DD V DD subaddress 0 SA0 SDA SCL CLK SYNC VSS A3 V3 A2 A1 A0 40 columns 1 PCF8579 V4 VLCD V DD V DD subaddress k 1 V DD 16 V DD C C C C C R V2 R V3 R V4 R V5 R V LCD VLCD VSS VSS OSC R OSC VSS V DD PCF8578 (ROW MODE) 8 unused columns V DD VSS / V DD V DD VLCD V3 V4 1 PCF8579 rows rows 16
Philips Semiconductors
LCD row/column driver for dot matrix graphic displays
LCD DISPLAY
16)
33
SCL SDA
16)
subaddress 0
40 columns
subaddress 1
40 columns
subaddress k 1
SA0
A0 A1 A2 A3
V DD
V DD VLCD V3 2 PCF8579
A0 A1 A2
V DD
V DD VLCD V3 k PCF8579
A0 A1 A2
SDA SCL CLK SYNC
VSS SYNC CLK SCL SDA SA0 VSS VSS
V4 A3 VSS SYNC CLK SCL SDA SA0 VSS VSS
V4 A3 VSS SYNC CLK SCL SDA SA0 VSS VSS
MSA847
Product specification
PCF8578
Fig.25 Split screen application with 1 : 16 multiplex rate for improved contrast.
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V DD VSS V DD VSS V DD VSS SA0 SDA SCL CLK SYNC VSS A3 V3 A2 k V4 PCF8579 A1 V LCD A0 40 columns V DD V DD subaddress 1 SA0 SDA SCL CLK SYNC VSS A3 V3 A2 V4 2 PCF8579 A1 VLCD A0 40 columns 1:32 multiplex rate 32 x 40 x k dots (k (20480 dots max.) 1:32 multiplex rate 32 x 40 x k dots (k (20480 dots max.) 40 columns V DD V DD subaddress 0 SA0 SDA SCL CLK SYNC VSS A3 V3 A2 V4 1 PCF8579 A1 VLCD A0 40 columns V DD V DD subaddress k 1 V DD V DD C C C V4 C C R V5 R V LCD VLCD VSS VSS OSC R OSC VSS V DD PCF8578 (ROW MODE) R V2 R (4 2 3)R V3 8 unused columns V DD VSS / V DD V DD VLCD V3 V4 1 PCF8579 32 rows
Philips Semiconductors
LCD row/column driver for dot matrix graphic displays
LCD DISPLAY
16) 32 16)
34
SCL SDA
subaddress 0
40 columns
subaddress 1
40 columns
subaddress k 1
SA0
A0 A1 A2 A3
V DD
V DD VLCD V3 2 PCF8579
A0 A1 A2
V DD
V DD VLCD V3 k PCF8579
A0 A1 A2
SDA SCL CLK SYNC
VSS SYNC CLK SCL SDA SA0 VSS VSS
V4 A3 VSS SYNC CLK SCL SDA SA0 VSS VSS
V4 A3 VSS SYNC CLK SCL SDA SA0 VSS VSS
MSA846
Product specification
PCF8578
Fig.26 Split screen application with 1 : 32 multiplex rate.
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SDA (4 2 3)R R R R OSC R R n.c. n.c.
Philips Semiconductors
LCD row/column driver for dot matrix graphic displays
VSS SCL V DD V LCD R0
LCD DISPLAY
PCF8578
35
R31/C31 C0 C27 C28 C39 C0 C27 C28 C39
PCF8579
PCF8579
Fig.27 Example of single plane wiring, single screen with 1 : 32 multiplex rate (PCF8578 in row driver mode).
n. c.
n. c.
Product specification
to other PCF8579s
PCF8578
MSA852
Philips Semiconductors
Product specification
LCD row/column driver for dot matrix graphic displays
15 CHIP DIMENSIONS AND BONDING PAD LOCATIONS
PCF8578
y SYNC TEST SDA VSS CLK SA0 SCL R0 R1 R2 R3 51 R4 50 49 48 47 46 VDD V2 V3 V4 V5 4.88 mm VLCD 9 10 11 12 43 13 14 42 0 0 41 40 39 38 37 C39 C38 C37 C36 C35 15 16 17 18 19 20 C34 21 C33 22 C32 23 R31/C31 24 R30/C30 25 R29/C29 26 R28/C28 27 R27/C27 28 R26/C26 29 R25/C25 30 R24/C24 R13/C13 R14/C14 R15/C15 R16/C16 R17/C17 R18/C18 R19/C19 R20/C20 R21/C21 R22/C22 R12/C12 x R11/C11 44 R10/C10 45 R5 R6 R7 R8/C8 R9/C9 36 35 34 33 32 31 R23/C23
MBH589
7
6
5
4
3
2
1
54
53
52
OSC
8
PCF8578
3.06 mm
Chip area: 14.93 mm2. Bonding pad dimensions: 120 µm × 120 µm. The numbers given in the small squares refer to the pad numbers.
Fig.28 Bonding pad locations.
2003 Apr 14
36
Philips Semiconductors
Product specification
LCD row/column driver for dot matrix graphic displays
PCF8578
Table 15 Bonding pad locations (dimensions in µm); all x/y coordinates are referenced to centre of chip, see Fig.28 PINS PAD NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 SYMBOL SDA SCL SYNC CLK VSS TEST SA0 OSC VDD V2 V3 V4 V5 VLCD C39 C38 C37 C36 C35 C34 C33 C32 R31/C31 R30/C30 R29/C29 R28/C28 R27/C27 R26/C26 R25/C25 R24/C24 R23/C23 R22/C22 R21/C21 R20/C20 R19/C19 R18/C18 R17/C17 R16/C16 x 174 −30 −234 −468 −726 −1014 −1308 −1308 −1308 −1308 −1308 −1308 −1308 −1308 −1308 −1308 −1308 −1308 −1308 −1308 −1014 −726 −468 −234 −30 174 468 672 876 1080 1308 1308 1308 1308 1308 1308 1308 1308 y VSO56 2241 2241 2241 2241 2241 2241 2241 1917 1113 873 663 459 255 51 −1149 −1353 −1557 −1773 −1995 −2241 −2241 −2241 −2241 −2241 −2241 −2241 −2241 −2241 −2241 −2241 −2241 −1977 −1731 −1515 −1305 −1101 −897 −693 1 2 3 4 5 6 7 8 9 10 11 12 13 14 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 LQFP64 7 8 9 10 11 12 13 16 20 21 22 23 24 25 29 30 31 32 33 34 35 37 38 39 40 41 42 43 44 45 46 48 49 50 51 52 53 54
2003 Apr 14
37
Philips Semiconductors
Product specification
LCD row/column driver for dot matrix graphic displays
PINS PAD NUMBER 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 − SYMBOL R15/C15 R14/C14 R13/C13 R12/C12 R11/C11 R10/C10 R9/C9 R8/C8 R7 R6 R5 R4 R3 R2 R1 R0 n.c. x 1308 1308 1308 1308 1308 1308 1308 1308 1308 1308 1308 1308 1080 876 672 468 − y VSO56 −489 −285 −81 123 351 603 1101 1305 1515 1731 1977 2241 2241 2241 2241 2241 − 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 15, 16
PCF8578
LQFP64 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 14, 15, 17 to 19, 26 to 28, 36, 47
2003 Apr 14
38
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C 39 C 38
16 CHIP-ON-GLASS INFORMATION
Philips Semiconductors
LCD row/column driver for dot matrix graphic displays
VDD V3 V4 VLCD VSS CLK SYNC SCL SDA
VDD
SC
R O
SA TE ST
0 O SC
D
V D
A3 A2 A1
VS S C LK C SY N SC L SD A R 0 R 1 R 2
V V2 3
V 4
A0
V3 V4 VLCD
SA 0 TE
V V5 LC D
ST D V D
VS S C LK C SY N SC L SD A C 0 C 1
VSS
c.
n.
CLK SYNC SCL SDA
C
39
C
38
V V4 LC D
V 3
PCF8578
PCF8579
R0 to R31
C0
C1
C2
C
37
Product specification
LCD DISPLAY
MSA850
PCF8578
If inputs SA0 and A0 to A3 are left unconnected they are internally pulled to VDD.
Fig.29 Typical chip-on-glass application (viewed from the underside of the chip).
Philips Semiconductors
Product specification
LCD row/column driver for dot matrix graphic displays
17 PACKAGE OUTLINES VSO56: plastic very small outline package; 56 leads
PCF8578
SOT190-1
D
E
A X
c y HE vM A
Z 56 29
Q A2 A1 pin 1 index Lp L 1 e bp 28 wM detail X (A 3) θ A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 3.3 0.13 A1 0.3 0.1 0.012 0.004 A2 3.0 2.8 0.12 0.11 A3 0.25 0.01 bp 0.42 0.30 c 0.22 0.14 D (1) 21.65 21.35 E (2) 11.1 11.0 e 0.75 HE 15.8 15.2 L 2.25 Lp 1.6 1.4 Q 1.45 1.30 v 0.2 w 0.1 y 0.1 Z (1) 0.90 0.55 θ
0.017 0.0087 0.85 0.012 0.0055 0.84
0.44 0.62 0.0295 0.43 0.60
0.063 0.089 0.055
0.057 0.035 0.008 0.004 0.004 0.051 0.022
7 0o
o
Notes 1. Plastic or metal protrusions of 0.3 mm (0.012 inch) maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT190-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION
ISSUE DATE 97-08-11 03-02-19
2003 Apr 14
40
Philips Semiconductors
Product specification
LCD row/column driver for dot matrix graphic displays
PCF8578
LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm
SOT314-2
c
y X A 48 49 33 32 ZE
e E HE wM bp 64 1 pin 1 index 16 ZD bp D HD wM B vM B vM A 17 detail X L Lp A A2 A1 (A 3) θ
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.20 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.18 0.12 D (1) 10.1 9.9 E (1) 10.1 9.9 e 0.5 HD HE L 1 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 1.45 1.05 1.45 1.05 θ 7 0o
o
12.15 12.15 11.85 11.85
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT314-2 REFERENCES IEC 136E10 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-01-19 03-02-25
2003 Apr 14
41
Philips Semiconductors
Product specification
LCD row/column driver for dot matrix graphic displays
18 SOLDERING 18.1 Introduction to soldering surface mount packages
PCF8578
If wave soldering is used the following conditions must be observed for optimal results: • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 18.4 Manual soldering
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 18.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferably be kept: • below 220 °C for all the BGA packages and packages with a thickness ≥ 2.5mm and packages with a thickness
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