PCF8593

INTEGRATED CIRCUITS DATA SH EET PCF8593 Low power clock/calendar Product specification Supersedes data of July 1994 File under Integrated Circuits, IC12 1997 Mar 25 Philips Semiconductors Product specification Low power clock/calendar CONTENTS 1 2 3 4 5 6 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.10.1 7.11 8 8.1 8.2 8.3 8.4 9 9.1 9.2 FEATURES GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Counter function modes Alarm function modes Control/status register Counter registers Alarm control register Alarm registers Timer Event counter mode Interrupt output Oscillator and divider Designing Initialization (see Fig.12) CHARACTERISTICS OF THE Bit transfer Start and stop conditions System configuration Acknowledge I2C-BUS PROTOCOL Addressing Clock/calendar READ/WRITE cycles I2C-BUS 10 11 12 13 14 14.1 14.1.1 14.1.2 14.1.3 15 16 16.1 16.2 16.2.1 16.2.2 16.3 16.3.1 16.3.2 16.3.3 17 18 19 LIMITING VALUES HANDLING DC CHARACTERISTICS AC CHARACTERISTICS PCF8593 APPLICATION INFORMATION Quartz frequency adjustment Method 1: Fixed OSCI capacitor Method 2: OSCI Trimmer Method 3: direct output PACKAGE OUTLINES SOLDERING Introduction DIP Soldering by dipping or by wave Repairing soldered joints SO Reflow soldering Wave soldering Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS 1997 Mar 25 2 Philips Semiconductors Product specification Low power clock/calendar 1 FEATURES • I2C-bus interface operating supply voltage: 2.5 to 6.0 V • Clock operating supply voltage (Tamb = 0 to +70 °C): 1.0 to 6.0 V • 8 bytes scratchpad RAM (when alarm not used) • Data retention voltage: 1.0 to 6.0 V • External RESET input resets I2C interface (only) • Operating current (fscl = 0 Hz, 32 kHz time base, VDD = 2.0 V): typ. 1 µA • Clock function with four year calendar • Universal timer with alarm and overflow indication • 24 or 12 hour format • 32.768 kHz or 50 Hz time base • Serial input/output bus (I2C-bus) • Automatic word address incrementing • Programmable alarm, timer and interrupt function • Space-saving SO8 package available • Slave address: – READ A3 – WRITE A2. 3 QUICK REFERENCE DATA SYMBOL VDD IDD IDD Tamb Tstg PARAMETER supply voltage operating mode supply current operating mode supply current clock mode operating ambient temperature storage temperature CONDITIONS I2C-bus active I2C-bus inactive fscl = 100 kHz fscl = 0 Hz; VDD = 5 V fscl = 0 Hz; VDD = 2 V MIN. 2.5 1.0 − − − −40 −65 − − − 4.0 1.0 − − TYP. 2 GENERAL DESCRIPTION PCF8593 The PCF8593 is a CMOS clock/calendar circuit, optimized for low power consumption. Addresses and data are transferred serially via the two-line bidirectional I2C-bus. The built-in word address register is incremented automatically after each written or read data byte. The built-in 32.768 kHz oscillator circuit and the first 8 bytes of RAM are used for the clock/calendar and counter functions. The next 8 bytes may be programmed as alarm registers or used as free RAM space. MAX. 6.0 6.0 200 15.0 8.0 +85 +150 V V UNIT µA µA µA °C °C 4 ORDERING INFORMATION TYPE NUMBER PCF8593P PCF8593T PACKAGE NAME DIP8 SO8 DESCRIPTION plastic dual in-line package; 8 leads (300 mil) plastic small outline package; 8 leads; body width 3.9 mm VERSION SOT97-1 SOT96-1 1997 Mar 25 3 Philips Semiconductors Product specification Low power clock/calendar 5 BLOCK DIAGRAM PCF8593 handbook, full pagewidth VDD 8 OSCI OSCO INT 1 2 7 OSCILLATOR 32.768 kHz DIVIDER 1 : 256 100 : 128 100 Hz control/status hundredths of a second seconds minutes hours year/date weekdays/months timer alarm control 00 01 RESET 3 RESET CONTROL LOGIC PCF8593 SCL SDA 6 5 I C-BUS INTERFACE 2 07 08 ADDRESS REGISTER alarm registers or RAM 0F 4 MBD808 V SS Fig.1 Block diagram. 6 PINNING SYMBOL OSCI OSCO RESET VSS SDA SCL INT VDD PIN 1 2 3 4 5 6 7 8 DESCRIPTION oscillator input, 50 Hz or event-pulse input oscillator output reset input (active LOW) negative supply serial data input/output serial clock input open drain interrupt output (active LOW) positive supply OSCI OSCO RESET V SS 1 2 3 4 MBD809 8 PCF8593P PCF8593T 7 6 5 V DD INT SCL SDA Fig.2 Pin configuration. 1997 Mar 25 4 Philips Semiconductors Product specification Low power clock/calendar 7 FUNCTIONAL DESCRIPTION PCF8593 a second, seconds, minutes, hours or days. Days are counted when an alarm is not programmed. Whenever an alarm event occurs the alarm flag of the control/status register is set. A timer alarm event will set the alarm flag and an overflow condition of the timer will set the timer flag. The open-drain interrupt output is switched on (active LOW) when the alarm or timer flag is set (enabled). The flags remain set until directly reset by a write operation. When the alarm is disabled (Bit 2 of control/status register = 0) the alarm registers at addresses 08 to 0F may be used as free RAM. 7.3 Control/status register The PCF8593 contains sixteen 8-bit registers with an 8-bit auto-incrementing address register, an on-chip 32.768 kHz oscillator circuit, a frequency divider and a serial two-line bidirectional I2C-bus interface. The first 8 registers (memory addresses 00 to 07) are designed as addressable 8-bit parallel registers. The first register (memory address 00) is used as a control/status register. The memory addresses 01 to 07 are used as counters for the clock function. The memory addresses 08 to 0F may be programmed as alarm registers or used as free RAM locations. 7.1 Counter function modes When the control/status register is programmed, a 32.768 kHz clock mode, a 50 Hz clock mode or an event-counter mode can be selected. In the clock modes the hundredths of a second, seconds, minutes, hours, date, month (four year calendar) and weekday are stored in a BCD format. The timer register stores up to 99 days. The event counter mode is used to count pulses applied to the oscillator input (OSCO left open-circuit). The event counter stores up to 6 digits of data. When one of the counters is read (memory locations 01 to 07), the contents of all counters are strobed into capture latches at the beginning of a read cycle. Therefore, faulty reading of the count during a carry condition is prevented. When a counter is written, other counters are not affected. 7.2 Alarm function modes The control/status register is defined as the memory location 00 with free access for reading and writing via the I2C-bus. All functions and options are controlled by the contents of the control/status register (see Fig.3). 7.4 Counter registers In the clock modes 24 h or 12 h format can be selected by setting the most significant bit of the hours counter register. The format of the hours counter is shown in Fig.5. The year and date are packed into memory location 05 (see Fig 6). The weekdays and months are packed into memory location 06 (see Fig.7). When reading these memory locations the year and weekdays are masked out when the mask flag of the control/status register is set. This allows the user to read the date and month count directly. In the event-counter mode events are stored in BCD format. D5 is the most significant and D0 the least significant digit. The divider is by-passed. In the different modes the counter registers are programmed and arranged as shown in Fig.4. Counter cycles are listed in Table 1. By setting the alarm enable bit of the control/status register the alarm control register (address 08) is activated. By setting the alarm control register a dated alarm, a daily alarm, a weekday alarm or a timer alarm may be programmed. In the clock modes, the timer register (address 07) may be programmed to count hundredths of 1997 Mar 25 5 Philips Semiconductors Product specification Low power clock/calendar PCF8593 handbook, full pagewidth MSB 7 6 5 4 3 2 1 LSB 0 memory location 00 timer flag (50% duty factor seconds flag if alarm enable bit is 0) alarm flag (50% duty factor minutes flag if alarm enable bit is 0) alarm enable bit: 0 alarm disabled: flags toggle alarm control register disabled (memory locations 08 to 0F can be treated as RAM) 1 enable Alarm Control register (memory location 08 is the Alarm Control register) mask flag: 0 read locations 05 to 06 unmasked 1 read date and month count directly function mode : 00 clock mode 32.768 kHz 01 clock mode 50 Hz 10 event-counter mode 11 test modes hold last count flag : 0 count 1 store and hold last count in capture latches stop counting flag : 0 count pulses 1 stop counting, reset divider MBD810 Fig.3 Control/status register. 1997 Mar 25 6 Philips Semiconductors Product specification Low power clock/calendar PCF8593 handbook, full pagewidth control/status hundredths of a second 1/10 s 1/100 s seconds 10 s 1s minutes 10 min 1 min hours 10 h 1h year/date 10 day 1 day weekday/month 10 month 1 month timer 10 day 1 day alarm control hundredths of a second 1/10 s 1/100 s alarm seconds alarm minutes alarm hours control/status D1 D3 D5 free free free T1 timer T0 D0 D2 D4 00 01 02 03 04 05 06 07 08 alarm control alarm D1 D3 D5 free alarm D0 D2 D4 09 0A 0B 0C 0D 0E 0F alarm date free free alarm timer EVENT COUNTER alarm month alarm timer CLOCK MODES MBD811 Fig.4 Register arrangement. 1997 Mar 25 7 Philips Semiconductors Product specification Low power clock/calendar PCF8593 handbook, full pagewidth MSB 7 6 5 4 3 2 1 LSB 0 memory location 04 (hours counter) unit hours BCD ten hours (0 to 12 binary) AM/PM flag: 0 AM 1 PM format: 0 24 h format, AM/PM flag remains unchanged 1 12 h format, AM/PM flag will be updated MBD812 Fig.5 Format of the hours counter. handbook, full pagewidth MSB 7 6 5 4 3 2 1 LSB 0 memory location 05 (year/date) unit hours BCD ten days (0 to 3 binary) year (0 to 3 binary, read as 0 if the mask flag is set) MBD813 Fig.6 Format of the year/date counter. handbook, full pagewidth MSB 7 6 5 4 3 2 1 LSB 0 memory location 06 (weekdays/months) unit months BCD ten months weekdays (0 to 6 binary, read as 0 if the mask flag is set) MBD814 Fig.7 Format of the weekdays/months counter. 1997 Mar 25 8 Philips Semiconductors Product specification Low power clock/calendar Table 1 Cycle length of the time counters, clock modes. UNIT Hundredths of a second Seconds Minutes Hours (24 h) Hours (12 h) COUNTING CYCLE 00 to 99 00 to 59 00 to 59 00 to 23 12 AM 01 AM to 11 AM 12 PM 01 PM to 11 PM Date 01 to 31 01 to 30 01 to 29 01 to 28 Months Year Weekdays Timer 7.5 01 to 12 0 to 3 0 to 6 00 to 99 Alarm control register CARRY TO NEXT UNIT 99 to 00 59 to 00 59 to 00 23 to 00 − − − 11 PM to 12 AM 31 to 01 30 to 01 29 to 01 28 to 01 12 to 01 − 6 to 0 no carry − − − − − − − − PCF8593 CONTENTS OF THE MONTH COUNTER 1, 3, 5, 7, 8, 10 and 12 4, 6, 9 and 11 2, year = 0 2, year = 1, 2 and 3 − − − − When the alarm enable bit of the control/status register is set (address 00, bit 2) the alarm control register (address 08) is activated. All alarm, timer, and interrupt output functions are controlled by the contents of the alarm control register (see Fig.8). 7.6 Alarm registers An alarm signal is generated when the contents of the alarm registers matches bit-by-bit the contents of the involved counter registers. The year and weekday bits are ignored in a dated alarm. A daily alarm ignores the month and date bits. When a weekday alarm is selected, the contents of the alarm weekday/month register will select the weekdays on which an alarm is activated (see Fig.9). Remark: in the 12 h mode, bits 6 and 7 of the alarm hours register must be the same as the hours counter. All alarm registers are allocated with a constant address offset of hexadecimal 08 to the corresponding counter registers (see Fig.4,Register arrangement). 1997 Mar 25 9 Philips Semiconductors Product specification Low power clock/calendar PCF8593 handbook, full pagewidth MSB 7 6 5 4 3 2 1 LSB 0 memory location 08 timer function : 000 001 010 011 100 101 110 111 no timer hundredths of a second seconds minutes hours days not used test mode, all counters in parallel timer interrupt enable : 0 1 timer flag, no interrupt timer flag, interrupt clock alarm function : 00 01 10 11 no clock alarm daily alarm weekday alarm dated alarm timer alarm enable : 0 1 no timer alarm timer alarm alarm interrupt enable : MBD815 (valid only when 'alarm enable' in control/status register is set) 0 1 alarm flag, no interrupt alarm flag, interrupt Fig.8 Alarm control register, clock mode. 1997 Mar 25 10 Philips Semiconductors Product specification Low power clock/calendar PCF8593 handbook, full pagewidth MSB 7 6 5 4 3 2 1 LSB 0 memory location 0E (alarm weekday/month) weekday 0 enabled when set weekday 1 enabled when set weekday 2 enabled when set weekday 3 enabled when set weekday 4 enabled when set weekday 5 enabled when set weekday 6 enabled when set not used MBD816 Fig.9 Selection of alarm weekdays. 7.7 Timer 7.8 Event counter mode The timer (location 07) is enabled by setting the control/status register = XX0X X1XX. The timer counts up from 0 (or a programmed value) to 99. On overflow, the timer resets to 0. The timer flag (LSB of control/status register) is set on overflow of the timer. This flag must be reset by software. The inverted value of this flag can be transferred to the external interrupt by setting bit 3 of the alarm control register. Additionally, a timer alarm can be programmed by setting the timer alarm enable (bit 6 of the alarm control register). When the value of the timer equals a pre-programmed value in the alarm timer register (location 0F), the alarm flag is set (bit 1 of the control/status register). The inverted value of the alarm flag can be transferred to the external interrupt by enabling the alarm interrupt (bit 6 of the alarm control register). Resolution of the timer is programmed via the 3 LSBs of the alarm control register (see Fig.11, Alarm and timer Interrupt logic diagram). Event counter mode is selected by bits 4 and 5 which are logic 1, 0 in the control/status register. The event counter mode is used to count pulses externally applied to the oscillator input (OSCO left open-circuit). The event counter stores up to 6 digits of data, which are stored as 6 hexadecimal values located in locations 1, 2, and 3. Thus, up to 1 million events may be recorded. An event counter alarm occurs when the event counter registers match the value programmed in locations 9, A, and B, and the event alarm is enabled (bits 4 and 5 which are logic 0, 1 in the alarm control register). In this event, the alarm flag (bit 1 of the control/status register) is set. The inverted value of this flag can be transferred to the interrupt pin (pin 7) by setting the alarm interrupt enable in the alarm control register. In this mode, the timer (location 07) increments once for every one, one-hundred, ten thousand, or 1 million events, depending on the value programmed in bits 0,1 and 2 of the alarm control register. In all other events, the timer functions are as in the clock mode. 1997 Mar 25 11 Philips Semiconductors Product specification Low power clock/calendar PCF8593 handbook, full pagewidth MSB 7 6 5 4 3 2 1 LSB 0 memory location 08 timer function : 000 001 010 011 100 101 110 111 no timer units 100 10 000 1 000 000 not allowed not allowed test mode, all counters in parallel timer interrupt enable : 0 1 timer flag, no interrupt timer flag, interrupt clock alarm function : 00 no event alarm 01 event alarm 10 not allowed 11not allowed timer alarm enable : 0 1 no timer alarm timer alarm alarm interrupt enable : MBD817 0 1 alarm flag, no interrupt alarm flag, interrupt Fig.10 Alarm control register, event-counter mode. 7.9 Interrupt output The conditions for activating the open-drain n-channel interrupt output INT (active LOW) are determined by appropriate programming of the alarm control register. These conditions are clock alarm, timer alarm, timer overflow, and event counter alarm. An interrupt occurs when the alarm flag or the timer flag is set, and the corresponding interrupt is enabled. In all events, the interrupt is cleared only by software resetting of the flag which initiated the interrupt. In the clock mode, if the alarm enable is not activated (alarm enable bit of control/status register is logic 0), the interrupt output toggles at 1 Hz with a 50% duty cycle (may be used for calibration). The OFF voltage of the interrupt output may exceed the supply voltage, up to a maximum of 6.0 V. A logic diagram of the interrupt output is shown in Fig.11. 1997 Mar 25 12 Philips Semiconductors Product specification Low power clock/calendar PCF8593 handbook, full pagewidth MUX mode select oscillator counter control CLOCK/CALENDAR ALARM TIMER clock alarm alarm control timer alarm overflow timer control 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CONTROL/STATUS REGISTER (1) ALARM CONTROL REGISTER alarm interrupt timer overflow interrupt INT MBD818 (1) If the alarm enable bit of the control/status register is reset (logic 0), a 1 Hz signal can be observed on the interrupt pin INT. Fig.11 Alarm and timer interrupt logic diagram. 1997 Mar 25 13 Philips Semiconductors Product specification Low power clock/calendar 7.10 Oscillator and divider PCF8593 A 32.768 kHz quartz crystal has to be connected to OSCI (pin 1) and OSCO (pin 2). A trimmer capacitor between OSCI and VDD is used for tuning the oscillator (see Chapter 14, Section 14.1). A 100 Hz clock signal is derived from the quartz oscillator for the clock counters. In the 50 Hz clock mode or event-counter mode the oscillator is disabled and the oscillator input is switched to a high-impedance state. This allows the user to feed the 50 Hz reference frequency or an external high-speed event signal into the input OSCI. 7.10.1 DESIGNING handbook, halfpage VDD 8 RR reset input VDD 3 RESET CR PCF8593 When designing the printed-circuit board layout, keep the oscillator components as close to the IC package as possible, and keep all other signal lines as far away as possible. In applications involving tight packing of components, shielding of the oscillator may be necessary. AC coupling of extraneous signals can introduce oscillator inaccuracy. 7.11 Initialization (see Fig.12) MBD819 To avoid overload of the internal diode by falling VDD, an external diode should be added in parallel to RR if CR ≥ 0.2 µF. Note that RC must be evaluated with the actual VDD of the application, as their value will be VDD rise-time dependent. Fig.12 RC reset. Note that immediately following power-on, all internal registers are undefined and, following a RESET pulse on pin 3, must be defined via software. Attention should be paid to the possibility that the device may be initially in event-counter mode, in which event the oscillator will not operate. Over-ride can be achieved via software. Reset is accomplished by applying an external RESET pulse (active LOW) at pin 3. When reset occurs only the I2C-bus interface is reset. The control/status register and all clock counters are not affected by RESET. RESET must return HIGH during device operation. An RC combination can also be utilized to provide a power-on RESET signal at pin 3. In this event, the values of the RC must fulfil the following relationship to guarantee power-on reset (see Fig.12). RESET input must be ≤0.3VDD when VDD reaches VDDmin (or higher). It is recommended to set the stop counting flag of the control/status register before loading the actual time into the counters. Loading of illegal states may lead to a temporary clock malfunction. 1997 Mar 25 14 Philips Semiconductors Product specification Low power clock/calendar 8 CHARACTERISTICS OF THE I2C-BUS PCF8593 The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy. 8.1 Bit transfer (see Fig.13) One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal. SDA SCL data line stable; data valid change of data allowed MBC621 Fig.13 Bit transfer. 8.2 Start and stop conditions (see Fig.14) Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P). SDA SDA SCL S START condition P STOP condition SCL MBC622 Fig.14 Definition of start and stop conditions. 1997 Mar 25 15 Philips Semiconductors Product specification Low power clock/calendar 8.3 System configuration (see Fig.15) PCF8593 A device generating a message is a ‘transmitter’, a device receiving a message is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’. SDA SCL MASTER TRANSMITTER / RECEIVER SLAVE TRANSMITTER / RECEIVER MASTER TRANSMITTER / RECEIVER MBA605 SLAVE RECEIVER MASTER TRANSMITTER Fig.15 System configuration. 8.4 Acknowledge (see Fig.16) The number of data bytes transferred between the start and stop conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH level signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a stop condition. DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER S START CONDITION MBC602 1 2 8 9 clock pulse for acknowledgement Fig.16 Acknowledgment on the I2C-bus. 1997 Mar 25 16 Philips Semiconductors Product specification Low power clock/calendar 9 9.1 I2C-BUS PROTOCOL Addressing PCF8593 Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. The addressing is always carried out with the first byte transmitted after the start procedure. The clock/calendar acts as a slave receiver or slave transmitter. Therefore the clock signal SCL is only an input signal, but the data signal SDA is a bidirectional line. The clock/calendar slave address is shown in Fig.17. handbook, halfpage 1 0 1 0 0 0 1 R/W group 1 group 2 MBD821 Fig.17 Slave address. 9.2 The Clock/calendar READ/WRITE cycles I2C-bus configuration for the different PCF8593 READ and WRITE cycles is shown in Figs 18, 19 and 20. handbook, full pagewidth acknowledgement from slave acknowledgement from slave acknowledgement from slave S SLAVE ADDRESS 0A WORD ADDRESS A DATA A P R/W n bytes auto increment memory word address MBD822 Fig.18 Master transmits to slave receiver (WRITE) mode. 1997 Mar 25 17 Philips Semiconductors Product specification Low power clock/calendar PCF8593 handbook, full pagewidth acknowledgement from slave acknowledgement from slave acknowledgement from slave acknowledgement from master S SLAVE ADDRESS 0A WORD ADDRESS A S SLAVE ADDRESS 1A DATA A R/W at this moment master transmitter becomes master - receiver and PCF8593 slave - receiver becomes slave - transmitter R/W n bytes auto increment memory word address no acknowledgement from master DATA 1 P last byte MBD823 auto increment memory word address Fig.19 Master reads after setting word address (write word address, READ data). handbook, full pagewidth acknowledgement from slave acknowledgement from slave acknowledgement from slave S SLAVE ADDRESS 1A DATA A DATA 1 P R/W n bytes auto increment word address last bytes auto increment word address MBD824 Fig.20 Master reads slave immediately after first byte (READ mode). 1997 Mar 25 18 Philips Semiconductors Product specification Low power clock/calendar 10 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD IDD ISS VI II IO Ptot PO Tamb Tstg supply voltage (pin 8) supply current (pin 8) supply current (pin 4) input voltage input current DC output current total power dissipation per package power dissipation per output operating ambient temperature storage temperature PARAMETER −0.8 − − −0.8 − − − − −40 −65 MIN. +7.0 50 50 PCF8593 MAX. UNIT V mA mA V mA mA mW mW °C °C VDD + 0.8 10 10 300 50 +85 +150 11 HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take precautions appropriate to handling MOS devices Advice can be found in Data Handbook IC12 under “Handling MOS Devices”. 12 DC CHARACTERISTICS VDD = 2.5 to 6.0 V; VSS = 0 V; Tamb = −40 to +85 °C; fosc = 32 kHz; unless otherwise specified. SYMBOL Supply VDD VDDosc supply voltage (operating mode) supply voltage (quartz oscillator) I2C-bus active I2C-bus note 2 Tamb = 0 to 70 °C Tamb = −40 to 85 °C IDD IDDO supply current (operating mode) supply current (clock mode with I2C-bus inactive) fscl = 100 kHz; clock mode; note 3 fscl = 0 Hz; inputs at VDD or VSS VDD = 2 V VDD = 5 V SDA, SCL, INT and RESET VIL VIH IOL ILI LOW level input voltage HIGH level input voltage LOW level output current input leakage current VOL = 0.4 V VI = VDD or VSS 0 0.7VDD 3 −1 − − − − 0.3VDD VDD − +1 V V mA µA − − 1.0 4.0 8.0 15 µA µA 1.0 1.2 − − − − 6.0 6.0 200 V V µA inactive 2.5 1.0 − − 6.0 6.0 V V PARAMETER CONDITIONS MIN. TYP.(1) MAX. UNIT 1997 Mar 25 19 Philips Semiconductors Product specification Low power clock/calendar PCF8593 SYMBOL Ci ILI INT IOL ILI SCL Ci ILI Notes PARAMETER input capacitance note 4 CONDITIONS − MIN. TYP.(1) − − − − − − 7 MAX. UNIT pF OSCI and RESET input leakage current Vl = VDD or VSS VOL = 0.4 V Vl = VDD or VSS note 4 VI = VDD or VSS −250 +250 − +1 nA LOW level output current input leakage current 1 −1 − −1 mA µA input capacitance input leakage current 7 +1 pF µA 1. Typical values measured at Tamb = 25 °C. 2. When powering up the device, VDD must exceed the specified minimum value by 300 mV to guarantee correct start-up of the oscillator. 3. Event counter mode: supply current dependent upon input frequency. 4. Tested on sample basis. handbook, halfpage 12 MBD826 IDDO (µA) 8 4 0 0 2 4 VDD (V) 6 fSCL = 32 kHz; Tamb = 25 °C. Fig.21 Typical supply current in clock mode as a function of supply voltage. 1997 Mar 25 20 Philips Semiconductors Product specification Low power clock/calendar 13 AC CHARACTERISTICS VDD = 2.5 to 6.0 V; VSS = 0 V; Tamb = −40 to +85 °C; unless otherwise specified. SYMBOL Oscillator Cosc ∆fosc fi Rs CL CT I2C-bus fSCL tSP tBUF tSU;STA tHD;STA tLOW tHIGH tr tf tSU;DAT tHD;DAT tVD;DAT tSU;STO Notes 1. Event counter mode only. integrated oscillator capacitance oscillator stability input frequency for ∆VDD = 100 mV; Tamb = 25 °C; VDD = 1.5 V note 1 20 − − − − 5 − − 4.7 4.7 4.0 4.7 4.0 − − 250 0 − 4.0 25 2 × 10−7 − − 10 − − − − − − − − − − − − − − 30 − 1 PARAMETER CONDITIONS MIN. TYP. PCF8593 MAX. UNIT pF MHz kΩ pF pF Quartz crystal parameters (f = 32.768 kHz) series resistance parallel load capacitance trimmer capacitance timing (see Fig.22; notes 2 and 3) SCL clock frequency tolerable spike width on bus bus free time START condition set-up time START condition hold time SCL LOW time SCL HIGH time SCL and SDA rise time SCL and SDA fall time data set-up time data hold time SCL LOW to data out valid STOP condition set-up time 100 100 − − − − − 1.0 0.3 − − 3.4 − kHz ns µs µs µs µs µs µs µs ns ns µs µs 40 − 25 2. All timing values are valid within the operating supply voltage and ambient temperature range and reference to VIL and VIH with an input voltage swing of VSS to VDD. 3. A detailed description of the I2C-bus specification, with applications, is given in brochure “The I2C-bus and how to use it”. This brochure may be ordered using the code 9398 393 40011. 1997 Mar 25 21 Philips Semiconductors Product specification Low power clock/calendar PCF8593 handbook, full pagewidth PROTOCOL START CONDITION (S) BIT 7 MSB (A7) BIT 6 (A6) BIT 0 LSB (R/W) ACKNOWLEDGE (A) STOP CONDITION (P) t SU;STA t LOW t HIGH 1 / f SCL SCL t BUF tr tf SDA t HD;STA t SU;DAT t HD;DAT t VD;DAT MBD820 t SU;STO Fig.22 I2C-bus timing diagram; rise and fall times refer to VIL and VIH. 1997 Mar 25 22 Philips Semiconductors Product specification Low power clock/calendar 14 APPLICATION INFORMATION 14.1 14.1.1 Quartz frequency adjustment METHOD 1: FIXED OSCI CAPACITOR Procedure: • Power-on • Apply RESET • Initialization (alarm functions). Routine: PCF8593 By evaluating the average capacitance necessary for the application layout a fixed capacitor can be used. The frequency is best measured via the 1 Hz signal which can be programmed to occur at the interrupt output (pin 7). The frequency tolerance depends on the quartz crystal tolerance, the capacitor tolerance and the device-to-device tolerance (on average ±5 × 10−6). Average deviations of ±5 minutes per year can be achieved. 14.1.2 METHOD 2: OSCI TRIMMER • Set clock to time T and set alarm to time T + ∆T • At time T + ∆T (interrupt) repeat routine. 14.1.3 METHOD 3: DIRECT OUTPUT Direct measurement of oscillator output (accounting for test probe capacitance). Using the alarm function (via the I2C-bus) a signal faster than 1 Hz can be generated at the interrupt output for fast setting of a trimmer. handbook, full pagewidth RESET V DD SDA (1) 1F SCL MASTER TRANSMITTER/ RECEIVER RESET SCL CLOCK CALENDAR OSCI OSCO PCF8593 V SS SDA V DD R R R: pull-up resistor tr R= C BUS MBD825 SDA SCL (I 2C-bus) (1) Example Philips DLC 196 Double-Layer Capacitor family. Fig.23 Application diagram. 1997 Mar 25 23 Philips Semiconductors Product specification Low power clock/calendar 15 PACKAGE OUTLINES DIP8: plastic dual in-line package; 8 leads (300 mil) PCF8593 SOT97-1 D seating plane ME A2 A L A1 c Z e b1 wM (e 1) b2 5 MH b 8 pin 1 index E 1 4 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.020 A2 max. 3.2 0.13 b 1.73 1.14 0.068 0.045 b1 0.53 0.38 0.021 0.015 b2 1.07 0.89 0.042 0.035 c 0.36 0.23 0.014 0.009 D (1) 9.8 9.2 0.39 0.36 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.10 e1 7.62 0.30 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 1.15 0.045 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT97-1 REFERENCES IEC 050G01 JEDEC MO-001AN EIAJ EUROPEAN PROJECTION ISSUE DATE 92-11-17 95-02-04 1997 Mar 25 24 Philips Semiconductors Product specification Low power clock/calendar PCF8593 SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 D E A X c y HE vMA Z 8 5 Q A2 A1 pin 1 index θ Lp 1 e bp 4 wM L detail X (A 3) A 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 5.0 4.8 0.20 0.19 E (2) 4.0 3.8 0.16 0.15 e 1.27 0.050 HE 6.2 5.8 0.24 0.23 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3 θ 0.0098 0.057 0.069 0.0039 0.049 0.019 0.0098 0.014 0.0075 0.039 0.028 0.041 0.016 0.024 0.028 0.004 0.012 8 0o o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT96-1 REFERENCES IEC 076E03S JEDEC MS-012AA EIAJ EUROPEAN PROJECTION ISSUE DATE 92-11-17 95-02-04 1997 Mar 25 25 Philips Semiconductors Product specification Low power clock/calendar 16 SOLDERING 16.1 Introduction PCF8593 Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. 16.3.2 WAVE SOLDERING Wave soldering techniques can be used for all SO packages if the following conditions are observed: • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. • The longitudinal axis of the package footprint must be parallel to the solder flow. • The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 16.3.3 REPAIRING SOLDERED JOINTS There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). 16.2 16.2.1 DIP SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 16.2.2 REPAIRING SOLDERED JOINTS Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. 16.3 16.3.1 SO REFLOW SOLDERING Reflow soldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 1997 Mar 25 26 Philips Semiconductors Product specification Low power clock/calendar 17 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values PCF8593 This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 18 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 19 PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1997 Mar 25 27 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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No. 5, 80640 GÜLTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 © Philips Electronics N.V. 1997 Internet: http://www.semiconductors.philips.com SCA53 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 417067/1200/03/pp28 Date of release: 1997 Mar 25 Document order number: 9397 750 01652