PCF8820U

INTEGRATED CIRCUITS DATA SHEET PCF8820 67 × 101 Grey-scale/ECB colour dot matrix LCD driver Product specification File under Integrated Circuits, IC12 2000 Dec 07 Philips Semiconductors Product specification 67 × 101 Grey-scale/ECB colour dot matrix LCD driver CONTENTS 1 2 3 4 5 6 6.1 6.2 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.2.7 6.2.8 6.2.9 6.2.10 6.2.11 6.2.12 6.2.13 6.2.14 6.2.15 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 FEATURES APPLICATIONS GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM PINNING Pad configuration Pad functions Row driver outputs Column driver outputs Ground supply Supply voltage Voltage multiplier output Voltage multiplier regulation input Supply voltage of bias voltage generator LCD intermediate bias voltages Serial data input Serial data output Serial clock input Slave address inputs Oscillator signal input External reset input Test pads FUNCTIONAL DESCRIPTION Oscillator I2C-bus interface controller Input filters Display Data RAM (DDRAM) Timing generator Address counter Display address counter Command decoder Column driver outputs Row driver outputs Bias voltage generator High voltage generator Temperature compensation Temperature sensor LCD driver waveforms DDRAM to display mapping DDRAM addressing 7.18 7.18.1 7.18.2 7.18.3 7.18.4 7.18.5 7.18.6 7.18.7 8 8.1 8.1.1 8.1.2 8.1.3 8.1.4 8.1.5 8.1.6 8.1.7 8.1.8 8.1.9 8.1.10 8.2 9 10 11 12 13 13.1 13.2 13.3 13.4 13.5 13.6 14 15 16 17 18 19 20 21 I2C-bus interface Bit transfer START and STOP conditions System configuration Acknowledge I2C-bus protocol Command decoder Display data byte INSTRUCTIONS PCF8820 Description of the bit functions Power-down mode Partial screen mode Y-address of DDRAM Bias system High voltage generator configuration Temperature read-out VLCD control register Grey-scale register and grey-scale level Direct drive mode Frame frequency calibration Reset and initialization LIMITING VALUES HANDLING DC CHARACTERISTICS TIMING APPLICATION INFORMATION Programming example for the PCF8820 Examples of effects on the display High voltage generator Application for COG Typical system configuration External supply of VLCDIN BONDING PAD INFORMATION DEVICE PROTECTION CIRCUITS TRAY INFORMATION DATA SHEET STATUS DEFINITIONS DISCLAIMERS BARE DIE DISCLAIMER PURCHASE OF PHILIPS I2C COMPONENTS 2000 Dec 07 2 Philips Semiconductors Product specification 67 × 101 Grey-scale/ECB colour dot matrix LCD driver 1 FEATURES PCF8820 • Single-chip LCD controller and driver for grey-scale/ Electrically Controlled Birefringence (ECB) colour • 4 grey levels/colours (2-bit) definable from 64 levels • 67 row and 101 column outputs • Display data RAM 67 × 101 × 2-bit with linear RAM addressing • Partial screen mode with reduced current consumption (8 rows at top or bottom of display) • On-chip: – Generation of LCD supply voltage (VLCDOUT); external supply also possible – Configurable voltage multiplier factor of 8, 7, 6, 5, 4, 3 or 2; direct drive also possible – Selectable linear temperature compensation of VLCDOUT – Generation of intermediate LCD bias voltages – Oscillator requires no external components; external clock also possible. • Temperature read-out • Fast mode I2C-bus interface (400 kbits/s) • Frame frequency calibration via software • Software selectable bias configuration • Compatible with 4-bit, 8-bit or 16-bit microcontrollers • Multiplex rates of 1 : 67 or 1 : 8 • Logic supply voltage range from 2.5 to 5.5 V (VDD1 to VSS1) • High voltage generator supply voltage range from 2.7 to 5.5 V (VDD2 to VSS1 and VDD3 to VSS2) • Bias voltage generator supply voltage range (VLCDIN to VSS1): – From 7 to 14.5 V at a multiplex rate of 1 : 67 – From 4.5 to 14.5 V in partial screen mode at a multiplex rate of 1 : 8. • Low power consumption, suitable for battery operated systems • Slim chip layout, suitable for chip-on-glass applications 4 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME PCF8820U − chip with bumps in tray DESCRIPTION VERSION − 2 APPLICATIONS • Mobile telecommunication systems • Battery powered equipment • Point of sale terminals • Instrumentation • Automotive information systems. 3 GENERAL DESCRIPTION • Software selectable top and bottom row swap for adapting driver to different glass-layouts • CMOS compatible inputs • Manufactured in silicon gate CMOS process. The PCF8820 is a low power CMOS LCD row/column driver, designed to drive grey-scale/ ECB colour dot matrix graphic displays at a multiplex rate of 1 : 67. In the partial screen mode, only 8 rows are driven at a multiplex rate of 1 : 8. This chip provides all the necessary display functions, including on-chip generation of the LCD supply voltage and LCD bias voltages. Consequently, fewer external components are required and the power consumption is low. The PCF8820 interfaces with most microcontrollers and communicates via a two-line bidirectional bus (I2C-bus). All inputs are CMOS compatible. Remark: the waveform generation for ECB colour is identical to that used for grey-scale. 2000 Dec 07 3 Philips Semiconductors Product specification 67 × 101 Grey-scale/ECB colour dot matrix LCD driver 5 BLOCK DIAGRAM PCF8820 handbook, full pagewidth V5 V4 V3 V2 C0 to C100 26 to 126 R0 to R66 3 to 25, 232 to 222, 148 to 127, 151 to 161 ROW DRIVERS 162 163 164 165 VLCDIN 166 to 171 BIAS VOLTAGE GENERATOR COLUMN DRIVERS VLCDSENSE VLCDOUT VDD1 VDD2 VDD3 VSS1 VSS2 T1 T2 T3 T4 T5 T6 SCL SDA_IN SDA_OUT RES 172 173 to 178 179 to 184 188 to 194 185 to 187 HIGH VOLTAGE GENERATOR PCF8820 OSCILLATOR 206 to 211 198 to 203 205 221 212 213 217 218 215, 216 195, 196 197 219 204 SA0 214 INPUT FILTERS I2C-BUS INTERFACE CONTROLLER COMMAND DECODER ADDRESS COUNTER DISPLAY DATA RAM (DDRAM) DISPLAY ADDRESS COUNTER TEMPERATURE SENSOR DISPLAY DATA LATCHES TIMING GENERATOR 220 OSC MGT114 SA1 Fig.1 Block diagram. 2000 Dec 07 4 Philips Semiconductors Product specification 67 × 101 Grey-scale/ECB colour dot matrix LCD driver 6 6.1 PINNING Pad configuration PAD 3 to 25 232 to 222 148 to 127 151 to 161 26 to 126 206 to 211 198 to 203 179 to 184 188 to 194 185 to 187 173 to 178 172 166 to 171 165 164 163 162 195 and 196 197 215 and 216 204 214 220 219 205 221 212 213 217 218 LCD row driver outputs (block 1) LCD row driver outputs (block 2) LCD row driver outputs (block 3) LCD row driver outputs (block 4) LCD column driver outputs ground supply 1 ground supply 2 supply voltage 1 of logic supply voltage 2 of high voltage generator; temperature read-out supply voltage 3 of high voltage generator; temperature read-out voltage multiplier output voltage multiplier regulation input supply voltage for LCD (bias voltage generator) LCD intermediate bias voltage 2; for test purposes only LCD intermediate bias voltage 3; for test purposes only LCD intermediate bias voltage 4; for test purposes only LCD intermediate bias voltage 5; for test purposes only serial data input serial data output (acknowledge) serial clock input I2C-bus slave address input 0 (bit 0) I2C-bus slave address input 1 (bit 1) oscillator signal input external reset input (active LOW) test 1 input test 2 output test 3 I/O test 4 I/O test 5 input test 6 output DESCRIPTION PCF8820 SYMBOL R0 to R22 R23 to R33 R34 to R55 R56 to R66 C0 to C100 VSS1 VSS2 VDD1 VDD2 VDD3 VLCDOUT VLCDSENSE VLCDIN V2 V3 V4 V5 SDA_IN SDA_OUT SCL SA0 SA1 OSC RES T1 T2 T3 T4 T5 T6 The pad configuration is shown in Fig.32. 2000 Dec 07 5 Philips Semiconductors Product specification 67 × 101 Grey-scale/ECB colour dot matrix LCD driver 6.2 6.2.1 Pad functions ROW DRIVER OUTPUTS PCF8820 Row driver outputs (R0 to R66) are the outputs for the LCD row drive signals. They should be connected directly to the 67 rows of the LCD. If less than 67 rows are required, the unused outputs must be left open-circuit. 6.2.2 COLUMN DRIVER OUTPUTS When an external supply voltage is used, pads VLCDIN, VLCDSENSE and VLCDOUT do not have to be connected together. However, if pads VLCDSENSE and VLCDOUT are both connected to pad VLCDIN, the current consumption can be reduced under the following conditions: • The output of VLCDOUT is set to high-impedance (see Table 8) • The HIGH voltage programming range is selected by setting bit PRS = 1, the maximum voltage multiplier on factor 8 and the VLCD control register on the maximum value (see Table 2). 6.2.8 LCD INTERMEDIATE BIAS VOLTAGES Column driver outputs (C0 to C100) are the outputs for the LCD column drive signals. They should be connected directly to the 101 columns of the LCD. If less than 101 columns are required, the unused column outputs must be left open-circuit. 6.2.3 GROUND SUPPLY The ground supply rails (VSS1 and VSS2) must be connected together. VSS1 is related to VDD1 and VDD3; VSS2 is related to VDD2. 6.2.4 SUPPLY VOLTAGE The LCD intermediate bias voltages (V2, V3, V4 and V5) which are applied to the LCD columns and rows are present on these pads for test purposes. They must be left open-circuit in the application. 6.2.9 SERIAL DATA INPUT SDA_IN is the serial data input from the I2C-bus. 6.2.10 SERIAL DATA OUTPUT The supply voltage rails (VDD1, VDD2 and VDD3) must be connected together when the same supply is used for both the logic circuits and for the voltage multiplier. When the circuits are fed separately, VDD2 and VDD3 must be connected to the same supply. 6.2.5 VOLTAGE MULTIPLIER OUTPUT SDA_OUT is the serial data output (data, acknowledge) for the I2C-bus. Connecting pad SDA_OUT to pad SDA_IN makes the SDA line fully I2C-bus compatible. Not connecting pad SDA_IN to pad SDA_OUT allows the device to be used in applications in which the acknowledge bit is not required. In Chip-On-Glass (COG) applications, it is sometimes beneficial not to connect pad SDA_OUT to pad SDA_IN. This is because in COG applications where the track resistance from pad SDA_OUT to the system SDA line is significant, a voltage divider is created by the bus pull-up resistor and the Indium Tin Oxide (ITO) track resistance. This divider could prevent the PCF8820 from asserting a valid logic 0 level during an acknowledge cycle. In COG applications, where the acknowledge cycle is required, the track resistance from the pad SDA_OUT to the system SDA line must be minimized to guarantee a valid LOW-level. 6.2.11 SERIAL CLOCK INPUT VLCDOUT is the output of the voltage multiplier of the high voltage generator. 6.2.6 VOLTAGE MULTIPLIER REGULATION INPUT VLCDSENSE is the regulation input of the high voltage multiplier and must be connected to VLCDOUT. 6.2.7 SUPPLY VOLTAGE OF BIAS VOLTAGE GENERATOR VLCD is the supply voltage on pad VLCDIN for the bias voltage generator which supplies the LCD outputs. The voltage on pad VLCDIN must not be lower than VDD1. If VLCD is generated internally, pad VLCDOUT must be connected to pad VLCDIN. If VLCD is supplied externally, the external supply voltage must be connected to pad VLCDIN. An external supply voltage must be applied after applying VDD1, and it must be removed before or when removing VDD1 (see Fig.25). It is recommended that an external supply voltage is applied after leaving the reset state. The external supply voltage can stay applied in the Power-down mode. SCL is the serial clock input from the I2C-bus. 2000 Dec 07 6 Philips Semiconductors Product specification 67 × 101 Grey-scale/ECB colour dot matrix LCD driver 6.2.12 SLAVE ADDRESS INPUTS 7.4 Display Data RAM (DDRAM) PCF8820 These inputs (SA0 and SA1) allow up to four PCF8820 drivers to be controlled on the same I2C-bus. Inputs SA0 and SA1 represent respectively bit 0 and bit 1 of the slave address. 6.2.13 OSCILLATOR SIGNAL INPUT The PCF8820 contains a 67 × 101 × 2-bit static RAM, which stores the display data. The RAM comprises 17 banks of 101 bytes (17 × 101 × 8 bits). Not all of the last bank is implemented. During RAM access, data is transferred to the RAM via the I2C-bus interface controller. 7.5 Timing generator Pad OSC must be connected directly to VDD1 when the on-chip oscillator is used. No external components are required. It should be noted that any voltage drop of VDD1 may affect the performance of the on-chip oscillator. An external clock must be connected to input OSC. 6.2.14 EXTERNAL RESET INPUT The timing generator produces the various signals required to drive the internal circuitry. Internal chip operation is not affected by operations on the I2C-bus. 7.6 Address counter A LOW-level on input RES initializes the chip. 6.2.15 TEST PADS The address counter generates write addresses to the DDRAM. During a write operation, display data is stored at the addressed locations. 7.7 Display address counter The test pads (T1, T2, T3, T4, T5 and T6) must not be accessible to the user. Pads T1, T3 and T4 must be connected to VSS1, pad T5 must be connected to VDD1, and pads T2 and T6 must be left open-circuit. 7 7.1 FUNCTIONAL DESCRIPTION Oscillator The display address counter generates read addresses to the DDRAM. During a read operation, display data is read out to the LCD. 7.8 Command decoder The command decoder receives command words which are followed by data byte(s) from the I2C-bus. The command decoder identifies the command words and determines the destination for the data byte(s). 7.9 Column driver outputs The on-chip oscillator provides the clock signal for the LCD system. The clock mode is controlled via the I2C-bus interface. A clock signal must always be present, except in the Power-down mode, to prevent the LCD entering a DC state. 7.2 I2C-bus interface controller The LCD driver section has 101 outputs (C0 to C100) which should be connected directly to the column drive inputs of the LCD. The column driver signals are generated in accordance with the multiplexed row signals and with the data in the display data latch. The programmed grey-scale levels are built-up in the LCD over four frames (N11, N12, N13 and N14) as shown in Figs 3, 4 and 5. 7.10 Row driver outputs The I2C-bus interface controller receives and executes the commands sent via the I2C-bus. The PCF8820 acts as an I2C-bus slave receiver/transmitter and therefore it cannot control the bus communication. 7.3 Input filters RC low-pass filters are provided on inputs SDA_IN, SCL and RES to enhance noise immunity in electrically adverse environments. The LCD driver section has 67 outputs (R0 to R66) which should be connected directly to the row drive inputs of the LCD. The row driver signals are generated in accordance with the selected LCD drive mode. 2000 Dec 07 7 Philips Semiconductors Product specification 67 × 101 Grey-scale/ECB colour dot matrix LCD driver 7.11 Bias voltage generator 7.14 Temperature sensor PCF8820 The bias voltage generator generates 4 buffered intermediate LCD bias voltages. It contains 4 operational amplifiers and an input reference voltage generator. It can operate in two voltage ranges: • Normal mode (from 7.0 to 14.5 V) • Partial screen mode (from 4.5 to 14.5 V). 7.12 High voltage generator The PCF8820 has a built-in temperature sensor. The sensor monitors the temperature and writes an 8-bit number into the status register. The temperature sensor and status register can both be accessed via the I2C-bus interface controller. The temperature sensor allows any temperature compensation to be implemented; any programmable parameter can be optimized as a function of the sensor read-out temperature. 7.15 LCD driver waveforms The high voltage generator contains a voltage multiplier which uses a charge pump circuit supplied by VDD2 and VDD3. The multiplier is software programmable with a factor from 2 to 8. In the direct drive mode the output voltage VLCDOUT = VDD2. 7.13 Temperature compensation The LCD waveforms are shown in Figs 3, 4 and 5. At frame inversion, the PCF8820 generates a dummy row cycle, where no row is selected. This ensures equal conditions for the first row after frame inversion as for the other rows. Therefore the effective multiplex rate in all modes is 1 : (multiplex rate + 1). 7.16 DDRAM to display mapping The viscosity of the liquid crystal depends on the temperature; so to maintain optimum contrast at lower temperatures VLCD needs usually to be increased. Fig.2 shows VLCD as a function of the temperature for a typical high multiplex rate liquid crystal. Linear temperature compensation is supported in the PCF8820. The temperature coefficient for VLCDOUT can be set to one of 8 values by setting bits TC2 to TC0. DDRAM to display mapping is shown in Fig.6. handbook, halfpage MGT123 VLCD (V) (1) (2) 0 Tamb (°C) (1) LCD characteristic. (2) Linear temperature compensation. Fig.2 LCD supply voltage as a function of the temperature. 2000 Dec 07 8 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... ook, full pagewidth 2000 Dec 07 9 Philips Semiconductors 67 × 101 Grey-scale/ECB colour dot matrix LCD driver Frame VLCD V2 V3 V5 VSS VLCD V2 V3 V5 VSS VLCD V2 V3 V5 VSS VLCD V2 V3 V5 VSS VLCD V3 VLCD − V2 0V V3 − V2 N11 N12 N13 N14 N21 state1 ROW 0 V4 R0(t) state2 ROW 1 V4 R1(t) 4 4 4 5 4 COL 0 V4 C0(t) xx79 16 x x 8 8 16 x x 7 9 16 COL 1 V4 C1(t) x x 7 9 16 x x 8 8 16 Vstate1(t) V4 − V5 0V − V5 V4 − VLCD −VLCD Vstate2(t) VLCD V3 VLCD − V2 0V V3 − V2 V4 − V5 0V − V5 V4 − VLCD −VLCD 0 0 1 2 66 0 0 1 2 66 0 0 1 2 66 0 0 1 2 66 0 0 1 2 66 MGT115 Product specification Vstate1(t) = C1(t) − R0(t) Vstate2(t) = C1(t) − R1(t) Example for setting grey-scale register. ROW0, COL0: GS = 17 ROW1, COL0: GS = 0 ROW0, COL1: GS = 30 ROW1, COL0: GS = 63 (63 will be set to 64; see Section 8.1.8). PCF8820 Fig.3 Typical LCD driver waveforms at a multiplex rate of 1 : 67. This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... ook, full pagewidth 2000 Dec 07 10 Vstate1(t) Vstate2(t) Philips Semiconductors 67 × 101 Grey-scale/ECB colour dot matrix LCD driver Frame VLCD V2 V3 V5 VSS VLCD V2 V3 V5 VSS VLCD V2 V3 V5 VSS VLCD V2 V3 V5 VSS VLCD V3 VLCD − V2 0V V3 − V2 N11 N12 N13 N14 N21 state1 ROW 0 V4 R0(t) state2 ROW 1 V4 R1(t) 4 4 4 5 4 COL 0 V4 C0(t) x x 7 9 16 x x 8 8 16 x x 7 9 16 COL 1 V4 C1(t) x x 7 9 16 x x 8 8 16 V4 − V5 0V − V5 V4 − VLCD −VLCD VLCD V3 VLCD − V2 0V V3 − V2 V4 − V5 0V − V5 V4 − VLCD −VLCD 0 0 1 2 7 0 0 1 2 7 0 0 1 2 7 0 0 1 2 7 0 0 1 2 7 MGT116 Product specification Vstate1(t) = C1(t) − R0(t) Vstate2(t) = C1(t) − R1(t) Example for setting grey-scale register. ROW0, COL0: GS = 17 ROW1, COL0: GS = 0 ROW0, COL1: GS = 30 ROW1, COL0: GS = 63 (63 will be set to 64; see Section 8.1.8). PCF8820 Fig.4 Typical LCD driver waveforms at a multiplex rate of 1 : 8 for partial screen mode. This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... ook, full pagewidth 2000 Dec 07 11 Philips Semiconductors 67 × 101 Grey-scale/ECB colour dot matrix LCD driver Frame VLCD N11 N12 N13 N14 N21 state1 ROW 0 0.5V LCD R0(t) VSS VLCD state2 ROW 1 0.5V LCD R1(t) VSS VLCD COL 0 C0(t) VSS VLCD COL 1 C1(t) VSS VLCD 0.5VLCD Vstate1(t) 0 V −0.5VLCD −VLCD VLCD 0.5VLCD Vstate2(t) 0 V −0.5VLCD −VLCD 0 0 1 2 7 0 0 1 2 7 0 0 1 2 7 0 0 1 2 7 0 0 1 2 7 MGT117 Product specification Vstate1(t) = C1(t) − R0(t). Vstate2(t) = C1(t) − R1(t). Example for setting grey-scale register. ROW0, COL0: GS = 0 ROW1, COL0: GS = 63 (63 will be set to 64; see Section 8.1.8). ROW0, COL1: GS = 63 (63 will be set to 64; see Section 8.1.8). ROW1, COL0: GS = 63 (63 will be set to 64; see Section 8.1.8). PCF8820 Fig.5 Typical LCD driver waveforms at a multiplex rate of 1 : 8, for partial screen mode and bias system 1/2. Philips Semiconductors Product specification 67 × 101 Grey-scale/ECB colour dot matrix LCD driver PCF8820 handbook, full pagewidth LSB DB0 MSB DB1 DB2 P0 LSB P1 MSB LSB P0 P1 P2 P3 P0 P1 P2 P3 P0 pixel 0 MSB bank 0 top of LCD R0 bank 1 R4 bank 2 R8 bank 3 R12 DB3 P1 LSB DB4 P2 MSB DB5 P2 LSB DB6 P3 MSB MSB DB7 P3 LSB . . . . . . bank 13 . . R16 LCD R52 bank 14 R56 bank 15 R60 bank 16 X X R64 R66 MGT118 R = row P = pixel Fig.6 DDRAM to display mapping. 2000 Dec 07 12 Philips Semiconductors Product specification 67 × 101 Grey-scale/ECB colour dot matrix LCD driver 7.17 DDRAM addressing PCF8820 Data is written in 8-bit bytes into the display data RAM matrix of the PCF8820 (see Figs 6 to 8). The display data RAM comprises a matrix of 67 × 101 × 2 bits. The columns are addressed by the address pointer. The address ranges are: X = 0 to 100 (64H) and Y = 0 to 16 (10H). It should be noted that only 3 rows are addressed in bank 16. Addresses outside these ranges are not allowed. Bit MX (see Table 3) enables or disables horizontal address space mirroring: • When bit MX = 0, mirroring is disabled. The address corresponds to Col0 (see Fig.7). • When bit MX = 1, mirroring is enabled and address X = 0 corresponds to Col0 (see Fig.8). Bit MX determines how data is written to the RAM. If bit MX is changed after writing data to the RAM, no change on the display will be visible. LSB handbook, full pagewidth Col0 0 MSB Y address 16 0 X address 100 MGT119 Fig.7 RAM X-address format for mirroring disabled. LSB handbook, full pagewidth Col0 0 MSB Y address 16 100 X address 0 MGT120 Fig.8 RAM X-address format for mirroring enabled. 2000 Dec 07 13 Philips Semiconductors Product specification 67 × 101 Grey-scale/ECB colour dot matrix LCD driver Bit V (see Table 3) selects either horizontal or vertical address mode: • In vertical address mode (bit V = 1), the Y-address is incremented after each byte (see Fig.9). After Y = 16, the Y-address sequence returns to Y = 0 and the X-address is incremented to address the next column. • In horizontal address mode (bit V = 0) the X-address is incremented after each byte (see Fig.10). After X = 100, the X-address sequence returns to X = 0 and the Y-address is incremented to address the next row. PCF8820 After the very last address (X = 100 and Y = 16), the address pointers return to the first address (X = 0 and Y = 0). It should be noted that in bank 16 only bits DB0 to DB5 of the data will be written into the RAM. handbook, full pagewidth 0 1 2 3 17 18 19 20 0 Y address 13 14 15 16 0 X address 1716 100 16 MGT121 Fig.9 Writing data to RAM sequence in vertical address mode. handbook, full pagewidth 0 101 202 303 404 1 102 203 304 2 3 4 5 100 201 0 Y address 1414 1515 1616 0 X address 1716 100 16 MGT122 Fig.10 Writing data to RAM sequence in horizontal address mode. 2000 Dec 07 14 Philips Semiconductors Product specification 67 × 101 Grey-scale/ECB colour dot matrix LCD driver 7.18 I2C-bus interface 7.18.2 START AND STOP CONDITIONS PCF8820 The I2C-bus allows bidirectional data communication between different ICs or modules. The serial data input line and serial data output line are connected together, so representing the Serial Data (SDA) line. See Section 13.4 for layout considerations. The SDA line and the Serial Clock Line (SCL) line must be connected to a positive supply voltage via a pull-up resistor. Data transfer may be initiated only when the bus is not busy. 7.18.1 BIT TRANSFER Both data and clock lines are HIGH when the bus is not busy (see Fig.12). A START condition (S) occurs when the data line goes from HIGH-to-LOW while the clock is HIGH. A STOP condition (P) occurs when the data line goes from LOW-to-HIGH while the clock is HIGH. One data bit is transferred during a clock pulse period. The data on the SDA line must remain stable during the HIGH period of the clock pulse, otherwise any change in the data within this period will be interpreted as a control signal (see Fig.11). handbook, full pagewidth SDA SCL data line stable; data valid change of data allowed MBC621 Fig.11 Bit transfer. handbook, full pagewidth SDA SDA SCL S START condition P STOP condition SCL MBC622 Fig.12 Definition of START and STOP conditions. 2000 Dec 07 15 Philips Semiconductors Product specification 67 × 101 Grey-scale/ECB colour dot matrix LCD driver 7.18.3 SYSTEM CONFIGURATION PCF8820 Thd system components are defined below (see Fig.13): • Transmitter: the device which sends data to the bus • Receiver: the device which receives data from the bus • Master: the device which initiates a transfer, generates clock signals and terminates a transfer • Slave: the device addressed by a master • Multi-master: more than one master can attempt to control the bus at the same time without corrupting the message • Arbitration: procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to do so and the message is not corrupted • Synchronization: procedure to synchronize the clock signals of two or more devices. 7.18.4 ACKNOWLEDGE During the acknowledge clock pulse a HIGH-level signal is put on the bus by the transmitter. A slave receiver which is addressed must generate an acknowledge bit after the reception of each data byte. A master receiver must generate an acknowledge bit after receiving a data byte that has been clocked out of the slave transmitter. The device that acknowledges must pull-down the SDA line to a LOW-level during the acknowledge clock pulse. Set-up and hold times must be taken into consideration to ensure that the SDA line is stable during the HIGH period of the acknowledge related clock pulse. A master receiver must signal an end-of-data to the slave transmitter by not generating an acknowledge bit on the last byte that has been clocked out of the slave transmitter. In this event the slave transmitter must leave the data line HIGH to allow the master to generate a STOP condition. For the PCF8820 the acknowledge bit is output at pad SDA_OUT. Each 8-bit data byte transferred over the bus must be followed by an acknowledge bit (see Fig.14). MASTER TRANSMITTER/ RECEIVER SDA SCL SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER MGA807 Fig.13 System configuration. handbook, full pagewidth DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER S START condition clock pulse for acknowledgement MBC602 1 2 8 9 Fig.14 Acknowledgement on the I2C-bus. 2000 Dec 07 16 Philips Semiconductors Product specification 67 × 101 Grey-scale/ECB colour dot matrix LCD driver 7.18.5 I2C-BUS PROTOCOL PCF8820 The PCF8820 is a slave transmitter/receiver. If data is to be read from the device, the SDA_OUT output must be used. Before any data is transferred over the I2C-bus, the destination device is addressed first (see Fig.15). The PCF8820 has four 7-bit slave addresses reserved: 0111 100, 0111 101, 0111 110 and 0111 111. The two least significant bits of the slave address are set by connecting slave address inputs SA1 and SA0 to either VSS1 (logic 0) or VDD1 (logic 1). A write sequence (see Fig.17) is initiated with a START condition (S) from the I2C-bus master which is followed by the slave address. Only the addressed slave acknowledges. After acknowledgement, one or more command words follow which define the status of the addressed slave. A command word consists of a control byte (see Fig.16) defining ‘continuation’ bit Co and ‘register selection’ bit RS, plus a data byte. The last control byte is indicated by resetting bit Co = 0. The control and data bytes are also acknowledged by all addressed slaves on the bus. Depending on the setting of bit RS in the last control byte, either a series of display data bytes or command data bytes may follow. If bit RS = 1, the data bytes are stored as display data in the DDRAM at the address specified by the data pointer. The data pointer is automatically incremented. If bit RS = 0, the data byte is interpreted as a command byte to be decoded and the device will be set according to the received commands. Only the addressed PCF8820 acknowledges after each byte is received. The I2C-bus master issues a stop condition (P) at the end of the transmission. slave address acknowledge bit S 0 1 1 1 1 SA1 SA0 R/W A START condition MGU185 slave read/write address bit bit 1 slave address bit 0 Fig.15 Slave address. register selection bit control byte Co RS X X X X X X MGT124 continuation bit Fig.16 Control byte. handbook, full pagewidth acknowledgement from PCF8820 acknowledgement from PCF8820 acknowledgement from PCF8820 acknowledgement from PCF8820 acknowledgement from PCF8820 SS S 0 1 1 1 1 A A 0 A 1 RS 10 slave address control byte A data byte A 0 RS control byte A data byte m ≥ 0 bytes AP R/W Co 2n ≥ 0 bytes Co 1 byte MGT125 update data pointer Fig.17 Write sequence: master transmits bytes to slave receiver. 2000 Dec 07 17 Philips Semiconductors Product specification 67 × 101 Grey-scale/ECB colour dot matrix LCD driver For a read sequence (see Fig.18), the addressed PCF8820 will immediately start to output the requested data until a NOT acknowledge is transmitted by the master. Before the read access, the user has to set bit RS to the appropriate value by a preceding write access. The sequence should be terminated by a STOP condition when no further access is required, or by a RE-START condition if further access is required. 7.18.6 COMMAND DECODER PCF8820 acknowledgement from PCF8820 SS S01111AA1A 10 slave address R/W not acknowledgement from master temperature readout value AP STOP condition MGT126 The command decoder identifies command words received via the I2C-bus. Bit 7 of the control byte is named bit Co (see Fig.16): • Bit Co = 1 indicates that only one command byte or DDRAM data byte will follow next • Bit Co = 0 indicates that a stream of command bytes or DDRAM data bytes will follow next depending on last status of bit RS. Bit 6 of a control byte is named bit RS: • Bit RS = 1 indicates that another DDRAM data byte will follow next • Bit RS = 0 indicates that another command byte will follow next. The definition of bits Co and RS is shown in Table 1. 7.18.7 DISPLAY DATA BYTE Fig.18 Read sequence: master receives bytes from slave transmitter status register. MSB LSB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 P3 P3 P2 P2 P1 P1 P0 P0 LSB MSB LSB MSB LSB MSB LSB MSB pixel 3 pixel 2 pixel 1 pixel 0 MGT127 Fig.19 Grey-scale display data byte. A display data byte for grey-scale is shown in Fig.19. Table 1 BIT Co Definition of bits Co and RS VALUE 0 1 RS 0 1 ACTION last control byte to be sent; only a stream of data bytes are allowed to follow; this stream may only be terminated by a STOP or RE-START condition another control byte will follow the data byte unless a STOP or RE-START condition is received data byte will be decoded and used to set up the device data byte will return the sensor temperature read-out data byte will be stored in the DDRAM RAM read-back (not supported) 2000 Dec 07 18 Philips Semiconductors Product specification 67 × 101 Grey-scale/ECB colour dot matrix LCD driver 8 INSTRUCTIONS I2C-bus. PCF8820 The clock of the The PCF8820 interfaces via the LCD is not required to process instructions. The data received by the PCF8820 is either instruction data which defines its operating mode or display data to be stored in its DDRAM. The type of data is identified by bit RS. When bit RS = 0, the PCF8820 will respond to the instructions. When bit RS = 1, the PCF8820 will load the data into its DDRAM. There are four types of instruction data whose functions are listed below: • Define PCF8820 functions, such as display configuration, etc. • Set DDRAM addresses • Perform data transfers to DDRAM • Other functions. Table 2 Instruction set CONTROL BITS(1) RS R/W DB7 DB6 In normal use, the most frequently used instructions are those which perform data transfers to the DDRAM. Address pointer update follows after the data byte has been written to the DRAM. This reduces the program load of the microcontroller. Undefined register locations are not allowed. The instruction set comprises several command pages. A command page is selected by setting bits H0 to H2. The instruction set is given in Table 2. The bit functions are described in detail in Section 8.1. COMMAND BYTE DESCRIPTION DB5 DB4 DB3 DB2 DB1 DB0 INSTRUCTION Independent command page (H2 = X, H1 = X, H0 = X); note 2 Write data Read temperature NOP Default H2 to H0 1 0 0 0 0 1 0 0 D7 TR7 0 0 D6 TR6 0 0 D5 TR5 0 0 D4 TR4 0 0 D3 TR3 0 0 D2 TR2 0 0 D1 TR1 0 0 D0 TR0 0 1 writes data to DDRAM reads sensor temperature read-out no operation jumps to function and RAM command page Function and RAM command page (H2 = 0, H1 = 0, H0 = 0) Instruction set Select function Set Y address of DDRAM Set X address of DDRAM 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 X6 0 0 0 X5 0 1 Y4 X4 1 DO Y3 X3 H2 PD Y2 X2 H1 V Y1 X1 H0 0 Y0 X0 selects a command page data order; power-down control; address mode selects Y-address of DDRAM: 0 ≤ Y ≤ 16 selects X-address of DDRAM: 0 ≤ X ≤ 100 Display setting command page (H2 = 0, H1 = 0, H0 = 1) Display control External display control Bias system Bias system 1/ 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 1 0 1 1 MX BS2 0 D MY BS1 0 E PS BS0 BS1/2 selects display mode mirror X; mirror Y; partial screen mode selects bias system set bias system 1/2 for partial screen mode 2000 Dec 07 19 Philips Semiconductors Product specification 67 × 101 Grey-scale/ECB colour dot matrix LCD driver CONTROL BITS(1) RS Display part 0 R/W 0 DB7 0 DB6 1 COMMAND BYTE PCF8820 INSTRUCTION DESCRIPTION DB5 0 DB4 0 DB3 0 DB2 DP2 DB1 DP1 DB0 DP0 set display for partial screen mode HVGen command page (H2 = 0, H1 = 1, H0 = 0) High voltage generator control High voltage generator configuration Temperature control Temperature measurement control VLCD control 0 0 0 0 0 0 0 1 PRS HVE set VLCDOUT programming range and high voltage generator on set voltage multiplier factor 0 0 0 0 0 0 1 S2 S1 S0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 TC2 0 TC1 0 TC0 SM set temperature coefficient start temperature measurement set VLCD register value: 0 ≤ VOP ≤ 127 0 0 1 VOP6 VOP5 VOP4 VOP3 VOP2 VOP1 VOP0 Grey-scale/colour command page (H2 = 0, H1 = 1, H0 = 1) Grey-scale register control Grey-scale level control 0 0 0 0 0 1 1 0 0 GS5 0 GS4 0 GS3 0 GS2 GR1 GS1 GR0 GS0 select grey-scale register: 0 ≤ GR ≤ 3 set grey-scale register value: 0 ≤ GS ≤ 63 Special feature command page (H2 = 1, H1 = 0, H0 = 0) Display off, direct drive mode Oscillator setting Row block swapping Notes 1. Bit R/W is set in the slave address byte; bit RS is set in the control byte. 2. X = don’t care. 0 0 0 0 0 0 0 1 DOF DM display off; voltage multiplier in direct drive mode select external clock; start oscillator calibration top row swap; bottom row swap 0 0 0 0 0 0 0 1 0 0 0 1 0 0 EC 0 OC 0 TRS BRS 2000 Dec 07 20 Philips Semiconductors Product specification 67 × 101 Grey-scale/ECB colour dot matrix LCD driver 8.1 Description of the bit functions Instruction set bit functions RESET STATE − − 000 VALUE − − 000 001 010 011 100 DO 0 PD 0 1 V 0 Y4 to Y0 X6 to X0 D, E 00 00 01 10 11 0 0 0 1 − − 1 0 1 data to be written to DDRAM read-out value of sensor temperature command page numbers function and RAM display setting high voltage generator setting grey-scale/colour special features data order when written to DDRAM normal (see Fig.6) swapped: DB7 DB0, DB6 DB1, etc. operation mode operating mode Power-down mode; see Section 8.1.1 address mode FUNCTION PCF8820 Table 3 BIT D7 to D0 TR7 to TR0 H2 to H0 horizontal address mode: data is written to DDRAM (see Fig.10) vertical address mode: data is written to DDRAM (see Fig.9) Y-address of the DDRAM points to the rows; the address range is from 0 to 16 (10H); see Section 8.1.3 X-address of the DDRAM points to the columns; the address range is from 0 to 100 (64H) display mode display blank: using the value in grey-scale register 0 all display segments on: using the value in grey-scale register 3 normal mode: using the values of the four grey-scale registers appropriate to the RAM data inverse video: using the values in all four grey-scale registers as in normal mode but with their values swapped (GS0 and GS3 values transposed, GS1 and GS2 values transposed) horizontal address space mirroring; see Figs 7 and 8; see Table 10 disabled: data to DDRAM is written from left (X = 0) to right (X = 100) enabled: data to DDRAM is written from right (X = 0) to left (X = 100) vertical address space mirroring; see Table 10 disabled: normal display enabled: data is immediately mirrored vertically on the LCD. The status of bit MY takes effect when data is read from the DDRAM and when generating column signals. MX 0 MY 0 0 1 0 1 2000 Dec 07 21 Philips Semiconductors Product specification 67 × 101 Grey-scale/ECB colour dot matrix LCD driver BIT PS 0 BS2, BS1, BS0 BS1/2 0 DP2, DP1, DP0 PRS 0 HVE 0 S2, S1, S0 000 000 001 010 011 100 101 110 TC2, TC1, TC0 000 000 001 010 011 100 101 110 111 SM 0 VOP6 to VOP0 0 0 1 − 0 1 0 1 0 1 000 000 111 000 0 1 − RESET STATE VALUE screen mode full display mode: multiplex rate is 1 : 67 partial screen mode: multiplex rate is 1 : 8; see Section 8.1.2. bias system selection bits; see Section 8.1.4 bias system selection setting of bits BS2 to BS0 bias system 1/2; see Section 8.1.4 display part DDRAM bank 0 to 1: first 8 rows DDRAM bank 14 to 15: last 8 rows VLCDOUT programming range; see Fig.20 LOW range HIGH range high voltage generator disabled enabled voltage multiplier factor; see Section 8.1.5 2 × VDD2 3 × VDD2 4 × VDD2 5 × VDD2 6 × VDD2 7 × VDD2 8 × VDD2 temperature coefficient; see Chapter 11 coefficient 0 coefficient 1 coefficient 2 coefficient 3 coefficient 4 coefficient 5 coefficient 6 coefficient 7 temperature measurement no measurement start measurement VLCD control register bits; see Section 8.1.7 FUNCTION PCF8820 2000 Dec 07 22 Philips Semiconductors Product specification 67 × 101 Grey-scale/ECB colour dot matrix LCD driver BIT GR1, GR0 00 00 01 10 11 GS5 to GS0 DOF 0 1 DM 0 EC 0 1 OC 0 TRS 0 0 1 0 1 0 1 1 0 − RESET STATE VALUE grey-scale register selection: register 0: applied if DDRAM content is 00 register 1: applied if DDRAM content is 01 register 2: applied if DDRAM content is 10 register 3: applied if DDRAM content is 11 FUNCTION PCF8820 grey-scale level bits; in the reset state all 4 grey-scale registers are reset to 0; see Section 8.1.8 display on/off display on display off: the state of the PCF8820 is equivalent to Power-down mode (bit PD = 1). However, temperature measurement is still possible drive of voltage multiplier no direct drive direct drive: VLCDOUT = VDD2; see Section 8.1.9 clock selection internal clock external clock oscillator setting; see Section 8.1.10 stop calibration of frame frequency start calibration of frame frequency top rows not swapped swapped: the signals for row driver outputs R23 to R33 appear at outputs R56 to R66, and the signals for row driver outputs R56 to R66 appear at outputs R23 to R33 bottom rows not swapped swapped: the signals for row driver outputs R0 to R22 appear at outputs R34 to R55, and the signals for row driver outputs R34 to R55 appear at outputs R0 to R22 BRS 0 0 1 2000 Dec 07 23 Philips Semiconductors Product specification 67 × 101 Grey-scale/ECB colour dot matrix LCD driver 8.1.1 POWER-DOWN MODE 8.1.3 Y-ADDRESS OF DDRAM PCF8820 During power-down (bit PD = 1) all static currents are switched off (no internal oscillator, no timing, no LCD segment drive system) and all LCD outputs are internally connected to VSS. To decrease the voltage at VLCDOUT very fast the following features can be used: • Select the direct drive mode by setting bit DM = 1 resulting in VLCDOUT = VDD2 • Select the non direct drive mode by setting bit DM = 0, resulting in VLCDOUT = 0 V (output high-impedance). During power-down: • All LCD outputs at VSS (display off) • Oscillator is off • Intermediate bias voltage generator is off • High voltage generator is disabled; however, the status of bit HVE is unchanged (see Table 8) • An external VLCD can be disconnected from VLCDIN • The I2C-bus is operational; commands can be executed • DDRAM contents is not cleared; DDRAM data can be written • Register settings remain unchanged • Temperature measurement is not possible. 8.1.2 PARTIAL SCREEN MODE Bits Y4 to Y0 define the Y-address of the DDRAM. Table 4 Y4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 8.1.4 Y-address Y3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 Y2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 Y1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 Y0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 RAM BANK bank 0 bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 bank 8 bank 9 bank 10 bank 11 bank 12 bank 13 bank 14 bank 15 bank 16 BIAS SYSTEM Partial screen mode allows data to be displayed of DDRAM bank 0 to 1 on the first 8 rows or bank 14 to 15 on the last 8 rows, depending on the status of bits DP2 to DP0. If bit MY = 0, data is displayed either on rows 0 to 7 (first 8 rows) or on rows 56 to 63 (last 8 rows). If bit MY = 1, data is displayed either on rows 66 to 59 (first 8 rows) or on rows 10 to 3 (last 8 rows). The partial screen mode also allows VLCDIN to be reduced to save power. Frame frequency calibration is not allowed in the partial screen mode. Different LCD bias voltage settings are required at different multiplex rates. The status of bits BS2 to BS0 and bit BS1/2 select different ‘bias systems’ which determine the intermediate bias voltage levels between VLCDIN and VSS1. It should be noted that the bias system selected by bit BS1/2 is independent of the bias systems selected by bits BS2 to BS0. A value ‘n’ attributed to each bias system is used to calculate these levels (see Table 5). The optimum value for ‘n’ is given by: n = M is the multiplex rate. M – 3 where Table 6 shows how bias voltage levels are calculated for three of the available bias systems using supported ‘n’ values. 2000 Dec 07 24 Philips Semiconductors Product specification 67 × 101 Grey-scale/ECB colour dot matrix LCD driver Table 5 BS2 0 0 0 0 1 1 1 1 X Table 6 Programming the required bias system BS1 0 0 1 1 0 0 1 1 X BS0 0 1 0 1 0 1 0 1 X BS1/2 0 0 0 0 0 0 0 0 1 n 7 6 5 4 3 2 1 0 −2 BIAS SYSTEM 1/ 11 1/ 10 1/ 9 1/ 8 1/ 7 1/ 6 1/ 5 1/ 4 1/ 2 PCF8820 COMMENT recommended at multiplex rate 1 : 67 recommended at multiplex rate 1 : 8 allows a lower VLCDIN at multiplex rate 1 : 8 Examples of LCD bias voltages CALCULATING BIAS VOLTAGE VLCDIN n+3 ------------ × V LCDIN n+4 n+2 ------------ × V LCDIN n+4 2 ------------ × V LCDIN n+4 1 ------------ × V LCDIN n+4 VSS1 8/ BIAS VOLTAGE LEVEL ON PAD VLCDOUT V2 V3 V4 V5 VSS1 8.1.5 BIAS SYSTEM 1/ 9 (n = 5) 1/ 4 (n = 0) 1/ 2 (n = −2) VLCDIN 9 VLCDIN 3/ 4 VLCDIN 1/ 2 × VLCDIN × VLCDIN × VLCDIN × VLCDIN VSS1 × VLCDIN × VLCDIN × VLCDIN × VLCDIN VSS1 × VLCDIN VSS1 7/ 9 1/ 2 2/ 9 1/ 2 VLCDIN 1/ 2 1/ 9 1/ 4 × VLCDIN VSS1 HIGH VOLTAGE GENERATOR CONFIGURATION The PCF8820 incorporates a software configurable voltage multiplier which uses a charge pump circuit supplied by VDD2 and VDD3. After a reset the voltage multiplier factor is set to 2 (VLCDOUT = 2 × VDD2). Other voltage multiplier factors are set by bits S2 to S0. To reduce high current peaks at voltage multiplier start-up, it is recommended that the voltage multiplier is switched on using the following procedure: 1. Set bit DM = 1 and bit PD = 1 2. Set multiplication factor to 2 by setting bits S2 to S0 to logic 0 3. Set register value VOP to the desired value, bit PRS = 1 and bit HVE = 1 4. Set bit PD = 0, which switches on the charge pump (at multiplication factor 2) 5. Increment the multiplication factor to the desired value for VLCDOUT using bits S2 to S0. 8.1.6 TEMPERATURE READ-OUT The PCF8820 has a built-in temperature sensor. At the end of a temperature measurement, the sensor writes a temperature value to the status register. The temperature value is an 8-bit number represented by bits TR7 to TR0 in the status register which can be read via the I2C-bus. To save power, the sensor need only be enabled when a measurement is required. A measurement is initialized by setting bit SM = 1 which will be automatically cleared after 5 clock cycles (from internal oscillator or external clock). The internal oscillator will be initialized and allowed to warm-up for approximately 2 frame periods, after which a measurement will be initiated at the start of the next frame and completing after 2 frames. 2000 Dec 07 25 Philips Semiconductors Product specification 67 × 101 Grey-scale/ECB colour dot matrix LCD driver It is not possible to measure temperature in Power-down mode. During a temperature measurement, the status register value remains zero until the measurement has completed and then the register is updated with the current temperature value (non-zero value). Because the I2C-bus interface is asynchronous to the temperature measurement, the value read from the status register should be validated by reading the status register a few times. During a temperature measurement, the temperature coefficient (TC) has to be selected. The ideal temperature read-out can be calculated by the 1 equation: TR ideal = 128 + ( T – 27 ° C ) × -a where T is the on-chip temperature in °C and ‘a’ is the conversion constant (see Chapter 11). To improve the accuracy of the temperature measurement, it is recommended that the temperature read-out is calibrated during the product’s final assembly. Calibration of the temperature read-out requires a measurement to be made at a defined ideal temperature. The offset between the ideal temperature value and the measured temperature value is calculated by: TRoffset = TRideal − TRmeas where TRmeas is the actual temperature read-out of the PCF8820. The offset value must be stored in a non-volatile register, such as an EEPROM. A calibrated temperature read-out can be calculated for each measurement by the equation: TRcal = TRmeas + TRoffset The accuracy after the calibration is ±10% ±1 bit of the difference between the measured temperature and the calibration temperature. For this reason, it is recommended that a calibration is performed at or near the most sensitive LCD temperature. For example: calibration temperature is 25 °C and the measured temperature is −20 °C. The relative error A = ±0.10 × {25 − (−20)} ±1 bit × a A = ±4.5 ±1.13 A = ±5.63 °C. This calibration accuracy is valid for temperature measurements made when the supply voltage value is the same as when it was calibrated. 8.1.7 VLCD CONTROL REGISTER PCF8820 The VLCDOUT value can be set by software using the bits VOP6 to VOP0 of the VLCD control register. The programmed value for VLCD has to be calculated for a reference temperature, called the cut-point temperature Tcp, using the equation: VLCD (at Tcp) = a + b × VOP The values for parameters Tcp, a and b are given in Table 7, and their relationship with the VLCD control register values are shown in Fig.20. The VLCDOUT generated is dependent on the operating temperature Toper, the selected temperature coefficient TC and the programmed value for VLCD at the reference temperature Tcp and is calculated by the equation: VLCD (at Toper) = VLCD (at Tcp) × {1 + TC × (Toper − Tcp)} Two overlapping VLCD ranges are selectable by bit PRS (see Table 7 and Fig.20). The maximum voltage that can be generated depends on the values of VDD2 and VDD3, and the display load current. At a multiplex rate of 1 : 67, the optimum operating voltage for the LCD can be calculated by the equation: 1 + 67 + 1 V LCD = ------------------------------------------------ × V th ≅ 6.975 × V th 1 2 ×  1 – -------------------   67 + 1 where Vth is the threshold voltage of the liquid crystal material used. The practical value for VLCD is determined by equating Voff(rms) with the defined LCD threshold voltage (Vth), which is the typically value when the LCD exhibits approximately 10% contrast. Table 7 Parameter values for programming VLCD control register VALUE SYMBOL BIT PRS = 0 Tcp a b programming range 23.0 4.500 0.045 4.5 to 10.215 BIT PRS = 1 23.0 10.215 0.045 °C V V UNIT 10.215 to 15.93 V 2000 Dec 07 26 Philips Semiconductors Product specification 67 × 101 Grey-scale/ECB colour dot matrix LCD driver PCF8820 handbook, full pagewidth VLCD (V) b a 00 01 02 03 04 05 LOW(1) 06 . . . 7D 7E 7F 00 01 02 03 04 05 HIGH(2) 06 . . . 7D 7E 7F register value MGT128 (1) Bit PRS = 0: VLCD programming range is LOW. (2) Bit PRS = 1: VLCD programming range is HIGH. Fig.20 Generated VLCDOUT set by programming VLCD control register value (bits VOP6 to VOP0). The programming range for the generated VLCDOUT allows values above the maximum value of VLCD. Therefore, the user must ensure that the VLCD control register value and the temperature coefficient selected, will never allow the maximum VLCD limit to be exceeded for all conditions and including all tolerances. The customer must also ensure that the VLCD control register value will never be lower than VDD1 or VDD2, except in the Power-down mode, for all conditions and including all tolerances. 8.1.8 GREY-SCALE REGISTER AND GREY-SCALE LEVEL The grey-scale level for each pixel is effected by writing the resultant grey-scale register value into the DDRAM (see Fig.6). One of the grey-scale registers can be used to create a blinking cursor. The intensity of the pixels comprising the cursor are to be defined by the value in the grey-scale register. The brightness/colour of the cursor pixels can be changed by selecting a different grey-scale register containing a different grey-scale value. A blinking cursor can be effected by continuously switching the content of one grey-scale register between the two grey-scales from e.g. white to black and back again with a frequency of 2 Hz giving the impression of a blinking cursor. This procedure causes less load for the microcontroller than changing all pixels which form the desired cursor. This implies the display has 3 grey-scale levels left e.g. off, grey and on. The PCF8820 has 4 grey-scale registers selected by bits GR0 and GR1, which define the four grey intensity levels. Each of the 4 registers contain 6 bits allowing to select one out of the 64 grey levels. A grey-scale register must be addressed before it can be written to by using the instruction ‘Grey-scale register’ (see Table 2). The content of the grey-scale register (bits GS5 to GS0) is set by the instruction ‘Grey-scale level control’ (see Table 2). It should be noted that a grey-scale register setting of 63 is internally converted to 64. Even numbers are preferred; odd numbers produce a small DC component in the waveform of the respective column (see Fig.3). 2000 Dec 07 27 Philips Semiconductors Product specification 67 × 101 Grey-scale/ECB colour dot matrix LCD driver 8.1.9 DIRECT DRIVE MODE PCF8820 The voltage multiplier is in the direct drive mode (VLCDOUT = VDD2) in the following settings (see Table 8): • If bit DM = 1 and Power-down mode (bit PD = 1) • If bit DM = 1 and display off mode (bit DOF = 1) • If bit DM = 1 and high voltage generator is disabled (bit HVE = 0). It is recommended to always select the direct drive mode before switching on the voltage multiplier. This is a feature which can be used to reduce VLCDOUT very quickly, or to avoid high current when the voltage multiplier starts up. Output VLCDOUT is high-impedance when bit DM = 0 and bit PD = 1, bit DM = 0 and bit DOF = 0 or when bit DM = 0, bit PD = 0 and bit HVE = 0. Table 8 DM 0 0 0 1 1 1 X Note 1. X = don’t care. 8.1.10 FRAME FREQUENCY CALIBRATION Output VLCDOUT as a function of bits DM, HVE, PD and DOF; note 1 HVE X X 0 0 X X 1 PD 1 X 0 0 1 X 0 DOF X 1 0 0 X 1 0 high Z high Z high Z VDD2 VDD2 VDD2 internally generated VLCD VLCDOUT The resulting frame frequency is calculated by the f clk equation: f frame = ------------- × pre-divider ratio [ Hz ] 1088 where fclk can be either the internal oscillator clock signal or an external clock signal source. Figure 21 shows the resulting frame frequency at different clock frequencies and at different pre-divider ratios, for a calibration period of 190 µs. The frame frequency calibration can also be used to set the frame frequency to a lower than typical value with a corresponding reduction in current consumption. The necessary calibration period (time between calibration start and stop) can be estimated by the equation: 77 (Hz) × 190 ( µ s ) t cal = ------------------------------------------------f frame where tcal is the calibration time in µs and fframe is the desired frame frequency in Hz. Figure 22 shows the resulting frame frequency as a function of the calibration period at different pre-divider ratios at a clock frequency of 336 kHz. 8.2 Reset and initialization After power-on the content of all internal registers including the DDRAM are in an undefined state. A reset pulse must be applied within a specified time to reset all internal registers. A reset can be achieved by applying an external reset pulse (active LOW) to pad RES. When reset occurs within the specified time all internal registers are reset, however the DDRAM is still undefined. After VDD1 has reached its minimum value, the RES input level must be ≤0.3VDD1 after a maximum time tsu (see Fig.24). After reset the state of the PCF8820 is as follows: • Default values of bits and registers as seen in Table 3 • All row and column outputs are at VSS (display off) • VLCDOUT is high-impedance • RAM data is undefined. The PCF8820 uses on-chip software to calibrate the frame frequency. After reset, the frame frequency calibration is disabled (bit OC = 0). Frame frequency calibration can only be performed if the PCF8820 is not in Power-down mode or in the partial screen mode. The calibration is initiated by setting bit OC = 1 and is stopped by setting bit OC = 0. The time between calibration start and stop must be 190 µs to give a frame frequency of 77 Hz (typical value). All other commands are allowed during a calibration. The frame frequency calibration uses a pre-divider which has a range from 1 : 1 to 1 : 15. The default ratio after reset is 1 : 4. The calibration period determines the pre-divider ratio for the oscillator frequency or external clock signal. 2000 Dec 07 28 Philips Semiconductors Product specification 67 × 101 Grey-scale/ECB colour dot matrix LCD driver PCF8820 handbook, full pagewidth 100 MGT129 1:2 95 f frame (Hz) 90 1:3 1:4 1:5 85 1:6 80 1:7 1:8 75 70 65 60 150 200 250 300 350 400 450 500 550 600 650 700 750 fclk (kHz) tcal = 190 µs. Fig.21 Calibrated frame frequency as a function of clock frequency and pre-divider ratio. handbook, full pagewidth 110 MGT130 1:3 100 f frame (Hz) 90 80 70 1:5 60 1:6 50 1:7 40 30 20 10 100 1:8 1:9 1:10 1:11 1:4 1:12 1:13 1:14 1:15 150 200 250 300 350 400 450 500 550 600 650 700 750 800 t cal (µs) fclk = 336 kHz. Fig.22 Frame frequency as a function of the calibration time and pre-divider ratio. 2000 Dec 07 29 Philips Semiconductors Product specification 67 × 101 Grey-scale/ECB colour dot matrix LCD driver 9 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); note 1. SYMBOL VDD VLCDIN Vn supply voltage supply voltage for the LCD voltage on any VLCD related pin any other pin II IO ISS Ptot P/out Tamb Tstg Tj Note DC input current DC output current ground supply current total power dissipation power dissipation per output ambient temperature storage temperature junction temperature −0.5 −0.5 −10 −10 −50 − − −40 −65 − VLCDIN + 0.5 VDD1 + 0.5 +10 +10 +50 100 10 +85 +150 150 PARAMETER −0.5 −0.5 MIN. +6.5 +15 MAX. PCF8820 UNIT V V V V V mA mA mA mW mW °C °C °C 1. All voltages are referred to VSS = 0 V. Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Parameters are valid over operating temperature range unless otherwise specified. 10 HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, it is good practice to take normal precautions appropriate to handling MOS devices (see “Handling MOS devices” ). 11 CHARACTERISTICS VDD1 = 2.5 to 5.5 V; VDD2 = VDD3 = 2.7 to 5.5 V; VSS1 = VSS2 = 0 V; VLCDIN = 4.5 to 14.5 V; Tamb = −40 to +85 °C; unless otherwise specified. SYMBOL Supplies VDD1 VDD2 VDD3 VLCDIN supply voltage 1 of logic circuits supply voltage 2 of voltage multiplier supply voltage 3 of voltage multiplier supply voltage of LCD graphic mode partial screen mode; note 1 2.5 2.7 2.7 7.0 VDD − − − − − 5.5 5.5 5.5 14.5 14.5 V V V V V PARAMETER CONDITIONS MIN. TYP. MAX. UNIT 2000 Dec 07 30 Philips Semiconductors Product specification 67 × 101 Grey-scale/ECB colour dot matrix LCD driver SYMBOL IDD(tot) PARAMETER total supply current into pins VDD1, VDD2 and VDD3 CONDITIONS Power-down mode; VLCDIN = 8.6 V (external); notes 2 and 3 partial screen mode; VLCDIN = 4.5 V (external); note 3 partial screen mode; VLCDIN = 4.5 V (internal); LCD load is 10 µA; voltage multiplier factor 3; bias system = 1/6; notes 3 and 4 normal mode; VLCDIN = 8.6 V (external); note 3 normal mode; VLCDIN = 8.6 V (internal); LCD load is 10 µA; voltage multiplier factor 5; bias system = 1/9; notes 3 and 4 ILCDIN supply current of VLCDIN Power-down mode; VLCDIN = 8.6 V (external); bias system = 1/9; VLCD control value = 28H; bit PRS = 1; notes 3 and 5 partial screen mode; VLCDIN = 4.5 V (external); LCD load is 10 µA; bias system = 1/6; VLCD control value = 00H; bit PRS = 0; notes 3, 4 and 5 normal mode; VLCDIN = 8.6 V (external); LCD load is 10 µA; bias system = 1/9; VLCD control value = 5CH; bit PRS = 0; notes 3, 4 and 5 − MIN. 0.5 TYP. PCF8820 MAX. 10 UNIT µA − 15 35 µA − 210 300 µA − 20 35 µA − 430 680 µA − 6 15 µA − 45 70 µA − 60 95 µA 2000 Dec 07 31 Philips Semiconductors Product specification 67 × 101 Grey-scale/ECB colour dot matrix LCD driver SYMBOL Logic inputs PADS SA0, SA1, RES, T1, T3, T4 and T5 VIL VIH IL PAD OSC VI VI IL I2C-bus PADS SDA_IN and SCL VIL VIH IL IOL IL Rcol LOW-level input voltage HIGH-level input voltage leakage current VI = VDD1 or VSS1 VOL = 0.4 V; VDD1 = 5 V VI = VDD1 or VSS1 VSS1 0.7VDD1 −1 3.0 −1 − − − − − − LOW-level input voltage HIGH-level input voltage leakage current VI = VDD1 or VSS1 VSS1 VDD1 − 0.1 −1 − − − LOW-level input voltage HIGH-level input voltage leakage current VI = VDD1 or VSS1 VSS1 0.7VDD1 −1 − − − PARAMETER CONDITIONS MIN. TYP. PCF8820 MAX. UNIT 0.3VDD1 VDD1 +1 V V µA VSS1 + 0.1 V VDD1 +1 V µA 0.3VDD1 5.5 +1 − +1 V V µA mA µA kΩ PAD SDA_OUT LOW-level output current leakage current Column and row outputs column output resistance C0 to C100 row output resistance R0 to R66 bias voltage tolerance C0 to C100 bias voltage tolerance R0 to R66 VDD1 = 5 V; VLCDIN = 12 V; − IL = 100 µA; outputs tested one at a time VDD1 = 5 V; VLCDIN = 12 V; − IL = 100 µA; outputs tested one at a time −100 −100 10 Rrow − 3.0 kΩ Vbias(col) Vbias(row) 0 0 +100 +100 mV mV LCD supply voltage generator STABILITY ∆VLCDOUT tolerance of internally generated VLCDOUT TC0 TC1 TC2 TC3 TC4 temperature coefficient 0 temperature coefficient 1 temperature coefficient 2 temperature coefficient 3 temperature coefficient 4 Tamb = −20 to +85 °C; VLCDOUT ≤ 12 V − − 4.6 % TEMPERATURE COEFFICIENT OF VLCDOUT; Tamb = −20 TO +85 °C − − − − − −0.04 × 10−3 − −1.89 × 10−3 − −2.05 × 10−3 − −2.22 × 10−3 − −2.38 × 10−3 − K−1 K−1 K−1 K−1 K−1 2000 Dec 07 32 Philips Semiconductors Product specification 67 × 101 Grey-scale/ECB colour dot matrix LCD driver SYMBOL TC5 TC6 TC7 Tcp a atol PARAMETER temperature coefficient 5 temperature coefficient 6 temperature coefficient 7 CONDITIONS − − − − − same supply voltage VDD repeatability affect of changing VDD Notes 1. The minimum value for VLCDIN is limited by the supply voltages VDD1 and VDD2: a) For VDD1 ≤ 4.5 V and VDD2 ≤ 4.5 V: VLCDIN > 4.5 V. b) For VDD1 > 4.5 V or VDD2 > 4.5 V: VLCDIN > highest value of VDD1 or VDD2. 2. All static currents are switched off in Power-down mode; no external clock. − − − MIN. TYP. −2.55 × 10−3 − −2.72 × 10−3 − −2.98 × 10−3 − 23 − − 10 1 PCF8820 MAX. UNIT K−1 K−1 K−1 °C °C/bit % bit bit/V REFERENCE TEMPERATURE cut-point temperature Temperature read-out conversion constant tolerance of a 1.13 − − − 0.5 3. VDD1 = VDD2 = VDD3 = 2.75 V; LCD outputs are open-circuit; inputs connected to VDD1 or VSS1; I2C-bus inactive; external clock with fext = 336 kHz; Tamb = 27 °C. 4. The typical currents are measured on a sample base with the DDRAM and grey-scale registers loaded with data which would produce the display shown in Fig.23 if an LCD was connected. Extensive use of grey-scales will increase current consumption compared to black and white mode. If specified, the maximum current is tested with a regular pattern which is equivalent in current to the display shown in Fig.23. 5. Voltage multiplier disabled; pins VLCDIN, VLCDOUT and VLCDSENSE connected together. handbook, full pagewidth MGT131 Fig.23 Display used to define DDRAM and grey-scales for current measurements. 2000 Dec 07 33 Philips Semiconductors Product specification 67 × 101 Grey-scale/ECB colour dot matrix LCD driver PCF8820 12 TIMING VDD1 = 2.5 to 5.5 V; VDD2 = VDD3 = 2.7 to 5.5 V; VSS1 = VSS2 = 0 V; VLCDIN = 4.5 to 14.5 V; Tamb = −40 °C to +85 °C; unless otherwise specified. SYMBOL Clock signal fframe fframe(cal1) fframe(cal2) fosc PAD OSC fext external clock frequency not calibrated 190 336 670 kHz LCD frame frequency LCD frame frequency LCD frame frequency oscillator frequency not calibrated; note 1 calibrated; accurate calibration timing of 190 µs; note 2 calibrated; accurate calibration timing of 190 µs not calibrated; note 3 44 68 63 190 77 77 77 336 158 91 96 670 Hz Hz Hz kHz PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Reset timing; see Fig.24 PAD RES tWL tWH tW(spike) tsu toper reset pulse width LOW reset pulse width HIGH tolerable spike width on RES input reset-LOW pulse set-up time after power-on end of reset to interface being operational VDD = 2.75 V; note 4 1.0 1.5 − − − − − − − − − − 10 30 3 µs µs ns µs µs LCD on and off timing; see Fig.25 PAD VLCDIN tLCD(on) tLCD(off) external LCD turn-on time external LCD turn-off time after VDD1 turns on before VDD1 turns off 1 1 − − − − ms ms I2C-bus timing; see Fig.26; note 5 PADS SCL and SDA fSCL tLOW tHIGH tSU;DAT tHD;DAT tr tf Cb tSU;STA tHD;STA SCL clock frequency SCL LOW time SCL HIGH time data set-up time data hold time rise time SDA and SCL fall time SDA and SCL capacitive load represented by each bus line set-up time repeated START hold time START condition note 6 note 6 0 1.3 0.6 100 0 20 + 0.1 Cb 20 + 0.1 Cb − 0.6 0.6 − − − − − − − − − − 400 − − − 0.9 300 300 400 − − kHz µs µs ns µs ns ns pF µs µs 2000 Dec 07 34 Philips Semiconductors Product specification 67 × 101 Grey-scale/ECB colour dot matrix LCD driver SYMBOL tSU;STO tW(spike) tBUF Notes f ext f osc 1. Frame frequency: f frame = ------------ or f frame = -----------4352 4352 2. VDD unchanged after frequency calibration. 3. Not available at any pad. PARAMETER set-up time for STOP condition tolerable spike width on bus BUS free time CONDITIONS 0.6 − 1.3 MIN. TYP. − − − PCF8820 MAX. − 50 − UNIT µs ns µs 4. Decoupling capacitor between VLCDIN and VSS1 is 100 nF. A higher capacitance increases tsu and a higher VDD1, VDD2 or VDD3 reduces tsu. 5. All timing values are valid within VDD1, VDD2, VDD3 and Tamb ranges and are referenced to VIL and VIH with an input voltage swing from VSS1 to VDD1. 6. Cb is the total capacitance (in pF) of one bus line. handbook, full pagewidth VDD1 t WH RES t WL t WL VDD1 t su RES t WL t WL t WH RES t oper SDA, SCL MGT135 Fig.24 Reset timing. 2000 Dec 07 35 Philips Semiconductors Product specification 67 × 101 Grey-scale/ECB colour dot matrix LCD driver PCF8820 handbook, full pagewidth VDD1 VLCDIN t LCD(on) t LCD(off) MGT136 Fig.25 Timing diagram of applying and removing the external LCD supply voltage to and from pad VLCDIN. ook, full pagewidth SDA t BUF t LOW tf SCL t HD;STA tr t HD;DAT t HIGH t SU;DAT SDA t SU;STA MGA728 t SU;STO Fig.26 I2C-bus timing. 2000 Dec 07 36 Philips Semiconductors Product specification 67 × 101 Grey-scale/ECB colour dot matrix LCD driver 13 APPLICATION INFORMATION 13.1 Programming example for the PCF8820 PCF8820 It should be noted that only a part of the LCD is shown in the LCD column of Table 9. Table 9 STEP DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 2 3 0 1 0 1 0 0 1 0 0 1 0 0 1 0 0 SA1 SA0 0 0 0 0 0 0 1 start slave address, R/W = 0 control byte: Co = 1, RS = 0 H2 to H0 independent command: select function and RAM command page (H2 to H0 = 000) control byte: Co = 1, RS = 0 function and RAM command page: select display setting command page (H2 to H0 = 001) control byte: Co = 1, RS = 0 display setting command page: set normal display mode (D = 1, E = 0) control byte: Co = 1, RS = 0 display setting command page: set bias system = 1/9 (BS2 to BS0 = 010) control byte: Co = 1, RS = 0 display setting command page: select first 8 rows for partial screen mode (DP2 to DP0 = 000) control byte: Co = 1, RS = 0 H2 to H0 independent command: select function and RAM command page (H2 to H0 = 000) control byte: Co = 1, RS = 0 function and RAM command page: select Power-down mode (PD = 1) and vertical address mode (V = 1) control byte: Co = 1, RS = 0 function and RAM command page: select special feature command page (H2 to H0 = 100) control byte: Co = 1, RS = 0 special feature command page: enable display (DOF = 0) and enable direct drive (DM = 1) to pre-charge the charge pump control byte: Co = 1, RS = 0 Programming example SERIAL BUS BYTE LCD OPERATION 4 5 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 6 7 8 9 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 10 11 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 12 13 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 14 15 1 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 16 17 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 18 19 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 20 1 0 0 0 0 0 0 0 2000 Dec 07 37 Philips Semiconductors Product specification 67 × 101 Grey-scale/ECB colour dot matrix LCD driver SERIAL BUS BYTE STEP DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 21 0 0 0 0 0 0 0 1 LCD PCF8820 OPERATION H2 to H0 independent command: select function and RAM command page (H2 to H0 = 000) control byte: Co = 1, RS = 0 function and RAM command page: select HVGen command page (H2 to H0 = 010) control byte: Co = 1, RS = 0 HVGen command page: select voltage multiplier factor 2× (S2 to S0 = 000) control byte: Co = 1, RS = 0 HVGen command page: select temperature coefficient 2 (TC2 to TC0 = 010) control byte: Co = 1, RS = 0 HVGen command page: select LOW VLCD programming range (PRS = 0), HVGen off (HVE = 0) control byte: Co = 1, RS = 0 HVGen command page: set VLCD to 8.595 V (VOP6 to VOP0 = 1011011) control byte: Co = 1, RS = 0 H2 to H0 independent command: select function and RAM command page (H2 to H0 = 000) control byte: Co = 1, RS = 0 function and RAM command page: select grey-scale/colour command page (H2 to H0 = 011) control byte: Co = 1, RS = 0 grey-scale/colour command page: select grey-scale register 0 (GR1 to GR0 = 00) control byte: Co = 1, RS = 0 grey-scale/colour command page: set grey-scale to 0 (GS5 to GS0 = 000000) control byte: Co = 1, RS = 0 grey-scale/colour command page: select grey-scale register 1 (GR1 to GR0 = 01) control byte: Co = 1, RS = 0 22 23 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 24 25 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 26 27 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 28 29 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 30 31 1 1 0 1 0 0 0 1 0 1 0 0 0 1 0 1 32 33 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 34 35 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 36 37 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 38 39 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 40 41 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 42 1 0 0 0 0 0 0 0 38 2000 Dec 07 Philips Semiconductors Product specification 67 × 101 Grey-scale/ECB colour dot matrix LCD driver SERIAL BUS BYTE STEP DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 43 1 0 0 1 0 1 0 0 LCD PCF8820 OPERATION grey-scale/colour command page: set grey-scale to 20 (GS5 to GS0 = 010100) control byte: Co = 1, RS = 0 grey-scale/colour command page: select grey-scale register 2 (GR1 to GR0 = 10) control byte: Co = 1, RS = 0 grey-scale/colour command page: set grey-scale register 2 to 40 (GS5 to GS0 = 101000) control byte: Co = 1, RS = 0 grey-scale/colour command page: select grey-scale register 3 (GR1 to GR0 = 11) control byte: Co = 1, RS = 0 grey-scale/colour command page: set grey-scale register 3 to 63 (GS5 to GS0 = 111111) control byte: Co = 1, RS = 0 H2 to H0 independent command: select function and RAM command page (H2 to H0 = 000) control byte: Co = 1, RS = 0 function and RAM command page: select HVGen command page (H2 to H0 = 010) control byte: Co = 1, RS = 0 HVGen command page: enable HVGen (HVE = 1) and select LOW VLCD programming range (PRS = 0) control byte: Co = 1, RS = 0 H2 to H0 independent command: select function and RAM command page (H2 to H0 = 000) control byte: Co = 1, RS = 0 function and RAM command page: select normal operation (PD = 0) and vertical address mode (V = 1) control byte: Co = 1, RS = 0 function and RAM command page: select HVGen command page (H2 to H0 = 010) 44 45 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 46 47 1 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 48 49 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 50 51 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 52 53 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 54 55 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 56 57 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 58 59 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 60 61 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 62 63 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 2000 Dec 07 39 Philips Semiconductors Product specification 67 × 101 Grey-scale/ECB colour dot matrix LCD driver SERIAL BUS BYTE STEP DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 64 65 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 LCD PCF8820 OPERATION control byte: Co = 1, RS = 0 HVGen command page: select voltage multiplier factor 3× (S2 to S0 = 001, incremented to 3x) control byte: Co = 1, RS = 0 HVGen command page: select voltage multiplier factor 4 (S2 to S0 = 010) control byte: Co = 1, RS = 0 HVGen command page: select voltage multiplier factor 5 (S2 to S0 = 011, incremented to 5x) control byte: Co = 0, RS = 1 data write column 0 (vertical addressing): address X and Y are initialized to 0 by default, so they are not set here data write: next write to subsequent rows filling up column 0 with ‘00H’ MGT144 66 67 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 68 69 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 70 71 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 MGT143 72 0 0 0 0 0 0 1 1 73 to 89 90 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 no display change data writes (17 bytes) data write column 1 (vertical addressing) MGT145 91 0 0 0 0 0 0 0 0 data write MGT145 92 to 108 109 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 no display change data writes (17 bytes) data write column 2 (vertical addressing) MGT146 110 0 0 0 0 0 0 0 0 data write MGT146 111 to 127 0 0 0 0 0 0 0 0 no display change data writes (17 bytes) 2000 Dec 07 40 Philips Semiconductors Product specification 67 × 101 Grey-scale/ECB colour dot matrix LCD driver SERIAL BUS BYTE STEP DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 128 0 0 0 0 0 0 0 0 LCD PCF8820 OPERATION data write column 3 (vertical addressing) MGT146 129 0 0 0 0 0 0 0 0 data write MGT146 130 to 146 147 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 no display change data writes (17 bytes) data write column 4 (vertical addressing) MGT147 148 0 0 0 0 0 0 1 1 data write MGT148 149 to 165 166 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 no display change data writes (17 bytes) data write column 5 (vertical addressing) MGT149 167 0 0 0 0 0 0 0 0 data write MGT149 168 to 184 185 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 no display change data writes (17 bytes) data write column 6 (vertical addressing) MGT150 186 0 0 0 0 0 0 1 1 data write: last data; stop transmission MGT151 187 188 189 0 1 0 1 0 0 1 0 0 1 0 0 1 0 0 SA1 SA0 0 0 0 0 0 0 1 no display change no display change no display change restart, slave address, R/W = 0 control byte: Co = 1, RS = 0 H2 to H0 independent command: select function and RAM command page (H2 to H0 = 000) 2000 Dec 07 41 Philips Semiconductors Product specification 67 × 101 Grey-scale/ECB colour dot matrix LCD driver SERIAL BUS BYTE STEP DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 190 191 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 no display change no display change LCD PCF8820 OPERATION control byte: Co = 1, RS = 0 function and RAM command page: select display setting command page (H2 to H0 = 001) control byte: Co = 1, RS = 0 display mode: set inverse video mode (D = 1, E = 1) MGT152 192 193 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 no display change 194 195 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 no display change no display change control byte: Co = 1, RS = 0 H2 to H0 independent command: select function and RAM command page (H2 to H0 = 000) control byte: Co = 1, RS = 0 set X address of RAM to ‘0000000’ control byte: Co = 1, RS = 0 set Y address of RAM to ‘00000’ control byte: Co = 0, RS = 1 data write column 1 (vertical addressing mode) 196 197 198 199 200 201 1 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 no display change no display change no display change no display change no display change MGT153 202 0 0 0 0 0 0 0 1 data write: last data; stop transmission MGT154 2000 Dec 07 42 Philips Semiconductors Product specification 67 × 101 Grey-scale/ECB colour dot matrix LCD driver 13.2 Examples of effects on the display PCF8820 Table 10 Examples showing the effects on the LCD of setting bits PS, DP2 to DP0, MX and MY EXAMPLE 1 PS 0 DP2 DP1 DP0 X X X MX 0 MY 0 DISPLAY DESCRIPTION normal display MGT155 2 0 X X X 1 0 X mirrored only MGT156 3 0 X X X 0 1 Y mirrored only MGT157 4 0 X X X 1 1 X and Y mirrored MGT158 5 1 0 0 0 0 0 partial screen mode only; first 8 rows selected MGT159 6 1 0 0 0 1 0 partial screen mode; X mirrored; first 8 rows selected MGT160 7 1 0 0 0 0 1 partial screen mode; Y mirrored; first 8 rows selected MGT161 8 1 0 0 0 1 1 partial screen mode; X and Y mirrored; first 8 rows selected MGT162 9 1 1 1 1 0 0 partial screen mode; last 8 rows selected MGT163 2000 Dec 07 43 Philips Semiconductors Product specification 67 × 101 Grey-scale/ECB colour dot matrix LCD driver EXAMPLE 10 PS 1 DP2 DP1 DP0 1 1 1 MX 1 MY 0 DISPLAY PCF8820 DESCRIPTION partial screen mode; X mirrored; last 8 rows selected MGT164 11 1 1 1 1 0 1 partial screen mode; Y mirrored; last 8 rows selected MGT165 12 1 1 1 1 1 1 partial screen mode; X and Y mirrored; last 8 rows selected MGT166 2000 Dec 07 44 Philips Semiconductors Product specification 67 × 101 Grey-scale/ECB colour dot matrix LCD driver 13.3 High voltage generator PCF8820 The high voltage generator contains a voltage multiplier which uses a charge pump circuit supplied by VDD2 and VDD3. The multiplier is software programmable with a factor from 2 to 8. In the direct drive mode the output voltage VLCDOUT = VDD2. When the charge pump is used the total supply current of the PCF8820 at a supply voltage of 3, 4 and 5 V is shown in Figs 27, 28 and 29. The separate graphs are shown for each voltage multiplier factor with the following conditions: • At Tamb • VDD1, VDD2 and VDD3 connected to the same power supply • Supply line resistors of 50 Ω (typical value) • Internal clock not calibrated • No LCD connected to the PCF8820 • All pixels defined at grey-scale level 32; this is the worst case • Bias system 1⁄9 • Full screen mode (bit PS = 0) at a multiplex rate of 1 : 67 • Normal display mode. The characteristics shown for each voltage multiplier factor are terminated before VLCDOUT has been reached the maximum value to indicate that the voltage cannot be increased any further. If a higher voltage is required, a higher voltage multiplier factor must be selected. Connecting a LCD may increase the current into pad VLCDIN which may affect the current taken by the charge pump and also its efficiency. The amount of current load may depend on the type of LCD used. It is advisable to evaluate the PCF8820 connected to the desired LCD and set to the required mode(s) to produce characteristics similar to Figs 27, 28 and 29. The customer can then use these graphs to select the most efficient and safe voltage multiplier factor for each mode required. handbook, full pagewidth 1.2 MGT132 IDD(tot) (mA) 1.0 x8 x7 0.8 x6 0.6 x5 0.4 x4 x3 0.2 x2 0 4 5 6 7 8 9 10 11 12 13 14 15 16 programmed VLCDOUT (V) Fig.27 Charge pump characteristics for VDD = 3 V. 2000 Dec 07 45 Philips Semiconductors Product specification 67 × 101 Grey-scale/ECB colour dot matrix LCD driver PCF8820 handbook, full pagewidth 1.0 MGT133 IDD(tot) (mA) 0.8 x8 x7 x6 x5 0.6 x4 0.4 x3 0.2 x2 0 4 5 6 7 8 9 10 11 12 13 14 15 16 programmed VLCDOUT (V) Fig.28 Charge pump characteristics for VDD = 4 V. handbook, full pagewidth 1.0 MGT134 IDD(tot) (mA) 0.8 x8 x7 x6 x5 x4 0.4 x3 0.6 0.2 x2 0 4 5 6 7 8 9 10 11 12 13 14 15 16 programmed VLCDOUT (V) Fig.29 Charge pump characteristics for VDD = 5 V. 2000 Dec 07 46 Philips Semiconductors Product specification 67 × 101 Grey-scale/ECB colour dot matrix LCD driver 13.4 Application for COG PCF8820 The PCF8820 physical pad positions are optimized for single plane wiring e.g. for Chip-On-Glass (COG) display modules (see Fig.30). The pad lines are as follows: • 3 input/output lines: SDA, SCL and RES • 101 column driver lines • 33 and 34 row driver lines • pads SA0, SA1 and OSC can be tied in the application to appropriate levels. For COG applications, it is recommended that the Indium Tin Oxide (ITO) track resistance is minimized for the I/O and power supply connections. These connections should have an optimum track resistance of 100 nF (470 nF to 1 µF recommended). A higher value of the capacitors is recommended to reduce the ripple voltage. handbook, full pagewidth LCD (67 × 101 pixels) 34 row drivers 101 colum drivers 33 row drivers PCF8820 SCL SDA_IN VDD1 VDD2 VDD3 VSS1 VSS2 RES R I/O VLCDIN VLCDSENSE VLCDOUT Rsupply Rcommon Cext2 VLCD Cext1 3 I/O VP1 MGT137 GND Fig.30 Application diagram for COG display module. 2000 Dec 07 47 Philips Semiconductors Product specification 67 × 101 Grey-scale/ECB colour dot matrix LCD driver 13.5 Typical system configuration 13.6 External supply of VLCDIN PCF8820 The PCF8820 is a low power LCD driver designed to interface with microcontrollers and a wide variety of LCDs. The host microcontroller and the PCF8820 are both connected to the I2C-bus. The SDA and SCL lines must be connected to the positive power supply via pull-up resistors. The internal oscillator requires no external components. The appropriate intermediate biasing voltage for the multiplexed LCD waveforms are generated on-chip. The only other connections required to complete the system are the power supplies (VDD1, VDD2 and VDD3) and ground supplies (VSS1 and VSS2), LCD supply (VLCDIN) and system reset (RES), including suitable capacitors for decoupling. If an external LCD supply voltage is used, it must be connected to pad VLCDIN. If pads VLCDOUT, VLCDSENSE and VLCDIN are connected together, the impedance of pad VLCDOUT should be set high-impedance by setting the status of bits shown in Table 8. To obtain the highest resistance and the lowest current into pad VLCDSENSE, it is recommended to set the VLCD programming range to HIGH (bit PRS = 1) and the VLCD control register value to 127 (maximum value) with bits VOP6 to VOP0. It should be noted that VLCDIN is not allowed to be lower than VDD1. An external VLCD must be applied after applying VDD1, and it must be turned off before (or when) VDD1 is turned off (see Fig.25). It is recommended that the external VLCD is applied after leaving the reset state. The external VLCD can stay turned on in Power-down mode. handbook, full pagewidth VLCD VP1 VP2 ≤ 5.5 V VLCDIN VLCDSENSE VDD1 VDD2 VDD3 VLCDOUT OSC 101 column drivers 67 row drivers LCD PANEL SDA_OUT Rpu Rpu HOST MICROCONTROLLER VSS1 PCF8820 SDA_IN VSS2 SCL SA0 RES SCL SDA I2C-bus MGT138 Fig.31 Typical system configuration. 2000 Dec 07 48 SA1 RES Philips Semiconductors Product specification 67 × 101 Grey-scale/ECB colour dot matrix LCD driver 14 BONDING PAD INFORMATION COORDINATES(1) SYMBOL dummy dummy row 0 row 1 row 2 row 3 row 4 row 5 row 6 row 7 row 8 row 9 row 10 row 11 row 12 row 13 row 14 row 15 row 16 row 17 row 18 row 19 row 20 row 21 row 22 col 0 col 1 col 2 col 3 col 4 col 5 col 6 col 7 col 8 col 9 col 10 col 11 col 12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 PAD x −5443.7 −5373.7 −5233.7 −5163.7 −5093.7 −5023.7 −4953.7 −4883.7 −4813.7 −4743.7 −4673.7 −4603.7 −4533.7 −4463.7 −4393.7 −4323.7 −4253.7 −4183.7 −4113.7 −4043.7 −3973.7 −3903.7 −3833.7 −3763.7 −3693.7 −3483.7 −3413.7 −3343.7 −3273.7 −3203.7 −3133.7 −3063.7 −2993.7 −2923.7 −2853.7 −2783.7 −2713.7 −2643.7 y −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 col 13 col 14 col 15 col 16 col 17 col 18 col 19 col 20 col 21 col 22 col 23 col 24 col 25 col 26 col 27 col 28 col 29 col 30 col 31 col 32 col 33 col 34 col 35 col 36 col 37 col 38 col 39 col 40 col 41 col 42 col 43 col 44 col 45 col 46 col 47 col 48 col 49 col 50 col 51 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 SYMBOL PAD x −2573.7 −2503.7 −2433.7 −2363.7 −2293.7 −2223.7 −2153.7 −2083.7 −2013.7 −1943.7 −1873.7 −1803.7 −1663.7 −1593.7 −1523.7 −1453.7 −1383.7 −1313.7 −1243.7 −1173.7 −1103.7 −1033.7 −963.7 −893.7 −823.7 −753.7 −683.7 −613.7 −543.7 −473.7 −403.7 −333.7 −263.7 −193.7 −123.7 −53.7 +16.3 +156.3 +226.3 PCF8820 COORDINATES(1) y −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 2000 Dec 07 49 Philips Semiconductors Product specification 67 × 101 Grey-scale/ECB colour dot matrix LCD driver COORDINATES(1) SYMBOL col 52 col 53 col 54 col 55 col 56 col 57 col 58 col 59 col 60 col 61 col 62 col 63 col 64 col 65 col 66 col 67 col 68 col 69 col 70 col 71 col 72 col 73 col 74 col 75 col 76 col 77 col 78 col 79 col 80 col 81 col 82 col 83 col 84 col 85 col 86 col 87 col 88 col 89 col 90 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 PAD x +296.3 +366.3 +436.3 +506.3 +576.3 +646.3 +716.3 +786.3 +856.3 +926.3 +996.3 +1066.3 +1136.3 +1206.3 +1276.3 +1346.3 +1416.3 +1486.3 +1556.3 +1626.3 +1696.3 +1766.3 +1836.3 +1976.3 +2046.3 +2116.3 +2186.3 +2256.3 +2326.3 +2396.3 +2466.3 +2536.3 +2606.3 +2676.3 +2746.3 +2816.3 +2886.3 +2956.3 +3026.3 y −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 col 91 col 92 col 93 col 94 col 95 col 96 col 97 col 98 col 99 col 100 row 55 row 54 row 53 row 52 row 51 row 50 row 49 row 48 row 47 row 46 row 45 row 44 row 43 row 42 row 41 row 40 row 39 row 38 row 37 row 36 row 35 row 34 dummy dummy row 56 row 57 row 58 row 59 row 60 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 SYMBOL PAD x +3096.3 +3166.3 +3236.3 +3306.3 +3376.3 +3446.3 +3516.3 +3586.3 +3656.3 +3726.3 +3866.3 +3936.3 +4006.3 +4076.3 +4146.3 +4216.3 +4286.3 +4356.3 +4426.3 +4496.3 +4566.3 +4636.3 +4706.3 +4776.3 +4846.3 +4916.3 +4986.3 +5056.3 +5126.3 +5196.3 +5266.3 +5336.3 +5476.3 +5581.3 +5301.3 +5231.3 +5161.3 +5091.3 +5021.3 PCF8820 COORDINATES(1) y −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 −1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 2000 Dec 07 50 Philips Semiconductors Product specification 67 × 101 Grey-scale/ECB colour dot matrix LCD driver COORDINATES(1) SYMBOL row 61 row 62 row 63 row 64 row 65 row 66 V5 V4 V3 V2 VLCDIN VLCDIN VLCDIN VLCDIN VLCDIN VLCDIN VLCDSENSE VLCDOUT VLCDOUT VLCDOUT VLCDOUT VLCDOUT VLCDOUT VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD3 VDD3 VDD3 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 PAD x +4951.3 +4881.3 +4811.3 +4741.3 +4671.3 +4601.3 +4421 +4261 +4101 +3941 +3806.3 +3726.3 +3646.3 +3566.3 +3486.3 +3406.3 +3326.3 +3246.3 +3166.3 +3086.3 +3006.3 +2926.3 +2846.3 +2451.3 +2371.3 +2291.3 +2211.3 +2131.3 +2051.3 +1921.3 +1841.3 +1761.3 +1681.3 +1601.3 +1521.3 +1441.3 +1361.3 +1281.3 +1201.3 y +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 SDA_IN SDA_IN SDA_OUT VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 SA0 T1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 T3 T4 SA1 SCL SCL T5 T6 RES OSC T2 row 33 row 32 row 31 row 30 row 29 row 28 row 27 row 26 row 25 row 24 row 23 dummy 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 SYMBOL PAD x +573.3 +493.3 +65.9 −233.7 −313.7 −393.7 −473.7 −553.7 −633.7 −833.7 −1033.7 −1113.7 −1193.7 −1273.7 −1353.7 −1433.7 −1513.7 −1713.7 −1913.7 −2113.7 −2355 −2435 −2958 −3158.7 −3454.7 −4158.7 −4282.7 −4498.7 −4568.7 −4638.7 −4708.7 −4778.7 −4848.7 −4918.7 −4988.7 −5058.7 −5128.7 −5198.7 −5478.7 PCF8820 COORDINATES(1) y +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 +1162.5 2000 Dec 07 51 Philips Semiconductors Product specification 67 × 101 Grey-scale/ECB colour dot matrix LCD driver COORDINATES(1) SYMBOL dummy dummy 234 235 PAD x −5548.7 −5618.7 −5594.0 +5594.0 +5469.0 −5369.0 y +1162.5 +1162.5 −1162.5 −1162.5 +1162.5 +1162.5 Pad pitch Pad size, aluminium Bump dimensions Wafer thickness (excluding bumps) Table 11 Bonding pad dimensions NAME PCF8820 DIMENSION 70 µm (minimum value) 62 × 100 µm 52 × 90 × 17.5 µm 381 µm Alignment marks Circle 1 Circle 2 Circle 3 Circle 4 Note 1. All x/y coordinates represent the position of the centre of each pad (in µm) with respect to the centre (x/y = 0) of the chip (see Fig.32). Passivation opening at pad 36 × 76 µm 2000 Dec 07 52 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2000 Dec 07 circle 4 (1) row 23 SDA_OUT pad 235 VSS1 row 33 T2 OSC RES SA1 T4 T3 T1 SA0 T6 T5 VSS2 SCL Philips Semiconductors VLCDSENSE VLCDOUT V2 V4 PC8820-1 y 2.59 mm 0, 0 x col 100 row 55 row 34 pad149 col 25 col 50 row 22 col 0 col 75 pad 1 row 0 row 56 circle 3 (1) pad 150 SDA_IN VLCDIN V3 V5 row 66 VDD2 VDD3 VDD1 handbook, full pagewidth 67 × 101 Grey-scale/ECB colour dot matrix LCD driver . . . . . . . . . . . . circle 1 (1) 11.46 mm MGT139 circle 2 (1) 53 (1) Circles 1 to 4 are alignment marks with a diameter of 100 µm. . . . . . . . . . . . . . . . . . . Product specification PCF8820 Fig.32 Bonding pad locations. Philips Semiconductors Product specification 67 × 101 Grey-scale/ECB colour dot matrix LCD driver 15 DEVICE PROTECTION CIRCUITS SYMBOL VDD1 PAD 179 to 184 REMARK note 1 INTERNAL CIRCUIT PCF8820 VSS1 MGU179 VDD2 188 to 194 note 1 VSS1 VSS2 MGU180 VDD3 185 to 187 note 1 VSS1 MGU179 VSS1 VSS2 206 to 211 198 to 203 note 1 note 1 VSS1 VSS2 MGU181 VLCDIN VLCDSENSE VLCDOUT 166 to 171 172 173 to 178 note 1 note 1 VSS1 MGU179 V2 V3 V4 V5 162 163 164 165 VLCDIN VSS1 MGU182 2000 Dec 07 54 Philips Semiconductors Product specification 67 × 101 Grey-scale/ECB colour dot matrix LCD driver SYMBOL SA0 SA1 T1 T2 T3 T4 T5 T6 OSC RES SCL SDA_IN SDA_OUT 204 214 205 221 212 213 217 218 220 219 215 and 216 195 and 196 197 VSS1 MGU179 PCF8820 PAD REMARK INTERNAL CIRCUIT VDD1 VSS1 MGU183 note 1 note 1 R0 to R22 (block 1) R23 to R33 (block 2) R34 to R55 (block 3) R56 to R66 (block 4) C0 to C24 (block 5) C25 to C49 (block 6) C50 to C74 (block 7) C75 to C100 (block 8) Note 3 to 25 232 to 222 148 to 127 151 to 161 26 to 50 51 to 75 76 to 100 101 to 126 VSS1 MGU184 VLCDIN 1 diode per block 1. Internally shorted via metal. 2000 Dec 07 55 Philips Semiconductors Product specification 67 × 101 Grey-scale/ECB colour dot matrix LCD driver 16 TRAY INFORMATION x PCF8820 handbook, full pagewidth A C y D B F E MGT141 For the dimensions of A to F: see Table 12. Fig.33 Tray details. Table 12 Tray dimensions DIMENSION A handbook, halfpage DESCRIPTION pocket pitch in x direction pocket pitch in y direction pocket width in x direction pocket width in y direction tray width in x direction tray width in y direction no. pockets in x direction no. pockets in y direction VALUE 13.77 mm 4.45 mm 11.61 mm 2.75 mm 50.8 mm 50.8 mm 3 10 B C D E F − − MGT142 PC8820-1 The orientation of the IC in a pocket is indicated by the position of the IC type name on the die surface with respect to the chamfer on the upper left corner of the tray. Refer to Fig.32 for the orientation and position of the type name on the die surface. Fig.34 Tray alignment. 2000 Dec 07 56 Philips Semiconductors Product specification 67 × 101 Grey-scale/ECB colour dot matrix LCD driver 17 DATA SHEET STATUS DATA SHEET STATUS Objective specification PRODUCT STATUS Development DEFINITIONS (1) PCF8820 This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Preliminary specification Qualification Product specification Production Note 1. Please consult the most recently issued data sheet before initiating or completing a design. 18 DEFINITIONS Short-form specification  The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition  Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information  Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 19 DISCLAIMERS Life support applications  These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes  Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 20 BARE DIE DISCLAIMER All die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a period of ninety (90) days from the date of Philips' delivery. If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post packing tests performed on individual die or wafer. Philips Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, Philips Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify their application in which the die is used. 2000 Dec 07 57 Philips Semiconductors Product specification 67 × 101 Grey-scale/ECB colour dot matrix LCD driver 21 PURCHASE OF PHILIPS I2C COMPONENTS PCF8820 Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 2000 Dec 07 58 Philips Semiconductors Product specification 67 × 101 Grey-scale/ECB colour dot matrix LCD driver NOTES PCF8820 2000 Dec 07 59 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW, Tel. +48 22 5710 000, Fax. +48 22 5710 001 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 58088 Newville 2114, Tel. +27 11 471 5401, Fax. +27 11 471 5398 South America: Al. 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Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 3341 299, Fax.+381 11 3342 553 For all other countries apply to: Philips Semiconductors, Marketing Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 © Philips Electronics N.V. 2000 Internet: http://www.semiconductors.philips.com SCA 70 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 403512/01/pp60 Date of release: 2000 Dec 07 Document order number: 9397 750 06586