PCK2021DGG

INTEGRATED CIRCUITS PCK2021 CK00 (100/133 MHz) spread spectrum differential system clock generator Product data File under Integrated Circuits, ICL03 2001 Oct 11 Philips Semiconductors Philips Semiconductors Product data CK00 (100/133 MHz) spread spectrum differential system clock generator PCK2021 FEATURES • 3.3 V operation • Six differential CPU clock pairs • Two PCI clocks at 33 MHz and one 3V66 clock • Two 48 MHz clocks at 3.3 V • One 14.318 MHz reference clock • Power management control pins • Host clock jitter less than 200 ps cycle-to-cycle • Host clock skew less than 150 ps pin-to-pin • Spread Spectrum capability • Optimized frequency and spread spectrum performance DESCRIPTION The PCK2021 is a clock synthesizer/driver for a Pentium III™ and other similar processors. The PCK2021 has six differential pair CPU current source outputs, two 33 MHz outputs, one 3V66 output, and two 48 MHz clocks which can be disabled on power-up, and one 3.3 V reference clock at 14.318 MHz which can also be disabled on power-up. The part possesses a dedicated power-down input pin for power management control. This input is synchronized on chip, and ensures glitch-free output transitions. In addition, the part can be configured to disable the 48 MHz outputs for lower power operation and an increase in the performance of the functioning outputs. The REF and PCI outputs can also be disabled for the highest performance of the Host outputs. PIN CONFIGURATION VDDPCI 1 VDD48 48M_0/SELA 48M_1/SELB VSS48 3V66 VSS3V66 VDD3V66 VDDCPU 2 3 4 5 6 7 8 9 48 PCI0 47 PCI1 46 VSSPCI 45 SEL133/100 44 NC 43 VDDA 42 VSSA 41 PWRDWN 40 VDDCPU 39 HCLK3 38 HCLKB3 37 VDDCPU 36 HCLK4 35 HCLKB4 34 VSSCPU 33 HCLK5 32 HCLKB5 31 VDD 30 MULTSEL0 29 MULTSEL1 28 VSS 27 VSSIREF 26 IREF 25 VDDIREF HCLK0 10 HCLKB0 11 VDDCPU 12 HCLK1 13 HCLKB1 14 VSSCPU 15 HCLK2 16 HCLKB2 17 VDDCPU 18 REF 19 SPREAD 20 VSSREF 21 XIN 22 XOUT 23 VDDREF 24 SW00960 ORDERING INFORMATION PACKAGES 48-Pin Plastic TSSOP 48-Pin Plastic SSOP TEMPERATURE RANGE 0 to +70 °C 0 to +70 °C ORDER CODE PCK2021DGG PCK2021DL DRAWING NUMBER SOT362-1 SOT370-1 Intel and Pentium III are trademarks of Intel Corporation. 2001 Oct 11 2 853-2301 27233 Philips Semiconductors Product data CK00 (100/133 MHz) spread spectrum differential system clock generator PCK2021 PIN DESCRIPTION PIN(S) 1, 2, 8, 9, 12, 18, 24, 25, 31, 37, 40 3, 4 6 10, 11 13, 14 16, 17 47, 48 39, 38 36, 35 33, 32 19 20 22 23 26 29, 30 41 45 5, 7, 15, 21, 27, 28, 34, 46 43 42 SYMBOL VDD FUNCTION 3.3 V power supply Pins 9, 12, and 18 supply host output pairs 0, 1, and 2. Pins 37 and 40 supply host output pairs 3, 4, and 5. 3.3 V fixed 48 MHz clock outputs. During power-up pins function as latched inputs that enable SELA and SELB prior to the pins being used for output of 3 V at 48 MHz. Part must be clocked to latch data in. 66 MHz clock: 66 MHZ reference clock Host output pair 0 Host output pair 1 Host output pair 2 33 MHz clocks: 33 MHz reference clocks Host output pair 3 Host output pair 4 Host output pair 5 3.3 V fixed 14.318 MHz output Enables spread spectrum mode when held LOW on differential host outputs, 3V66 and PCI clocks. Asserts LOW. Crystal input Crystal output This pin controls the reference current for the host pairs. This pin requires a fixed precision resistor tied to ground in order to establish the correct current. Select input pin used to control the scaling of the HCLK and HCLKB output current. Device enters power-down mode when held LOW. Asserts LOW. Select input pin for enabling 133 MHz or 100 MHz CPU outputs Ground 48M_0/SELA 48M_1/SELB 3V66 HCLK0 HCLKB0 HCLK1 HCLKB1 HCLK2 HCLKB2 PCI0 PCI1 HCLK3 HCLKB3 HCLK4 HCLKB4 HCLK5 HCLKB5 REF SPREAD XIN XOUT IREF MULTSEL0 MULTSEL1 PWRDWN SEL133/100 VSS VDDA VSSA 3.3 V power supply for analog circuits Ground for analog circuits 2001 Oct 11 3 Philips Semiconductors Product data CK00 (100/133 MHz) spread spectrum differential system clock generator PCK2021 BLOCK DIAGRAM PWRDWN XIN 14.318 MHz OSC USB PLL PWRDWN SELA/B PWRDWN SELC REF[0] (14.318 MHz) XOUT 48MHz[0..1] (3 V) HOST[0..5] (100/133 MHz) IREF IBIAS PWRDWN SYS PLL HOST_BAR[0..5] (100/133 MHz) PWRDWN PCI[0..1] (33 MHz) PWRDWN SEL133/100 LOGIC SPREAD MULTSEL0 MULTSEL1 PWRDWN 3V66[0] (66 MHz) SW00961 FUNCTION TABLE SEL100/133 0 0 0 0 1 1 1 SELA 0 0 1 1 0 0 1 SELB 0 1 0 1 0 1 0 HOST 100 MHz 100 MHz 100 MHz Hi-Z 133 MHz 133 MHz 200 MHz 48MHz 48 MHz Disable/Low Disable/Low Hi-Z 48 MHz Disable/Low 48 MHz PCI33MHz 33.3 MHz 33.3 MHz Disable/Low Hi-Z 33.3 MHz 33.3 MHz 33.3 MHz 66MHz 66.7 MHz 66.7 MHz 66.7 MHz Hi-Z 66.7 MHz 66.7 MHz 66.7 MHz REFCLK 14.3 MHz 14.3 MHz Disable/Low Hi-Z 14.3 MHz 14.3 MHz 14.3 MHz 2001 Oct 11 4 Philips Semiconductors Product data CK00 (100/133 MHz) spread spectrum differential system clock generator PCK2021 Table 1. Host swing select functions MULTSEL0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 MULTSEL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 BOARD IMPEDANCE 60 Ω 50 Ω 60 Ω 50 Ω 60 Ω 50 Ω 60 Ω 50 Ω 30 Ω 25 Ω 30 Ω 25 Ω 30 Ω 25 Ω 30 Ω 25 Ω IREF RREF = 475 1% IREF = 2.32 mA RREF = 475 1% IREF = 2.32 mA RREF = 475 1% IREF = 2.32 mA RREF = 475 1% IREF = 2.32 mA RREF = 475 1% IREF = 2.32 mA RREF = 475 1% IREF = 2.32 mA RREF = 475 1% IREF = 2.32 mA RREF = 475 1% IREF = 2.32 mA RREF = 221 1% IREF = 5 mA RREF = 221 1% IREF = 5 mA RREF = 221 1% IREF = 5 mA RREF = 221 1% IREF = 5 mA RREF = 221 1% IREF = 5 mA RREF = 221 1% IREF = 5 mA RREF = 221 1% IREF = 5 mA RREF = 221 1% IREF = 5 mA IOH IOH = 5*IREF IOH = 5*IREF IOH = 6*IREF IOH = 6*IREF IOH = 4*IREF IOH = 4*IREF IOH = 7*IREF IOH = 7*IREF IOH = 5*IREF IOH = 5*IREF IOH = 6*IREF IOH = 6*IREF IOH = 4*IREF IOH = 4*IREF IOH = 7*IREF IOH = 7*IREF VOH @ IREF = 2.32 mA 0.71 V 0.59 V 0.85 V 0.71 V 0.56 V 0.47 V 0.99 V 0.82 V 0.75 V 0.62 V 0.90 V 0.75 V 0.60 V 0.50 V 1.05 V 0.84 V NOTE: The outputs are optimized for the configurations shown shaded. CONDITIONS IOUT IOUT VDD = 3.3 V VDD = 3.3 V ±5% CONFIGURATION All combinations; see Table 1 above All combinations; see Table 1 above LOAD Nominal test load for given configuration Nominal test load for given configuration MIN. –7% of IOH see Table 1 above –12% of IOH see Table 1 above MAX. +7% of IOH see Table 1 above +12% of IOH see Table 1 above POWER-DOWN MODE PWRDWN HCLK/HCLKB 3V66 PCI 48MHz LOW REFCLK LOW Asserts LOW Host = 2*IREF LOW LOW 0 = Active Host_bar = undriven NOTE: The differential outputs should have a voltage forced across them when power-down is asserted. SPREAD SPECTRUM FUNCTION SPREAD # 1 0 FUNCTION Host, PCI, and 3V66 No Spread Host, PCI, and 3V66 spread t0.5% 5 48 MHz PLL REFCLK No Spread No Spread 2001 Oct 11 Philips Semiconductors Product data CK00 (100/133 MHz) spread spectrum differential system clock generator PCK2021 ABSOLUTE MAXIMUM RATINGS SYMBOL VDD3 IIK VI IOK VO IO Tstg Ptot PARAMETER DC 3.3 V supply DC input diode current DC input voltage DC output diode current DC output voltage DC output source or sink current Storage temperature range Power dissipation per package plastic medium-shrink (TSSOP) For temperature range 0 °C to +70 °C; above +55 °C derate linearly with 11.3 mW/K VI < 0 Note 2 VO > VDD or VO < 0 Note 2 VO = 0 to VDD CONDITIONS LIMITS MIN –0.5 — –0.5 — –0.5 — –65 — MAX 4.6 –50 VDD ±50 VDD+0.5 ±50 +150 850 UNIT V mA V mA V mA °C mW NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other condition beyond those indicated under “recommended operating condition” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage rating may be exceeded if the input and output current ratings are observed. RECOMMENDED OPERATING CONDITIONS SYMBOL VDD3 AVDD PARAMETER DC 3.3 V supply voltage DC 3.3 V analog supply voltage Capacitive load on: 3V666 CL PCI 48 MHz clock REF fref Tamb Reference frequency, oscillator normal value Operating ambient temperature range in free air 1 device load, possible 2 Must meet JEDEC PCI 2.1 Spec. Requirements 1 device load 1 device load 10 10 10 10 14.31818 0 30 30 20 20 14.31818 +70 pF pF pF pF MHz °C CONDITIONS LIMITS MIN 3.135 3.135 MAX 3.465 3.465 UNIT V V POWER MANAGEMENT CONDITION MAXIMUM 3.3 V SUPPLY CONSUMPTION MAXIMUM DISCRETE CAPACITANCE LOADS VDDL = 3.465 V ALL STATIC INPUTS = VDD3 OR VSS 60 mA 250 mA Power-down mode (PWRDWN = 0) Full active 100/133 MHz 2001 Oct 11 6 Philips Semiconductors Product data CK00 (100/133 MHz) spread spectrum differential system clock generator PCK2021 DC ELECTRICAL CHARACTERISTICS Tamb = 0 to +70 °C SYMBOL VIH VIL VOH3 VOL3 VOHP VOLP IO OH IO OH IO OH IO OL IO OL VO OL ±II ±IOZ Cin Cout Cxtal PARAMETER HIGH level input voltage LOW level input voltage 3.3 V output HIGH voltage REF, 48M 3.3 V output LOW voltage REF, 48M 3.3 V output HIGH voltage 3V66/PCI 3.3 V output LOW voltage 3V66/PCI Output HIGH current 3V66/PCI Output HIGH current 48 MHz, REF Output HIGH current HOST/HOST_BAR Output LOW current 3V66/PCI Output LOW current 48 MHz, REF HOST/HOST_BAR Input leakage current 3-State output OFF-State current Input pin capacitance Output pin capacitance Crystal input capacitance CONDITIONS VDD (V) 3.135 to 3.465 3.135 to 3.465 3.135 to 3.465 3.135 to 3.465 3.135 to 3.465 3.135 to 3.465 3.135 3.465 3.135 3.465 3.135 to 3.465 to 3.135 3.465 3.135 3.465 VSS = 0 V 3.465 3.465 IOH = –1 mA IOH = 1 mA IOH = –1 mA IOH = 1 mA VOUT = 1.0 V VOUT = 3.135 V VOUT = 1.0 V VOUT = 3.135 V 0.66 V 0.76 V VOUT = 1.95 V VOUT = 0.4 V VOUT = 1.95 V VOUT = 0.4 V RS = 33.2 Ω RP = 49.9 Ω 0 < VIN < VDD3 VOUT = VDD or GND IO = 0 Type 5 y 12 – 55 Ω Type 3 y 20 – 60 Ω Type X1 Type X1 Type 5 y 12 – 55 Ω Type 3 y 20 – 60 Ω Type X1 Type X1 OTHER MIN 2.0 VSS–0.3 2.0 — 2.4 — –33 — –29 — 11 — 30 — 29 — — –50 — — — 13.5 LIMITS TYP — — — — — — — — — — — — — — — — — — — — — — MAX VDD+0.3 0.8 — 0.4 — 0.55 — –33 — –23 — 12.7 — 38 — 27 0.05 50 101 5 6 22.5 UNIT V V V V V V mA mA mA mA mA mA mA mA mA mA V µA µA pF pF pF NOTE: 1. REF output limit is 100 mA. 2001 Oct 11 7 Philips Semiconductors Product data CK00 (100/133 MHz) spread spectrum differential system clock generator PCK2021 AC ELECTRICAL CHARACTERISTICS VDD3 = 3.3 V ±5%; fcrystal = 14.31818 MHz Host clock outputs Tamb = 0 to +70 °C; see Figure 1 for waveforms and Figure 6 for test setup. LIMITS SYMBOL tPERIOD Abs Min Period tRISE tFALL tJITTER DUTY CYCLE tSKEW Vcrossover REFER TO NOTES ON PAGE 10. PARAMETER HOST CLK average period Absolute minimum host clock period HOST CLK rise time HOST CLK fall time HOST_CLK cycle-to-cycle jitter Output duty cycle HOST CLK pin-to-pin skew 133 MHz MODE MIN 7.5 7.35 175 175 — 45 — 45% VOH MAX 7.65 N/A 700 700 150 55 150 55% VOH 100 MHz MODE MIN 10.0 9.85 175 175 — 45 — 45% VOH MAX 10.2 N/A 700 700 150 55 110 55% VOH ns ns ns ps ps % ps V 11, 14, 19 11, 14, 19 11, 15, 19 11, 15, 19 11, 12, 14, 19 11, 14, 19 11, 14, 19 11, 14, 19 UNITS NOTES USB clock output, 48MHz Tamb = 0 to +70 °C; lump capacitance test load = 20 pF LIMITS SYMBOL f fD tRISE tFALL tJITTER DUTY CYCLE Frequency, actual Deviation from 48 MHz 3V48MHZCLK rise time 3V48MHZCLK fall time Cycle-to-cycle jitter Output duty cycle –0 1.0 1.0 — 45 PARAMETER 48 MHz MODE MIN 48.000 +167 4.0 4.0 450 55 MAX MHz ppm ns ns ps % 4 4 8, 19 8, 19 17, 19 17, 19 UNITS NOTES REFER TO NOTES ON PAGE 10. PCI Outputs Tamb = 0 to +70 °C SYMBOL tPERIOD tHIGH tLOW tRISE tFALL DUTY CYCLE tJITTER tSKEW Period High time Low time Rise time Fall time Duty cycle Cycle-to-cycle jitter Pin-to-pin skew PARAMETER LIMITS MIN 30.0 12.0 12.0 0.5 0.5 45 — — MAX N/A N/A N/A 2.0 2.0 55 200 150 UNITS ns ns ns ns ns % ps ps NOTES 2, 3, 9, 19 5, 10, 19 6, 10, 19 8, 19 17, 19 17, 19 17, 19 2 REFER TO NOTES ON PAGE 10. 2001 Oct 11 8 Philips Semiconductors Product data CK00 (100/133 MHz) spread spectrum differential system clock generator PCK2021 3V66 Outputs Tamb = 0 to +70 °C SYMBOL tPERIOD tHIGH tLOW tRISE tFALL DUTY CYCLE tJITTER Period High time Low time Rise time Fall time Duty cycle Cycle-to-cycle jitter PARAMETER LIMITS MIN 15.0 5.25 5.05 0.5 0.5 45 — MAX 16.0 N/A N/A 2.0 2.0 55 400 UNITS ns ns ns ns ns % ps NOTES 2, 3, 9, 19 5, 10, 19 6, 10, 19 8, 19 17, 19 17, 19 17, 19 REFER TO NOTES ON PAGE 10. REF clock output Tamb = 0 to +70 °C; lump capacitance test load = 20 pF LIMITS SYMBOL f tJITTER DUTY CYCLE Frequency, actual Cycle-to-cycle jitter Output duty cycle — 45 PARAMETER 48 MHz MODE MIN 14.318 300 55 MAX MHz ps % 16, 19 17, 19 17, 19 UNITS NOTES REFER TO NOTES ON PAGE 10. All outputs Tamb = 0 to +70 °C LIMITS SYMBOL tPZL, tPZH tPZL, tPZH tSTABLE PARAMETER Output enable delay (all outputs) Output disable delay (all outputs) All clock stabilization from power-up 133 MHz MODE MIN 1.0 1.0 — MAX 10.0 10.0 3 100 MHz MODE MIN 1.0 1.0 — MAX 10.0 10.0 3 ns ns ms 19 19 7, 19 UNITS NOTES REFER TO NOTES ON PAGE 10. 2001 Oct 11 9 Philips Semiconductors Product data CK00 (100/133 MHz) spread spectrum differential system clock generator PCK2021 Group offset limits GROUP 3V66 to PCI OFFSET 0–500 ps, 3V66 leads MEASUREMENT LOADS (LUMPED) 30 pF MEASUREMENT POINTS 1.5 V NOTES 18, 19 NOTES TO THE AC TABLES: 1. Output drivers must have monotonic rise/fall times through the specified VOL/VOH levels. 2. Period, jitter, offset, and skew measured on rising edge at 1.5 V for 3.3 V clocks. 3. PCI is a fixed 33 MHz and 3V66 is a fixed 66 MHz. 4. Frequency accuracy of 48 MHz must be +167 ppm to match USB default. 5. tHIGH is measured at 2.4 V for 3.3 V outputs, as shown in Figure 7. 6. tLOW is measured at 0.4 V for all outputs as shown in Figure 7. 7. the time is specified from when VDDQ achieves its normal operating level (typical condition VDDQ = 3.3 V) until the frequency output is stable and operating within specification. 8. tRISE and tFALL are measured as a transition through the threshold region VOL = 0.4 V and VOH = 2.4 V (1 mA) JEDEC specification. 9. The average period over any 1 µs period of time must be greater than the minimum specified period. 10. Calculated at minimum edge rate (1 V/ns) to guarantee 45–55% duty cycle. Pulse width is required to be wider at faster edge rate to ensure duty specification is met. 11. Test load is RS = 33.2 Ω, RP = 49.9 Ω. 12. Must be guaranteed in a realistic system environment. 13. Configured for VOH = 0.71 V in a 50 Ω environment. 14. Measured at crossing points. 15. Measured at 20% to 80%. 16. Frequency generated by crystal oscillator 17. Voltage measure point (VM = 1.5 V). 18. All offsets are to be measured at rising edges. 19. Parameters are guaranteed by design. 2001 Oct 11 10 Philips Semiconductors Product data CK00 (100/133 MHz) spread spectrum differential system clock generator PCK2021 AC WAVEFORMS VM = 1.25 V @ VDDL and 1.5 V @ VDD3 VX = VOL + 0.3 V VY = VOH – 0.3 V VOL and VOH are the typical output voltage drop that occur with the output load. VOH HOST CLK 50% 50% VSS tPERIOD VI SEL1, SEL0 GND VM SW00962 tPLZ VDD OUTPUT LOW-to-OFF OFF-to-LOW VM VX tPZL Figure 1. HOST CLOCK COMPONENT MEASUREMENT POINTS VOH = 2.4 V VOL VDDL VIH = 2.0 V 1.5 V VIL = 0.7 V SYSTEM MEASUREMENT POINTS tPHZ VOH OUTPUT HIGH-to-OFF OFF-to-HIGH VSS outputs enabled VY VM tPZH VOL = 0.4 V VSS SW00668 outputs disabled outputs enabled Figure 2. 3.3 V clock waveforms SW00662 Figure 3. State enable and disable times VDD S1 2 VDD Open VSS 500 Ω VI PULSE GENERATOR DUT VO RT CL 500 Ω TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 2 VDD VSS VDD = VDD3 SW00963 Figure 4. Load circuitry for switching times 2001 Oct 11 11 Philips Semiconductors Product data CK00 (100/133 MHz) spread spectrum differential system clock generator PCK2021 PWRDWN HOST CLK (INTERNAL) PCICLK (INTERNAL) PWRDWN HOST CLK (EXTERNAL) PCICLK (EXTERNAL) OSC & VCO USB (48 MHz) Figure 5. Power management VDD CL RS HOST CRYSTAL 14.318 MHz DUT RS = 33.2 Ω RP = 50 Ω HOST_BAR RS CL RP = 50 Ω Figure 6. HOST CLOCK measurements tPERIOD DUTY CYCLE tHIGH 3.3V CLOCKING INTERFACE 2.4 V 1.5 V 0.4 V tLOW tRISE tFALL SW00943 Figure 7. 3.3 V clock waveforms 2001 Oct 11 12 Á Á Á Á SW00669 SW00671 Philips Semiconductors Product data CK00 (100/133 MHz) spread spectrum differential system clock generator PCK2021 TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 2001 Oct 11 13 Philips Semiconductors Product data CK00 (100/133 MHz) spread spectrum differential system clock generator PCK2021 SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1 2001 Oct 11 14 Philips Semiconductors Product data CK00 (100/133 MHz) spread spectrum differential system clock generator PCK2021 Data sheet status Data sheet status [1] Objective data Preliminary data Product status [2] Development Qualification Definitions This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. Product data Production [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 © Koninklijke Philips Electronics N.V. 2001 All rights reserved. Printed in U.S.A. Date of release: 10-01 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. Document order number: 9397 750 08953 Philips Semiconductors 2001 Oct 11 15