PCKEP14

PCKEP14 2.5 V/3.3 V 1:5 differential ECL/PECL/HSTL clock driver Rev. 01 — 30 October 2002 Product data 1. Description The PCKEP14 is a low skew 1-to-5 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The ECL/PECL input signals can be either differential or single-ended (if the VBB output is used). HSTL inputs can be used when the PCKEP14 is operating under PECL conditions. The PCKEP14 specifically guarantees low output-to-output skew. Optimal design, layout, and processing minimize skew within a device, and from device to device. To ensure that the tight skew specification is realized, both sides of any differential output need to be terminated identically into 50 Ω resistors, even if only one output is being used. If an output pair is unused, both outputs may be left open (unterminated) without affecting skew. The common enable (EN) is synchronous, outputs are enabled/disabled in the LOW state. This avoids a runt clock pulse when the device is enabled/disabled, as can happen with an asynchronous control. The internal flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. The PCKEP14, as with most other ECL devices, can be operated from a positive VCC supply in PECL mode. This allows the PCKEP14 to be used for high performance clock distribution in +3.3 V or +2.5 V systems. 2. Features s s s s s s s s s 100 ps device-to-device skew 25 ps within device skew 400 ps typical propagation delay Maximum frequency > 2 GHz (typical) Contains temperature compensation PECL and HSTL mode: VCC = 2.375 V to 3.8 V with VEE = 0 V NECL mode: VCC = 0 V with VEE = −2.375 V to −3.8 V LVDS input compatible Open input default state. Philips Semiconductors PCKEP14 2.5 V/3.3 V 1:5 differential ECL/PECL/HSTL clock driver 3. Pinning information 3.1 Pinning Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 1 2 3 4 20 VCC 19 EN 18 VCC 17 CLK1 Q0 1 Q0 2 Q1 3 20 VCC 19 EN 18 VCC PCKEP14PW Q1 4 Q2 5 Q2 6 Q3 7 Q3 8 Q4 9 Q4 10 17 CLK1 16 CLK1 15 VBB 14 CLK0 13 CLK0 12 CLK_SEL 11 VEE PCKEP14D 5 6 7 8 9 16 CLK1 15 VBB 14 CLK0 13 CLK0 12 CLK_SEL 11 VEE Q4 10 002aaa354 002aaa221 Fig 1. SO20 pin configuration. Fig 2. TSSOP20 pin configuration. 3.2 Pin description Table 1: Symbol Q0-Q4 Q0-Q4 VEE CLK_SEL CLK0, CLK1 CLK0, CLK1 VBB VCC EN Pin description Pin 1, 3, 5, 7, 9 2, 4, 6, 8, 10 11 12 13, 16 14, 17 15 18, 20 19 Description Positive ECL/PECL output Negative ECL/PECL output Negative supply ECL/PECL active clock select input. Pin will default LOW when left open. ECL/PECL/HSTL CLK input. Pins will default LOW when left open. ECL/PECL/HSTL CLK input. Pins will default to VCC/2 when left open. Reference voltage output Positive supply ECL synchronous enable 3.2.1 Power supply connection CAUTION All VCC and VEE pins must be connected to power supply to guarantee proper operation. MSC895 9397 750 09565 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 — 30 October 2002 2 of 15 Philips Semiconductors PCKEP14 2.5 V/3.3 V 1:5 differential ECL/PECL/HSTL clock driver 4. Ordering information Table 2: Ordering information Package Name PCKEP14D PCKEP14PW SO20 TSSOP20 Description plastic small outline package 8 leads; body width 7.5 mm plastic thin shrink small outline package; 20 leads; body width 4.4 mm Version SOT163-1 SOT360-1 Type number 5. Logic diagram Q0 1 20 VCC Q0 2 19 EN Q1 3 18 VCC Q1 4 D Q 5 17 CLK1 Q2 16 CLK1 Q2 6 1 0 15 VBB Q3 7 14 CLK0 Q3 8 13 CLK0 Q4 9 12 CLK_SEL Q4 10 11 VEE 002aaa222 Fig 3. Logic diagram. CAUTION All VCC and VEE pins must be connected to power supply to guarantee proper operation. MSC895 9397 750 09565 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 — 30 October 2002 3 of 15 Philips Semiconductors PCKEP14 2.5 V/3.3 V 1:5 differential ECL/PECL/HSTL clock driver 6. Function table Table 3: CLK0 L H X X X [1] Function table CLK1 X X L H X CLK_SEL L L H H X EN L L L L H Q L H L H L[1] On next negative transition of CLK0 or CLK1. 7. Attributes Table 4: Attributes Value 75 kΩ 37.5 kΩ Human Body Model Machine Model Charged Device Model moisture sensitivity, indefinite time out of drypack flammability rating Meets or exceeds JEDEC Specification EIA/JEDS78 IC latch-up test. > 2.5 kV > 100 V > 1 kV Level 1 UL-94 code V-0 A 1/8” Characteristic internal input pull-down resistor internal input pull-up resistor ESD protection 9397 750 09565 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 — 30 October 2002 4 of 15 Philips Semiconductors PCKEP14 2.5 V/3.3 V 1:5 differential ECL/PECL/HSTL clock driver 8. Limiting values Table 5: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCC VEE VI Iout IBB Tamb Tstg Rth(j-a) Rth(j-c) Tsld Parameter PECL mode power supply NECL mode power supply PECL mode input voltage NECL mode input voltage output current VBB source current operating ambient temperature storage temperature range thermal resistance from junction to ambient thermal resistance from junction to case soldering temperature 0 LFPM 500 LFPM Conditions VEE = 0 V VCC = 0 V VEE = 0 V; VI ≤ VCC VCC = 0 V; VI ≥ VEE continuous surge Min 0 −40 −65 23 Max 4.1 −4.1 4.1 −4.1 50 100 0.1 +85 +150 140 100 41 265 Unit V V V V mA mA mA °C °C °C/W °C/W °C/W °C 9. Static characteristics Table 6: PECL DC characteristics[1] VCC = 2.5 V; VEE = 0 V [2] Symbol IEE VOH VOL VIH VIL VIHCMR Parameter power supply current HIGH-level output voltage LOW-level output voltage HIGH-level input voltage LOW-level input voltage HIGH-level input voltage, common mode range (differential) HIGH-level input current LOW-level input current output reference voltage CLK CLK VBB [1] [2] [3] [4] [3] Conditions Tamb = −40 °C Min 45 Typ 60 Max 75 Tamb = +25 °C Min 45 Typ 60 Max 75 Tamb = +85 °C Min 45 Typ 60 Max 75 Unit mA 1355 1480 1605 1355 1500 1605 1355 1510 1605 mV 555 555 720 805 875 2.5 555 555 1.2 700 805 875 2.5 555 555 1.2 710 805 875 2.5 mV mV V [3] single-ended single-ended [4] 1335 1.2 1620 1335 - 1620 1275 - 1620 mV IIH IIL 0.5 - 150 - 0.5 - 150 - 0.5 - 150 - µA µA µA −150 - −150 - −150 - 1075 1165 1265 1065 1165 1265 1085 1180 1270 mV Devices are designed to meet the DC specifications shown in this table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 LFPM is maintained. Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to −1.3 V. All loading with 50 Ω to VCC − 2 V. VIHCMR(min) varies 1:1 with VEE, VIHCMR(max) varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 9397 750 09565 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 — 30 October 2002 5 of 15 Philips Semiconductors PCKEP14 2.5 V/3.3 V 1:5 differential ECL/PECL/HSTL clock driver Table 7: PECL DC characteristics[1] VCC = 3.3 V; VEE = 0 V [2] Symbol IEE VOH VOL VIH VIL VBB VIHCMR Parameter power supply current HIGH-level output voltage LOW-level output voltage HIGH-level input voltage output reference voltage HIGH-level input voltage, common mode range (differential) HIGH-level input current LOW-level input current CLK CLK [1] [2] [3] [4] [5] [3] Conditions 45 Tamb = −40 °C Min Typ 60 Max 75 45 Tamb = +25 °C Min Typ 60 Max 75 45 Tamb = +85 °C Min Typ 60 Max 75 Unit mA 2155 2280 2405 2155 2300 2405 2155 2310 2405 mV 1355 1515 1605 1355 1500 1605 1355 1500 1605 mV 2135 1355 2420 2135 1675 1355 2420 2135 1675 1355 2420 mV 1675 mV [3] single-ended LOW-level input voltage single-ended [4] 1875 1965 2065 1865 1965 2065 1885 1980 2070 mV 1.2 3.3 1.2 3.3 1.2 3.3 V [5] IIH IIL 0.5 - 150 - 0.5 - 150 - 0.5 - 150 - µA µA µA −150 - −150 - −150 - Devices are designed to meet the DC specifications shown in this table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 LFPM is maintained. Input and output parameters vary 1:1 with VCC. VEE can vary +0.925 V to −0.5 V. All loading with 50 Ω to VCC − 2 V. Single-ended input operation is limited to VCC ≥ 3.0 V in PECL mode. VIHCMR(min) varies 1:1 with VEE, VIHCMR(max) varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 9397 750 09565 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 — 30 October 2002 6 of 15 Philips Semiconductors PCKEP14 2.5 V/3.3 V 1:5 differential ECL/PECL/HSTL clock driver Table 8: NECL DC characteristics[1] VCC = 0 V; VEE = −3.8 V to −2.375 V [2] Symbol Parameter IEE VOH VOL VIH VIL VBB VIHCMR power supply current HIGH-level output voltage LOW-level output voltage HIGH-level input voltage LOW-level input voltage output reference voltage HIGH-level input voltage, common mode range (differential) HIGH-level input current LOW-level input current CLK CLK single-ended single-ended [4] [3] Conditions 45 Tamb = −40 °C Min Typ 60 Max 75 45 Tamb = +25 °C Min Typ 60 Max 75 45 Tamb = +85 °C Min Typ 60 Max 95 −895 Unit mA mV −1145 −1020 −895 −1145 −1000 −895 −1145 −990 [3] −1945 −1785 −1695 −1945 −1800 −1695 −1945 −1800 −1695 mV −1165 −1945 −880 −1165 −880 −1165 −880 mV −1625 −1945 - −1625 −1945 - −1625 mV −1425 −1335 −1235 −1435 −1335 −1235 −1415 −1320 −1230 mV VEE+1.2 0 VEE+1.2 0 VEE+1.2 0 V [5] IIH IIL 0.5 −150 - 150 - 0.5 −150 - 150 - 0.5 −150 - 150 - µA µA µA [1] [2] [3] [4] [5] Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 LFPM is maintained. Input and output parameters vary 1:1 with VCC. VEE can vary +0.925 V to −0.5 V. All loading with 50 Ω to VCC − 2 V. Single-ended input operation is limited to VEE ≤ 3.0 V in NECL mode. VIHCMR(min) varies 1:1 with VEE, VIHCMR(max) varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Table 9: HSTL DC characteristics VCC = 2.375 V to 3.8 V; VEE = 0 V. Symbol Parameter VIH VIL HIGH-level input voltage LOW-level input voltage Conditions Tamb = −40 °C Min 1200 Typ 400 Max Tamb = +25 °C Min 1200 Typ 400 Max Tamb = +85 °C Min 1200 Typ 400 Max mV mV Unit 9397 750 09565 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 — 30 October 2002 7 of 15 Philips Semiconductors PCKEP14 2.5 V/3.3 V 1:5 differential ECL/PECL/HSTL clock driver 10. Dynamic characteristics Table 10: AC characteristics (VCC = 0 V; VEE = −2.375 V to −3.8 V) or (VCC = 2.375 V to 3.8 V; VEE = 0 V) [1] Symbol Parameter Conditions see Figure 4 Tamb = −40 °C Min HSTL) Tamb = +25 °C Min 275 100 200 150 125 Typ >2 360 15 150 0.2 50 140 800 200 Max 475 25 175 2 430 15 200 0.2 50 140 800 200 Max 525 25 225 2 345 10 100 0.2 50 140 800 205 Max 425 25 125