PDTA114EU

DISCRETE SEMICONDUCTORS DATA SHEET book, halfpage M3D102 PDTA114EU PNP resistor-equipped transistor Product specification Supersedes data of 1998 May 18 1999 Apr 13 Philips Semiconductors Product specification PNP resistor-equipped transistor FEATURES • Built-in bias resistors R1 and R2 (typ. 10 kΩ each) • Simplification of circuit design • Reduces number of components and board space. APPLICATIONS • Especially suitable for space reduction in interface and driver circuits • Inverter circuit configurations without use of external resistors. DESCRIPTION PNP resistor-equipped transistor in a SOT323 plastic package. NPN complement: PDTC114EU. PINNING MGA893 - 1 PDTA114EU handbook, 4 columns 3 3 R1 1 R2 2 1 Top view 2 MAM135 Fig.1 Simplified outline (SOT323) and symbol. MARKING TYPE NUMBER 1 2 3 MARKING CODE(1) ∗03 PDTA114EU Note PIN 1 2 3 DESCRIPTION base/input emitter/ground (+) collector/output Fig.2 Equivalent inverter symbol. 1. ∗ = - : Made in Hong Kong. ∗ = t : Made in Malaysia. 1999 Apr 13 2 Philips Semiconductors Product specification PNP resistor-equipped transistor LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VCBO VCEO VEBO VI PARAMETER collector-base voltage collector-emitter voltage emitter-base voltage input voltage positive negative IO ICM Ptot Tstg Tj Tamb Note 1. Transistor mounted on an FR4 printed-circuit board. THERMAL CHARACTERISTICS SYMBOL Rth j-a Note 1. Transistor mounted on an FR4 printed-circuit board. CHARACTERISTICS Tamb = 25 °C unless otherwise specified. SYMBOL ICBO ICEO IEBO hFE VCEsat Vi(off) Vi(on) R1 R2 ------R1 Cc PARAMETER collector cut-off current collector cut-off current emitter cut-off current DC current gain input-off voltage input-on voltage input resistor resistor ratio collector capacitance CONDITIONS IE = 0; VCB = −50 V IB = 0; VCE = −30 V IB = 0; VCE = −30 V; Tj = 150 °C IC = 0; VEB = −5 V IC = −5 mA; VCE = −5 V IC = −100 µA; VCE = −5 V IC = −10 mA; VCE = −0.3 V MIN. − − − − 30 − − −2.5 7 0.8 IE = ie = 0; VCB = −10 V; f = 1 MHz − PARAMETER thermal resistance from junction to ambient CONDITIONS note 1 VALUE 625 output current (DC) peak collector current total power dissipation storage temperature junction temperature operating ambient temperature Tamb ≤ 25 °C; note 1 − − − − − −65 − −65 CONDITIONS open emitter open base open collector − − − MIN. PDTA114EU MAX. −50 −50 −10 10 −40 −100 −100 200 +150 150 +150 V V V V V UNIT mA mA mW °C °C °C UNIT K/W TYP. − − − − − − −1.1 −1.8 10 1 − MAX. −100 −1 −50 −400 − −150 −0.8 − 13 1.2 3 UNIT nA µA µA µA mV V V kΩ collector-emitter saturation voltage IC = −10 mA; IB = −0.5 mA pF 1999 Apr 13 3 Philips Semiconductors Product specification PNP resistor-equipped transistor PDTA114EU 103 handbook, halfpage hFE (2) MBK780 handbook, halfpage −1 MBK779 (1) VCEsat (V) 102 (3) −10−1 (1) (2) (3) 10 1 −10−1 −1 −10 IC (mA) −102 −10−2 −1 −10 IC (mA) −102 VCE = −5 V. (1) Tamb = 150 °C. (2) Tamb = 25 °C. (3) Tamb = −40 °C. IC/IB = 20. (1) Tamb = 100 °C. (2) Tamb = 25 °C. (3) Tamb = −40 °C. Fig.3 DC current gain as a function of collector current; typical values. Fig.4 Collector-emitter saturation voltage as a function of collector current; typical values. handbook, halfpage −10 MBK782 −102 handbook, halfpage Vi(on) MBK781 Vi(off) (V) (V) −10 −1 (1) (2) (3) (1) (2) (3) −1 −10−1 −10−2 −10−1 −1 IC (mA) −10 −10−1 −10−1 −1 −10 IC (mA) −102 VCE = −5 V. (1) Tamb = −40 °C. (2) Tamb = 25 °C. (3) Tamb = 100 °C. VCE = −0.3 V. (1) Tamb = −40 °C. (2) Tamb = 25 °C. (3) Tamb = 100 °C. Fig.5 Input-off voltage as a function of collector current; typical values. Fig.6 Input-on voltage as a function of collector current; typical values. 1999 Apr 13 4 Philips Semiconductors Product specification PNP resistor-equipped transistor PACKAGE OUTLINE Plastic surface mounted package; 3 leads PDTA114EU SOT323 D B E A X y HE vMA 3 Q A A1 c 1 e1 e bp 2 wM B Lp detail X 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.8 A1 max 0.1 bp 0.4 0.3 c 0.25 0.10 D 2.2 1.8 E 1.35 1.15 e 1.3 e1 0.65 HE 2.2 2.0 Lp 0.45 0.15 Q 0.23 0.13 v 0.2 w 0.2 OUTLINE VERSION SOT323 REFERENCES IEC JEDEC EIAJ SC-70 EUROPEAN PROJECTION ISSUE DATE 97-02-28 1999 Apr 13 5 Philips Semiconductors Product specification PNP resistor-equipped transistor DEFINITIONS Data Sheet Status Objective specification Preliminary specification Product specification Limiting values PDTA114EU This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1999 Apr 13 6 Philips Semiconductors Product specification PNP resistor-equipped transistor NOTES PDTA114EU 1999 Apr 13 7 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 115002/00/06/pp8 Date of release: 1999 Apr 13 Document order number: 9397 750 05614