PLHS501

Philips Semiconductors Programmable Logic Devices Product specification Programmable macro logic PML™ PLHS501/PLHS501I FEATURES • Programmable Macro Logic device • Full connectivity • TTL compatible • SNAP development system: – Supports third-party schematic entry formats – Macro library – Versatile netlist format for design portability – Logic, timing, and fault simulation PIN CONFIGURATION A Package (52-pin PLCC) I17 I16 I15 I14 I13 I12 I11 I10 I9 7 VCC 8 I18 9 I19 10 I20 11 I21 12 I22 13 I23 14 B4 15 B5 16 B6 17 B7 18 O0 19 GND 20 21 22 23 24 25 26 27 28 29 30 31 32 33 6 5 4 3 2 1 I8 I7 I6 I5 46 VCC 45 I4 44 I3 43 I2 42 I1 41 I0 40 B3 39 B2 38 B1 37 B0 36 X7 35 X6 34 GND 52 51 50 49 48 47 • Delay per internal NAND function = 6.5ns (typ) • Testable in unprogrammed state • Security fuse allows protection of proprietary designs STRUCTURE O1 O2 O3 O4 O5 O6 O7 X0 X1 X2 X3 X4 X5 • NAND gate based architecture – 72 foldback NAND terms • 136 input-wide logic terms • 44 additional logic terms • 24 dedicated inputs (I0 – I23) • 8 bidirectional I/Os with individual 3-State enable: – 4 Active-High (B4 – B7) – 4 Active-Low (B0 – B3) DESCRIPTION The PLHS501 is a high-density Bipolar Programmable Macro Logic device. PML incorporates a programmable NAND structure. The NAND architecture is an efficient method for implementing any logic function. The SNAP software development system provides a user friendly environment for design entry. SNAP eliminates the need for a detailed understanding of the PLHS501 architecture and makes it transparent to the user. PLHS501 is also supported on the Philips Semiconductors SNAP software development systems. The PLHS501 is ideal for a wide range of microprocessor support functions, including bus interface and control applications. The PLHS501 is also processed to industrial requirements for operation over an extended temperature range of –40°C to +85°C and supply voltage of 4.5V to 5.5V. ARCHITECTURE The core of the PLHS501 is a programmable fuse array of 72 NAND gates. The output of each gate folds back upon itself and all other NAND gates. In this manner, full connectivity of all logic functions is achieved in the PLHS501. Any logic function can be created within the core of the device without wasting valuable I/O pins. Furthermore, a speed advantage is acquired by implementing multi-level logic within a fast internal core without incurring any delays from the I/O buffers. • 16 dedicated outputs: – 4 Active-High outputs O0, O1 with common 3-State enable O2, O3 with common 3-State enable – 4 Active-Low outputs: O4, O5 with common 3-State enable O6, O7 with common 3-State enable – 8 Exclusive-OR outputs: X0, X1 with common 3-State enable X2, X3 with common 3-State enable X4, X5 with common 3-State enable X6, X7 with common 3-State enable PML is a trademark of Philips Semiconductors October 22, 1993 1 853–1207 11164 Philips Semiconductors Programmable Logic Devices Product specification Programmable macro logic PML™ PLHS501/PLHS501I ORDERING INFORMATION DESCRIPTION 52-Pin Plastic Leaded Chip Carrier 52-Pin Plastic Leaded Chip Carrier OPERATING CONDITIONS Commercial Temperature Range ±5% Power Supply Industrial Temperature Range ±10% Power Supply ORDER CODE PLHS501A PLHS501IA DRAWING NUMBER 0397E 0397E DESIGN DEVELOPMENT TOOLS SNAP The SNAP Software Development System provides the necessary tools for designing with PML. SNAP provides the following: SNAP operates on an IBM® PC/XT, PC/AT, PS/2, or any compatible system with DOS 2.1 or higher. The minimum system configuration for SNAP is 640K bytes of RAM and a hard disk. SNAP provides primitive PML function libraries for third-party schematic design packages. Custom macro function libraries can be defined in schematic or equation form. After the completion of a design, the software compiles the design for syntax and completeness. Complete simulation can be carried out using the different simulation tools available. The programming data is generated in JEDEC format. Using the Device Programmer Interface (DPI) module of SNAP, the JEDEC fusemap is sent from the host computer to the device programmer. DESIGN SECURITY The PLHS501 has a programmable security fuse that controls the access to the data programmed in the device. By using this programmable feature, proprietary designs implemented in the device cannot be copied or retrieved. • Schematic entry netlist generation from third-party schematic design packages such as OrCAD/SDT III™ and FutureNet™. • Macro library for standard TTL functions and user defined functions • Boolean equation entry • State equation entry • Syntax and design entry checking • Simulator includes logic simulation, fault simulation and timing simulation. PROGRAMMING/SOFTWARE SUPPORT Refer to Section 9 (Development Software) and Section 10 (Third-party Programmer/ Software Support) of this data handbook for additional information. FutureNet is a trademark of FutureNet Corporation. OrCAD/SDT is a trademark of OrCAD, Inc. IBM is a registered trademark of International Business Machines Corporation. October 22, 1993 2 Philips Semiconductors Programmable Logic Devices Product specification Programmable macro logic PML™ PLHS501/PLHS501I PLHS501 FUNCTIONAL BLOCK DIAGRAM 24 DEDICATED INPUTS NAND ARRAY I N T E R C O N N E C T 16 DEDICATED OUTPUTS 8 BIDIRECTIONAL I/OS October 22, 1993 3 Philips Semiconductors Programmable Logic Devices Product specification Programmable macro logic PML™ PLHS501/PLHS501I FUNCTIONAL DIAGRAM 71 0 I0 I23 x2 x2 x2 x2 x2 x2 x4 x4 x4 x4 x4 x4 x4 x4 x4 B0 – B3 x4 B4 – B7 x4 X0, X2, X4, X6 X1, X3, X5, X7 x4 x2 O0, O2 x2 O1, O3 x2 x2 O4, O6 O5, O7 DETAIL A October 22, 1993 4 Philips Semiconductors Programmable Logic Devices Product specification Programmable macro logic PML™ PLHS501/PLHS501I DETAIL A 40 B3 39 B2 38 B1 37 B0 15 B4 16 B5 17 B6 18 B7 28 X0 29 X1 30 X2 31 X3 32 X4 33 X5 35 X6 36 X7 19 O0 21 O1 22 O2 23 O3 24 O4 25 O5 26 O6 27 O7 October 22, 1993 5 Philips Semiconductors Programmable Logic Devices Product specification Programmable macro logic PML™ ABSOLUTE MAXIMUM RATINGS1 RATINGS SYMBOL VCC VIN VOUT IIN IOUT Tamb Tstg PARAMETER Supply voltage Input voltage Output voltage Input currents Output currents Operating temperature range Storage temperature range 0 –65 –30 MIN MAX +7 +5.5 +5.5 +30 +100 +75 +150 UNIT VDC VDC VDC mA mA °C °C PLHS501/PLHS501I NOTE: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied. THERMAL RATINGS TEMPERATURE Maximum junction Maximum ambient Allowable thermal rise ambient to junction 150°C 75°C 75°C VIRGIN STATE A factory shipped virgin device contains all fusible links open, such that: 1. All product terms are enabled. 2. All bidirectional (B) pins are outputs. 3. All outputs are enabled. 4. All outputs are Active-High except B0 – B3 (fusible I/O) and O4 – O7 which are Active-Low. October 22, 1993 6 Philips Semiconductors Programmable Logic Devices Product specification Programmable macro logic PML™ PLHS501/PLHS501I DC ELECTRICAL CHARACTERISTICS Commercial= 0°C ≤ Tamb ≤ +75°C, 4.75V ≤ VCC ≤ 5.25V Industrial = –40°C ≤ Tamb ≤ +85°C, 4.5V ≤ VCC ≤ 5.5V LIMITS SYMBOL Input VIL VIH VIC voltage2 Low High Clamp2, 3 VCC = MIN VCC = MAX VCC = MIN, IIN = –12mA 0.8 2.0 –0.8 –1.2 V V V PARAMETER TEST CONDITION MIN TYP1 MAX UNIT Output voltage VOL VOH Low2, 4 High2, 5 VCC = MIN IOL = 10mA IOH = –2mA 0.45 2.4 V V Input current IIL IIH Low High VCC = MAX VIN = 0.45V VIN = 5.5V –100 40 µA µA Output current IO(OFF) IOS ICC Capacitance CIN CB Input I/O VCC = 5V VIN = 2.0V VOUT = 2.0V 8 15 pF pF Hi-Z state9 Short circuit3, 5, 6 VCC supply current8 VCC = MAX VOUT = 5.5V VOUT = 0.45V VOUT = 0V VCC = MAX 80 –140 –70 225 295 µA mA mA –15 NOTES: 1. All typical values are at VCC = 5V, Tamb = +25°C. 2. All voltage values are with respect to network ground terminal. 3. Test one at a time. 4. For Pins 15 – 19, 21 – 27 and 37 – 40, VOL is measured with Pins 5 and 41 = 8,75V, Pin 43 = 0V and Pins 42 and 44 = 4.5V. For Pins 28 – 33 and 35 – 36, VOL is measured under same conditions EXCEPT Pin 44 = 0V. 5. VOH is measured with Pins 5 and 41 = 8.75V, Pins 42 and 43 = 4.5V and Pin 44 = 0V. 6. Duration of short circuit should not exceed 1 second. 7. ICC is measured with all dedicated inputs at 0V and bidirectional and output pins open. 8. Measured at VT = VOL + 0.5V. 9. Leakage values are a combination of input and output leakage. TEST LOAD CIRCUITS VCC +5V S1 VOLTAGE WAVEFORMS +3.0V 90% C1 C2 I0 BY 10% R1 0V tR tF 2.5ns R2 CL +3.0V 2.5ns INPUTS I10 BW DUT 90% BZ BX GND OX 10% OUTPUTS 0V NOTE: C1 and C2 are to bypass VCC to GND. 2.5ns 2.5ns MEASUREMENTS: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified. Input Pulses October 22, 1993 7 Philips Semiconductors Programmable Logic Devices Product specification Programmable macro logic PML™ PLHS501/PLHS501I SNAP RESOURCE SUMMARY DESIGNATIONS 71 I0 DIN501 NIN501 0 I23 FBNAND x2 x2 x2 x2 x2 x2 x4 NAND x4 x4 x4 x4 x4 x4 x4 B0 – B3 OUT501 x4 x4 B4 – B7 NOU501 x4 x4 X0, X2, X4, X6 EXO501 X1, X3, X5, X7 x2 O0, O2 x2 O1, O3 O4, O6 O5, O7 NOU501 x2 x2 TOU501 October 22, 1993 8 Philips Semiconductors Programmable Logic Devices Product specification Programmable macro logic PML™ MACRO CELL SPECIFICATIONS1 (SNAP Resource Summary Designations in Parantheses) Commercial:Tamb = 0°C to +75°C, 4.75V ≤ VCC ≤ 5.25V, CL = 30pF, R2 = 1000Ω, R1 = 470Ω Industrial: Tamb = –40°C to +85°C, 4.5V ≤ VCC ≤ 5.5V, CL = 30pF, R2 = 1000Ω, R1 = 470Ω Input Buffer (DIN501 [Non-inverting], NIN501 [Inverting]) X I Y PLHS501/PLHS501I LIMITS SYMBOL MIN 0.05 –0.02 TYP 0.1 –0.05 LIMITS MIN 4.5 5 2.5 4 TYP 5.5 6 3 4 MAX 6.5 7.5 3.5 4.5 UNIT ns ns ns ns NOTES With 0 p-terms load With 0 p-terms load MAX 0.15 –0.08 UNIT ns/p-term ns/p-term ∆tHL ∆tLH PARAMETER SYMBOL tPHL tPLH tPHL tPLH To (Output) X X Y Y From (Input) I I I I Input Pins: 1 – 7, 9 – 14, 41 – 45, 48 – 52. Bidirectional Pins: 15 – 18, 37 – 40. Maximum internal fan-out: 16 p-terms on X or Y. NAND Output Buffer with 3-State Control (TOU501) Tri–Ctrl In Out PARAMETER SYMBOL tPHL tPLH tOE2 tOD2 To (Output) Out Out Out Out From (Input) In In Tri-Ctrl Tri-Ctrl MIN 8.5 8.5 8.5 8.5 LIMITS TYP 14.0 14.0 15 12.5 MAX 17.5 16 18.5 17.0 UNIT ns ns ns ns Output Pins: 24 – 27. Internal Foldback NAND (FBNAND) Input Output LIMITS SYMBOL MIN 0.05 –0.0 TYP 0.1 –0.05 LIMITS MIN 4.0 5.5 TYP 4.5 6.5 MAX 6.8 8 UNIT ns ns NOTES With 0 p-terms load MAX 0.15 –0.1 UNIT ns/p-term ns/p-term ∆tPHL ∆tPLH PARAMETER SYMBOL tPHL tPLH To (Output) Out From (Input) Any Maximum internal loading of 16 terms. Notes are on following page. October 22, 1993 9 Philips Semiconductors Programmable Logic Devices Product specification Programmable macro logic PML™ PLHS501/PLHS501I MACRO CELL SPECIFICATIONS1 (Continued) (SNAP Resource Summary Designations in Parantheses) Commercial:Tamb = 0°C to +75°C, 4.75V ≤ VCC ≤ 5.25V, CL = 30pF, R2 = 1000Ω, R1 = 470Ω Industrial: Tamb = –40°C to +85°C, 4.5V ≤ VCC ≤ 5.5V, CL = 30pF, R2 = 1000Ω, R1 = 470Ω AND Output Buffer with 3-State Control (NOU501) Tri–Ctrl In Out PARAMETER SYMBOL tPHL tPLH tOE2 tOD2 To (Output) Output Output Out Out From (Input) In In Tri-Ctrl Tri-Ctrl MIN 8.0 8.0 8.5 8.5 LIMITS TYP 11 11 15 12.5 MAX 13 13 18.5 17.0 UNIT ns ns ns ns Bidirectional and Output Pins: 19, 21, 22, 23, 15 – 18. NAND Output Buffer (OUT501) In Out PARAMETER SYMBOL tPHL tPLH To (Output) Out Out From (Input) In In MIN 8.5 8.5 LIMITS TYP 14 14 MAX 17.5 16.0 UNIT ns ns Bidirectional Pins: 37 – 40. Ex–OR Output Buffer (EXO501) Tri–Ctrl A Out B PARAMETER SYMBOL tPHL tPLH tOE2 tOD2 To (Output) Out Out Out Out From (Input) A or B A or B Tri-Ctrl Tri-Ctrl MIN 8.5 8.5 8.5 8.5 LIMITS TYP 14 14 15 12.5 MAX 17.5 16.0 18.5 17.0 UNIT ns ns ns ns Ex-OR Output Pins: 28 – 33. NOTES: 1. Limits are guaranteed with internal feedback buffers simultaneously switching cumulative maximum of eight outputs. 2. For 3-State output; output enable times are tested with CL = 30pF to the 1.5V level, and S1 is open for high-impedance to High tests and closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output voltage of VT = (VOH – 0.5V) with S1 open, and Low-to-High impedance tests are made to the VT = (VOL + 0.5V) level with S1 closed. October 22, 1993 10 Philips Semiconductors Programmable Logic Devices Product specification Programmable macro logic PML™ PLHS501/PLHS501I PLHS501 GATE AND SPEED ESTIMATE TABLE FUNCTION Gates NANDs ANDs NORs ORs Decoders 3-to-8 4-to-16 5-to-32 Encoders 8-to-3 16-to-4 32-to-5 Multiplexers 4-to-1 8-to-1 16-to-1 27-to-1 Flip-Flops D-type Flip-Flop T-type Flip-Flop J-K-type Flip-Flop Adders 8-bit Barrel Shifters 8-bit Latches D-latch 3 2 levels of logic with one shared gate 72 11ns 2 levels of logic 45 15.5ns Full carry-lookahead (four levels of logic) 6 6 10 30MHz 30MHz 30MHz With asynchronous S-R With asynchronous S-R With asynchronous S-R 5 9 17 28 11ns 11ns 11ns 11ns Inverted inputs available 15 32 41 11ns 11ns 11ns Inverted inputs, 2 logic levels Inverted inputs, 2 logic levels Inverted inputs, 2 logic levels, factored solution. 8 16 32 11ns 11ns 11ns Inverted inputs available Inverted inputs available Inverted inputs available (24 chip outputs only) 1 1 1 1 6.5ns 6.5ns 6.5ns 6.5ns For 1 to 32 input variables For 1 to 32 input variables For 1 to 32 input variables For 1 to 32 input variables INTERNAL NAND EQUVALENT TYPICAL tPD fMAX COMMENTS Can address only 27 external inputs - more if internal October 22, 1993 11 Philips Semiconductors Programmable Logic Devices Product specification Programmable macro logic PML™ PLHS501/PLHS501I APPLICATIONS MASTER MODULE SPECIFIC SLAVE MODULE SPECIFIC ARBITRATION BUS CONTROL PLHS501 CLOCK ORIGINATION SLOT ID SLOT ID CLOCK ADDRESS, DATA, CONTROL AND PARITY NUBUS ARBITRATION Simplified NUBUS™ Diagram (10MHz Operating Frequency) –ADL –CDSETUP –M/–IO –S1 –S0 –A2 –A1 –A0 –CMD D07 | D00 CHRESET 8 POS BYTE 2 CARD I.D. POS BYTE 1 CARD I.D. POS BYTE 0 TRANSCEIVER CONTROL BUFEN DIR 7-BIT LATCH 7 8-BIT LATCH 8 POS BYTE 2 DATA OUTPUT 8 OCTAL 3 to 1 MULTIPLEXER 8 3-STATE DRIVER 8 8 Block Diagram of Basic POS Implementation in PLHS501 NuBus is a trademark of Texas Instruments, Inc. October 22, 1993 12