PLS159A

Philips Semiconductors Programmable Logic Devices Product specification Programmable logic sequencer (16 × 45 × 12) PLS159A DESCRIPTION The PLS159A is a 3-State output, registered logic element combining AND/OR gate arrays with clocked J-K flip-flops. These J-K flip-flops are dynamically convertible to D-type via a “fold-back” inverting buffer and control gate FC. It features 8 registered I/O outputs (F) in conjunction with 4 bidirectional I/O lines (B). These yield variable I/O gate and register configurations via control gates (D, L) ranging from 16 inputs to 12 outputs. The AND/OR arrays consist of 32 logic AND gates, 13 control AND gates, and 21 OR gates with fusible link connections for programming I/O polarity and direction. All AND gates are linked to 4 inputs (I), bidirectional I/O lines (B), internal flip-flop outputs (Q), and Complement Array output (C). The Complement Array consists of a NOR gate optionally linked to all AND gates for generating and propagating complementary AND terms. On-chip T/C buffers couple either True (I, B, Q) or Complement (I, B, Q, C) input polarities to all AND gates, whose outputs can be optionally linked to all OR gates. Any of the 32 AND gates can drive bidirectional I/O lines (B), whose output polarity is individually programmable through a set of Ex-OR gates for implementing AND-OR or AND-NOR logic functions. Similarly, any of the 32 AND gates can drive the J-K inputs of all flip-flops. There are 4 AND gates for the Asynchronous Preset/Reset functions. All flip-flops are positive edge-triggered and can be used as input, output or I/O (for interfacing with a bidirectional data bus) in conjunction with load control gates (L), steering inputs (I), (B), (Q) and programmable output select lines (E). The PLS159A is field-programmable, enabling the user to quickly generate custom patterns using standard programming equipment. FEATURES • High-speed version of PLS159 • fMAX = 18MHz – 25MHz clock rate PIN CONFIGURATIONS N Package CLK I0 I1 I2 I3 B0 B1 B2 B3 1 2 3 4 5 6 7 8 9 20 19 18 17 16 15 14 13 12 11 VCC F7 F6 F5 F4 F3 F2 F1 F0 OE • Field-Programmable (Ni-Cr link) • 4 dedicated inputs • 13 control gates • 32 AND gates • 21 OR gates • 45 product terms: – 32 logic terms – 13 control terms GND 10 • 4 bidirectional I/O lines • 8 bidirectional registers • J-K, T, or D-type flip-flops • Power-on reset feature on all flip-flops • Asynchronous Preset/Reset • Complement Array • Active-High or -Low outputs • Programmable OE control • Positive edge-triggered clock • Input loading: –100µA (max.) • Power dissipation: 750mW (typ.) • TTL compatible • 3-State outputs APPLICATIONS (Fn = 1) N = Plastic Dual In-Line Package (300mil-wide) A Package I1 3 I2 I3 B0 B1 B2 4 5 6 7 8 9 10 11 12 13 I0 CLK VCC F7 2 1 20 19 18 17 16 15 14 F6 F5 F4 F3 F2 B3 GND OE F0 F1 A = Plastic Leaded Chip Carrier • Random sequential logic • Synchronous up/down counters • Shift registers • Bidirectional data buffers • Timing function generators • System controllers/synchronizers • Priority encoder/registers ORDERING INFORMATION DESCRIPTION 20-Pin Plastic Dual In-Line Package (300mil-wide) 20-Pin Plastic Leaded Chip Carrier ORDER CODE PLS159AN PLS159AA DRAWING NUMBER 0408D 0400E October 22, 1993 25 853–1159 11164 Philips Semiconductors Programmable Logic Devices Product specification Programmable logic sequencer (16 × 45 × 12) PLS159A LOGIC DIAGRAM (LOGIC TERMS-T) (CONTROL TERMS) 11 OE I0 I1 I2 I3 2 3 4 5 F0 F1 F2 F3 F4 F5 F6 F7 B0 B1 B2 B3 C C S3 X3 S2 X2 S1 X1 S0 X0 M7 P J K M6 J K M5 J K M4 J K Q CK’ P J K M2 J K M1 J K M0 J K 31 24 23 16 15 87 0 FC Q CK’ 1 CLK Q CK’ 12 F0 Q CK’ 13 F1 R Q CK’ 14 F2 Q CK’ 16 F4 Q CK’ 17 F5 R Q CK’ 18 F6 PB RB PA RA LB LA D3 D2 D1 D0 EA EB 9 8 7 6 B3 B2 B1 B0 19 F7 M3 15 F3 CK NOTES: 1. All OR gate inputs with a blown link float to logic “0”. 2. All other gates and control inputs with a blown link float to logic “1”. 3. ⊕ denotes WIRE-OR. 4. Programmable connection. October 22, 1993 26 Philips Semiconductors Programmable Logic Devices Product specification Programmable logic sequencer (16 × 45 × 12) PLS159A FUNCTIONAL DIAGRAM (LOGIC TERMS) PB a b RB (CONTROL TERMS) PA RA LB LA D a a b b EA EB OE Q Q C C S X P J M K (4) CK R Q B F P J M K (4) R Q F CK T31 T0 FC CK CLK LOGIC FUNCTION Q3 1 Q2 0 Q1 1 Q0 0 SR PRESENT STATE A B C ... Sn + 1 NEXT STATE FLIP-FLOP TRUTH TABLE OE H L L X X X L L L L H H X X X X X ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ L H L L L L L L L X X XX L X X L L CK P RJ KQ F Hi-Z H L H Q H L Q H* L* H* * L* * STATE REGISTER 0 0 0 1 ⋅⋅⋅ XH X L L HX L L L L SET Q0: J0 = (Q3 K0 = 0 ⋅ Q2 Q1 Q0) A B C . . . ⋅ ⋅ ⋅⋅⋅ L L L L H H +10V LQ HL LH HQ HL LH HL LH RESET Q1: J1 = 0 K1 = (Q3 Q2 Q1 Q0) A B C . . . ⋅ ⋅ ⋅ ⋅⋅⋅ LH LH L L HOLD Q2: J2 = 0 K2 = 0 NOTES: 1. Positive Logic: J-K = T0 + T1 + T2 ……………… T31 Tn = C⋅ (I0 ⋅ I1 ⋅ I2 …) ⋅ (Q0 ⋅ Q1 …) ⋅ (B0 ⋅ B1 ⋅ …) 2. ↑ denotes transition from Low to High level. 3. X = Don’t care 4. * = Forced at Fn pin for loading the J-K flip-flop in the Input mode. The load control term, Ln must be enabled (HIGH) and the p-terms that are connected to the associated flip-flop must be forced LOW (disabled) during Preload. 5. At P = R = H, Q = H. The final state of Q depends on which is released first. 6. * * = Forced at Fn pin to load J-K flip-flop independent of program code (Diagnostic mode), 3-State B outputs. TOGGLE Q3: J3 = (Q3 Q2 Q1 Q0) A B C . . . ⋅ ⋅ ⋅ ⋅⋅⋅ K3 = (Q3⋅ Q2 ⋅ Q1 ⋅ Q0) ⋅ A ⋅ B ⋅ C . . . LH X L NOTE: Similar logic functions are applicable for D and T mode flip-flops. XH October 22, 1993 27 Philips Semiconductors Programmable Logic Devices Product specification Programmable logic sequencer (16 × 45 × 12) PLS159A VIRGIN STATE The factory shipped virgin device contains all fusible links intact, such that: 1. OE is always enabled. 2. Preset and Reset are always disabled. 3. All transition terms are disabled. 4. All flip-flops are in D-mode unless otherwise programmed to J-K only or J-K or D (controlled). 5. All B pins are inputs and all F pins are outputs unless otherwise programmed. CAUTION: PLS159A PROGRAMMING ALGORITHM The programming voltage required to program the PLS159A is higher (17.5V) than that required to program the PLS159 (14.5V). Consequently, the PLS159 programming algorithm will not program the PLS159A. Please exercise caution when accessing programmer device codes to insure that the correct algorithm is used. THERMAL RATINGS TEMPERATURE Maximum junction Maximum ambient Allowable thermal rise ambient to junction 150°C 75°C 75°C ABSOLUTE MAXIMUM RATINGS1 RATINGS SYMBOL VCC VIN VOUT IIN IOUT Tamb Tstg Supply voltage Input voltage Output voltage Input currents Output currents Operating temperature range Storage temperature range 0 –65 –30 PARAMETER MIN MAX +7 +5.5 +5.5 +30 +100 +75 +150 UNIT VDC VDC VDC mA mA °C °C NOTES: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied. October 22, 1993 28 Philips Semiconductors Programmable Logic Devices Product specification Programmable logic sequencer (16 × 45 × 12) PLS159A DC ELECTRICAL CHARACTERISTICS 0°C ≤ Tamb ≤ +75°C, 4.75V ≤ VCC ≤ 5.25V LIMITS SYMBOL Input VIH VIL VIC Output VOH VOL voltage2 High Low Clamp voltage2 High Low VCC = MIN, IOH = –2mA IOL = 10mA 2.4 0.35 0.5 V V VCC = MAX VCC = MIN VCC = MIN, IIN = –12mA –0.8 2.0 0.8 –1.2 V V V PARAMETER TEST CONDITION MIN TYP1 MAX UNIT Input current IIH IIL High Low VCC = MAX, VIN = 5.5V VIN = 0.45V