PLUS153DN

Philips Semiconductors Programmable Logic Devices Product specification Programmable logic arrays (18 × 42 × 10) PLUS153B/D DESCRIPTION The PLUS153 PLDs are high speed, combinatorial Programmable Logic Arrays. The Philips Semiconductors state-of-the-art Oxide Isolated Bipolar fabrication process is employed to produce propagation delays as short as 12ns. The 20-pin PLUS153 devices have a programmable AND array and a programmable OR array. Unlike PAL® devices, 100% product term sharing is supported. Any of the 32 logic product terms can be connected to any or all of the 10 output OR gates. Most PAL ICs are limited to 7 AND terms per OR function; the PLUS153 devices can support up to 32 input wide OR functions. The polarity of each output is user-programmable as either active-High or active-Low, thus allowing AND-OR or AND-NOR logic implementation. This feature adds an element of design flexibility, particularly when implementing complex decoding functions. The PLUS153 devices are user-programmable using one of several commercially available, industry standard PLD programmers. FEATURES • I/O propagation delays (worst case) – PLUS153B – 15ns max. – PLUS153D – 12ns max. PIN CONFIGURATIONS N Package I0 I1 I2 I3 I4 I5 I6 I7 B0 1 2 3 4 5 6 7 8 9 20 VCC 19 B9 18 B8 17 B7 16 B6 15 B5 14 B4 13 B3 12 B2 11 B1 • Functional superset of 16L8 and most other 20-pin combinatorial PAL devices • Two programmable arrays – Supports 32 input wide OR functions • 8 inputs • 10 bi-directional I/O • 42 AND gates – 32 logic product terms – 10 direction control terms GND 10 • Programmable output polarity – Active-High or Active-Low N = Plastic Dual In-Line Package (300mil-wide) • Security fuse • 3-State outputs • Power dissipation: 750mW (typ.) • TTL Compatible APPLICATIONS I3 I4 I5 I6 I7 4 5 6 7 8 A Package I2 3 I1 2 I0 VCC B9 1 20 19 18 B8 17 B7 16 B6 15 B5 14 B4 9 10 11 12 13 • Random logic • Code converters • Fault detectors • Function generators • Address mapping • Multiplexing tPD (MAX) 15ns 12ns 15ns 12ns B0 GND B1 B2 B3 A = Plastic Leaded Chip Carrier ORDERING INFORMATION DESCRIPTION 20-Pin Plastic Dual-In-Line 300mil-wide 20-Pin Plastic Dual-In-Line 300mil-wide 20-Pin Plastic Leaded Chip Carrier 20-Pin Plastic Leaded Chip Carrier ORDER CODE PLUS153BN PLUS153DN PLUS153BA PLUS153DA DRAWING NUMBER 0408D 0408D 0400E 0400E ®PAL is a registered trademark of Monolithic Memories, Inc., a wholly owned subsidiary of Advanced Micro Devices Corporation. October 22, 1993 9 853–1285 11164 Philips Semiconductors Programmable Logic Devices Product specification Programmable logic arrays (18 × 42 × 10) PLUS153B/D LOGIC DIAGRAM (LOGIC TERMS–P) I0 I1 I2 I3 I4 I5 I6 I7 1 2 3 4 5 6 7 8 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 (CONTROL TERMS) S9 X9 X8 X7 X6 X5 X4 X3 X2 X1 31 24 23 16 15 87 0 X0 S8 S7 S6 S5 S4 S3 S2 S1 S0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 19 B9 18 B8 17 B7 16 B6 15 B5 14 B4 13 B3 12 B2 11 B1 9 B0 NOTES: 1. All programmed ‘AND’ gate locations are pulled to logic “1”. 2. All programmed ‘OR’ gate locations are pulled to logic “0”. 3. Programmable connection. October 22, 1993 10 Philips Semiconductors Programmable Logic Devices Product specification Programmable logic arrays (18 × 42 × 10) PLUS153B/D FUNCTIONAL DIAGRAM P31 I0 P0 D0 D9 I7 B0 B9 S9 X9 B9 S0 X0 B0 ABSOLUTE MAXIMUM RATINGS1 RATING SYMBOL VCC VIN VOUT IIN IOUT Tamb Tstg PARAMETER Supply voltage Input voltage Output voltage Input currents Output currents Operating free-air temperature range Storage temperature range 0 –65 –30 MIN MAX +7 +5.5 +5.5 +30 +100 +75 +150 UNIT VDC VDC VDC mA mA °C °C THERMAL RATINGS TEMPERATURE Maximum junction Maximum ambient Allowable thermal rise ambient to junction 150°C 75°C 75°C NOTES: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied. October 22, 1993 11 Philips Semiconductors Programmable Logic Devices Product specification Programmable logic arrays (18 × 42 × 10) PLUS153B/D DC ELECTRICAL CHARACTERISTICS 0°C ≤ Tamb ≤ +75°C, 4.75 ≤ VCC ≤ 5.25V LIMITS SYMBOL Input VIL VIH VIC Output voltage2 Low High Clamp voltage2 VCC = MIN VOL VOH Low4 High5 IOL = 15mA IOH = –2mA 2.4 0.5 V V VCC = MIN VCC = MAX VCC = MIN, IIN = –12mA 2.0 –0.8 –1.2 0.8 V V V PARAMETER TEST CONDITIONS MIN TYP1 MAX UNIT Input current9 VCC = MAX IIL IIH Low High VIN = 0.45V VIN = VCC –100 40 µA µA Output current VCC = MAX IO(OFF) Hi-Z state8 VOUT = 2.7V VOUT = 0.45V IOS ICC Capacitance VCC = 5V CIN CB Input I/O VIN = 2.0V VB = 2.0V 8 15 pF pF Short circuit3, 5, 6 VCC supply current7 VOUT = 0V VCC = MAX –15 150 80 –140 –70 200 mA mA µA NOTES: 1. All typical values are at VCC = 5V, Tamb = +25°C. 2. All voltage values are with respect to network ground terminal. 3. Test one at a time. 4. Measured with inputs I0 – I2 = 0V, inputs I3 – I5 = 4.5V, inputs I7 = 4.5V and I6 = 10V. For outputs B0 – B4 and for outputs B5 – B9 apply the same conditions except I7 = 0V. 5. Same conditions as Note 4 except I7 = +10V. 6. Duration of short circuit should not exceed 1 second. 7. ICC is measured with inputs I0 – I7 and B0 – B9 = 0V. 8. Leakage values are a combination of input and output leakage. 9. IIL and IIH limits are for dedicated inputs only (I0 – I7). October 22, 1993 12 Philips Semiconductors Programmable Logic Devices Product specification Programmable logic arrays (18 × 42 × 10) PLUS153B/D AC ELECTRICAL CHARACTERISTICS 0°C ≤ Tamb ≤ +75°C, 4.75V ≤ VCC ≤ 5.25V, R1 = 300Ω, R2 = 390Ω LIMITS SYMBOL PARAMETER FROM TO TEST CONDITION tPD tOE tOD Propagation Delay2 Output Enable1 Output Disable1 Input +/– Input +/– Input +/– Output +/– Output – Output + CL = 30pF CL = 30pF CL = 5pF MIN PLUS153B TYP 11 11 11 MAX 15 15 15 MIN PLUS153D TYP 10 10 10 MAX 12 12 12 ns ns ns UNIT NOTES: 1. For 3-State output; output enable times are tested with CL = 30pF to the 1.5V level, and S1 is open for high-impedance to High tests and closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output voltage of VT = (VOH – 0.5V) with S1 open, and Low-to-High impedance tests are made to the VT = (VOL + 0.5V) level with S1 closed. 2. All propagation delays are measured and specified under worst case conditions. VOLTAGE WAVEFORMS +3.0V 90% TEST LOAD CIRCUIT VCC 10% +5V S1 0V 5ns +3.0V 90% tR tF 5ns C1 C2 I0 BY R1 INPUTS 10% 0V 5ns 5ns I7 BW DUT R2 CL BX GND BZ OUTPUTS MEASUREMENTS: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified. Input Pulses NOTE: C1 and C2 are to bypass VCC to GND. TIMING DEFINITIONS SYMBOL tPD tOD PARAMETER Propagation delay between input and output. Delay between input change and when output is off (Hi-Z or High). Delay between input change and when output reflects specified output level. TIMING DIAGRAM +3V I, B 1.5V 1.5V 1.5V 0V VOH B 1.5V VT tOD tOE 1.5V VOL tPD tOE October 22, 1993 13 Philips Semiconductors Programmable Logic Devices Product specification Programmable logic arrays (18 × 42 × 10) PLUS153B/D LOGIC PROGRAMMING The PLUS153B/D is fully supported by industry standard (JEDEC compatible) PLD CAD tools, including Philips Semiconductors SNAP design software package. ABEL™ and CUPL™ design software packages also support the PLUS153B/D architecture. All packages allow Boolean and state equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic capture format. PLUS153B/D logic designs can also be generated using the program table entry format, which is detailed on the following page. This program table entry format is supported by SNAP only. To implement the desired logic functions, the state of each logic variable from logic equations (I, B, O, P, etc.) is assigned a symbol. The symbols for TRUE, COMPLEMENT, INACTIVE, PRESET, etc., are defined below. PROGRAMMING AND SOFTWARE SUPPORT Refer to Section 9 (Development Software) and Section 10 (Third-Party Programmer/Software Support) of this data handbook for additional information. OUTPUT POLARITY – (B) S B X X S B ACTIVE LEVEL HIGH1 (NON–INVERTING) CODE H ACTIVE LEVEL LOW CODE L (INVERTING) AND ARRAY – (I, B) I, B I, B I, B I, B I, B I, B I, B I, B I, B I, B I, B I, B P, D STATE INACTIVE1, 2 CODE O STATE I, B P, D CODE H STATE I, B P, D CODE L STATE DON’T CARE P, D CODE – OR ARRAY – (B) P S P S VIRGIN STATE A factory shipped virgin device contains all fusible links intact, such that: 1. All outputs are at “H” polarity. 2. All Pn terms are disabled. 3. All Pn terms are active on all outputs. Pn STATUS ACTIVE1 CODE A Pn STATUS INACTIVE CODE • NOTES: 1. This is the initial unprogrammed state of all links. 2. Any gate Pn will be unconditionally inhibited if both the true and complement of an input (either I or B) are left intact. ABEL is a trademark of Data I/O Corp. CUPL is a trademark of Logical Devices, Inc. October 22, 1993 14 AND ACTIVE B(0) All AND gates are pulled to a logic “0” (Low). Output polarity is non–inverting. CONTROL A NOTES In the unprogrammed state: October 22, 1993 OR CUSTOMER NAME PURCHASE ORDER # PHILIPS DEVICE # CUSTOMER SYMBOLIZED PART # TOTAL NUMBER OF PARTS PROGRAM TABLE # 9 8 7 6 5 4 3 2 1 0 11 15 14 13 12 10 INACTIVE INACTIVE 0 I, B H CF(XXXX) PROGRAM TABLE I, B HIGH LOW L (POL) H L I, B(I) Unused I and B bits in the AND array should be programmed as Don’t Care (–). Unused product terms in the OR array should be programmed as INACTIVE (o). DON’T CARE — REV DATE T E R M 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 PIN VARIABLE NAME 7 Programmable logic arrays (18 × 42 × 10) Philips Semiconductors Programmable Logic Devices 8 7 6 6 5 5 4 I 3 4 3 2 2 1 1 0 AND 9 8 19 18 17 16 15 14 13 12 11 15 7 6 5 4 3 2 1 0 B(I) 9 9 8 7 6 5 4 3 2 OR B(0) POLARITY 19 18 17 16 15 14 13 12 11 1 PLUS153B/D Product specification 9 0 Philips Semiconductors Programmable Logic Devices Product specification Programmable logic arrays (18 × 42 × 10) PLUS153B/D SNAP RESOURCE SUMMARY DESIGNATIONS P31 DIN153 I0 NIN153 P0 D0 D9 I7 B0 DIN153 NIN153 B9 AND CAND TOUT153 S9 X9 OR B9 S0 X0 EXOR153 B0 October 22, 1993 16