PLUS16L8-7A

Philips Semiconductors Programmable Logic Devices Product specification PAL devices 16L8, 16R8, 16R6, 16R4 PLUS16R8D/-7 SERIES FEATURES • Ultra high-speed – tPD = 7.5ns and fMAX = 74MHz for the PLUS16R8-7 Series – tPD = 10ns and fMAX = 60 MHz for the PLUS16R8D Series DESCRIPTION The Philips Semiconductors PLUS16XX family consists of ultra high-speed 7.5ns and 10ns versions of Series 20 PAL devices. The PLUS16XX family is 100% functional and pin-compatible with the 16L8, 16R8, 16R6, and 16R4 Series devices. The sum of products (AND-OR) architecture is comprised of 64 programmable AND gates and 8 fixed OR gates. Multiple bidirectional pins provide variable input/output pin ratios. Individual 3-State control of all outputs and registers with feedback (R8, R6, R4) is also provided. Proprietary designs can be protected by programming the security fuse. The PLUS16R8, R6, and R4 have D-type flip-flops which are loaded on the Low-to-High transition of the clock input. In order to facilitate state machine design and testing, a power-up reset function has been incorporated into these devices to reset all internal registers to Active-Low after a specific period of time. The Philips Semiconductors State-of-the-Art oxide isolation Bipolar fabrication process is employed to achieve high-performance operation. The PLUS16XX family of devices are field programmable, enabling the user to quickly generate custom patterns using standard programming equipment. See the programmer chart for qualified programmers. The SNAP software package from Philips Semiconductors supports easy design entry for the PLUS16XX series as well as other PLD devices from Philips Semiconductors. The PLUS16XX series are also supported by other standard CAD tools for PAL-type devices. Order codes are listed in the Ordering Information table. • 100% functionally and pin-for-pin compatible with industry standard 20-pin PAL® ICs • Power-up reset function to enhance state machine design and testability • Design support provided via SNAP and other CAD tools for Series 20 PAL devices • Field-programmable on industry standard programmers • Security fuse • Individual 3-State control of all outputs DEVICE NUMBER PLUS16L8 PLUS16R8 PLUS16R6 PLUS16R4 DEDICATED INPUTS 10 8 8 8 COMBINATORIAL OUTPUTS 8 (6 I/O) 0 2 I/O 4 I/O REGISTERED OUTPUTS 0 8 6 4 ORDERING INFORMATION DESCRIPTION ORDER CODE PLUS16R8DN PLUS16R6DN PLUS16R4DN PLUS16L8DN PLUS16R8–7N PLUS16R6–7N PLUS16R4–7N PLUS16L8–7N PLUS16R8DA PLUS16R6DA PLUS16R4DA PLUS16L8DA PLUS16R8–7A PLUS16R6–7A PLUS16R4–7A PLUS16L8–7A DRAWING NUMBER 20-Pin Plastic Dual-In-Line 300mil-wide 0408B 20-Pin Plastic Leaded Chip Carrier (PLCC) 0400E NOTE: The PLUS16XX series of devices are also processed to military requirements for operation over the military temperature range. For specifications and ordering information, consult the Philips Semiconductors Military Data Book. ®PAL is a registered trademark of Advanced Micro Devices, Inc. September 10, 1993 36 853–1358 10777 Philips Semiconductors Programmable Logic Devices Product specification PAL devices 16L8, 16R8, 16R6, 16R4 PLUS16R8D/-7 SERIES PIN CONFIGURATIONS PLUS16L8 PLUS16R8 I0 1 20 VCC CLK 1 20 VCC I1 2 19 O7 I0 2 DQ Q DQ Q DQ Q AND OR ARRAY DQ Q DQ Q DQ Q DQ Q DQ Q 19 Q7 I2 3 18 B6 I1 3 18 Q6 I3 4 17 B5 I2 4 17 Q5 I4 5 AND OR ARRAY 16 B4 I3 5 16 Q4 I5 6 15 B3 I4 6 15 Q3 I6 7 14 B2 I5 7 14 Q2 I7 8 13 B1 I6 8 13 Q1 I8 9 12 O0 I7 9 12 Q0 GND 10 11 I9 GND 10 11 OE PLUS16L8 I2 3 I1 2 I0 VCC O7 1 20 19 I1 3 PLUS16R8 I0 2 CLK VCC Q7 1 20 19 I3 I4 I5 I6 I7 4 5 6 7 8 AND OR ARRAY OUTPUTS 18 B6 17 B5 16 B4 15 B3 14 B2 9 10 11 12 O0 13 B1 I2 I3 I4 I5 I6 4 5 6 7 8 AND OR ARRAY OUTPUTS 18 Q6 17 Q5 16 Q4 15 Q3 14 Q2 9 I7 10 11 12 Q0 13 Q1 I8 GND I9 GND OE SYMBOL I O Q B CLK OE VCC GND DESCRIPTION Dedicated Input Dedicated combinatorial Output Registered output Bidirectional (input/output) Clock input Output Enable Supply Voltage Ground SYMBOL I O Q B CLK OE VCC GND DESCRIPTION Dedicated Input Dedicated combinatorial Output Registered output Bidirectional (input/output) Clock input Output Enable Supply Voltage Ground September 10, 1993 37 Philips Semiconductors Programmable Logic Devices Product specification PAL devices 16L8, 16R8, 16R6, 16R4 PLUS16R8D/-7 SERIES PIN CONFIGURATIONS PLUS16R6 PLUS16R4 CLK 1 20 VCC CLK 1 20 VCC I0 2 19 B7 I0 2 19 B7 I1 3 DQ Q DQ Q AND OR ARRAY DQ Q DQ Q DQ Q DQ Q 18 Q6 I1 3 18 B6 I2 4 17 Q5 I2 4 DQ Q AND OR ARRAY DQ Q DQ Q DQ Q 17 Q5 I3 5 16 Q4 I3 5 16 Q4 I4 6 15 Q3 I4 6 15 Q3 I5 7 14 Q2 I5 7 14 Q2 I6 8 13 Q1 I6 8 13 B1 I7 9 12 B0 I7 9 12 B0 GND 10 11 OE GND 10 11 OE PLUS16R6 I1 3 I0 2 CLK VCC B7 1 20 19 I1 3 PLUS16R4 I0 2 CLK VCC B7 1 20 19 I2 I3 I4 I5 I6 4 5 6 7 8 AND OR ARRAY OUTPUTS 18 Q6 17 Q5 16 Q4 15 Q3 14 Q2 9 I7 10 11 12 B0 13 Q1 I2 I3 I4 I5 I6 4 5 6 7 8 AND OR ARRAY OUTPUTS 18 B6 17 Q5 16 Q4 15 Q3 14 Q2 9 I7 10 11 12 B0 13 B1 GND OE GND OE SYMBOL I O Q B CLK OE VCC GND DESCRIPTION Dedicated Input Dedicated combinatorial Output Registered output Bidirectional (input/output) Clock input Output Enable Supply Voltage Ground SYMBOL I O Q B CLK OE VCC GND DESCRIPTION Dedicated Input Dedicated combinatorial Output Registered output Bidirectional (input/output) Clock input Output Enable Supply Voltage Ground September 10, 1993 38 Philips Semiconductors Programmable Logic Devices Product specification PAL devices 16L8, 16R8, 16R6, 16R4 PLUS16R8D/-7 SERIES LOGIC DIAGRAM I0 1 0 PLUS16L8 19 7 I1 2 8 18 15 I2 3 16 17 23 I3 4 24 PRODUCT TERMS (0–63) 16 31 I4 5 32 15 39 I5 6 40 14 47 I6 7 48 13 55 I7 8 56 12 63 I8 9 0 INPUTS (0–31) 31 11 O7 B6 B5 B4 B3 B2 B1 O0 I9 NOTES: 1. All unprogrammed or virgin “AND” gate locations are pulled to logic “0”. 2. Programmable connections. September 10, 1993 39 Philips Semiconductors Programmable Logic Devices Product specification PAL devices 16L8, 16R8, 16R6, 16R4 PLUS16R8D/-7 SERIES LOGIC DIAGRAM CLK 1 0 DQ 7 I0 2 8 DQ 15 I1 3 16 DQ 23 I2 4 24 PRODUCT TERMS (0–63) DQ 31 I3 5 32 DQ 39 I4 6 40 DQ 47 I5 7 48 DQ 55 I6 8 56 DQ 63 I7 9 0 INPUTS (0–31) 31 Q Q Q Q Q Q Q Q PLUS16R8 19 Q7 18 Q6 17 Q5 16 Q4 15 Q3 14 Q2 13 Q1 12 Q0 11 OE NOTES: 1. All unprogrammed or virgin “AND” gate locations are pulled to logic “0”. 2. Programmable connections. September 10, 1993 40 Philips Semiconductors Programmable Logic Devices Product specification PAL devices 16L8, 16R8, 16R6, 16R4 PLUS16R8D/-7 SERIES LOGIC DIAGRAM CLK 1 0 PLUS16R6 19 7 I0 2 8 DQ 15 I1 3 16 DQ 23 I2 4 24 PRODUCT TERMS (0–63) DQ 31 I3 5 32 DQ 39 I4 6 40 DQ 47 I5 7 48 DQ 55 I6 8 56 12 63 I7 9 0 INPUTS (0–31) 31 11 Q 13 Q 14 Q 15 Q 16 Q 17 Q 18 B7 Q6 Q5 Q4 Q3 Q2 Q1 B0 OE NOTES: 1. All unprogrammed or virgin “AND” gate locations are pulled to logic “0”. 2. Programmable connections. September 10, 1993 41 Philips Semiconductors Programmable Logic Devices Product specification PAL devices 16L8, 16R8, 16R6, 16R4 PLUS16R8D/-7 SERIES LOGIC DIAGRAM CLK 1 0 PLUS16R4 19 7 I0 2 8 18 15 I1 3 16 DQ 23 I2 4 24 PRODUCT TERMS (0–63) DQ 31 I3 5 32 DQ 39 I4 6 40 DQ 47 I5 7 48 13 55 I6 8 56 12 63 I7 9 0 INPUTS (0–31) 31 11 Q 14 Q 15 Q 16 Q 17 B7 B6 Q5 Q4 Q3 Q2 B1 B0 OE NOTES: 1. All unprogrammed or virgin “AND” gate locations are pulled to logic “0”. 2. Programmable connections. September 10, 1993 42 Philips Semiconductors Programmable Logic Devices Product specification PAL devices 16L8, 16R8, 16R6, 16R4 PLUS16R8D/-7 SERIES FUNCTIONAL DESCRIPTIONS The PLUS16XX series utilizes the familiar sum-of-products implementation consisting of a programmable AND array and a fixed OR array. These devices are capable of replacing an equivalent of four or more SSI/MSI integrated circuits to reduce package count and board area occupancy, consequently improving reliability and design cycle over Standard Cell or gate array options. By programming the security fuse, proprietary designs can be protected from duplication. The PLUS16XX series consists of four PAL-type devices. Depending on the particular device type, there are a variable number of combinatorial and registered outputs available to the designer. The PLUS16L8 is a combinatorial part with 8 user configurable outputs (6 bidirectional), while the other three devices, PLUS16R8, PLUS16R6, PLUS16R4, have respectively 8, 6, and 4 output registers. use a product term to control the enable function. Programmable Bidirectional Pins The PLUS16XX products feature variable Input/Output ratios. In addition to 8 dedicated inputs, each combinatorial output pin of the registered devices can be individually programmed as an input or output. The PLUS16L8 provides 10 dedicated inputs and 6 Bidirectional I/O lines that can be individually configured as inputs or outputs. series are supported by SLICE, the PC-based software development tool from Philips Semiconductors. The PLUS16XX family of devices are also supported by standard CAD tools for PAL devices, including ABEL and CUPL. SLICE is available free of charge to qualified users. Logic Programming The PLUS16XX series is fully supported by industry standard (JEDEC compatible) PLD CAD tools, including Philips Semiconductors SNAP design software package. ABEL™ CUPL™ and PALASM® 90 design software packages also support the PLUS16XX architecture. All packages allow Boolean and state equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic capture format. Output Registers The PLUS16R8 has 8 output registers, the 16R6 has 6, and the 16R4 has 4. Each output register is a D-type flip-flop which is loaded on the Low-to-High transition of the clock input. These output registers are capable of feeding the outputs of the registers back into the array to facilitate design of synchronous state machines. Power-up Reset 3-State Outputs The PLUS16XX series devices also feature 3-State output buffers on each output pin which can be programmed for individual control of all outputs. The registered outputs (Qn) are controlled by an external input (/OE), and the combinatorial outputs (On, Bn) By resetting all flip-flops to a logic Low, as the power is turned on, the PLUS16R8, R6, R4 enhance state machine design and initialization capability. Programming/Software Support Ref to Section 9 (Development Software) and Section 10. (Third-Party Programmer/ Software Support) of the PLD data handbook for additional information. Software Support Like other Programmable Logic Devices from Philips Semiconductors, the PLUS16XX AND ARRAY – (I, B) I, B I, B I, B I, B I, B I, B I, B I, B I, B I, B I, B I, B P, D STATE INACTIVE1, 2 CODE O STATE I, B P, D CODE H STATE I, B P, D CODE L STATE DON’T CARE P, D CODE – VIRGIN STATE A factory shipped virgin device contains all fusible links intact, such that: 1. All outputs are at “H” polarity. 2. All Pn terms are disabled. 3. All Pn terms are active on all outputs. ABEL is a trademark of Data I/O Corp. CUPL is a trademark of Logical Devices, Inc. PALASM is a registered trademark of AMD Corp. September 10, 1993 43 Philips Semiconductors Programmable Logic Devices Product specification PAL devices 16L8, 16R8, 16R6, 16R4 PLUS16R8D/-7 SERIES ABSOLUTE MAXIMUM RATINGS1 RATINGS SYMBOL VCC VIN VOUT IIN IOUT Tstg PARAMETER Supply voltage Input voltage Output voltage Input currents Output currents Storage temperature range –65 MIN –0.5 –1.2 –0.5 –30 MAX +7 +8.0 VCC + 0.5V +30 +100 +150 UNIT VDC VDC VDC mA mA THERMAL RATINGS TEMPERATURE Maximum junction Maximum ambient Allowable thermal rise ambient to junction 150°C 75°C 75°C °C NOTE: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied. OPERATING RANGES RATINGS SYMBOL VCC Tamb PARAMETER Supply voltage Operating free–air temperature MIN +4.75 0 MAX +5.25 +75 UNIT VDC °C September 10, 1993 44 Philips Semiconductors Programmable Logic Devices Product specification PAL devices 16L8, 16R8, 16R6, 16R4 PLUS16R8D/-7 SERIES DC ELECTRICAL CHARACTERISTICS 0°C ≤ Tamb ≤ +75°C, 4.75 ≤ VCC ≤ 5.25V LIMITS SYMBOL Input VIL VIH VIC voltage2 Low High Clamp VCC = MIN VCC = MAX VCC = MIN, IIN = –18mA 2.0 –0.8 –1.5 0.8 V V V PARAMETER TEST CONDITIONS MIN TYP1 MAX UNIT Output voltage VCC = MIN, VIN = VIH or VIL VOL VOH Input current VCC = MAX IIL IIH II Low3 High3 Maximum input current VIN = 0.40V VIN = 2.7V VIN = VCC = VCCMAX –250 25 100 µA µA µA Low High IOL = 24mA IOH = –3.2 mA 2.4 0.5 V V Output current VCC = MAX IOZH IOZL IOS ICC Capacitance6 CIN Input VCC = 5V VOUT = 2.0V CB I/O (B) VOUT = 2V, f = 1MHz NOTES: 1. All typical values are at VCC = 5V, Tamb = +25°C. 2. All voltage values are with respect to network ground terminal. 3. Leakage current for bidirectional pins is the worst case of IIL and IOZL or IIH and IOZH. 4. Test one at a time. 5. Duration of short circuit should not exceed 1 second. 6. These parameters are not 100% tested but periodically sampled. 8 8 pF pF Output leakage Output leakage Short circuit 4, 5 VOUT = 2.7V VOUT = 0.4V VOUT = 0V VCC = MAX –30 160 100 –100 –90 180 µA µA mA mA VCC supply current September 10, 1993 45 Philips Semiconductors Programmable Logic Devices Product specification PAL devices 16L8, 16R8, 16R6, 16R4 PLUS16R8D/-7 SERIES AC ELECTRICAL CHARACTERISTICS R1 = 200Ω, R2 = 390Ω, 0°C ≤ Tamb ≤ +75°C, 4.75 ≤ VCC ≤ 5.25V LIMITS SYMBOL PARAMETER FROM TO MIN1 Pulse Width tCKH tCKL tCKP Clock High Clock Low Period CK+ CK– CK+ CK– CK+ CK+ 5 5 10 7 7 14 ns ns ns –7 TYP MAX MIN1 D MAX UNIT Setup & Hold time tIS tIH Input Input Input or feedback CK+ CK+ Input or feedback 7 0 9 0 ns ns Propagation delay tCKO tCKF tPD tOE1 tOE2 tOD1 tOD2 tSKW tPPR Clock Clock3 Output (16L8, R6, R4)2 Output Output Output Output Output Power-Up Reset enable4 enable4,5 disable4 disable4,5 CK± CK± I, B OE I OE I Q VCC+ Q± Q Output Output enable Output enable Output disable Output disable Q Q+ 3 3 3 3 3 3 6.5 3 7.5 8 10 8 10 1 10 3 3 3 3 3 3 7.5 6.5 10 10 10 10 10 1 10 ns ns ns ns ns ns ns ns ns Frequency (16R8, R6, R4) No feedback 1/ (tCKL + tCKH)6 fMAX Internal feedback 1/ (tIS + tCKF)6 External feedback 1/ (tIS + tCKO)6 100 90 74 71.4 64.5 60.6 MHz MHz MHz * For definitions of the terms, please refer to the Timing/Frequency Definitions tables. NOTES: 1. CL = 0pF while measuring minimum output delays. 2. tPD test conditions: CL = 50pF (with jig and scope capacitance), VIH = 3V, VIL = 0V, VOH = VOL = 1.5V. 3. tCKF was calculated from measured Internal fMAX. 4. For 3-State output; output enable times are tested with CL = 50pF to the 1.5V level, and S1 is open for high-impedance to High tests and closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output voltage of VT = (VOH – 0.5V) with S1 open, and Low-to-High impedance tests are made to the VT = (VOL + 0.5V) level with S1 closed. 5. Same function as tOE1 and tOD1, with the difference of using product term control. 6. Not 100% tested, but calculated at initial characterization and at any time a modification in design takes place which may affect the frequency. September 10, 1993 46 Philips Semiconductors Programmable Logic Devices Product specification PAL devices 16L8, 16R8, 16R6, 16R4 PLUS16R8D/-7 SERIES TEST LOAD CIRCUIT VCC +5V S1 C1 C2 I0 B0/O0 R1 Bn/On DUT INPUTS In CLK Qn OE GND Q0 R2 CL NOTE: C1 and C2 are to bypass VCC to GND. OUTPUT REGISTER SKEW 3V CLK 0V 3V Qn (REGISTERED OUTPUT) 1.5V 0V tSKW Qn + 1 (REGISTERED OUTPUT) 3V 1.5V 0V CLOCK TO FEEDBACK PATH CLK tIS D Q tCKF September 10, 1993 47 Philips Semiconductors Programmable Logic Devices Product specification PAL devices 16L8, 16R8, 16R6, 16R4 PLUS16R8D/-7 SERIES TIMING DIAGRAMS1, 2 +3V I, B (INPUTS) 1.5V 1.5V 0V tIH CLK 1.5V tIS +3V 1.5V 1.5V TIMING DEFINITIONS SYMBOL tCKH tCKL tCKP tIS PARAMETER Width of input clock pulse. Interval between clock pulses. Clock period. Required delay between beginning of valid input and positive transition of clock. Required delay between positive transition of clock and end of valid input data. Delay between positive transition of clock and when internal Q output of flip-flop becomes valid. Delay between positive transition of clock and when outputs become valid (with OE Low). Delay between beginning of Output Enable Low and when outputs become valid. Delay between beginning of Output Enable High and when outputs are in the Off-State. Delay between predefined Output Enable High, and when combinational outputs become valid. Delay between predefined Output Enable Low and when combinational outputs are in the Off-State. Delay between VCC (after power-on) and when flip-flop outputs become preset at “1” (internal Q outputs at “0”). Propagation delay between combinational inputs and outputs. tIS tCKH tCKL tCKP Q (REGISTERED OUTPUTS) 1.5V VT tCKO tOD1 OE 1.5V 1.5V tOE1 Flip-Flop Outputs +3V 1.5V O, B (COMBINATORIAL OUTPUTS) I, B (OUTPUT ENABLE) 4.5V Q (REGISTERED OUTPUTS) I, B (INPUTS) CLK tIS NOTES: 1. Input pulse amplitude is 0V to 3V. 2. Input rise and fall times are 2.5ns. September 10, 1993 ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ VCC tPPR ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ I, B (INPUTS) tPD 1.5V tOE2 tOD2 +3V +1.5V 0V +1.5V Gate Outputs 1.5V 1.5V VOL tCKO +3V 1.5V 0V tIH 1.5V tCKH tIS+tCKF 1.5V tCKL tIS +3V 1.5V 0V 1.5V Power–Up Reset ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ VT ÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇ 0V VOH VOL +3V tIH 0V tCKF tCKO 0V tOE1 VOH tOD1 VOL tOE2 tOD2 VCC tPPR 0V tPD VOH FREQUENCY DEFINITIONS fMAX No feedback: Determined by the minimum clock period, 1/(tCKL + tCKH). Internal feedback: Determined by the internal delay from flip-flop outputs through the internal feedback and array to the flip-flop inputs, 1/(tIS + tCKF). External feedback: Determined by clock-to-output delay and input setup time, 1/(tIS + tCKO). 48 Philips Semiconductors Programmable Logic Devices Product specification PAL devices 16L8, 16R8, 16R6, 16R4 PLUS16R8D/-7 SERIES OUTPUT REGISTER PRELOAD The output registers can be preloaded to any desired state during device testing. This permits any state to be tested without having to step through the entire state-machine sequence. Each register is preloaded individually by following the steps given below. Step 1. Step 2. Step 3. Step 4. With VCC at 5V and Pin 1 at VIL, raise Pin 11 to VIHH. Apply either VIL or VIH to the output corresponding to the register to be preloaded. Pulse Pin 1, clocking in preload data. Remove output voltage, then lower Pin 11 to VIL. Preload can be verified by observing the voltage level at the output pin. VIHH PIN 11 OE tsu td td VIL VIH tw PIN 1 CLOCK VIH REGISTERED I/O INPUT VIL NOTE: td = tsu = tw = 100ns to 1000ns. VIHH = 10.25V to 10.75V. Pin number references for DIP package. September 10, 1993 49 ÇÇ ÇÇ ÉÉ ÇÇ ÉÉ ÇÇ ÉÉ ÉÉ td VIL VOH OUTPUT VOL Philips Semiconductors Programmable Logic Devices Product specification PAL devices 16L8, 16R8, 16R6, 16R4 PLUS16R8D/-7 SERIES PROGRAMMING/SOFTWARE Refer to Section 9 (Development Software) and Section 10 (Third-Party Programmer/Software Support) of this data handbook for additional information. SNAP RESOURCE SUMMARY DESIGNATIONS I0 – I9 10 DINPAL7 NINPAL7 PROGRAMMABLE AND ARRAY AND 1 8 1 8 DINPAL7 NINPAL7 OR OR NOUTPAL7 NOUTPAL7 O0, O7 B1 – B6 PLUS16L8 CLK 8 CKPAL7 DINPAL7 I0 – I7 OE NOEPAL7 NINPAL7 PROGRAMMABLE AND ARRAY AND NINPAL7 DINPAL7 8 OR 8 OR D Q Q DFFPAL7 Q D Q DFFPAL7 NOUTPAL7 NOUTPAL7 Q0 Q7 PLUS16R8 September 10, 1993 50 Philips Semiconductors Programmable Logic Devices Product specification PAL devices 16L8, 16R8, 16R6, 16R4 PLUS16R8D/-7 SERIES SNAP RESOURCE SUMMARY DESIGNATIONS (Continued) I0 – I7 8 CKPAL7 DINPAL7 NINPAL7 NOEPAL7 CLK OE PROGRAMMABLE AND ARRAY AND 1 8 OR NINPAL7 DINPAL7 8 OR D Q Q DFFPAL7 NOUTPAL7 NOUTPAL7 B0, B7 Q1 – Q6 PLUS16R6 I0 – I7 8 CLK OE CKPAL7 DINPAL7 NINPAL7 NOEPAL7 PROGRAMMABLE AND ARRAY AND 1 8 OR NINPAL7 DINPAL7 8 OR D Q Q DFFPAL7 NOUTPAL7 NOUTPAL7 B0, B1, B6, B7 Q2 – Q5 PLUS16R4 September 10, 1993 51