PLUS173-10A

Philips Semiconductors Programmable Logic Devices Product specification Programmable logic array (22 × 42 × 10) PLUS173–10 DESCRIPTION The PLUS173–10 PLD is a high speed, combinatorial Programmable Logic Array. The Philips Semiconductors state-of-the-art Oxide Isolated Bipolar fabrication process is employed to produce maximum propagation delays of 10ns or less. The 24-pin PLUS173–10 device has a programmable AND array and a programmable OR array. Unlike PAL® devices, 100% product term sharing is supported. Any of the 32 logic product terms can be connected to any or all of the 10 output OR gates. Most PAL ICs are limited to 7 AND terms per OR function; the PLUS173–10 device can support up to 32 input wide OR functions. The polarity of each output is userprogrammable as either Active-High or Active-Low, thus allowing AND-OR or AND-NOR logic implementation. This feature adds an element of design flexibility, particularly when implementing complex decoding functions. The PLUS173–10 device is userprogrammable using one of several commercially available, industry standard PLD programmers. FEATURES • I/O propagation delays – 10ns (worst case) PIN CONFIGURATIONS N Package I0 1 I1 2 I2 3 I3 4 I4 5 I5 6 I6 7 I7 8 I8 9 I9 10 I10 11 GND 12 24 VCC 23 B9 22 B8 21 B7 20 B6 19 B5 18 B4 17 B3 16 B2 15 B1 14 B0 13 I11 • Functional superset of 20L10 and most other 24-pin combinatorial PAL devices • Two programmable arrays – Supports 32 input wide OR functions • 12 inputs • 10 bi-directional I/O • 42 AND gates – 32 logic product terms – 10 direction control terms • Programmable output polarity – Active-High or Active-Low • Security fuse • 3-State outputs • Power dissipation: 850mW (typ.) • TTL Compatible APPLICATIONS N = Plastic Dual In-Line (300mil-wide) A Package I3 4 NC 5 I4 6 I5 7 I6 8 I7 9 I8 10 NC 11 12 I9 13 14 15 16 17 18 I2 3 I1 2 I0 VCC B9 B8 1 28 27 26 25 NC 24 B7 23 B6 22 B5 21 B4 20 B3 19 NC • Random logic • Code converters • Fault detectors • Function generators • Address mapping • Multiplexing I10 GND I11 B0 B1 B2 A = Plastic Leaded Chip Carrier ORDERING INFORMATION DESCRIPTION 24-Pin Plastic Dual In-Line 300mil-wide 28-Pin Plastic Leaded Chip Carrier tPD (MAX) 10ns 10ns ORDER CODE PLUS173–10N PLUS173–10A DRAWING NUMBER 0410D 0401F ®PAL is a registered trademark of Advanced Micro Devices Corporation. October 22, 1993 41 853–1422 11164 Philips Semiconductors Programmable Logic Devices Product specification Programmable logic array (22 × 42 × 10) PLUS173–10 LOGIC DIAGRAM (LOGIC TERMS–P) I0 I1 I2 I3 I4 I5 I6 I7 I8 1 2 3 4 5 6 7 8 9 (CONTROL TERMS) I9 10 I10 11 I11 13 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 S9 X9 X8 X7 X6 X5 X4 X3 X2 X1 31 24 23 16 15 87 0 X0 S8 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 23 B9 22 B8 S7 21 B7 S6 20 B6 S5 19 B5 S4 18 B4 S3 17 B3 S2 16 B2 S1 15 B1 S0 14 B0 NOTES: 1. All programmed ‘AND’ gate locations are pulled to logic “1”. 2. All programmed ‘OR’ gate locations are pulled to logic “0”. 3. Programmable connection. October 22, 1993 42 Philips Semiconductors Programmable Logic Devices Product specification Programmable logic array (22 × 42 × 10) PLUS173–10 FUNCTIONAL DIAGRAM P31 I0 P0 D0 D9 I11 B0 B9 S9 X9 B9 S0 B0 X0 ABSOLUTE MAXIMUM RATINGS1 RATING SYMBOL VCC VIN VOUT IIN IOUT Tamb Tstg PARAMETER Supply voltage Input voltage Output voltage Input currents Output currents Operating free-air temperature range Storage temperature range 0 –65 –30 Min Max +7 +5.5 +5.5 +30 +100.0 +75 +150 UNIT VDC VDC VDC mA mA °C °C THERMAL RATINGS TEMPERATURE Maximum junction Maximum ambient Allowable thermal rise ambient to junction 150°C 75°C 75°C NOTES: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied. October 22, 1993 43 Philips Semiconductors Programmable Logic Devices Product specification Programmable logic array (22 × 42 × 10) PLUS173–10 DC ELECTRICAL CHARACTERISTICS 0°C ≤ Tamb ≤ +75°C, 4.75 ≤ VCC ≤ 5.25V LIMITS SYMBOL Input VIL VIH VIC Output voltage2 Low High Clamp voltage2 VCC = MIN VOL VOH Low4 High5 IOL = 15mA IOH = –2mA 2.4 0.4 2.9 0.5 V V VCC = MIN VCC = MAX VCC = MIN, IIN = –12mA 2.0 –0.8 –1.2 0.8 V V V PARAMETER TEST CONDITIONS MIN TYP1 MAX UNIT Input current9 VCC = MAX IIL IIH Low High VIN = 0.45V VIN = VCC –20 1 –100 40 µA µA Output current VCC = MAX IO(OFF) Hi-Z state8 VOUT = 2.7V VOUT = 0.45V IOS ICC Capacitance VCC = 5V IIN CB Input I/O VIN = 2.0V VB = 2.0V 8 15 pF pF Short circuit3, 5, 6 VCC supply current7 VOUT = 0V VCC = MAX –15 0 –15 –30 170 80 –140 –70 210 mA mA µA NOTES: 1. All typical values are at VCC = 5V, Tamb = +25°C. 2. All voltage values are with respect to network ground terminal. 3. Test one at a time. 4. Measured with inputs I0 – I4 = 0V, inputs I5 – I9 = 4.5V, I11 = 4.5V and I10 = 10V. For outputs B0 – B4 and for outputs B5 – B9 apply the same conditions except I11 = 0V. 5. Same conditions as Note 4 except input I11 = +10V. 6. Duration of short circuit should not exceed 1 second. 7. ICC is measured with inputs I0 – I11 and B0 – B9 = 0V. Part in Virgin State. 8. Leakage values are a combination of input and output leakage. 9. IIL and IIH limits are for dedicated inputs only (I0 – I11). October 22, 1993 44 Philips Semiconductors Programmable Logic Devices Product specification Programmable logic array (22 × 42 × 10) PLUS173–10 AC ELECTRICAL CHARACTERISTICS 0°C ≤ Tamb ≤ +75°C, 4.75 ≤ VCC ≤ 5.25V, R1 = 300Ω, R2 = 390Ω TEST SYMBOL tPD tOE tOD PARAMETER Propagation Delay2 FROM Input +/– Input +/– Input +/– TO Output +/– Output – Output + CONDITION CL = 30pF CL = 30pF CL = 5pF MIN LIMITS TYP 8 8 8 MAX 10 10 10 UNIT ns ns ns Output Enable1 Output Disable1 NOTES: 1. For 3-State outputs; output enable times are tested with CL = 30pF to the 1.5V level, and S1 is open for high-impedance to High tests and closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output voltage of VT = (VOH – 0.5V) with S1 open, and Low-to-High impedance tests are made to the VT = (VOL + 0.5V) level with S1 closed. 2. All propagation delays are measured and specified under worst case conditions. VOLTAGE WAVEFORM +3.0V 90% TEST LOAD CIRCUIT VCC +5V S1 10% 0V 5ns +3.0V 90% tR tF 5ns C1 C2 In BZ R1 INPUTS In BM DUT R2 CL 10% 0V 5ns 5ns BM GND BZ OUTPUTS MEASUREMENTS: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified. NOTE: C1 and C2 are to bypass VCC to GND. Input Pulses Test Load Circuit TIMING DEFINITIONS SYMBOL tPD tOD PARAMETER Propagation delay between input and output. Delay between input change and when output is off (Hi-Z or High). Delay between input change and when output reflects specified output level. TIMING DIAGRAM +3V I, B 1.5V 1.5V 1.5V 0V VOH B 1.5V VT tOD tOE 1.5V VOL tPD tOE October 22, 1993 45 Philips Semiconductors Programmable Logic Devices Product specification Programmable logic array (22 × 42 × 10) PLUS173–10 LOGIC PROGRAMMING The PLUS173–10 is fully supported by industry standard (JEDEC compatible) PLD CAD tools, including Philips Semiconductors SNAP design software package. ABEL™ and CUPL™ design software packages also support the PLUS173–10 architecture. All packages allow Boolean and state equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic capture format. PLUS173–10 logic designs can also be generated using the program table entry format, which is detailed on the following page. This program table entry format is supported by SNAP only. To implement the desired logic functions, the state of each logic variable from logic equations (I, B, O, P, etc.) is assigned a symbol. The symbols for TRUE, COMPLEMENT, INACTIVE, PRESET, etc., are defined below. PROGRAMMING AND SOFTWARE SUPPORT Refer to Section 9 (Development Software) and Section 10 (Third-party Programmer/ Software Support) of this data handbook for additional information. OUTPUT POLARITY – (B) S B X X S B ACTIVE LEVEL HIGH1 (NON-INVERTING) CODE H ACTIVE LEVEL LOW CODE L (INVERTING) AND ARRAY – (I, B) I, B I, B I, B I, B I, B I, B I, B I, B I, B I, B I, B I, B P, D STATE INACTIVE1, 2 CODE O STATE I, B P, D CODE H STATE I, B P, D CODE L STATE DON’T CARE P, D CODE – OR ARRAY – (B) P S P S VIRGIN STATE A factory shipped virgin device contains all fusible links intact, such that: 1. All outputs are at “H” polarity. 2. All Pn terms are disabled. 3. All Pn terms are active on all outputs. Pn STATUS ACTIVE1 CODE A Pn STATUS INACTIVE CODE • NOTES: 1. This is the initial unprogrammed state of all link pairs. It is normally associated with all unused (inactive) AND gates Pn, Dn. 2. Any gate Pn, Dn will be unconditionally inhibited if both the true and complement of any input (I, B) are left intact. ABEL is a trademark of Data I/O Corp. CUPL is a trademark of Logical Devices, Inc. October 22, 1993 46 AND ACTIVE B(0) INACTIVE CONTROL HIGH LOW L (POL) H 2. Unused I and B bits in the AND array must be programmed Don’t Care (—). 3. Unused product terms can be left blank. A OR CUSTOMER NAME INACTIVE 0 October 22, 1993 NOTES 1. The PLA is shipped with all links intact. Thus a background of entries corresponding to states of virgin links exists in the table. (Shown BLANK for clarity.) I, B H I, B L I, B(I) PHILIPS DEVICE # DON’T CARE — PLA PROGRAM TABLE PROGRAM TABLE # T E R M 9 8 7 6 5 4 3 2 1 0 11 15 14 13 12 10 REV DATE 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 PIN VARIABLE NAME 11 10 9 Programmable logic array (22 × 42 × 10) Philips Semiconductors Programmable Logic Devices 13 11 10 8 9 7 8 7 6 I 6 5 5 4 3 4 3 2 2 1 AND 1 0 47 9 8 7 6 B(I) 5 4 3 2 1 0 23 22 21 20 19 18 17 16 15 14 9 8 7 6 5 4 3 2 1 0 OR B(0) POLARITY 23 22 21 20 19 18 17 16 15 14 PLUS173–10 Product specification Philips Semiconductors Programmable Logic Devices Product specification Programmable logic array (22 × 42 × 10) PLUS173–10 SNAP RESOURCE SUMMARY DESIGNATIONS P31 DIN173 I0 NIN173 P0 D0 D9 I11 B0 DIN173 NIN173 B9 AND CAND TOUT173 S9 X9 OR B9 S0 B0 X0 EXOR173 October 22, 1993 48