PMWD19UN

PMWD19UN Dual µTrenchMOS™ ultra low level FET Rev. 01 — 20 December 2002 M3D647 Product data 1. Product profile 1.1 Description Dual N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOS™ technology. Product availability: PMWD19UN in SOT530-1 (TSSOP8). 1.2 Features s Surface mounting package s Very low threshold s Low profile s Fast switching. 1.3 Applications s Portable appliances s Battery management s PCMCIA cards s Load switching. 1.4 Quick reference data s VDS ≤ 30 V s Ptot ≤ 2.3 W s ID ≤ 5.6 A s RDSon ≤ 23 mΩ. 2. Pinning information Table 1: Pin 1 2,3 4 5 6,7 8 Pinning - SOT530-1, simplified outline and symbol Description drain1 (d1) source1 (s1) gate1 (g1) gate2 (g2) source2 (s2) drain2 (d2) 1 Top view 4 MBK885 Simplified outline 8 5 Symbol d1 d2 s1 g1 s2 g2 MSD901 SOT530-1 Philips Semiconductors PMWD19UN Dual µTrenchMOS™ ultra low level FET 3. Limiting values Table 2: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDS VDGR VGS ID IDM Ptot Tstg Tj IS ISM drain-source voltage (DC) drain-gate voltage gate-source voltage drain current (DC) peak drain current total power dissipation storage temperature junction temperature source (diode forward) current (DC) Tsp = 25 °C peak source (diode forward) current Tsp = 25 °C; pulsed; tp ≤ 10 µs Tsp = 25 °C; VGS = 4.5 V; Figure 2 and 3 Tsp = 100 °C; VGS = 4.5 V; Figure 2 Tsp = 25 °C; pulsed; tp ≤ 10 µs; Figure 3 Tsp = 25 °C; Figure 1 Conditions 25 °C ≤ Tj ≤ 150 °C 25 °C ≤ Tj ≤ 150 °C; RGS = 20 kΩ Min −55 −55 Max 30 30 ±10 5.6 3.4 20 2.3 +150 +150 2 7 Unit V V V A A A W °C °C A A Source-drain diode 9397 750 10833 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 — 20 December 2002 2 of 12 Philips Semiconductors PMWD19UN Dual µTrenchMOS™ ultra low level FET 120 Pder (%) 80 03aa17 120 Ider (%) 80 03aa25 40 40 0 0 50 100 150 Tsp (°C) 200 0 0 50 100 150 200 Tsp (°C) P tot P der = ---------------------- × 100 % P ° tot ( 25 C ) VGS ≥ 4.5 V ID I der = ------------------- × 100 % I ° D ( 25 C ) Fig 1. Normalized total power dissipation as a function of solder point temperature. Fig 2. Normalized continuous drain current as a function of solder point temperature. 102 ID (A) 10 1 ms 10 ms 1 100 ms DC 10-1 1s 003aaa358 Limit RDSon = VDS/ID tp = 10 µs 10-2 10-1 1 10 VDS (V) 102 Tsp = 25 °C; IDM is single pulse Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage. 9397 750 10833 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 — 20 December 2002 3 of 12 Philips Semiconductors PMWD19UN Dual µTrenchMOS™ ultra low level FET 4. Thermal characteristics Table 3: Rth(j-sp) Rth(j-a) Thermal characteristics Conditions Figure 4 minimum footprint; mounted on printed-circuit board Min Typ Max 55 70 100 Unit K/W K/W thermal resistance from junction to solder point thermal resistance from junction to ambient Symbol Parameter 4.1 Transient thermal impedance 102 Zth(j-sp) (K/W) 003aaa275 δ = 0.5 0.2 10 0.1 0.05 0.02 1 single pulse P δ= tp T tp T 10-1 10-4 10-3 10-2 10-1 1 10 tp (s) t 102 Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration. 9397 750 10833 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 — 20 December 2002 4 of 12 Philips Semiconductors PMWD19UN Dual µTrenchMOS™ ultra low level FET 5. Characteristics Table 4: Characteristics Tj = 25 °C unless otherwise specified Symbol Parameter Static characteristics V(BR)DSS drain-source breakdown voltage ID = 250 µA; VGS = 0 V Tj = 25 °C Tj = −55 °C VGS(th) IDSS gate-source threshold voltage drain-source leakage current ID = 1 mA; VDS = VGS; Figure 9 VDS = 30 V; VGS = 0 V Tj = 25 °C Tj = 150 °C IGSS RDSon gate-source leakage current drain-source on-state resistance VGS = ±10 V; VDS = 0 V VGS = 4.5 V; ID = 3.5 A; Figure 7 and 8 Tj = 25 °C Tj = 150 °C VGS = 1.8 V; ID = 3.5 A; Figure 7 VGS = 2.5 V; ID = 3.5 A; Figure 7 Dynamic characteristics Qg(tot) Qgs Qgd Ciss Coss Crss td(on) tr td(off) tf VSD trr Qr total gate charge gate-source charge gate-drain (Miller) charge input capacitance output capacitance reverse transfer capacitance turn-on delay time rise time turn-off delay time fall time source-drain (diode forward) voltage IS = 4 A; VGS = 0 V; Figure 12 reverse recovery time recovered charge IS = 4 A; dIS/dt = −100 A/µs; VR = 30 V; VGS = 0 V VDD = 15 V; ID = 1 A; VGS = 4.5 V; RG = 6 Ω VGS = 0 V; VDS = 10 V; f = 1 MHz; Figure 11 ID = 5 A; VDD = 16 V; VGS = 5 V; Figure 13 28 2.3 6.1 161 128 15 23 56 30 0.67 50 19 1.2 nC nC nC pF pF pF ns ns ns ns V ns nC 19 32 25 21 1 100 100 23 39 35 26 µA µA nA mΩ mΩ mΩ mΩ mΩ 30 27 0.45 0.7 V V V Conditions Min Typ Max Unit 1478 - Source-drain diode 9397 750 10833 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 — 20 December 2002 5 of 12 Philips Semiconductors PMWD19UN Dual µTrenchMOS™ ultra low level FET 4 ID (A) 3 4.5 V VGS = 1.3 V 003aaa276 8 ID (A) 6 003aaa277 1.2 V 2 4 Tj = 150 °C 25 °C 1 1.1 V 2 1.0 V 0 0 0.5 1 1.5 VDS (V) 2 0 0.0 0.5 1.0 1.5 VGS (V) 2.0 Tj = 25 °C Tj = 25 °C and 150 °C; VDS > ID × RDSon Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values. Fig 6. Transfer characteristics: drain current as a function of gate-source voltage; typical values. 100 RDSon (mΩ) 1.2 V 75 003aaa278 2 a 1.5 03aa27 50 1.3 V 1 25 4.5 V 0 0 1 2 VGS = 1.8 V 2.5 V 0.5 0 3 ID (A) 4 -60 0 60 120 Tj (°C) 180 Tj = 25 °C R DSon a = ----------------------------R DSon ( 25 ° C ) Fig 8. Normalized drain source on-state resistance factor as a function of junction temperature. Fig 7. Drain-source on-state resistance as a function of drain current; typical values. 9397 750 10833 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 — 20 December 2002 6 of 12 Philips Semiconductors PMWD19UN Dual µTrenchMOS™ ultra low level FET 1 VGS(th) (V) 0.8 typ 03aj65 10-3 ID (A) 10-4 03aj64 0.6 min min 0.4 10-5 0.2 typ 0 -60 0 60 120 Tj (°C) 180 10-6 0 0.2 0.4 0.6 0.8 1 VGS (V) ID = 1 mA; VDS = VGS Tj = 25 °C; VDS = 5 V Fig 9. Gate-source threshold voltage as a function of junction temperature. Fig 10. Sub-threshold drain current as a function of gate-source voltage. 104 C (pF) 003aaa279 4 IS (A) 3 003aaa280 103 Ciss 150 °C 2 Coss Crss 102 Tj = 25 °C 1 10 10-1 1 10 2 VDS (V) 10 0 0 0.2 0.4 0.6 0.8 1 VSD (V) VGS = 0 V; f = 1 MHz Tj = 25 °C and 150 °C; VGS = 0 V Fig 11. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values. Fig 12. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values. 9397 750 10833 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 — 20 December 2002 7 of 12 Philips Semiconductors PMWD19UN Dual µTrenchMOS™ ultra low level FET 5 VGS (V) 4 003aaa281 3 2 1 0 0 10 20 QG (nC) 30 ID = 5 A; VDD = 16 V Fig 13. Gate-source voltage as a function of gate charge; typical values. 9397 750 10833 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 — 20 December 2002 8 of 12 Philips Semiconductors PMWD19UN Dual µTrenchMOS™ ultra low level FET 6. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 4.4 mm SOT530-1 E D A X c y HE Z vMA 8 5 A2 A1 pin 1 index Lp L detail X (A3) A θ 1 e bp 4 wM 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.10 A1 0.15 0.05 A2 0.95 0.85 A3 0.25 bp 0.30 0.19 c 0.20 0.13 D(1) 3.10 2.90 E(2) 4.50 4.30 e 0.65 HE 6.50 6.30 L 0.94 Lp 0.70 0.50 v 0.10 w 0.10 y 0.10 Z(1) 0.70 0.35 θ 8° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT530-1 REFERENCES IEC JEDEC MO-153 EIAJ EUROPEAN PROJECTION ISSUE DATE 99-12-27 00-02-24 Fig 14. SOT530-1 (TSSOP8). 9397 750 10833 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 — 20 December 2002 9 of 12 Philips Semiconductors PMWD19UN Dual µTrenchMOS™ ultra low level FET 7. Revision history Table 5: Rev Date 01 20021220 Revision history CPCN Description Product data (9397 750 10833) 9397 750 10833 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 — 20 December 2002 10 of 12 Philips Semiconductors PMWD19UN Dual µTrenchMOS™ ultra low level FET 8. Data sheet status Level I II Data sheet status[1] Objective data Preliminary data Product status[2][3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). III Product data Production [1] [2] [3] Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 9. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 11. Trademarks TrenchMOS — is a trademark of Koninklijke Philips Electronics N.V 10. Disclaimers Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors Contact information For additional information, please visit http://www.semiconductors.philips.com. For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com. 9397 9397 750 10833 Fax: +31 40 27 24825 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 — 20 December 2002 11 of 12 Philips Semiconductors PMWD19UN Dual µTrenchMOS™ ultra low level FET Contents 1 1.1 1.2 1.3 1.4 2 3 4 4.1 5 6 7 8 9 10 11 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data. . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 1 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4 Transient thermal impedance . . . . . . . . . . . . . . 4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 10 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 © Koninklijke Philips Electronics N.V. 2002. Printed in The Netherlands All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 20 December 2002 Document order number: 9397 750 10833