SJA1000

INTEGRATED CIRCUITS DATA SHEET SJA1000 Stand-alone CAN controller Product specification Supersedes data of 1999 Aug 17 File under Integrated Circuits, IC18 2000 Jan 04 Philips Semiconductors Product specification Stand-alone CAN controller CONTENTS 1 2 3 4 5 6 6.1 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.1.6 6.1.7 6.2 6.2.1 6.2.2 6.3 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.3.6 6.3.7 6.3.8 6.3.9 6.4 6.4.1 6.4.2 6.4.3 6.4.4 6.4.5 6.4.6 6.4.7 6.4.8 6.4.9 6.4.10 6.4.11 6.4.12 6.4.13 6.4.14 6.4.15 6.4.16 6.4.17 6.5 6.5.1 6.5.2 FEATURES GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Description of the CAN controller blocks Interface Management Logic (IML) Transmit Buffer (TXB) Receive Buffer (RXB, RXFIFO) Acceptance Filter (ACF) Bit Stream Processor (BSP) Bit Timing Logic (BTL) Error Management Logic (EML) Detailed description of the CAN controller PCA82C200 compatibility Differences between BasicCAN and PeliCAN mode BasicCAN mode BasicCAN address layout Reset values Control Register (CR) Command Register (CMR) Status Register (SR) Interrupt Register (IR) Transmit buffer layout Receive buffer Acceptance filter PeliCAN mode PeliCAN address layout Reset values Mode Register (MOD) Command Register (CMR) Status Register (SR) Interrupt Register (IR) Interrupt Enable Register (IER) Arbitration Lost Capture register (ALC) Error Code Capture register (ECC) Error Warning Limit Register (EWLR) RX Error Counter Register (RXERR) TX Error Counter Register (TXERR) Transmit buffer Receive buffer Acceptance filter RX Message Counter (RMC) RX Buffer Start Address register (RBSA) Common registers Bus Timing Register 0 (BTR0) Bus Timing Register 1 (BTR1) 2 6.5.3 6.5.4 7 8 9 10 10.1 10.2 11 12 12.1 12.2 12.2.1 12.2.2 12.3 12.3.1 12.3.2 12.3.3 13 14 SJA1000 Output Control Register (OCR) Clock Divider Register (CDR) LIMITING VALUES THERMAL CHARACTERISTICS DC CHARACTERISTICS AC CHARACTERISTICS AC timing diagrams Additional AC information PACKAGE OUTLINES SOLDERING Introduction DIP Soldering by dipping or by wave Repairing soldered joints SO Reflow soldering Wave soldering Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS 2000 Jan 04 Philips Semiconductors Product specification Stand-alone CAN controller 1 FEATURES 2 GENERAL DESCRIPTION SJA1000 • Pin compatibility to the PCA82C200 stand-alone CAN controller • Electrical compatibility to the PCA82C200 stand-alone CAN controller • PCA82C200 mode (BasicCAN mode is default) • Extended receive buffer (64-byte FIFO) • CAN 2.0B protocol compatibility (extended frame passive in PCA82C200 compatibility mode) • Supports 11-bit identifier as well as 29-bit identifier • Bit rates up to 1 Mbits/s • PeliCAN mode extensions: – Error counters with read/write access – Programmable error warning limit – Last error code register – Error interrupt for each CAN-bus error – Arbitration lost interrupt with detailed bit position – Single-shot transmission (no re-transmission) – Listen only mode (no acknowledge, no active error flags) – Hot plugging support (software driven bit rate detection) – Acceptance filter extension (4-byte code, 4-byte mask) – Reception of ‘own’ messages (self reception request) • 24 MHz clock frequency • Interfaces to a variety of microprocessors • Programmable CAN output driver configuration • Extended ambient temperature range (−40 to +125 °C). 3 ORDERING INFORMATION The SJA1000 is a stand-alone controller for the Controller Area Network (CAN) used within automotive and general industrial environments. It is the successor of the PCA82C200 CAN controller (BasicCAN) from Philips Semiconductors. Additionally, a new mode of operation is implemented (PeliCAN) which supports the CAN 2.0B protocol specification with several new features. PACKAGE TYPE NUMBER NAME SJA1000 SJA1000T DIP28 SO28 DESCRIPTION plastic dual in-line package; 28 leads (600 mil) plastic small outline package; 28 leads; body width 7.5 mm VERSION SOT117-1 SOT136-1 2000 Jan 04 3 Philips Semiconductors Product specification Stand-alone CAN controller 4 BLOCK DIAGRAM SJA1000 handbook, full pagewidth 22 3 to 7, 11, 16 ALE/AS, CS, RD/E, WR, CLKOUT, MODE, INT AD7 to AD0 SJA1000 control INTERFACE MANAGEMENT LOGIC 8 VDD1 VSS1 7 8 address/data 2, 1, 28 to 23 internal bus 12 15 VDD3 VSS3 TX0 TX1 RX0 RX1 VSS2 VDD2 MESSAGE BUFFER BIT STREAM PROCESSOR BIT TIMING LOGIC 13 14 19 20 21 TRANSMIT BUFFER RECEIVE FIFO 18 RECEIVE BUFFER ACCEPTANCE FILTER ERROR MANAGEMENT LOGIC XTAL1 XTAL2 9 10 OSCILLATOR RESET 17 RST MGK623 Fig.1 Block diagram. 2000 Jan 04 4 Philips Semiconductors Product specification Stand-alone CAN controller 5 PINNING SYMBOL AD7 to AD0 ALE/AS CS RD/E WR CLKOUT PIN 2, 1, 28 to 23 3 4 5 6 7 multiplexed address/data bus ALE input signal (Intel mode), AS input signal (Motorola mode) chip select input, LOW level allows access to the SJA1000 DESCRIPTION SJA1000 RD signal (Intel mode) or E enable signal (Motorola mode) from the microcontroller WR signal (Intel mode) or RD/WR signal (Motorola mode) from the microcontroller clock output signal produced by the SJA1000 for the microcontroller; the clock signal is derived from the built-in oscillator via the programmable divider; the clock off bit within the clock divider register allows this pin to disable ground for logic circuits input to the oscillator amplifier; external oscillator signal is input via this pin; note 1 output from the oscillator amplifier; the output must be left open-circuit when an external oscillator signal is used; note 1 mode select input 1 = selects Intel mode 0 = selects Motorola mode VSS1 XTAL1 XTAL2 MODE 8 9 10 11 VDD3 TX0 TX1 VSS3 INT 12 13 14 15 16 5 V supply for output driver output from the CAN output driver 0 to the physical bus line output from the CAN output driver 1 to the physical bus line ground for output driver interrupt output, used to interrupt the microcontroller; INT is active LOW if any bit of the internal interrupt register is set; INT is an open-drain output and is designed to be a wired-OR with other INT outputs within the system; a LOW level on this pin will reactivate the IC from sleep mode reset input, used to reset the CAN interface (active LOW); automatic power-on reset can be obtained by connecting RST via a capacitor to VSS and a resistor to VDD (e.g. C = 1 µF; R = 50 kΩ) 5 V supply for input comparator input from the physical CAN-bus line to the input comparator of the SJA1000; a dominant level will wake up the SJA1000 if sleeping; a dominant level is read, if RX1 is higher than RX0 and vice versa for the recessive level; if the CBP bit (see Table 49) is set in the clock divider register, the CAN input comparator is bypassed to achieve lower internal delays if an external transceiver circuitry is connected to the SJA1000; in this case only RX0 is active; HIGH is interpreted as recessive level and LOW is interpreted as dominant level ground for input comparator 5 V supply for logic circuits RST 17 VDD2 RX0, RX1 18 19, 20 VSS2 VDD1 Note 21 22 1. XTAL1 and XTAL2 pins should be connected to VSS1 via 15 pF capacitors. 2000 Jan 04 5 Philips Semiconductors Product specification Stand-alone CAN controller SJA1000 handbook, halfpage handbook, halfpage AD6 1 AD7 2 ALE/AS 3 CS 4 RD/E 5 WR 6 CLKOUT 7 28 AD5 27 AD4 26 AD3 25 AD2 24 AD1 23 AD0 22 VDD1 AD6 1 AD7 2 ALE/AS 3 CS 4 RD/E 5 WR 6 CLKOUT 7 28 AD5 27 AD4 26 AD3 25 AD2 24 AD1 23 AD0 22 VDD1 SJA1000 VSS1 8 XTAL1 9 XTAL2 10 MODE 11 VDD3 12 TX0 13 TX1 14 MGK616 SJA1000T 21 VSS2 20 RX1 19 RX0 18 VDD2 17 RST 16 INT 15 VSS3 VSS1 8 XTAL1 9 XTAL2 10 MODE 11 VDD3 12 TX0 13 TX1 14 MGK617 21 VSS2 20 RX1 19 RX0 18 VDD2 17 RST 16 INT 15 VSS3 Fig.2 Pin configuration (DIP28). Fig.3 Pin configuration (SO28). 2000 Jan 04 6 Philips Semiconductors Product specification Stand-alone CAN controller 6 6.1 6.1.1 FUNCTIONAL DESCRIPTION Description of the CAN controller blocks INTERFACE MANAGEMENT LOGIC (IML) SJA1000 oscillator drifts) and to define the sample point and the number of samples to be taken within a bit time. 6.1.7 ERROR MANAGEMENT LOGIC (EML) The interface management logic interprets commands from the CPU, controls addressing of the CAN registers and provides interrupts and status information to the host microcontroller. 6.1.2 TRANSMIT BUFFER (TXB) The EML is responsible for the error confinement of the transfer-layer modules. It receives error announcements from the BSP and then informs the BSP and IML about error statistics. 6.2 Detailed description of the CAN controller The transmit buffer is an interface between the CPU and the Bit Stream Processor (BSP) that is able to store a complete message for transmission over the CAN network. The buffer is 13 bytes long, written to by the CPU and read out by the BSP. 6.1.3 RECEIVE BUFFER (RXB, RXFIFO) The SJA1000 is designed to be software and pin-compatible to its predecessor, the PCA82C200 stand-alone CAN controller. Additionally, a lot of new functions are implemented. To achieve the software compatibility, two different modes of operation are implemented: • BasicCAN mode; PCA82C200 compatible • PeliCAN mode; extended features. The mode of operation is selected with the CAN-mode bit located within the clock divider register. Default mode upon reset is the BasicCAN mode. 6.2.1 PCA82C200 COMPATIBILITY The receive buffer is an interface between the acceptance filter and the CPU that stores the received and accepted messages from the CAN-bus line. The Receive Buffer (RXB) represents a CPU-accessible 13-byte window of the Receive FIFO (RXFIFO), which has a total length of 64 bytes. With the help of this FIFO the CPU is able to process one message while other messages are being received. 6.1.4 ACCEPTANCE FILTER (ACF) The acceptance filter compares the received identifier with the acceptance filter register contents and decides whether this message should be accepted or not. In the event of a positive acceptance test, the complete message is stored in the RXFIFO. 6.1.5 BIT STREAM PROCESSOR (BSP) In BasicCAN mode the SJA1000 emulates all known registers from the PCA82C200 stand-alone CAN controller. The characteristics, as described in Sections 6.2.1.1 to 6.2.1.4 are different from the PCA82C200 design with respect to software compatibility. 6.2.1.1 Synchronization mode The bit stream processor is a sequencer which controls the data stream between the transmit buffer, RXFIFO and the CAN-bus. It also performs the error detection, arbitration, stuffing and error handling on the CAN-bus. 6.1.6 BIT TIMING LOGIC (BTL) The SYNC bit in the control register is removed (CR.6 in the PCA82C200). Synchronization is only possible by a recessive-to-dominant transition on the CAN-bus. Writing to this bit has no effect. To achieve compatibility to existing application software, a read access to this bit will reflect the previously written value (flip-flop without effect). 6.2.1.2 Clock divider register The bit timing logic monitors the serial CAN-bus line and handles the bus line-related bit timing. It is synchronized to the bit stream on the CAN-bus on a ‘recessive-to-dominant’ bus line transition at the beginning of a message (hard synchronization) and re-synchronized on further transitions during the reception of a message (soft synchronization). The BTL also provides programmable time segments to compensate for the propagation delay times and phase shifts (e.g. due to The clock divider register is used to select the CAN mode of operation (BasicCAN/PeliCAN). Therefore one of the reserved bits within the PCA82C200 is used. Writing a value between 0 and 7, as allowed for the PCA82C200, will enter the BasicCAN mode. The default state is divide by 12 for Motorola mode and divide by 2 for Intel mode. An additional function is implemented within another of the reserved bits. Setting of bit CBP (see Table 49) enables the internal RX input comparator to be bypassed thereby reducing the internal delays if an external transceiver circuit is used. 7 2000 Jan 04 Philips Semiconductors Product specification Stand-alone CAN controller 6.2.1.3 Receive buffer 6.3 6.3.1 BasicCAN mode BASICCAN ADDRESS LAYOUT SJA1000 The dual receive buffer concept of the PCA82C200 is replaced by the receive FIFO from the PeliCAN controller. This has no effect to the application software except for the data overrun probability. Now more than two messages may be received (up to 64 bytes) until a data overrun occurs. The SJA1000 appears to a microcontroller as a memory-mapped I/O device. An independent operation of both devices is guaranteed by a RAM-like implementation of the on-chip registers. The address area of the SJA1000 consists of the control segment and the message buffers. The control segment is programmed during an initialization download in order to configure communication parameters (e.g. bit timing). Communication over the CAN-bus is also controlled via this segment by the microcontroller. During initialization the CLKOUT signal may be programmed to a value determined by the microcontroller. A message, which should be transmitted, has to be written to the transmit buffer. After a successful reception the microcontroller may read the received message from the receive buffer and then release it for further use. The exchange of status, control and command signals between the microcontroller and the SJA1000 is performed in the control segment. The layout of this segment is shown in Table 3. After an initial download, the contents of the registers acceptance code, acceptance mask, bus timing registers 0 and 1 and output control should not be changed. Therefore these registers may only be accessed when the reset request bit in the control register is set HIGH. For register access, two different modes have to be distinguished: • Reset mode • Operating mode. The reset mode (see Table 3, control register, bit Reset Request) is entered automatically after a hardware reset or when the controller enters the bus-off state (see Table 5, status register, bit Bus Status). The operating mode is activated by resetting of the reset request bit in the control register. 6.2.1.4 CAN 2.0B The SJA1000 is designed to support the full CAN 2.0B protocol specification, which means that the extended oscillator tolerance is implemented as well as the processing of extended frame messages. In BasicCAN mode it is possible to transmit and receive standard frame messages only (11-bit identifier). If extended frame messages (29-bit identifier) are detected on the CAN-bus, they are tolerated and an acknowledge is given if the message was correct, but there is no receive interrupt generated. 6.2.2 DIFFERENCES BETWEEN BASICCAN AND PELICAN MODE In the PeliCAN mode the SJA1000 appears with a re-organized register mapping with a lot of new features. All known bits from the PCA82C200 design are available as well as several new ones. In the PeliCAN mode the complete CAN 2.0B functionality is supported (29-bit identifier). Main new features of the SJA1000 are: • Reception and transmission of standard and extended frame format messages • Receive FIFO (64-byte) • Single/dual acceptance filter with mask and code register for standard and extended frame • Error counters with read/write access • Programmable error warning limit • Last error code register • Error interrupt for each CAN-bus error • Arbitration lost interrupt with detailed bit position • Single-shot transmission (no re-transmission on error or arbitration lost) • Listen only mode (monitoring of the CAN-bus, no acknowledge, no error flags) • Hot plugging supported (disturbance-free software driven bit rate detection) • Disable CLKOUT by hardware. 2000 Jan 04 8 Philips Semiconductors Product specification Stand-alone CAN controller Table 1 BasicCAN address allocation; note 1 OPERATING MODE SEGMENT READ control control (FFH) status interrupt (FFH) (FFH) (FFH) (FFH) (FFH) test transmit buffer identifier (10 to 3) identifier (2 to 0), RTR and DLC data byte 1 data byte 2 data byte 3 data byte 4 data byte 5 data byte 6 data byte 7 data byte 8 receive buffer identifier (10 to 3) identifier (2 to 0), RTR and DLC data byte 1 data byte 2 data byte 3 data byte 4 data byte 5 data byte 6 data byte 7 data byte 8 (FFH) clock divider control command − − − − − − − test; note 2 identifier (10 to 3) identifier (2 to 0), RTR and DLC data byte 1 data byte 2 data byte 3 data byte 4 data byte 5 data byte 6 data byte 7 data byte 8 identifier (10 to 3) identifier (2 to 0), RTR and DLC data byte 1 data byte 2 data byte 3 data byte 4 data byte 5 data byte 6 data byte 7 data byte 8 − clock divider; note 3 WRITE control (FFH) status interrupt acceptance code acceptance mask bus timing 0 bus timing 1 output control test (FFH) (FFH) (FFH) (FFH) (FFH) (FFH) (FFH) (FFH) (FFH) (FFH) identifier (10 to 3) identifier (2 to 0), RTR and DLC data byte 1 data byte 2 data byte 3 data byte 4 data byte 5 data byte 6 data byte 7 data byte 8 (FFH) clock divider READ SJA1000 CAN ADDRESS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Notes RESET MODE WRITE control command − − acceptance code acceptance mask bus timing 0 bus timing 1 output control test; note 2 − − − − − − − − − − identifier (10 to 3) identifier (2 to 0), RTR and DLC data byte 1 data byte 2 data byte 3 data byte 4 data byte 5 data byte 6 data byte 7 data byte 8 − clock divider 1. It should be noted that the registers are repeated within higher CAN address areas (the most significant bits of the 8-bit CPU address are not decoded: CAN address 32 continues with CAN address 0 and so on). 2. Test register is used for production testing only. Using this register during normal operation may result in undesired behaviour of the device. 3. Some bits are writeable in reset mode only (CAN mode and CBP). 2000 Jan 04 9 Philips Semiconductors Product specification Stand-alone CAN controller 6.3.2 RESET VALUES SJA1000 Detection of a ‘reset request’ results in aborting the current transmission/reception of a message and entering the reset mode. On the ‘1-to-0’ transition of the reset request bit, the CAN controller returns to the operating mode. Table 2 Reset mode configuration; notes 1 and 2 VALUE SETTING BIT CR.0 BY SOFTWARE OR DUE TO BUS-OFF 0 X 1 X X X X 1 (reset mode) note 3 REGISTER BIT SYMBOL NAME RESET BY HARDWARE Control CR.7 CR.6 CR.5 CR.4 CR.3 CR.2 CR.1 CR.0 − − − OIE EIE TIE RIE RR − − − GTS CDO RRB AT TR BS ES TS RS TCS TBS DOS RBS − − − WUI DOI EI TI RI reserved reserved reserved Overrun Interrupt Enable Error Interrupt Enable Transmit Interrupt Enable Receive Interrupt Enable Reset Request reserved reserved reserved Go To Sleep Clear Data Overrun Release Receive Buffer Abort Transmission Transmission Request Bus Status Error Status Transmit Status Receive Status Transmission Complete Status Transmit Buffer Status Data Overrun Status Receive Buffer Status reserved reserved reserved Wake-Up Interrupt Data Overrun Interrupt Error Interrupt Transmit Interrupt Receive Interrupt 10 0 X 1 X X X X 1 (reset mode) note 3 Command CMR.7 CMR.6 CMR.5 CMR.4 CMR.3 CMR.2 CMR.1 CMR.0 Status SR.7 SR.6 SR.5 SR.4 SR.3 SR.2 SR.1 SR.0 0 (bus-on) 0 (ok) 0 (idle) 0 (idle) 1 (complete) 1 (released) 0 (absent) 0 (empty) 1 1 1 0 (reset) 0 (reset) 0 (reset) 0 (reset) 0 (reset) X X 0 (idle) 0 (idle) X 1 (released) 0 (absent) 0 (empty) 1 1 1 0 (reset) 0 (reset) X; note 4 0 (reset) 0 (reset) Interrupt IR.7 IR.6 IR.5 IR.4 IR.3 IR.2 IR.1 IR.0 2000 Jan 04 Philips Semiconductors Product specification Stand-alone CAN controller SJA1000 VALUE SETTING BIT CR.0 BY SOFTWARE OR DUE TO BUS-OFF X X X X X X X X X X X X X X X X X X X X X X X X X X X X; note 5 X REGISTER BIT SYMBOL NAME RESET BY HARDWARE Acceptance code Acceptance mask Bus timing 0 AC.7 to 0 AM.7 to 0 BTR0.7 BTR0.6 BTR0.5 BTR0.4 BTR0.3 BTR0.2 BTR0.1 BTR0.0 AC AM SJW.1 SJW.0 BRP.5 BRP.4 BRP.3 BRP.2 BRP.1 BRP.0 SAM TSEG2.2 TSEG2.1 TSEG2.0 TSEG1.3 TSEG1.2 TSEG1.1 TSEG1.0 OCTP1 OCTN1 OCPOL1 OCTP0 OCTN0 OCPOL0 Acceptance Code Acceptance Mask Synchronization Jump Width 1 Synchronization Jump Width 0 Baud Rate Prescaler 5 Baud Rate Prescaler 4 Baud Rate Prescaler 3 Baud Rate Prescaler 2 Baud Rate Prescaler 1 Baud Rate Prescaler 0 Sampling Time Segment 2.2 Time Segment 2.1 Time Segment 2.0 Time Segment 1.3 Time Segment 1.2 Time Segment 1.1 Time Segment 1.0 Output Control Transistor P1 Output Control Transistor N1 Output Control Polarity 1 Output Control Transistor P0 Output Control Transistor N0 Output Control Polarity 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X; note 5 00000000 (Intel); 00000101 (Motorola) Bus timing 1 BTR1.7 BTR1.6 BTR1.5 BTR1.4 BTR1.3 BTR1.2 BTR1.1 BTR1.0 Output control OC.7 OC.6 OC.5 OC.4 OC.3 OC.2 OC.1 OC.0 OCMODE1 Output Control Mode 1 OCMODE0 Output Control Mode 0 TXB RXB CDR Transmit Buffer Receive Buffer Clock Divider Register Transmit buffer Receive buffer Clock divider − − − 2000 Jan 04 11 Philips Semiconductors Product specification Stand-alone CAN controller Notes 1. X means that the value of these registers or bits is not influenced. 2. Remarks in brackets explain functional meaning. 3. Reading the command register will always reflect a binary ‘11111111’. 4. On bus-off the error interrupt is set, if enabled. SJA1000 5. Internal read/write pointers of the RXFIFO are reset to their initial values. A subsequent read access to the RXB would show undefined data values (parts of old messages). If a message is transmitted, this message is written in parallel to the receive buffer but no receive interrupt is generated and the receive buffer area is not locked. So, even if the receive buffer is empty, the last transmitted message may be read from the receive buffer until it is overridden by the next received or transmitted message. Upon a hardware reset, the RXFIFO pointers are reset to the physical RAM address ‘0’. Setting CR.0 by software or due to the bus-off event will reset the RXFIFO pointers to the currently valid FIFO start address which is different from the RAM address ‘0’ after the first release receive buffer command. 6.3.3 CONTROL REGISTER (CR) The contents of the control register are used to change the behaviour of the CAN controller. Bits may be set or reset by the attached microcontroller which uses the control register as a read/write memory. Table 3 BIT CR.7 CR.6 CR.5 CR.4 Bit interpretation of the control register (CR); CAN address 0 SYMBOL − − − OIE − − − Overrun Interrupt Enable NAME VALUE − − − 1 reserved; note 1 reserved; note 2 reserved; note 3 enabled; if the data overrun bit is set, the microcontroller receives an overrun interrupt signal (see also status register; Table 5) disabled; the microcontroller receives no overrun interrupt signal from the SJA1000 enabled; if the error or bus status change, the microcontroller receives an error interrupt signal (see also status register; Table 5) disabled; the microcontroller receives no error interrupt signal from the SJA1000 enabled; when a message has been successfully transmitted or the transmit buffer is accessible again, (e.g. after an abort transmission command) the SJA1000 transmits a transmit interrupt signal to the microcontroller disabled; the microcontroller receives no transmit interrupt signal from the SJA1000 FUNCTION 0 CR.3 EIE Error Interrupt Enable 1 0 CR.2 TIE Transmit Interrupt Enable 1 0 2000 Jan 04 12 Philips Semiconductors Product specification Stand-alone CAN controller SJA1000 BIT CR.1 SYMBOL RIE NAME Receive Interrupt Enable VALUE 1 FUNCTION enabled; when a message has been received without errors, the SJA1000 transmits a receive interrupt signal to the microcontroller disabled; the microcontroller receives no transmit interrupt signal from the SJA1000 present; detection of a reset request results in aborting the current transmission/reception of a message and entering the reset mode absent; on the ‘1-to-0’ transition of the reset request bit, the SJA1000 returns to the operating mode 0 CR.0 RR Reset Request; note 4 1 0 Notes 1. Any write access to the control register has to set this bit to logic 0 (reset value is logic 0). 2. In the PCA82C200 this bit was used to select the synchronization mode. Because this mode is not longer implemented, setting this bit has no influence on the microcontroller. Due to software compatibility setting this bit is allowed. This bit will not change after hardware or software reset. In addition the value written by users software is reflected. 3. Reading this bit will always reflect a logic 1. 4. During a hardware reset or when the bus status bit is set to logic 1 (bus-off), the reset request bit is set to logic 1 (present). If this bit is accessed by software, a value change will become visible and takes effect first with the next positive edge of the internal clock which operates with 1⁄2 of the external oscillator frequency. During an external reset the microcontroller cannot set the reset request bit to logic 0 (absent). Therefore, after having set the reset request bit to logic 0, the microcontroller must check this bit to ensure that the external reset pin is not being held LOW. Changes of the reset request bit are synchronized with the internal divided clock. Reading the reset request bit reflects the synchronized status. After the reset request bit is set to logic 0 the SJA1000 will wait for: a) One occurrence of bus-free signal (11 recessive bits), if the preceding reset request has been caused by a hardware reset or a CPU-initiated reset b) 128 occurrences of bus-free, if the preceding reset request has been caused by a CAN controller initiated bus-off, before re-entering the bus-on mode; it should be noted that several registers are modified if the reset request bit was set (see also Table 2). 6.3.4 COMMAND REGISTER (CMR) A command bit initiates an action within the transfer layer of the SJA1000. The command register appears to the microcontroller as a write only memory. If a read access is performed to this address the byte ‘11111111’ is returned. Between two commands at least one internal clock cycle is needed to process. The internal clock is divided by two from the external oscillator frequency. 2000 Jan 04 13 Philips Semiconductors Product specification Stand-alone CAN controller Table 4 BIT CMR.7 CMR.6 CMR.5 CMR.4 Bit interpretation of the command register (CMR); CAN address 1 SYMBOL − − − GTS − − − Go To Sleep; note 1 NAME VALUE − − − 1 0 CMR.3 CMR.2 CDO RRB Clear Data Overrun; note 2 Release Receive Buffer; note 3 1 0 1 reserved reserved reserved FUNCTION SJA1000 sleep; the SJA1000 enters sleep mode if no CAN interrupt is pending and there is no bus activity wake up; SJA1000 operates normal clear; data overrun status bit is cleared no action released; the receive buffer, representing the message memory space in the RXFIFO is released no action present; if not already in progress, a pending transmission request is cancelled absent; no action present; a message will be transmitted absent; no action 0 CMR.1 AT Abort Transmission; note 4 Transmission Request; note 5 1 0 CMR.0 TR 1 0 Notes 1. The SJA1000 will enter sleep mode if the sleep bit is set to logic 1 (sleep); there is no bus activity and no interrupt is pending. Setting of GTS with at least one of the previously mentioned exceptions valid will result in a wake-up interrupt. After sleep mode is set, the CLKOUT signal continues until at least 15 bit times have passed, to allow a host microcontroller clocked via this signal to enter its own standby mode before the CLKOUT goes LOW. The SJA1000 will wake up when one of the three previously mentioned conditions is negated: after ‘Go To Sleep’ is set LOW (wake-up), there is bus activity or INT is driven LOW (active). On wake-up, the oscillator is started and a wake-up interrupt is generated. A sleeping SJA1000 which wakes up due to bus activity will not be able to receive this message until it detects 11 consecutive recessive bits (bus-free sequence). It should be noted that setting of GTS is not possible in reset mode. After clearing of reset request, setting of GTS is possible first, when bus-free is detected again. 2. This command bit is used to clear the data overrun condition indicated by the data overrun status bit. As long as the data overrun status bit is set no further data overrun interrupt is generated. It is allowed to give the clear data overrun command at the same time as a release receive buffer command. 3. After reading the contents of the receive buffer, the microcontroller can release this memory space of the RXFIFO by setting the release receive buffer bit to logic 1. This may result in another message becoming immediately available within the receive buffer. This event will force another receive interrupt, if enabled. If there is no other message available no further receive interrupt is generated and the receive buffer status bit is cleared. 4. The abort transmission bit is used when the CPU requires the suspension of the previously requested transmission, e.g. to transmit a more urgent message before. A transmission already in progress is not stopped. In order to see if the original message had been either transmitted successfully or aborted, the transmission complete status bit should be checked. This should be done after the transmit buffer status bit has been set to logic 1 (released) or a transmit interrupt has been generated. 5. If the transmission request was set to logic 1 in a previous command, it cannot be cancelled by setting the transmission request bit to logic 0. The requested transmission may be cancelled by setting the abort transmission bit to logic 1. 2000 Jan 04 14 Philips Semiconductors Product specification Stand-alone CAN controller 6.3.5 STATUS REGISTER (SR) SJA1000 The content of the status register reflects the status of the SJA1000. The status register appears to the microcontroller as a read only memory. Table 5 BIT SR.7 Bit interpretation of the status register (SR); CAN address 2 SYMBOL BS NAME Bus Status; note 1 1 0 SR.6 ES Error Status; note 2 1 0 SR.5 SR.4 SR.3 TS RS TCS Transmit Status; note 3 Receive Status; note 3 Transmission Complete Status; note 4 1 0 1 0 1 0 SR.2 TBS Transmit Buffer Status; note 5 1 0 VALUE FUNCTION bus-off; the SJA1000 is not involved in bus activities bus-on; the SJA1000 is involved in bus activities error; at least one of the error counters has reached or exceeded the CPU warning limit ok; both error counters are below the warning limit transmit; the SJA1000 is transmitting a message idle; no transmit message is in progress receive; the SJA1000 is receiving a message idle; no receive message is in progress complete; the last requested transmission has been successfully completed incomplete; the previously requested transmission is not yet completed released; the CPU may write a message into the transmit buffer locked; the CPU cannot access the transmit buffer; a message is waiting for transmission or is already in process overrun; a message was lost because there was not enough space for that message in the RXFIFO absent; no data overrun has occurred since the last clear data overrun command was given full; one or more messages are available in the RXFIFO empty; no message is available SR.1 DOS Data Overrun Status; note 6 1 0 SR.0 RBS Receive Buffer Status; note 7 1 0 2000 Jan 04 15 Philips Semiconductors Product specification Stand-alone CAN controller Notes SJA1000 1. When the transmit error counter exceeds the limit of 255 [the bus status bit is set to logic 1 (bus-off)] the CAN controller will set the reset request bit to logic 1 (present) and an error interrupt is generated, if enabled. It will stay in this mode until the CPU clears the reset request bit. Once this is completed the CAN controller will wait the minimum protocol-defined time (128 occurrences of the bus-free signal). After that the bus status bit is cleared (bus-on), the error status bit is set to logic 0 (ok), the error counters are reset and an error interrupt is generated, if enabled. 2. Errors detected during reception or transmission will affect the error counters according to the CAN 2.0B protocol specification. The error status bit is set when at least one of the error counters has reached or exceeded the CPU warning limit of 96. An error interrupt is generated, if enabled. 3. If both the receive status and the transmit status bits are logic 0 (idle) the CAN-bus is idle. 4. The transmission complete status bit is set to logic 0 (incomplete) whenever the transmission request bit is set to logic 1. The transmission complete status bit will remain at logic 0 (incomplete) until a message is transmitted successfully. 5. If the CPU tries to write to the transmit buffer when the transmit buffer status bit is at logic 0 (locked), the written byte will not be accepted and will be lost without being indicated. 6. When a message that shall be received has passed the acceptance filter successfully (i.e. earliest after arbitration field), the CAN controller needs space in the RXFIFO to store the message descriptor. Accordingly there must be enough space for each data byte which has been received. If there is not enough space to store the message, that message will be dropped and the data overrun condition will be indicated to the CPU only, if this received message has no errors until the last but one bit of end of frame (message becomes valid). 7. After reading a message stored in the RXFIFO and releasing this memory space with the command release receive buffer, this bit is cleared. If there is another message available within the FIFO this bit is set again with the next bit quantum (tscl). 2000 Jan 04 16 Philips Semiconductors Product specification Stand-alone CAN controller 6.3.6 INTERRUPT REGISTER (IR) SJA1000 The interrupt register allows the identification of an interrupt source. When one or more bits of this register are set, the INT pin is activated (LOW). After this register is read by the microcontroller, all bits are reset what results in a floating level at INT. The interrupt register appears to the microcontroller as a read only memory. Table 6 BIT IR.7 IR.6 IR.5 IR.4 Bit interpretation of the interrupt register (IR); CAN address 3 SYMBOL − − − WUI − − − Wake-Up Interrupt; note 2 Data Overrun Interrupt; note 3 NAME − − − 1 0 1 VALUE reserved; note 1 reserved; note 1 reserved; note 1 set; this bit is set when the sleep mode is left reset; this bit is cleared by any read access of the microcontroller set; this bit is set on a ‘0-to-1’ transition of the data overrun status bit, when the data overrun interrupt enable is set to logic 1 (enabled) reset; this bit is cleared by any read access of the microcontroller set; this bit is set on a change of either the error status or bus status bits if the error interrupt enable is set to logic 1 (enabled) reset; this bit is cleared by any read access of the microcontroller set; this bit is set whenever the transmit buffer status changes from logic 0 to logic 1 (released) and transmit interrupt enable is set to logic 1 (enabled) reset; this bit is cleared by any read access of the microcontroller set; this bit is set while the receive FIFO is not empty and the receive interrupt enable bit is set to logic 1 (enabled) reset; this bit is cleared by any read access of the microcontroller FUNCTION IR.3 DOI 0 IR.2 EI Error Interrupt 1 0 IR.1 TI Transmit Interrupt 1 0 IR.0 RI Receive Interrupt; note 4 1 0 Notes 1. Reading this bit will always reflect a logic 1. 2. A wake-up interrupt is also generated if the CPU tries to set go to sleep while the CAN controller is involved in bus activities or a CAN interrupt is pending. 3. The overrun interrupt bit (if enabled) and the data overrun status bit are set at the same time. 4. The receive interrupt bit (if enabled) and the receive buffer status bit are set at the same time. It should be noted that the receive interrupt bit is cleared upon a read access, even if there is another message available within the FIFO. The moment the release receive buffer command is given and there is another message valid within the receive buffer, the receive interrupt is set again (if enabled) with the next tscl. 2000 Jan 04 17 Philips Semiconductors Product specification Stand-alone CAN controller 6.3.7 TRANSMIT BUFFER LAYOUT SJA1000 The global layout of the transmit buffer is shown in Table 7. The buffer serves to store a message from the microcontroller to be transmitted by the SJA1000. It is subdivided into a descriptor and data field. The transmit buffer can be written to and read out by the microcontroller in operating mode only. In reset mode a ‘FFH’ is reflected for all bytes. Table 7 Layout of transmit buffer BITS FIELD NAME 7 descriptor identifier byte 1 identifier byte 2 data TX data 1 TX data 2 TX data 3 TX data 4 TX data 5 TX data 6 TX data 7 TX data 8 ID.10 ID.2 6 ID.9 ID.1 5 ID.8 ID.0 4 ID.7 RTR 3 ID.6 DLC.3 2 ID.5 DLC.2 1 ID.4 DLC.1 0 ID.3 DLC.0 CAN ADDRESS 10 11 12 13 14 15 16 17 18 19 transmit data byte 1 transmit data byte 2 transmit data byte 3 transmit data byte 4 transmit data byte 5 transmit data byte 6 transmit data byte 7 transmit data byte 8 specified correctly to avoid bus errors if two CAN controllers start a remote frame transmission with the same identifier simultaneously. The range of the data byte count is 0 to 8 bytes and is coded as follows: DataByteCount = 8 × DLC.3 + 4 × DLC.2 + 2 × DLC.1 + DLC.0 For reasons of compatibility no data length code >8 should be used. If a value >8 is selected, 8 bytes are transmitted in the data frame with the data length code specified in DLC. 6.3.7.1 Identifier (ID) The identifier consists of 11 bits (ID.10 to ID.0). ID.10 is the most significant bit, which is transmitted first on the bus during the arbitration process. The identifier acts as the message’s name. It is used in a receiver for acceptance filtering and also determining the bus access priority during the arbitration process. The lower the binary value of the identifier the higher the priority. This is due to a larger number of leading dominant bits during arbitration. 6.3.7.2 Remote Transmission Request (RTR) If this bit is set, a remote frame will be transmitted via the bus. This means that no data bytes are included within this frame. Nevertheless, it is necessary to specify the correct data length code which depends on the corresponding data frame with the same identifier coding. If the RTR bit is not set, a data frame will be sent including the number of data bytes as specified by the data length code. 6.3.7.4 Data field The number of transferred data bytes is determined by the data length code. The first bit transmitted is the most significant bit of data byte 1 at address 12. 6.3.8 RECEIVE BUFFER 6.3.7.3 Data Length Code (DLC) The number of bytes in the data field of a message is coded by the data length code. At the start of a remote frame transmission the data length code is not considered due to the RTR bit being at logic 1 (remote). This forces the number of transmitted/received data bytes to be logic 0. Nevertheless, the data length code must be 2000 Jan 04 18 The global layout of the receive buffer is very similar to the transmit buffer described in Section 6.3.7. The receive buffer is the accessible part of the RXFIFO and is located in the range between CAN address 20 and 29. Philips Semiconductors Product specification Stand-alone CAN controller SJA1000 handbook, full pagewidth 64-byte FIFO message 3 message 2 release receive buffer command incoming messages message 1 29 28 27 26 25 24 23 22 21 20 receive buffer window CAN address MGK618 Message 1 is now available in the receive buffer. Fig.4 Example of the message storage within the RXFIFO. Identifier, remote transmission request bit and data length code have the same meaning and location as described in the transmit buffer but within the address range 20 to 29. As illustrated in Fig.4 the RXFIFO has space for 64 message bytes in total. The number of messages that can be stored in the FIFO at any particular moment depends on the length of the individual messages. If there is not enough space for a new message within the RXFIFO, the CAN controller generates a data overrun condition. A message which is partly written into the RXFIFO, when the data overrun condition occurs, is deleted. This situation is indicated to the microcontroller via the status register and the data overrun interrupt, if enabled and the frame was received without any errors until the last but one bit of end of frame (RX message becomes valid). 6.3.9 ACCEPTANCE FILTER With the help of the acceptance filter the CAN controller is able to allow passing of received messages to the RXFIFO only when the identifier bits of the received message are equal to the predefined ones within the acceptance filter registers. The acceptance filter is defined by the acceptance code register (ACR; see Section 6.3.9.1) and the acceptance mask register (AMR; see Section 6.3.9.2). 2000 Jan 04 19 Philips Semiconductors Product specification Stand-alone CAN controller 6.3.9.1 Table 8 AC.7 SJA1000 Acceptance Code Register (ACR) ACR bit allocation; can address 4 BIT 6 AC.6 BIT 5 AC.5 BIT 4 AC.4 BIT 3 AC.3 BIT 2 AC.2 BIT 1 AC.1 BIT 0 AC.0 BIT 7 This register can be accessed (read/write), if the reset request bit is set HIGH (present). When a message is received which passes the acceptance test and there is receive buffer space left, then the respective descriptor and data field are sequentially stored in the RXFIFO. When the complete message has been correctly received the following occurs: • The receive status bit is set HIGH (full) • If the receive interrupt enable bit is set HIGH (enabled), the receive interrupt is set HIGH (set). The acceptance code bits (AC.7 to AC.0) and the eight most significant bits of the message’s identifier (ID.10 to ID.3) must be equal to those bit positions which are marked relevant by the acceptance mask bits (AM.7 to AM.0). If the conditions as described in the following equation are fulfilled, acceptance is given: (ID.10 to ID.3) ≡ (AC.7 to AC.0)] ∨ (AM.7 to AM.0) ≡ 11111111 6.3.9.2 Table 9 Acceptance Mask Register (AMR) AMR bit allocation; CAN address 5 BIT 6 AM.6 BIT 5 AM.5 BIT 4 AM.4 BIT 3 AM.3 6.4 6.4.1 BIT 2 AM.2 BIT 1 AM.1 BIT 0 AM.0 BIT 7 AM.7 This register can be accessed (read/write), if the reset request bit is set HIGH (present). The acceptance mask register qualifies which of the corresponding bits of the acceptance code are ‘relevant’ (AM.X = 0) or ‘don’t care’ (AM.X = 1) for acceptance filtering. PeliCAN mode PELICAN ADDRESS LAYOUT 6.3.9.3 Other registers The other registers are described in Section 6.5. The CAN controller’s internal registers appear to the CPU as on-chip memory mapped peripheral registers. Because the CAN controller can operate in different modes (operating/reset; see also Section 6.4.3), one has to distinguish between different internal address definitions. Starting from CAN address 32 the complete internal RAM (80-byte) is mapped to the CPU interface. 2000 Jan 04 20 Philips Semiconductors Product specification Stand-alone CAN controller Table 10 PeliCAN address allocation; note 1 CAN ADDRESS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 mode (00H) status interrupt interrupt enable reserved (00H) bus timing 0 bus timing 1 output control test reserved (00H) arbitration lost capture error code capture error warning limit RX error counter TX error counter RX frame information SFF; note 3 RX frame information EFF; note 4 OPERATING MODE READ mode command − − interrupt enable − − − − test; note 2 − − − − − − TX frame information SFF; note 3 TX frame information EFF; note 4 TX identifier 1 TX identifier 2 TX identifier 3 TX identifier 4 TX data 1 TX data 2 TX data 3 TX data 4 TX data 5 TX data 6 21 WRITE SJA1000 RESET MODE READ mode (00H) status interrupt interrupt enable reserved (00H) bus timing 0 bus timing 1 output control test reserved (00H) arbitration lost capture error code capture error warning limit WRITE mode command − − interrupt enable − bus timing 0 bus timing 1 output control test; note 2 − − − error warning limit RX error counter RX error counter TX error counter TX error counter acceptance code 0 acceptance code 1 acceptance code 2 acceptance code 3 acceptance mask 0 acceptance mask 1 acceptance mask 2 acceptance mask 3 reserved (00H) reserved (00H) reserved (00H) acceptance code 0 acceptance code 1 acceptance code 2 acceptance code 3 acceptance mask 0 acceptance mask 1 acceptance mask 2 acceptance mask 3 − − − 17 18 19 20 21 22 23 24 25 26 2000 Jan 04 RX identifier 1 RX identifier 1 TX identifier 1 RX identifier 2 RX identifier 2 TX identifier 2 RX data 1 RX data 2 RX data 3 RX data 4 RX data 5 RX data 6 RX data 7 RX data 8 RX identifier 3 TX data 1 RX identifier 4 TX data 2 RX data 1 RX data 2 RX data 3 RX data 4 RX data 5 RX data 6 TX data 3 TX data 4 TX data 5 TX data 6 TX data 7 TX data 8 Philips Semiconductors Product specification Stand-alone CAN controller SJA1000 CAN ADDRESS 27 28 29 30 31 32 33 ↓ 95 96 ↓ 108 109 110 111 112 ↓ 127 Notes OPERATING MODE READ (FIFO RAM); note 5 (FIFO RAM); note 5 RX data 7 RX data 8 − − − − clock divider; note 6 WRITE TX data 7 TX data 8 RESET MODE READ reserved (00H) reserved (00H) RX message counter RX buffer start address clock divider internal RAM address 0 internal RAM address 1 ↓ internal RAM address 63 internal RAM address 64 ↓ internal RAM address 76 internal RAM address 77 internal RAM address 78 internal RAM address 79 (00H) ↓ (00H) − − − RX buffer start address clock divider internal RAM address 0 internal RAM address 1 ↓ internal RAM address 63 internal RAM address 64 ↓ internal RAM address 76 internal RAM address 77 internal RAM address 78 internal RAM address 79 − ↓ − WRITE RX message counter RX buffer start address clock divider internal RAM address 0 (FIFO) − internal RAM address 1 (FIFO) − ↓ internal RAM address 63 (FIFO) internal RAM address 64 (TX buffer) ↓ internal RAM address 76 (TX buffer) ↓ − − ↓ − internal RAM address 77 (free) − internal RAM address 78 (free) − internal RAM address 79 (free) − (00H) ↓ (00H) − ↓ − 1. It should be noted that the registers are repeated within higher CAN address areas (the most significant bit of the 8-bit CPU address is not decoded: CAN address 128 continues with CAN address 0 and so on). 2. Test register is used for production testing only. Using this register during normal operation may result in undesired behaviour of the device. 3. SFF = Standard Frame Format. 4. EFF = Extended Frame Format. 5. These address allocations reflect the FIFO RAM space behind the current message. The contents are random after power-up and contain the beginning of the next message which is received after the current one. If no further message is received, parts of old messages may occur here. 6. Some bits are writeable in reset mode only (CAN mode, CBP, RXINTEN and clock off). 2000 Jan 04 22 Philips Semiconductors Product specification Stand-alone CAN controller 6.4.2 RESET VALUES SJA1000 Detection of a set reset mode bit results in aborting the current transmission/reception of a message and entering the reset mode. On the ‘1-to-0’ transition of the reset mode bit, the CAN controller returns to the mode defined within the mode register. Table 11 Reset mode configuration; notes 1 and 2 VALUE REGISTER BIT SYMBOL NAME RESET BY HARDWARE 0 (reserved) 0 (wake-up) 0 (dual) 0 (normal) 0 (normal) 1 (present) 0 (reserved) 0 (absent) 0 (no action) 0 (no action) 0 (absent) 0 (absent) 0 (bus-on) 0 (ok) 1 (wait idle) 1 (wait idle) 1 (complete) 1 (released) 0 (absent) 0 (empty) 0 (reset) 0 (reset) 0 (reset) 0 (reset) 0 (reset) 0 (reset) 0 (reset) 0 (reset) SETTING MOD.0 BY SOFTWARE OR DUE TO BUS-OFF 0 (reserved) 0 (wake-up) X X X 1 (present) 0 (reserved) 0 (absent) 0 (no action) 0 (no action) 0 (absent) 0 (absent) X X 1 (wait idle) 1 (wait idle) X 1 (released) 0 (absent) 0 (empty) 0 (reset) 0 (reset) 0 (reset) 0 (reset) 0 (reset) X; note 3 0 (reset) 0 (reset) Mode MOD.7 to 5 MOD.4 MOD.3 MOD.2 MOD.1 MOD.0 − SM AFM STM LOM RM − SRR CDO RRB AT TR BS ES TS RS TCS TBS DOS RBS BEI ALI EPI WUI DOI EI TI RI reserved Sleep Mode Acceptance Filter Mode Self Test Mode Listen Only Mode Reset Mode reserved Self Reception Request Clear Data Overrun Release Receive Buffer Abort Transmission Transmission Request Bus Status Error Status Transmit Status Receive Status Transmission Complete Status Transmit Buffer Status Data Overrun Status Receive Buffer Status Bus Error Interrupt Arbitration Lost Interrupt Error Passive Interrupt Wake-Up Interrupt Data Overrun Interrupt Error Warning Interrupt Transmit Interrupt Receive Interrupt Command CMR.7 to 5 CMR.4 CMR.3 CMR.2 CMR.1 CMR.0 Status SR.7 SR.6 SR.5 SR.4 SR.3 SR.2 SR.1 SR.0 Interrupt IR.7 IR.6 IR.5 IR.4 IR.3 IR.2 IR.1 IR.0 2000 Jan 04 23 Philips Semiconductors Product specification Stand-alone CAN controller SJA1000 VALUE REGISTER BIT SYMBOL NAME RESET BY HARDWARE X X X X X X X SETTING MOD.0 BY SOFTWARE OR DUE TO BUS-OFF X X X X X X X X X X X X X X X X X X X X X X X X Interrupt enable IER.7 IER.6 IER.5 IER.4 IER.3 IER.2 IER.1 IER.0 BEIE ALIE EPIE WUIE DOIE EIE TIE RIE SJW.1 SJW.0 BRP.5 BRP.4 BRP.3 BRP.2 BRP.1 BRP.0 SAM TSEG2.2 TSEG2.1 TSEG2.0 TSEG1.3 TSEG1.2 TSEG1.1 TSEG1.0 Bus Error Interrupt Enable Arbitration Lost Interrupt Enable Error Passive Interrupt Enable Wake-Up Interrupt Enable Data Overrun Interrupt Enable Error Warning Interrupt Enable Transmit Interrupt Enable Synchronization Jump Width 1 Synchronization Jump Width 0 Baud Rate Prescaler 5 Baud Rate Prescaler 4 Baud Rate Prescaler 3 Baud Rate Prescaler 2 Baud Rate Prescaler 1 Baud Rate Prescaler 0 Sampling Time Segment 2.2 Time Segment 2.1 Time Segment 2.0 Time Segment 1.3 Time Segment 1.2 Time Segment 1.1 Time Segment 1.0 Receive Interrupt Enable X X X X X X X X X X X X X X X X X Bus timing 0 BTR0.7 BTR0.6 BTR0.5 BTR0.4 BTR0.3 BTR0.2 BTR0.1 BTR0.0 Bus timing 1 BTR1.7 BTR1.6 BTR1.5 BTR1.4 BTR1.3 BTR1.2 BTR1.1 BTR1.0 2000 Jan 04 24 Philips Semiconductors Product specification Stand-alone CAN controller SJA1000 VALUE REGISTER BIT SYMBOL NAME RESET BY HARDWARE X X SETTING MOD.0 BY SOFTWARE OR DUE TO BUS-OFF X X X X X X X X X X X X; note 4 X; note 4 X X; note 5 X X 0 X X Output control OCR.7 OCR.6 OCR.5 OCR.4 OCR.3 OCR.2 OCR.1 OCR.0 OCTP1 OCTN1 OCPOL1 OCTP0 OCTN0 OCPOL0 OCMODE1 OCMODE0 ALC ECC EWLR RXERR TXERR TXB RXB ACR0 to ACR3 AMR0 to AMR3 RMC RBSA CDR Output Control Transistor P1 Output Control Transistor N1 Output Control Transistor P0 Output Control Transistor N0 Output Control Mode 1 Output Control Mode 0 Arbitration Lost Capture Error Code Capture Error Warning Limit Register Receive Error Counter Transmit Error Counter Transmit Buffer Receive Buffer Acceptance Code Registers Acceptance Mask Registers RX Message Counter RX Buffer Start Address Clock Divider Register Output Control Polarity 1 X X X Output Control Polarity 0 X X X 0 0 96 0 (reset) 0 (reset) X X; note 5 X X 0 00000000 00000000 Intel; 00000101 Motorola Arbitration lost capture Error code capture Error warning limit RX error counter TX error counter TX buffer RX buffer ACR 0 to 3 AMR 0 to 3 RX message counter RX buffer start address Clock divider − − − − − − − − − − − − 2000 Jan 04 25 Philips Semiconductors Product specification Stand-alone CAN controller Notes 1. X means that the value of these registers or bits is not influenced. 2. Remarks in brackets explain functional meaning. 3. On bus-off the error warning interrupt is set, if enabled. SJA1000 4. If the reset mode was entered due to a bus-off condition, the receive error counter is cleared and the transmit error counter is initialized to 127 to count-down the CAN-defined bus-off recovery time consisting of 128 occurrences of 11 consecutive recessive bits. 5. Internal read/write pointers of the RXFIFO are reset to their initial values. A subsequent read access to the RXB would show undefined data values (parts of old messages). If a message is transmitted, this message is written in parallel to the receive buffer. A receive interrupt is generated only if this transmission was forced by the self reception request. So, even if the receive buffer is empty, the last transmitted message may be read from the receive buffer until it is overwritten by the next received or transmitted message. Upon a hardware reset, the RXFIFO pointers are reset to the physical RAM address ‘0’. Setting CR.0 by software or due to the bus-off event will reset the RXFIFO pointers to the currently valid FIFO start address (RBSA register) which is different from the RAM address ‘0’ after the first release receive buffer command. 6.4.3 MODE REGISTER (MOD) The contents of the mode register are used to change the behaviour of the CAN controller. Bits may be set or reset by the CPU which uses the control register as a read/write memory. Reserved bits are read as logic 0. Table 12 Bit interpretation of the mode register (MOD); CAN address ‘0’ BIT MOD.7 MOD.6 MOD.5 MOD.4 SYMBOL − − − SM − − − Sleep Mode; note 1 NAME VALUE − − − 1 reserved reserved reserved sleep; the CAN controller enters sleep mode if no CAN interrupt is pending and if there is no bus activity wake-up; the CAN controller wakes up if sleeping single; the single acceptance filter option is enabled (one filter with the length of 32 bit is active) dual; the dual acceptance filter option is enabled (two filters, each with the length of 16 bit are active) self test; in this mode a full node test is possible without any other active node on the bus using the self reception request command; the CAN controller will perform a successful transmission, even if there is no acknowledge received normal; an acknowledge is required for successful transmission FUNCTION 0 MOD.3 AFM Acceptance Filter Mode; note 2 1 0 MOD.2 STM Self Test Mode; note 2 1 0 2000 Jan 04 26 Philips Semiconductors Product specification Stand-alone CAN controller SJA1000 BIT MOD.1 SYMBOL LOM NAME Listen Only Mode; notes 2 and 3 VALUE 1 FUNCTION listen only; in this mode the CAN controller would give no acknowledge to the CAN-bus, even if a message is received successfully; the error counters are stopped at the current value normal reset; detection of a set reset mode bit results in aborting the current transmission/reception of a message and entering the reset mode normal; on the ‘1-to-0’ transition of the reset mode bit, the CAN controller returns to the operating mode 0 MOD.0 RM Reset Mode; note 4 1 0 Notes 1. The SJA1000 will enter sleep mode if the sleep mode bit is set to logic 1 (sleep); then there is no bus activity and no interrupt is pending. Setting of SM with at least one of the previously mentioned exceptions valid will result in a wake-up interrupt. After sleep mode is set, the CLKOUT signal continues until at least 15 bit times have passed, to allow a host microcontroller clocked via this signal to enter its own standby mode before the CLKOUT goes LOW. The SJA1000 will wake up when one of the three previously mentioned conditions is negated: after SM is set LOW (wake-up), there is bus activity or INT is driven LOW (active). On wake-up, the oscillator is started and a wake-up interrupt is generated. A sleeping SJA1000 which wakes up due to bus activity will not be able to receive this message until it detects 11 consecutive recessive bits (bus-free sequence). It should be noted that setting of SM is not possible in reset mode. After clearing of reset mode, setting of SM is possible first, when bus-free is detected again. 2. A write access to the bits MOD.1 to MOD.3 is only possible, if the reset mode is entered previously. 3. This mode of operation forces the CAN controller to be error passive. Message transmission is not possible. The listen only mode can be used e.g. for software driven bit rate detection and ‘hot plugging’. All other functions can be used like in normal mode. 4. During a hardware reset or when the bus status bit is set to logic 1 (bus-off), the reset mode bit is also set to logic 1 (present). If this bit is accessed by software, a value change will become visible and takes effect first with the next positive edge of the internal clock which operates at half of the external oscillator frequency. During an external reset the microcontroller cannot set the reset mode bit to logic 0 (absent). Therefore, after having set the reset mode bit to logic 1, the microcontroller must check this bit to ensure that the external reset pin is not being held HIGH. Changes of the reset request bit are synchronized with the internal divided clock. Reading the reset request bit reflects the synchronized status. After the reset mode bit is set to logic 0 the CAN controller will wait for: a) One occurrence of bus-free signal (11 recessive bits), if the preceding reset has been caused by a hardware reset or a CPU-initiated reset. b) 128 occurrences of bus-free, if the preceding reset has been caused by a CAN controller initiated bus-off, before re-entering the bus-on mode. 2000 Jan 04 27 Philips Semiconductors Product specification Stand-alone CAN controller 6.4.4 COMMAND REGISTER (CMR) SJA1000 A command bit initiates an action within the transfer layer of the CAN controller. This register is write only, all bits will return a logic 0 when being read. Between two commands at least one internal clock cycle is needed in order to proceed. The internal clock is half of the external oscillator frequency. Table 13 Bit interpretation of the command register (CMR); CAN address 1 BIT CMR.7 CMR.6 CMR.5 CMR.4 SYMBOL − − − SRR reserved reserved reserved Self Reception Request; notes 1 and 2 Clear Data Overrun; note 3 Release Receive Buffer; note 4 NAME VALUE − − − 1 0 CMR.3 CMR.2 CDO RRB 1 0 1 − − − present; a message shall be transmitted and received simultaneously − (absent) clear; the data overrun status bit is cleared − (no action) released; the receive buffer, representing the message memory space in the RXFIFO is released − (no action) present; if not already in progress, a pending transmission request is cancelled − (absent) present; a message shall be transmitted − (absent) FUNCTION 0 CMR.1 AT Abort Transmission; notes 5 and 2 Transmission Request; notes 6 and 2 1 0 CMR.0 TR 1 0 Notes 1. Upon self reception request a message is transmitted and simultaneously received if the acceptance filter is set to the corresponding identifier. A receive and a transmit interrupt will indicate correct self reception (see also self test mode in mode register). 2. Setting the command bits CMR.0 and CMR.1 simultaneously results in sending the transmit message once. No re-transmission will be performed in the event of an error or arbitration lost (single-shot transmission). Setting the command bits CMR.4 and CMR.1 simultaneously results in sending the transmit message once using the self reception feature. No re-transmission will be performed in the event of an error or arbitration lost. Setting the command bits CMR.0, CMR.1 and CMR.4 simultaneously results in sending the transmit message once as described for CMR.0 and CMR.1. The moment the transmit status bit is set within the status register, the internal transmission request bit is cleared automatically. Setting CMR.0 and CMR.4 simultaneously will ignore the set CMR.4 bit. 3. This command bit is used to clear the data overrun condition indicated by the data overrun status bit. As long as the data overrun status bit is set no further data overrun interrupt is generated. 4. After reading the contents of the receive buffer, the CPU can release this memory space in the RXFIFO by setting the release receive buffer bit to logic 1. This may result in another message becoming immediately available within the receive buffer. If there is no other message available, the receive interrupt bit is reset. 2000 Jan 04 28 Philips Semiconductors Product specification Stand-alone CAN controller SJA1000 5. The abort transmission bit is used when the CPU requires the suspension of the previously requested transmission, e.g. to transmit a more urgent message before. A transmission already in progress is not stopped. In order to see if the original message has been either transmitted successfully or aborted, the transmission complete status bit should be checked. This should be done after the transmit buffer status bit has been set to logic 1 or a transmit interrupt has been generated. It should be noted that a transmit interrupt is generated even if the message was aborted because the transmit buffer status bit changes to ‘released’. 6. If the transmission request was set to logic 1 in a previous command, it cannot be cancelled by setting the transmission request bit to logic 0. The requested transmission may be cancelled by setting the abort transmission bit to logic 1. 6.4.5 STATUS REGISTER (SR) The content of the status register reflects the status of the CAN controller. The status register appears to the CPU as a read only memory. Table 14 Bit interpretation of the status register (SR); CAN address 2 BIT SR.7 SYMBOL BS NAME Bus Status; note 1 VALUE 1 0 SR.6 ES Error Status; note 2 1 FUNCTION bus-off; the CAN controller is not involved in bus activities bus-on; the CAN controller is involved in bus activities error; at least one of the error counters has reached or exceeded the CPU warning limit defined by the Error Warning Limit Register (EWLR) ok; both error counters are below the warning limit transmit; the CAN controller is transmitting a message idle receive; the CAN controller is receiving a message idle complete; last requested transmission has been successfully completed incomplete; previously requested transmission is not yet completed released; the CPU may write a message into the transmit buffer locked; the CPU cannot access the transmit buffer; a message is either waiting for transmission or is in the process of being transmitted 0 SR.5 TS Transmit Status; note 3 1 0 SR.4 RS Receive Status; note 3 1 0 SR.3 TCS Transmission Complete Status; note 4 1 0 SR.2 TBS Transmit Buffer Status; note 5 1 0 2000 Jan 04 29 Philips Semiconductors Product specification Stand-alone CAN controller SJA1000 BIT SR.1 SYMBOL DOS NAME Data Overrun Status; note 6 VALUE 1 0 FUNCTION overrun; a message was lost because there was not enough space for that message in the RXFIFO absent; no data overrun has occurred since the last clear data overrun command was given full; one or more complete messages are available in the RXFIFO empty; no message is available SR.0 RBS Receive Buffer Status; note 7 1 0 Notes 1. When the transmit error counter exceeds the limit of 255, the bus status bit is set to logic 1 (bus-off), the CAN controller will set the reset mode bit to logic 1 (present) and an error warning interrupt is generated, if enabled. The transmit error counter is set to 127 and the receive error counter is cleared. It will stay in this mode until the CPU clears the reset mode bit. Once this is completed the CAN controller will wait the minimum protocol-defined time (128 occurrences of the bus-free signal) counting down the transmit error counter. After that the bus status bit is cleared (bus-on), the error status bit is set to logic 0 (ok), the error counters are reset and an error warning interrupt is generated, if enabled. Reading the TX error counter during this time gives information about the status of the bus-off recovery. 2. Errors detected during reception or transmission will effect the error counters according to the CAN 2.0B protocol specification. The error status bit is set when at least one of the error counters has reached or exceeded the CPU warning limit (EWLR). An error warning interrupt is generated, if enabled. The default value of EWLR after hardware reset is 96. 3. If both the receive status and the transmit status bits are logic 0 (idle) the CAN-bus is idle. If both bits are set the controller is waiting to become idle again. After a hardware reset 11 consecutive recessive bits have to be detected until the idle status is reached. After bus-off this will take 128 of 11 consecutive recessive bits. 4. The transmission complete status bit is set to logic 0 (incomplete) whenever the transmission request bit or the self reception request bit is set to logic 1. The transmission complete status bit will remain at logic 0 until a message is transmitted successfully. 5. If the CPU tries to write to the transmit buffer when the transmit buffer status bit is logic 0 (locked), the written byte will not be accepted and will be lost without this being indicated. 6. When a message that is to be received has passed the acceptance filter successfully, the CAN controller needs space in the RXFIFO to store the message descriptor and for each data byte which has been received. If there is not enough space to store the message, that message is dropped and the data overrun condition is indicated to the CPU at the moment this message becomes valid. If this message is not completed successfully (e.g. due to an error), no overrun condition is indicated. 7. After reading all messages within the RXFIFO and releasing their memory space with the command release receive buffer this bit is cleared. 2000 Jan 04 30 Philips Semiconductors Product specification Stand-alone CAN controller 6.4.6 INTERRUPT REGISTER (IR) SJA1000 The interrupt register allows the identification of an interrupt source. When one or more bits of this register are set, a CAN interrupt will be indicated to the CPU. After this register is read by the CPU all bits are reset except for the receive interrupt bit. The interrupt register appears to the CPU as a read only memory. Table 15 Bit interpretation of the interrupt register (IR); CAN address 3 BIT IR.7 SYMBOL BEI NAME Bus Error Interrupt VALUE 1 FUNCTION set; this bit is set when the CAN controller detects an error on the CAN-bus and the BEIE bit is set within the interrupt enable register reset set; this bit is set when the CAN controller lost the arbitration and becomes a receiver and the ALIE bit is set within the interrupt enable register reset set; this bit is set whenever the CAN controller has reached the error passive status (at least one error counter exceeds the protocol-defined level of 127) or if the CAN controller is in the error passive status and enters the error active status again and the EPIE bit is set within the interrupt enable register reset set; this bit is set when the CAN controller is sleeping and bus activity is detected and the WUIE bit is set within the interrupt enable register reset set; this bit is set on a ‘0-to-1’ transition of the data overrun status bit and the DOIE bit is set within the interrupt enable register reset set; this bit is set on every change (set and clear) of either the error status or bus status bits and the EIE bit is set within the interrupt enable register reset set; this bit is set whenever the transmit buffer status changes from ‘0-to-1’ (released) and the TIE bit is set within the interrupt enable register reset set; this bit is set while the receive FIFO is not empty and the RIE bit is set within the interrupt enable register reset; no more message is available within the RXFIFO 0 IR.6 ALI Arbitration Lost Interrupt 1 0 IR.5 EPI Error Passive Interrupt 1 0 IR.4 WUI Wake-Up Interrupt; note 1 1 0 IR.3 DOI Data Overrun Interrupt 1 0 IR.2 EI Error Warning Interrupt 1 0 IR.1 TI Transmit Interrupt 1 0 IR.0 RI Receive Interrupt; note 2 1 0 2000 Jan 04 31 Philips Semiconductors Product specification Stand-alone CAN controller Notes SJA1000 1. A wake-up interrupt is also generated, if the CPU tries to set the sleep bit while the CAN controller is involved in bus activities or a CAN interrupt is pending. 2. The behaviour of this bit is equivalent to that of the receive buffer status bit with the exception, that RI depends on the corresponding interrupt enable bit (RIE). So the receive interrupt bit is not cleared upon a read access to the interrupt register. Giving the command ‘release receive buffer’ will clear RI temporarily. If there is another message available within the FIFO after the release command, RI is set again. Otherwise RI remains cleared. 6.4.7 INTERRUPT ENABLE REGISTER (IER) The register allows to enable different types of interrupt sources which are indicated to the CPU. The interrupt enable register appears to the CPU as a read/write memory. Table 16 Bit interpretation of the interrupt enable register (IER); CAN address 4 BIT IER.7 SYMBOL BEIE NAME Bus Error Interrupt Enable Arbitration Lost Interrupt Enable Error Passive Interrupt Enable VALUE 1 0 IER.6 ALIE 1 0 IER.5 EPIE 1 FUNCTION enabled; if an bus error has been detected, the CAN controller requests the respective interrupt disabled enabled; if the CAN controller has lost arbitration, the respective interrupt is requested disabled enabled; if the error status of the CAN controller changes from error active to error passive or vice versa, the respective interrupt is requested disabled enabled; if the sleeping CAN controller wakes up, the respective interrupt is requested disabled enabled; if the data overrun status bit is set (see status register; Table 14), the CAN controller requests the respective interrupt disabled enabled; if the error or bus status change (see status register; Table 14), the CAN controller requests the respective interrupt disabled enabled; when a message has been successfully transmitted or the transmit buffer is accessible again (e.g. after an abort transmission command), the CAN controller requests the respective interrupt disabled enabled; when the receive buffer status is ‘full’ the CAN controller requests the respective interrupt disabled 0 IER.4 WUIE Wake-Up Interrupt Enable Data Overrun Interrupt Enable 1 0 IER.3 DOIE 1 0 IER.2 EIE Error Warning Interrupt Enable 1 0 IER.1 TIE Transmit Interrupt Enable 1 0 IER.0 RIE Receive Interrupt Enable; note 1 1 0 2000 Jan 04 32 Philips Semiconductors Product specification Stand-alone CAN controller Note SJA1000 1. The receive interrupt enable bit has direct influence to the receive interrupt bit and the external interrupt output INT. If RIE is cleared, the external INT pin will become HIGH immediately, if there is no other interrupt pending. 6.4.8 ARBITRATION LOST CAPTURE REGISTER (ALC) This register contains information about the bit position of losing arbitration. The arbitration lost capture register appears to the CPU as a read only memory. Reserved bits are read as logic 0. Table 17 Bit interpretation of the arbitration lost capture register (ALC); CAN address 11 BIT ALC.7 to ALC.5 ALC.4 ALC.3 ALC.2 ALC.1 ALC.0 SYMBOL − BITNO4 BITNO3 BITNO2 BITNO1 BITNO0 NAME reserved bit number 4 bit number 3 bit number 2 bit number 1 bit number 0 VALUE For value and function see Table 18 FUNCTION On arbitration lost, the corresponding arbitration lost interrupt is forced, if enabled. At the same time, the current bit position of the bit stream processor is captured into the arbitration lost capture register. The content within this register is fixed until the users software has read out its contents once. The capture mechanism is then activated again. The corresponding interrupt flag located in the interrupt register is cleared during the read access to the interrupt register. A new arbitration lost interrupt is not possible until the arbitration lost capture register is read out once. handbook, full pagewidth start of frame standard frame and extended frame messages ID.28 ID.27 ID.26 ID.25 ID.24 ID.23 ID.22 ID.21 ID.20 ID.19 ID.18 SRTR IDE 00 01 02 03 04 05 06 07 08 09 10 11 12 extended frame messages ID.17 ID.16 ID.15 ID.14 ID.13 ID.12 ID.11 ID.10 ID.9 ID.8 ID.7 ID.6 ID.5 ID.4 ID.3 ID.2 ID.1 ID.0 RTR 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 MGK619 Fig.5 Arbitration lost bit number interpretation. 2000 Jan 04 33 Philips Semiconductors Product specification Stand-alone CAN controller SJA1000 handbook, full pagewidth start of frame arbitration lost TX RX ID.28 ID.27 ID.26 ID.25 ID.24 ID.23 ID.22 ID.21 ID.20 ID.19 ID.18 SRTR IDE MGK620 Fig.6 Example of arbitration lost bit number interpretation; result: ALC = 08. 2000 Jan 04 34 Philips Semiconductors Product specification Stand-alone CAN controller Table 18 Function of bits 4 to 0 of the arbitration lost capture register BITS(1) ALC.4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Notes 1. Binary coded frame bit number where arbitration was lost. 2. Bit RTR for standard frame messages. 3. Extended frame messages only. ALC.3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 ALC.2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ALC.1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ALC.0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DECIMAL VALUE 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 FUNCTION SJA1000 arbitration lost in bit 1 of identifier arbitration lost in bit 2 of identifier arbitration lost in bit 3 of identifier arbitration lost in bit 4 of identifier arbitration lost in bit 5 of identifier arbitration lost in bit 6 of identifier arbitration lost in bit 7 of identifier arbitration lost in bit 8 of identifier arbitration lost in bit 9 of identifier arbitration lost in bit 10 of identifier arbitration lost in bit 11 of identifier arbitration lost in bit SRTR; note 2 arbitration lost in bit IDE arbitration lost in bit 12 of identifier; note 3 arbitration lost in bit 13 of identifier; note 3 arbitration lost in bit 14 of identifier; note 3 arbitration lost in bit 15 of identifier; note 3 arbitration lost in bit 16 of identifier; note 3 arbitration lost in bit 17 of identifier; note 3 arbitration lost in bit 18 of identifier; note 3 arbitration lost in bit 19 of identifier; note 3 arbitration lost in bit 20 of identifier; note 3 arbitration lost in bit 21 of identifier; note 3 arbitration lost in bit 22 of identifier; note 3 arbitration lost in bit 23 of identifier; note 3 arbitration lost in bit 24 of identifier; note 3 arbitration lost in bit 25 of identifier; note 3 arbitration lost in bit 26 of identifier; note 3 arbitration lost in bit 27 of identifier; note 3 arbitration lost in bit 28 of identifier; note 3 arbitration lost in bit 29 of identifier; note 3 arbitration lost in bit RTR; note 3 2000 Jan 04 35 Philips Semiconductors Product specification Stand-alone CAN controller 6.4.9 ERROR CODE CAPTURE REGISTER (ECC) SJA1000 This register contains information about the type and location of errors on the bus. The error code capture register appears to the CPU as a read only memory. Table 19 Bit interpretation of the error code capture register (ECC); CAN address 12 BIT ECC.7(1) ECC.6(1) ECC.5 ECC.4(2) ECC.3(2) ECC.2(2) ECC.1(2) ECC.0(2) Notes 1. For bit interpretation of bits ECC.7 and ECC.6 see Table 20. 2. For bit interpretation of bits ECC.4 to ECC.0 see Table 21. Table 20 Bit interpretation of bits ECC.7 and ECC.6 BIT ECC.7 0 0 1 1 BIT ECC.6 0 1 0 1 bit error form error stuff error other type of error FUNCTION SYMBOL ERRC1 ERRC0 DIR SEG4 SEG3 SEG2 SEG1 SEG0 NAME Error Code 1 Error Code 0 Direction Segment 4 Segment 3 Segment 2 Segment 1 Segment 0 VALUE − − 1 0 − − − − − − − RX; error occurred during reception TX; error occurred during transmission − − − − − FUNCTION 2000 Jan 04 36 Philips Semiconductors Product specification Stand-alone CAN controller Table 21 Bit interpretation of bits ECC.4 to ECC.0; note 1 BIT ECC.4 BIT ECC.3 BIT ECC.2 BIT ECC.1 BIT ECC.0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 Note 1. Bit settings reflect the current frame segment to distinguish between different error events. If a bus error occurs, the corresponding bus error interrupt is always forced, if enabled. At the same time, the current position of the bit stream processor is captured into the error code capture register. The content within this register is fixed until the users software has read out its content once. The capture mechanism is then activated again. The corresponding interrupt flag located in the interrupt register is cleared during the read access to the interrupt register. A new bus error interrupt is not possible until the capture register is read out once. 6.4.10 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 0 0 1 1 1 0 0 0 1 1 0 0 0 1 1 1 0 1 1 1 0 1 0 0 0 1 1 1 0 0 1 1 1 0 0 0 1 1 0 0 1 0 1 1 0 start of frame ID.28 to ID.21 ID.20 to ID.18 bit SRTR bit IDE ID.17 to ID.13 ID.12 to ID.5 ID.4 to ID.0 bit RTR reserved bit 1 reserved bit 0 data length code data field CRC sequence CRC delimiter acknowledge slot acknowledge delimiter end of frame intermission active error flag passive error flag tolerate dominant bits error delimiter overload flag FUNCTION SJA1000 ERROR WARNING LIMIT REGISTER (EWLR) The error warning limit can be defined within this register. The default value (after hardware reset) is 96. In reset mode this register appears to the CPU as a read/write memory. In operating mode it is read only. Note, that a content change of the EWLR is only possible, if the reset mode was entered previously. An error status change (see status register; Table 14) and an error warning interrupt forced by the new register content will not occur until the reset mode is cancelled again. 2000 Jan 04 37 Philips Semiconductors Product specification Stand-alone CAN controller Table 22 Bit interpretation of the error warning limit register (EWLR); CAN address 13 BIT 7 EWL.7 6.4.11 BIT 6 EWL.6 BIT 5 EWL.5 BIT 4 EWL.4 BIT 3 EWL.3 BIT 2 EWL.2 BIT 1 EWL.1 SJA1000 BIT 0 EWL.0 RX ERROR COUNTER REGISTER (RXERR) The RX error counter register reflects the current value of the receive error counter. After a hardware reset this register is initialized to logic 0. In operating mode this register appears to the CPU as a read only memory. A write access to this register is possible only in reset mode. If a bus-off event occurs, the RX error counter is initialized to logic 0. The time bus-off is valid, writing to this register has no effect. Note, that a CPU-forced content change of the RX error counter is only possible, if the reset mode was entered previously. An error status change (see status register; Table 14), an error warning or an error passive interrupt forced by the new register content will not occur, until the reset mode is cancelled again. Table 23 Bit interpretation of the RX error counter register (RXERR); CAN address 14 BIT 7 RXERR.7 6.4.12 BIT 6 RXERR.6 BIT 5 RXERR.5 BIT 4 RXERR.4 BIT 3 RXERR.3 BIT 2 RXERR.2 BIT 1 RXERR.1 BIT 0 RXERR.0 TX ERROR COUNTER REGISTER (TXERR) The TX error counter register reflects the current value of the transmit error counter. In operating mode this register appears to the CPU as a read only memory. A write access to this register is possible only in reset mode. After a hardware reset this register is initialized to logic 0. If a bus-off event occurs, the TX error counter is initialized to 127 to count the minimum protocol-defined time (128 occurrences of the bus-free signal). Reading the TX error counter during this time gives information about the status of the bus-off recovery. If bus-off is active, a write access to TXERR in the range from 0 to 254 clears the bus-off flag and the controller will wait for one occurrence of 11 consecutive recessive bits (bus-free) after the reset mode has been cleared. Table 24 Bit interpretation of the TX error counter register (TXERR); CAN address 15 BIT 7 TXERR.7 BIT 6 TXERR.6 BIT 5 TXERR.5 BIT 4 TXERR.4 BIT 3 TXERR.3 BIT 2 TXERR.2 BIT 1 TXERR.1 BIT 0 TXERR.0 Writing 255 to TXERR allows to initiate a CPU-driven bus-off event. It should be noted that a CPU-forced content change of the TX error counter is only possible, if the reset mode was entered previously. An error or bus status change (see status register; Table 14), an error warning or an error passive interrupt forced by the new register content will not occur until the reset mode is cancelled again. After leaving the reset mode, the new TX counter content is interpreted and the bus-off event is performed in the same way, as if it was forced by a bus error event. That means, that the reset mode is entered again, the TX error counter is initialized to 127, the RX counter is cleared and all concerned status and interrupt register bits are set. Clearing of reset mode now will perform the protocol-defined bus-off recovery sequence (waiting for 128 occurrences of the bus-free signal). If the reset mode is entered again before the end of bus-off recovery (TXERR > 0), bus-off keeps active and TXERR is frozen. 2000 Jan 04 38 Philips Semiconductors Product specification Stand-alone CAN controller 6.4.13 TRANSMIT BUFFER SJA1000 The transmit buffer has a length of 13 bytes and is located in the CAN address range from 16 to 28. Note, that a direct access to the transmit buffer RAM is possible using the CAN address space from 96 to 108. This RAM area is reserved for the transmit buffer. The three following bytes may be used for general purposes (CAN address 109, 110 and 111). The global layout of the transmit buffer is shown in Fig.7. One has to distinguish between the Standard Frame Format (SFF) and the Extended Frame Format (EFF) configuration. The transmit buffer allows the definition of one transmit message with up to eight data bytes. 6.4.13.1 Transmit buffer layout The transmit buffer layout is subdivided into descriptor and data fields where the first byte of the descriptor field is the frame information byte (frame information). It describes the frame format (SFF or EFF), remote or data frame and the data length. Two identifier bytes for SFF or four bytes for EFF messages follow. The data field contains up to eight data bytes. handbook, full pagewidth CAN address 16 17 18 19 20 21 22 23 24 25 26 27 28 TX frame information TX identifier 1 TX identifier 2 TX data byte 1 TX data byte 2 TX data byte 3 TX data byte 4 TX data byte 5 TX data byte 6 TX data byte 7 TX data byte 8 unused unused CAN address 16 17 18 19 20 21 22 23 24 25 26 27 28 TX frame information TX identifier 1 TX identifier 2 TX identifier 3 TX identifier 4 TX data byte 1 TX data byte 2 TX data byte 3 TX data byte 4 TX data byte 5 TX data byte 6 TX data byte 7 TX data byte 8 MGK621 a. Standard frame format. b. Extended frame format. Fig.7 Transmit buffer layout for standard and extended frame format configurations. 6.4.13.2 Descriptor field of the transmit buffer The bit layout of the transmit buffer is represented in Tables 25 to 27 for SFF and Tables 28 to 32 for EFF. The given configuration is chosen to be compatible with the receive buffer layout (see Section 6.4.14.1). 2000 Jan 04 39 Philips Semiconductors Product specification Stand-alone CAN controller Table 25 TX frame information (SFF); CAN address 16 BIT 7 FF(1) Notes 1. Frame format. 2. Remote transmission request. BIT 6 RTR(2) BIT 5 X(3) BIT 4 X(3) BIT 3 DLC.3(4) BIT 2 DLC.2(4) BIT 1 DLC.1(4) SJA1000 BIT 0 DLC.0(4) 3. Don’t care; recommended to be compatible to receive buffer (0) in case of using the self reception facility (self test). 4. Data length code bit. Table 26 TX identifier 1 (SFF); CAN address 17; note 1 BIT 7 ID.28 Note 1. ID.X means identifier bit X. Table 27 TX identifier 2 (SFF); CAN address 18; note 1 BIT 7 ID.20 Notes 1. ID.X means identifier bit X. 2. Don’t care; recommended to be compatible to receive buffer (RTR) in case of using the self reception facility (self test). 3. Don’t care; recommended to be compatible to receive buffer (0) in case of using the self reception facility (self test). Table 28 TX frame information (EFF); CAN address 16 BIT 7 FF(1) Notes 1. Frame format. 2. Remote transmission request. 3. Don’t care; recommended to be compatible to receive buffer (0) in case of using the self reception facility (self test). 4. Data length code bit. Table 29 TX identifier 1 (EFF); CAN address 17; note 1 BIT 7 ID.28 Note 1. ID.X means identifier bit X. BIT 6 ID.27 BIT 5 ID.26 BIT 4 ID.25 BIT 3 ID.24 BIT 2 ID.23 BIT 1 ID.22 BIT 0 ID.21 BIT 6 RTR(2) BIT 5 X(3) BIT 4 X(3) BIT 3 DLC.3(4) BIT 2 DLC.2(4) BIT 1 DLC.1(4) BIT 0 DLC.0(4) BIT 6 ID.19 BIT 5 ID.18 BIT 4 X(2) BIT 3 X(3) BIT 2 X(3) BIT 1 X(3) BIT 0 X(3) BIT 6 ID.27 BIT 5 ID.26 BIT 4 ID.25 BIT 3 ID.24 BIT 2 ID.23 BIT 1 ID.22 BIT 0 ID.21 2000 Jan 04 40 Philips Semiconductors Product specification Stand-alone CAN controller Table 30 TX identifier 2 (EFF); CAN address 18; note 1 BIT 7 ID.20 Note 1. ID.X means identifier bit X. Table 31 TX identifier 3 (EFF); CAN address 19; note 1 BIT 7 ID.12 Note 1. ID.X means identifier bit X. Table 32 TX identifier 4 (EFF); CAN address 20; note 1 BIT 7 ID.4 Notes 1. ID.X means identifier bit X. BIT 6 ID.3 BIT 5 ID.2 BIT 4 ID.1 BIT 3 ID.0 BIT 2 X(2) BIT 1 X(3) BIT 6 ID.11 BIT 5 ID.10 BIT 4 ID.9 BIT 3 ID.8 BIT 2 ID.7 BIT 1 ID.6 BIT 6 ID.19 BIT 5 ID.18 BIT 4 ID.17 BIT 3 ID.16 BIT 2 ID.15 BIT 1 ID.14 SJA1000 BIT 0 ID.13 BIT 0 ID.5 BIT 0 X(3) 2. Don’t care; recommended to be compatible to receive buffer (RTR) in case of using the self reception facility (self test). 3. Don’t care; recommended to be compatible to receive buffer (0) in case of using the self reception facility (self test). Table 33 Frame Format (FF) and Remote Transmission Request (RTR) bits BIT FF RTR VALUE 1 0 1 0 FUNCTION EFF; extended frame format will be transmitted by the CAN controller SFF; standard frame format will be transmitted by the CAN controller remote; remote frame will be transmitted by the CAN controller data; data frame will be transmitted by the CAN controller For reasons of compatibility no data length code >8 should be used. If a value >8 is selected, 8 bytes are transmitted in the data frame with the Data Length Code specified in DLC. 6.4.13.3 Data Length Code (DLC) The number of bytes in the data field of a message is coded by the data length code. At the start of a remote frame transmission the data length code is not considered due to the RTR bit being logic 1 (remote). This forces the number of transmitted/received data bytes to be 0. Nevertheless, the data length code must be specified correctly to avoid bus errors, if two CAN controllers start a remote frame transmission with the same identifier simultaneously. The range of the data byte count is 0 to 8 bytes and is coded as follows: DataByteCount = 8 × DLC.3 + 4 × DLC.2 + 2 × DLC.1 + DLC.0 6.4.13.4 Identifier (ID) In Standard Frame Format (SFF) the identifier consists of 11 bits (ID.28 to ID.18) and in Extended Frame Format (EFF) messages the identifier consists of 29 bits (ID.28 to ID.0). ID.28 is the most significant bit, which is transmitted first on the bus during the arbitration process. The identifier acts as the message’s name, used in a receiver for acceptance filtering, and also determines the bus access priority during the arbitration process. 2000 Jan 04 41 Philips Semiconductors Product specification Stand-alone CAN controller The lower the binary value of the identifier the higher the priority. This is due to the larger number of leading dominant bits during arbitration. 6.4.14 RECEIVE BUFFER SJA1000 6.4.13.5 Data field The number of transferred data bytes is defined by the data length code. The first bit transmitted is the most significant bit of data byte 1 at CAN address 19 (SFF) or CAN address 21 (EFF). The global layout of the receive buffer is very similar to the transmit buffer described in the previous section. The receive buffer is the accessible part of the RXFIFO and is located in the range between CAN address 16 and 28. Each message is subdivided into a descriptor and a data field. handbook, full pagewidth 64-byte FIFO message 3 28 27 26 25 24 23 22 21 20 19 18 17 16 message 2 release receive buffer command incoming messages message 1 receive buffer window CAN address MGK622 Message 1 is now available in the receive buffer. Fig.8 Example of the message storage within the RXFIFO. 6.4.14.1 Descriptor field of the receive buffer The bit layout of the receive buffer is represented in Tables 34 to 36 for SFF and Tables 37 to 41 for EFF. The given configuration is chosen to be compatible with the transmit buffer layout (see Section 6.4.13.2). Table 34 RX frame information (SFF); CAN address 16 BIT 7 FF(1) Notes 1. Frame format. 2. Remote transmission request. 3. Data length code bit. BIT 6 RTR(2) BIT 5 0 BIT 4 0 BIT 3 DLC.3(3) BIT 2 DLC.2(3) BIT 1 DLC.1(3) BIT 0 DLC.0(3) 2000 Jan 04 42 Philips Semiconductors Product specification Stand-alone CAN controller Table 35 RX identifier 1 (SFF); CAN address 17; note 1 BIT 7 ID.28 Note 1. ID.X means identifier bit X. Table 36 RX identifier 2 (SFF); CAN address 18; note 1 BIT 7 ID.20 Notes 1. ID.X means identifier bit X. 2. Remote transmission request. Table 37 RX frame information (EFF); CAN address 16 BIT 7 FF(1) Notes 1. Frame format. 2. Remote transmission request. 3. Data length code bit. Table 38 RX identifier 1 (EFF); CAN address 17; note 1 BIT 7 ID.28 Note 1. ID.X means identifier bit X. Table 39 RX identifier 2 (EFF); CAN address 18; note 1 BIT 7 ID.20 Note 1. ID.X means identifier bit X. Table 40 RX identifier 3 (EFF); CAN address 19; note 1 BIT 7 ID.12 Note 1. ID.X means identifier bit X. BIT 6 ID.11 BIT 5 ID.10 BIT 4 ID.9 BIT 3 ID.8 BIT 2 ID.7 BIT 1 ID.6 BIT 6 ID.19 BIT 5 ID.18 BIT 4 ID.17 BIT 3 ID.16 BIT 2 ID.15 BIT 1 ID.14 BIT 6 ID.27 BIT 5 ID.26 BIT 4 ID.25 BIT 3 ID.24 BIT 2 ID.23 BIT 1 ID.22 BIT 6 RTR(2) BIT 5 0 BIT 4 0 BIT 3 DLC.3(3) BIT 2 DLC.2(3) BIT 1 DLC.1(3) BIT 6 ID.19 BIT 5 ID.18 BIT 4 RTR(2) BIT 3 0 BIT 2 0 BIT 1 0 BIT 6 ID.27 BIT 5 ID.26 BIT 4 ID.25 BIT 3 ID.24 BIT 2 ID.23 BIT 1 ID.22 SJA1000 BIT 0 ID.21 BIT 0 0 BIT 0 DLC.0(3) BIT 0 ID.21 BIT 0 ID.13 BIT 0 ID.5 2000 Jan 04 43 Philips Semiconductors Product specification Stand-alone CAN controller Table 41 RX identifier 4 (EFF); can address 20; note 1 BIT 7 ID.4 Notes 1. ID.X means identifier bit X. 2. Remote transmission request. Remark: the received data length code located in the frame information byte represents the real sent data length code, which may be greater than 8 (depends on sender). Nevertheless the maximum number of received data bytes is 8. This should be taken into account by reading a message from the receive buffer. As described in Fig.8 the RXFIFO has space for 64 message bytes in total. It depends on the data length how many messages can fit in it at one time. If there is not enough space for a new message within the RXFIFO, the CAN controller generates a data overrun condition the moment this message becomes valid and the acceptance test was positive. A message which is partly written into the RXFIFO, when the data overrun situation occurs, is deleted. This situation is indicated to the CPU via the status register and the data overrun interrupt, if enabled. 6.4.15 ACCEPTANCE FILTER BIT 6 ID.3 BIT 5 ID.2 BIT 4 ID.1 BIT 3 ID.0 BIT 2 RTR(2) BIT 1 0 SJA1000 BIT 0 0 6.4.15.1 Single filter configuration In this filter configuration one long filter (4-bytes) could be defined. The bit correspondences between the filter bytes and the message bytes depend on the currently received frame format. Standard frame: if a standard frame format message is received, the complete identifier including the RTR bit and the first two data bytes are used for acceptance filtering. Messages may also be accepted if there are no data bytes existing due to a set RTR bit or if there is none or only one data byte because of the corresponding data length code. For a successful reception of a message, all single bit comparisons have to signal acceptance. Note, that the 4 least significant bits of AMR1 and ACR1 are not used. In order to be compatible with future products these bits should be programmed to be ‘don’t care’ by setting AMR1.3, AMR1.2, AMR1.1 and AMR1.0 to logic 1. With the help of the acceptance filter the CAN controller is able to allow passing of received messages to the RXFIFO only when the identifier bits of the received message are equal to the predefined ones within the acceptance filter registers. The acceptance filter is defined by the Acceptance Code Registers (ACRn) and the Acceptance Mask Registers (AMRn). The bit patterns of messages to be received are defined within the acceptance code registers. The corresponding acceptance mask registers allow to define certain bit positions to be ‘don’t care’. Two different filter modes are selectable within the mode register (MOD.3, AFM; see Section 6.4.3): • Single filter mode (bit AFM is logic 1) • Dual filter mode (bit AFM is logic 0). 2000 Jan 04 44 Philips Semiconductors Product specification Stand-alone CAN controller SJA1000 MSB handbook, full pagewidth 7 6 5 4 3 2 1 LSB MSB 0 7 6 5 4 3 2 1 LSB MSB 0 7 6 5 4 3 2 1 LSB MSB 0 7 6 5 4 3 2 1 LSB 0 CAN ADDRESS 16; ACR0 CAN ADDRESS 17; ACR1 CAN ADDRESS 18; ACR2 CAN ADDRESS 19; ACR3 unused CAN ADDRESS 20; AMR0 7 6 5 4 3 2 1 0 CAN ADDRESS 21; AMR1 7 6 5 4 3 2 1 0 CAN ADDRESS 22; AMR2 7 6 5 4 3 2 1 0 CAN ADDRESS 23; AMR3 7 6 5 4 3 2 1 0 unused DB1.6 DB1.5 DB1.4 DB1.3 DB1.2 DB1.1 DB1.0 DB2.7 DB2.6 DB2.5 DB2.4 DB2.3 DB2.2 DB2.1 (1) DB1.7 ACR = Acceptance Code Register message bit acceptance code bit acceptance mask bit =1 1 & AMR = Acceptance Mask Register logic 1 = accepted logic 0 = not accepted MGK624 DBX.Y means data byte X, bit Y. Fig.9 Single filter configuration, receiving standard frame messages. Extended frame: if an extended frame format message is received, the complete identifier including the RTR bit is used for acceptance filtering. For a successful reception of a message, all single bit comparisons have to signal acceptance. It should be noted that the 2 least significant bits of AMR3 and ACR3 are not used. In order to be compatible with future products these bits should be programmed to be ‘don’t care’ by setting AMR3.1 and AMR3.0 to logic 1. 2000 Jan 04 45 DB2.0 ID.28 ID.27 ID.26 ID.25 ID.24 ID.23 ID.22 ID.21 ID.20 ID.19 ID.18 RTR Philips Semiconductors Product specification Stand-alone CAN controller SJA1000 MSB handbook, full pagewidth 7 6 5 4 3 2 1 LSB MSB 0 7 6 5 4 3 2 1 LSB MSB 0 7 6 5 4 3 2 1 LSB MSB 0 7 6 5 4 3 2 1 LSB 0 CAN ADDRESS 16; ACR0 CAN ADDRESS 17; ACR1 CAN ADDRESS 18; ACR2 CAN ADDRESS 19; ACR3 unused CAN ADDRESS 20; AMR0 7 6 5 4 3 2 1 0 CAN ADDRESS 21; AMR1 7 6 5 4 3 2 1 0 CAN ADDRESS 22; AMR2 7 6 5 4 3 2 1 0 CAN ADDRESS 23; AMR3 7 6 5 4 3 2 1 0 unused ID.28 ID.27 ID.26 ID.25 ID.24 ID.23 ID.22 ID.21 ID.20 ID.19 ID.18 ID.17 ID.16 ID.15 ID.14 ID.13 ID.12 ID.10 ID.11 RTR ID.9 ID.8 ID.7 ID.6 ID.5 ID.4 ID.3 ID.2 ID.1 ID.0 ACR = Acceptance Code Register message bit acceptance code bit acceptance mask bit =1 1 & AMR = Acceptance Mask Register logic 1 = accepted logic 0 = not accepted MGK625 Fig.10 Single filter configuration, receiving extended frame messages. 6.4.15.2 Dual filter configuration In this filter configuration two short filters can be defined. A received message is compared with both filters to decide, whether this message should be copied into the receive buffer or not. If at least one of the filters signals an acceptance, the received message becomes valid. The bit correspondences between the filter bytes and the message bytes depends on the currently received frame format. Standard frame: if a standard frame message is received, the two defined filters are looking different. The first filter compares the complete standard identifier including the RTR bit and the first data byte of the message. The second filter just compares the complete standard identifier including the RTR bit. For a successful reception of a message, all single bit comparisons of at least one complete filter have to signal acceptance. In case of a set RTR bit or a data length code of logic 0 no data byte is existing. Nevertheless a message may pass filter 1, if the first part up to the RTR bit signals acceptance. If no data byte filtering is required for filter 1, the four least significant bits of AMR1 and AMR3 have to be set to logic 1 (don’t care). Then both filters are working identically using the standard identifier range including the RTR bit. 2000 Jan 04 46 Philips Semiconductors Product specification Stand-alone CAN controller SJA1000 handbook, full pagewidth MSB 7 filter 1 6 5 4 3 2 1 LSB 0 MSB CA 17; ACR1 7 6 54 3 2 LSB CA 17; ACR1 10 3 2 LSB CA 19; ACR3 10 CAN ADDRESS 16; ACR0 CAN ADDRESS 20; AMR0 7 6 5 4 3 2 1 0 CA 21; AMR1 7 6 5 4 CA 21; AMR1 3 2 1 0 CA 23; AMR3 3 2 1 0 DB1.7 DB1.6 DB1.5 DB1.4 DB1.3 DB1.2 DB1.1 message (1) CAN ADDRESS 22; AMR2 7 filter 2 CAN ADDRESS 18; ACR2 7 6 5 4 3 2 1 0 LSB MSB 6 5 4 3 2 1 0 CA 23; AMR3 7 6 5 4 CA = CAN Address ACR = Acceptance Code Register AMR = Acceptance Mask Register CA 19; ACR3 7 6 5 4 MSB & acceptance mask bit filter 1 acceptance code bit 1 =1 1 logic 1 = accepted logic 0 = not accepted message bit =1 acceptance code bit filter 2 acceptance mask bit 1 & MGK626 DBX.Y = data byte X, bit Y. Fig.11 Dual filter configuration, receiving standard frame messages. 2000 Jan 04 47 DB1.0 ID.28 ID.27 ID.26 ID.25 ID.24 ID.23 ID.22 ID.21 ID.20 ID.19 ID.18 RTR Philips Semiconductors Product specification Stand-alone CAN controller SJA1000 Extended frame: if an extended frame message is received, the two defined filters are looking identically. Both filters are comparing the first two bytes of the extended identifier range only. For a successful reception of a message, all single bit comparisons of at least one complete filter have to indicate acceptance. handbook, full pagewidth MSB 7 filter 1 6 5 4 3 2 1 LSB 0 MSB 7 6 5 4 3 2 1 LSB 0 CAN ADDRESS 16; ACR0 CAN ADDRESS 17; ACR1 CAN ADDRESS 20; AMR0 7 6 5 4 3 2 1 0 CAN ADDRESS 21; AMR1 7 6 5 4 3 2 1 0 ID.28 ID.27 ID.26 ID.25 ID.24 ID.23 ID.22 ID.21 ID.20 ID.19 ID.18 ID.17 ID.16 ID.15 2 ID.14 1 message CAN ADDRESS 22; AMR2 7 filter 2 CAN ADDRESS 18; ACR2 7 6 5 4 3 2 1 0 LSB MSB 6 5 4 3 2 1 0 CAN ADDRESS 23; AMR3 7 6 5 4 3 0 ID.13 CAN ADDRESS 19; ACR3 7 6 5 4 3 2 1 0 LSB MSB ACR = Acceptance Code Register AMR = Acceptance Mask Register & acceptance mask bit filter 1 acceptance code bit 1 =1 1 logic 1 = accepted logic 0 = not accepted message bit =1 acceptance code bit filter 2 acceptance mask bit 1 & MGK627 Fig.12 Dual filter configuration, receiving extended frame messages. 2000 Jan 04 48 Philips Semiconductors Product specification Stand-alone CAN controller 6.4.16 RX MESSAGE COUNTER (RMC) SJA1000 The RMC register (CAN address 29) reflects the number of messages available within the RXFIFO. The value is incremented with each receive event and decremented by the release receive buffer command. After any reset event, this register is cleared. Table 42 Bit interpretation of the RX message counter (RMC); CAN address 29 BIT 7 (0)(1) Note 1. This bit cannot be written. During read-out of this register always a zero is given. 6.4.17 RX BUFFER START ADDRESS REGISTER (RBSA) If a message exceeds RAM address 63, it continues at RAM address 0. The release receive buffer command is always given while there is at least one more message available within the FIFO. RBSA is updated to the beginning of the next message. On hardware reset, this pointer is initialized to ‘00H’. Upon a software reset (setting of reset mode) this pointer keeps its old value, but the FIFO is cleared; this means that the RAM contents are not changed, but the next received (or transmitted) message will override the currently visible message within the receive buffer window. The RX buffer start address register appears to the CPU as a read only memory in operating mode and as read/write memory in reset mode. It should be noted that a write access to RBSA takes effect first after the next positive edge of the internal clock frequency, which is half of the external oscillator frequency. BIT 6 (0)(1) BIT 5 (0)(1) BIT 4 RMC.4 BIT 3 RMC.3 BIT 2 RMC.2 BIT 1 RMC.1 BIT 0 RMC.0 The RBSA register (CAN address 30) reflects the currently valid internal RAM address, where the first byte of the received message, which is mapped to the receive buffer window, is stored. With the help of this information it is possible to interpret the internal RAM contents. The internal RAM address area begins at CAN address 32 and may be accessed by the CPU for reading and writing (writing in reset mode only). Example: if RBSA is set to 24 (decimal), the current message visible in the receive buffer window (CAN address 16 to 28) is stored within the internal RAM beginning at RAM address 24. Because the RAM is also mapped directly to the CAN address space beginning at CAN address 32 (equal to RAM address 0) this message may also be accessed using CAN address 56 and the following bytes (CAN address = RBSA + 32 > 24 + 32 = 56). Table 43 Bit interpretation of the RX buffer start address register (RBSA); CAN address 30 BIT 7 (0)(1) Note 1. This bit cannot be written. During read-out of this register always a zero is given. BIT 6 (0)(1) BIT 5 RBSA.5 BIT 4 RBSA.4 BIT 3 RBSA.3 BIT 2 RBSA.2 BIT 1 RBSA.1 BIT 0 RBSA.0 2000 Jan 04 49 Philips Semiconductors Product specification Stand-alone CAN controller 6.5 6.5.1 Common registers BUS TIMING REGISTER 0 (BTR0) SJA1000 The contents of the bus timing register 0 defines the values of the Baud Rate Prescaler (BRP) and the Synchronization Jump Width (SJW). This register can be accessed (read/write) if the reset mode is active. In operating mode this register is read only, if the PeliCAN mode is selected. In BasicCAN mode a ‘FFH’ is reflected. Table 44 Bit interpretation of bus timing register 0 (BTR0); CAN address 6 BIT 7 SJW.1 BIT 6 SJW.0 BIT 5 BRP.5 BIT 4 BRP.4 BIT 3 BRP.3 BIT 2 BRP.2 BIT 1 BRP.1 BIT 0 BRP.0 6.5.1.1 Baud Rate Prescaler (BRP) The period of the CAN system clock tscl is programmable and determines the individual bit timing. The CAN system clock is calculated using the following equation: tscl = 2 × tCLK × (32 × BRP.5 + 16 × BRP.4 + 8 × BRP.3 + 4 × BRP.2 + 2 × BRP.1 + BRP.0 + 1) 1 where tCLK = time period of the XTAL frequency = -----------f XTAL 6.5.1.2 Synchronization Jump Width (SJW) To compensate for phase shifts between clock oscillators of different bus controllers, any bus controller must re-synchronize on any relevant signal edge of the current transmission. The synchronization jump width defines the maximum number of clock cycles a bit period may be shortened or lengthened by one re-synchronization: tSJW = tscl × (2 × SJW.1 + SJW.0 + 1) 6.5.2 BUS TIMING REGISTER 1 (BTR1) The contents of bus timing register 1 defines the length of the bit period, the location of the sample point and the number of samples to be taken at each sample point. This register can be accessed (read/write) if the reset mode is active. In operating mode, this register is read only, if the PeliCAN mode is selected. In BasicCAN mode a ‘FFH’ is reflected. Table 45 Bit interpretation of bus timing register 1 (BTR1); CAN address 7 BIT 7 SAM BIT 6 TSEG2.2 BIT 5 TSEG2.1 BIT 4 TSEG2.0 BIT 3 TSEG1.3 BIT 2 TSEG1.2 BIT 1 TSEG1.1 BIT 0 TSEG1.0 6.5.2.1 BIT SAM Sampling (SAM) VALUE 1 0 FUNCTION triple; the bus is sampled three times; recommended for low/medium speed buses (class A and B) where filtering spikes on the bus line is beneficial single; the bus is sampled once; recommended for high speed buses (SAE class C) 2000 Jan 04 50 Philips Semiconductors Product specification Stand-alone CAN controller 6.5.2.2 Time Segment 1 (TSEG1) and Time Segment 2 (TSEG2) SJA1000 TSEG1 and TSEG2 determine the number of clock cycles per bit period and the location of the sample point, where: tSYNCSEG = 1 × tscl tTSEG1 = tscl × (8 × TSEG1.3 + 4 × TSEG1.2 + 2 × TSEG1.1 + TSEG1.0 + 1) tTSEG2 = tscl × (4 × TSEG2.2 + 2 × TSEG2.1 + TSEG2.0 + 1) handbook, full pagewidth XTAL tCLK tscl CAN tTSEG1 Baud Rate Prescaler (BRP) tSYNCSEG tTSEG2 nominal bit time SYNC SEG TSEG1 TSEG2 SYNC SEG TSEG1 MGK628 sample point(s) Possible values are BRP = 000001, TSEG1 = 0101 and TSEG2 = 010. Fig.13 General structure of a bit period. 6.5.3 OUTPUT CONTROL REGISTER (OCR) The output control register allows the set-up of different output driver configurations under software control. This register may be accessed (read/write) if the reset mode is active. In operating mode, this register is read only, if the PeliCAN mode is selected. In BasicCAN mode a ‘FFH’ is reflected. Table 46 Bit interpretation of the output control register (OCR); CAN address 8 BIT 7 OCTP1 BIT 6 OCTN1 BIT 5 OCPOL1 BIT 4 OCTP0 BIT 3 OCTN0 BIT 2 OCPOL0 BIT 1 OCMODE1 BIT 0 OCMODE0 2000 Jan 04 51 Philips Semiconductors Product specification Stand-alone CAN controller SJA1000 handbook, full pagewidth OCTP1 OCTN1 OCPOL1 OCTP0 OCTN0 OCPOL0 OCMODE1 OCMODE0 TXCLK TXD TRANSMIT LOGIC VDD TP0 TX0 TN0 VSS VDD TP1 TX1 TN1 VSS MGK629 transmitter Fig.14 Transceiver input/output control logic. If the SJA1000 is in the sleep mode a recessive level is output on the TX0 and TX1 pins with respect to the contents within the output control register. If the SJA1000 is in the reset state (reset request = HIGH) or the external reset pin RST is pulled LOW the outputs TX0 and TX1 are floating. The transmit output stage is able to operate in different modes. Table 47 shows the output control register settings. Table 47 Interpretation of OCMODE bits OCMODE1 0 0 1 1 Note 1. In test output mode TXn will reflect the bit, detected on RX pins, with the next positive edge of the system clock. TN1, TN0, TP1 and TP0 are configured in accordance with the setting of OCR. OCMODE0 0 1 0 1 bi-phase output mode test output mode; note 1 normal output mode clock output mode DESCRIPTION 6.5.3.1 Normal output mode In normal output mode the bit sequence (TXD) is sent via TX0 and TX1. The voltage levels on the output driver pins TX0 and TX1 depend on both the driver characteristic programmed by OCTPx, OCTNx (float, pull-up, pull-down, push-pull) and the output polarity programmed by OCPOLx. 2000 Jan 04 52 Philips Semiconductors Product specification Stand-alone CAN controller 6.5.3.2 Clock output mode SJA1000 For the TX0 pin this is the same as in normal output mode. However, the data stream to TX1 is replaced by the transmit clock (TXCLK). The rising edge of the transmit clock (non-inverted) marks the beginning of a bit period. The clock pulse width is 1 × tscl. handbook, full pagewidth HIGH LOW HIGH TX0 TX1 LOW MGK630 1 bit time Fig.15 Example of clock output mode. 6.5.3.3 Bi-phase output mode In contrast to the normal output mode the bit representation is time variant and toggled. If the bus controllers are galvanically decoupled from the bus line by a transformer, the bit stream is not allowed to contain a DC component. This is achieved by the following scheme. During recessive bits all outputs are deactivated (floating). Dominant bits are sent with alternating levels on TX0 and TX1, i.e. the first dominant bit is sent on TX0, the second is sent on TX1, and the third one is sent on TX0 again, and so on. One possible configuration example of the bi-phase output mode timing is shown in Fig.16. 2000 Jan 04 53 Philips Semiconductors Product specification Stand-alone CAN controller SJA1000 handbook, full pagewidth recessive dominant HIGH TX0 LOW HIGH TX1 LOW MGK631 bitstream Fig.16 Bi-phase output mode example (output control register = F8H). 6.5.3.4 Test output mode f osc In test output mode the level connected to RX is reflected at TXn with the next positive edge of the system clock -------2 corresponding to the programmed polarity in the output control register. Table 48 shows the relationship between the bits of the output control register and the output pins TX0 and TX1. 2000 Jan 04 54 Philips Semiconductors Product specification Stand-alone CAN controller Table 48 Output pin configuration; note 1 DRIVE Float Pull-down TXD X 0 1 0 1 Pull-up 0 1 0 1 Push-pull 0 1 0 1 Notes 1. X = don’t care. 2. TPX is the on-chip output transistor X, connected to VDD. 3. TNX is the on-chip output transistor X, connected to VSS. OCTPX 0 0 0 0 0 1 1 1 1 1 1 1 1 OCTNX 0 1 1 1 1 0 0 0 0 1 1 1 1 OCPOLX X 0 0 1 1 0 0 1 1 0 0 1 1 TPX(2) off off off off off off on on off off on on off TNX(3) off on off off on off off off off on off off on SJA1000 TXX(4) float LOW float float LOW float HIGH HIGH float LOW HIGH HIGH LOW 4. TXX is the serial output level on pin TX0 or TX1. It is required that the output level on the CAN-bus line is dominant when TXD = 0 and recessive when TXD = 1. The bit sequence (TXD) is sent via TX0 and TX1. The voltage levels on the output driver pins depends on both the driver characteristics programmed by OCTP, OCTN (float, pull-up, pull-down, push-pull) and the output polarity programmed by OCPOL. 6.5.4 CLOCK DIVIDER REGISTER (CDR) selection between BasicCAN mode and PeliCAN mode is made here. The default state of the register after hardware reset is divide-by-12 for Motorola mode (00000101) and divide-by-2 for Intel mode (00000000). On software reset (reset request/reset mode) this register is not influenced. The reserved bit (CDR.4) will always reflect a logic 0. The application software should always write a logic 0 to this bit in order to be compatible with future features, which may be 1-active using this bit. The clock divider register controls the CLKOUT frequency for the microcontroller and allows to deactivate the CLKOUT pin. Additionally a dedicated receive interrupt pulse on TX1, a receive comparator bypass and the Table 49 Bit interpretation of the clock divider register (CDR); CAN address 31 BIT 7 CAN mode Note 1. This bit cannot be written. During read-out of this register always a zero is given. BIT 6 CBP BIT 5 RXINTEN BIT 4 (0)(1) BIT 3 clock off BIT 2 CD.2 BIT 1 CD.1 BIT 0 CD.0 2000 Jan 04 55 Philips Semiconductors Product specification Stand-alone CAN controller 6.5.4.1 CD.2 to CD.0 SJA1000 The bits CD.2 to CD.0 are accessible without restrictions in reset mode as well as in operating mode. These bits are used to define the frequency at the external CLKOUT pin. For an overview of selectable frequencies see Table 50. Table 50 CLKOUT frequency selection; note 1 CD.2 0 CD.1 0 CD.0 0 f osc -------2 f osc -------4 f osc -------6 f osc -------8 f osc -------10 f osc -------12 f osc -------14 fosc CLKOUT FREQUENCY 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 Note 1 1 1. fosc is the frequency of the external oscillator (XTAL). 6.5.4.2 Clock off 6.5.4.4 CBP Setting this bit allows the external CLKOUT pin of the SJA1000 to be disabled. A write access is possible only in reset mode. If this bit is set, CLKOUT is LOW during sleep mode, otherwise it is HIGH. 6.5.4.3 RXINTEN This bit allows the TX1 output to be used as a dedicated receive interrupt output. When a received message has passed the acceptance filter successfully, a receive interrupt pulse with the length of one bit time is always output at the TX1 pin (during the last bit of end of frame). The transmit output stage should operate in normal output mode. The polarity and output drive are programmable via the output control register (see also Section 6.5.3). A write access is only possible in reset mode. Setting of CDR.6 allows to bypass the CAN input comparator and is only possible in reset mode. This is useful in the event that the SJA1000 is connected to an external transceiver circuit. The internal delay of the SJA1000 is reduced, which will result in a longer maximum possible bus length. If CBP is set, only RX0 is active. The unused RX1 input should be connected to a defined level (e.g. VSS). 6.5.4.5 CAN mode CDR.7 defines the CAN mode. If CDR.7 is at logic 0 the CAN controller operates in BasicCAN mode. If set to logic 1 the CAN controller operates in PeliCAN mode. Write access is only possible in reset mode. 2000 Jan 04 56 Philips Semiconductors Product specification Stand-alone CAN controller 7 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134); all voltages referenced to VSS. SYMBOL VDD II, IO IOT(sink) IOT(source) Tamb Tstg Ptot Vesd PARAMETER supply voltage input/output current on all pins except TX0 and TX1 sink current of TX0 and TX1 together source current of TX0 and TX1 together operating ambient temperature storage temperature total power dissipation electrostatic discharge on all pins note 2 note 3 note 4 Notes note 1 note 1 CONDITIONS − − − −40 −65 − −1500 −200 MIN. −0.5 SJA1000 MAX. +6.5 ±4 30 −20 +125 +150 1.0 +1500 +200 V UNIT mA mA mA °C °C W V V 1. IOT is allowed in case of a bus failure condition because then the TX outputs are switched off automatically after a short time (bus-off state). During normal operation IOT is a peak current, permitted for t < 100 ms. The average output current must not exceed 10 mA for each TX output. 2. This value is based on the maximum allowable die temperature and the thermal resistance of the package, not on device power consumption. 3. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ resistor. 4. Machine model: equivalent to discharging a 200 pF capacitor through a 25 Ω plus 2.5 µH circuit. 8 THERMAL CHARACTERISTICS PARAMETER thermal resistance from junction to ambient CONDITION in free air VALUE 67 UNIT K/W SYMBOL Rth(j-a) 9 DC CHARACTERISTICS VDD = 5 V (±10%); VSS = 0 V; Tamb = −40 to +125 °C; all voltages referenced to VSS; unless otherwise specified. SYMBOL Supplies VDD IDD Ism supply voltage operating supply current sleep mode supply current fosc = 24 MHz; note 1 oscillator inactive; note 2 4.5 − − 5.5 15 40 V mA µA PARAMETER CONDITIONS MIN. MAX. UNIT 2000 Jan 04 57 Philips Semiconductors Product specification Stand-alone CAN controller SJA1000 SYMBOL Inputs VIL1 VIL2 VIL3 VIH1 VIH2 VIH3 hysRST ILI Outputs VOL VOH PARAMETER CONDITIONS MIN. −0.5 − −0.5 2.0 0.7VDD 2.4 500 MAX. UNIT LOW-level input voltage on pins ALE/AS, CS, RD/E, WR and MODE LOW-level input voltage on pins XTAL1 and INT LOW-level input voltage on pins RST, AD0 to AD7 and RX0(5) HIGH-level input voltage on pins ALE/AS, CS, RD/E, WR and MODE HIGH-level input voltage on pins XTAL1 and INT HIGH-level input voltage on pins RST, AD0 to AD7 and RX0(5) input hysteresis at pins RST, AD0 to AD7 and RX0(5) input leakage current on all pins except XTAL1, RX0 and RX1 0.45 V < VI(D) < VDD; note 3 +0.8 0.3VDD +0.6 V V V VDD + 0.5 V − V VDD + 0.5 V − ±2 mV µA − LOW-level output voltage for pins AD0 to AD7, CLKOUT and INT HIGH-level output voltage for pins AD0 to AD7 and CLKOUT IOL = 4 mA IOH = −4 mA − VDD − 0.4 0.4 − V V CAN input comparator (see also Fig.22) Vth(i)(diff) Vhys II VOL(TX) differential input threshold voltage hysteresis voltage input current − VDD = 5 V ±10%; 1.4 V < VI(RX) < VDD − 1.4 V; 8 notes 4 and 6 − VDD = 5 V ±10% IO = 1.2 mA; note 6 IO = 10 mA VOH(TX) HIGH-level output voltage at pins TX0 and TX1 VDD = 5 V ±10% IO = 1.2 mA; note 6 IO = 10 mA Notes 1. AD0 to AD7 = ALE = RD = WR = CS = VDD; RST = MODE = VSS; RX0 = 2.7 V; RX1 = 2.3 V; XTAL1 = 0.5 V or VDD − 0.5 V; all outputs unloaded. 2. AD0 to AD7 = ALE = RD = WR = INT = RST = CS = MODE = RX0 = VDD; RX1 = XTAL1 = VSS; all outputs unloaded. 3. VI(D) = input voltage on all digital input pins. 4. VI(RX) = input voltage on pins RX0 and RX1. 5. Only if comparator bypass mode is active. 6. Not tested during production. 2000 Jan 04 58 VDD − 0.05 − VDD − 0.4 − V V − − 0.05 0.4 V V ±32 30 ±400 mV mV nA CAN output driver LOW-level output voltage at pins TX0 and TX1 Philips Semiconductors Product specification Stand-alone CAN controller SJA1000 10 AC CHARACTERISTICS VDD = 5 V ±10%; VSS = 0 V; CL = 50 pF (output pins); Tamb = −40 to +125 °C; unless otherwise specified; note 1. SYMBOL fosc tsu(A-AL) th(AL-A) tW(AL) tRLQV tEHQV tRHDZ tELDZ tDVWH tWHDX tWHLH tELAH tsu(i)(D-EL) th(i)(EL-D) tLLWL tLLRL tLLEH tsu(R-EH) tW(W) tW(R) tW(E) tCLWL tCLRL tCLEH tWHCH tRHCH tELCH tW(RST) tSD PARAMETER oscillator frequency address set-up to ALE/AS LOW address hold after ALE LOW ALE/AS pulse width RD LOW to valid data output E HIGH to valid data output data float after RD HIGH data float after E LOW input data valid to WR HIGH input data hold after WR HIGH WR HIGH to next ALE HIGH E LOW to next AS HIGH input data set-up to E LOW input data hold after E LOW ALE LOW to WR LOW ALE LOW to RD LOW AS LOW to E HIGH set-up time of RD/WR to E HIGH WR pulse width RD pulse width E pulse width CS LOW to WR LOW CS LOW to RD LOW CS LOW to E HIGH WR HIGH to CS HIGH RD HIGH to CS HIGH E LOW to CS HIGH RST pulse width VDD = 5 V ±10%; VDIF = ±32 mV; 1.4 V < VI(RX) < VDD − 1.4 V; note 2 Motorola mode Motorola mode Motorola mode Intel mode Intel mode Motorola mode Motorola mode Intel mode Intel mode Motorola mode Intel mode Intel mode Motorola mode Intel mode Intel mode Motorola mode Intel mode Motorola mode Intel mode Motorola mode Intel mode Intel mode CONDITIONS − 8 2 8 − − − − 8 8 15 15 8 8 10 10 10 5 20 40 40 0 0 0 0 0 0 100 − MIN. 24 − − − 50 50 30 30 − − − − − − − − − − − − − − − − − − − − 40 MAX. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns UNIT MHz Input comparator/output driver sum of input and output delays ns Notes 1. AC characteristics are not tested during production. 2. The analog input comparator may be bypassed internally using the CBP bit in the clock divider register, if external transceiver circuitry is used. This results in reduced delays (