TSA5522M

INTEGRATED CIRCUITS DATA SH EET TSA5522 1.4 GHz I2C-bus controlled synthesizer Product specification Supersedes data of 1995 Mar 22 File under Integrated Circuits, IC02 1996 Jan 23 Philips Semiconductors Product specification 1.4 GHz I2C-bus controlled synthesizer FEATURES • Complete 1.4 GHz single chip system • Three PNP band switch buffers (20 mA) • Four bus-controlled bidirectional ports (NPN open-collector outputs); only one port in 16-pin version • 33 V tuning voltage output • In-lock detector • 5-step ADC • Mixer-Oscillator (M/O) band switch output • 15-bit programmable divider • Programmable reference divider ratio (512, 640 or 1024) • Programmable charge-pump current (50 or 250 µA) • Varicap drive disable • I2C-bus format – address plus 4 data bytes transmission (write mode) – address plus 1 status byte transmission (read mode) – three independent addresses • Low power and low radiation. ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TSA5522M TSA5522T SSOP20 SO16 DESCRIPTION plastic shrink small outline package; 20 leads; body width 4.4 mm plastic small outline package; 16 leads; body width 3.9 mm APPLICATIONS • TV tuners and front-ends • VCR tuners. TSA5522 VERSION SOT266-1 SOT109-1 1996 Jan 23 2 Philips Semiconductors Product specification 1.4 GHz I2C-bus controlled synthesizer QUICK REFERENCE DATA SYMBOL VCC1 VCC2 ICC1 ICC2 fRF Vi(RF) PARAMETER supply voltage (+5 V) band switch supply voltage (+12 V) supply current band switch supply current RF input frequency RF input voltage fi = 80 to 150 MHz fi = 150 to 1000 MHz fi = 1000 to 1400 MHz fxtal Io(PNP) Io(NPN) Tamb Tstg Note 1. One band switch buffer ON; Io = 20 mA. GENERAL DESCRIPTION (see Fig.1) The device is a single chip PLL frequency synthesizer designed for TV and VCR tuning systems. The circuit consists of a divide-by-eight prescaler with its own preamplifier, a 15-bit programmable divider, a crystal oscillator and its programmable reference divider and a phase/frequency detector combined with a charge-pump which drives the tuning amplifier, including 33 V output. Three high-current PNP band switch buffers are provided for band switching together with four open-collector NPN outputs (only one open-collector output on 16-pin devices). These ports can also be used as input ports [one Analog-to Digital Converter (ADC) and three general purpose I/O ports (not available on 16-pin devices)]. An output is provided to control a Philips mixer/oscillator IC in combination with the PNP buffers state. Depending on the reference divider ratio (512, 640 or 1024), the phase comparator operates at 3.90625 kHz, 6.25 kHz or 7.8125 kHz with a 4 MHz crystal. The LOCK detector bit FL is set to logic 1 when the loop is locked and is read on the SDA line (status byte) during a read operation. crystal oscillator input frequency PNP band switch buffers output current NPN open-collector output current operating ambient temperature storage temperature (IC) note 1 CONDITIONS MIN. 4.5 VCC1 − − 64 − 25 − 28 − 26 − − − −20 −40 − 12 22 27 − − − − 4 20 20 − − TYP. TSA5522 MAX. 5.5 13.5 30 32 1400 3 3 3 − 25 25 +85 +150 UNIT V V mA mA MHz dBm dBm dBm MHz mA mA °C °C The ADC is available for digital AFC control. The ADC code is read during a read operation on the I2C-bus. The ADC input is combined with the port P6. In the TEST mode, this port is also used as a TEST output for fref and 1⁄ f 2 div (see Table 4). I2C-bus format Five serial bytes (including address byte) are required to address the device, select the VCO frequency, program the ports, set the charge-pump current and the reference divider ratio. The device has three independent I2C-bus addresses selected by applying a specific voltage on AS input (see Table 3). The general address C2 is always valid. 1996 Jan 23 3 1996 Jan 23 PRESCALER DIVIDE-BY-8 11 CP 12 f div 15-BIT PROGRAMMABLE DIVIDER BLOCK DIAGRAM handbook, full pagewidth Philips Semiconductors RF1 2 RF2 3 V tune AMP 28 DIVIDER 512/640/1024 CP RSA 15-BIT FREQUENCY REGISTER IN-LOCK DETECTOR LOGIC RSB T2,T1,T0 XTAL XTAL OSCILLATOR f ref DIGITAL PHASE COMPARATOR CHARGE PUMP POWER-ON RESET SCL 17 LOCK TSA5522 OS 1.4 GHz I2C-bus controlled synthesizer SDA RSA,RSB 18 I2 C -BUS 1 5 7-BIT PORTS REGISTER 7-BIT CONTROL REGISTER VCC1 VEE 4 GATE T2,T1,T0 PNP BUFFERS BAND SWITCH 6 V CC2 P1 P6 P5 P0 P2 P4 P7 10 9 8 13 16 15 14 AS 19 TRANSCEIVER ADC COMPARATORS 4 BS 7 n.c. MLD226 Product specification TSA5522 Fig.1 Block diagram (SSOP20). Philips Semiconductors Product specification 1.4 GHz I2C-bus controlled synthesizer PINNING SYMBOL VCC1 RF1 RF2 BS VEE VCC2 n.c. P2 P1 P0 CP Vtune P6 P7 P5 P4 SCL SDA AS XTAL SO16 1 2 3 4 5 6 − 7 8 9 10 11 12 − − − 13 14 15 16 SSOP20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 voltage supply (+5 V) RF signal input 1 RF signal input 2 band switch output to mixer/oscillator drive ground voltage supply (+12 V) not connected PNP band switch buffer output 2 PNP band switch buffer output 1 PNP band switch buffer output 0 charge-pump output tuning voltage output NPN open-collector output/ADC input NPN open-collector output/comparator input NPN open-collector output/comparator input NPN open-collector output/comparator input serial clock input serial data input/output address selection input crystal oscillator input DESCRIPTION TSA5522 handbook, halfpage handbook, halfpage V CC1 RF1 RF2 BS V EE V CC2 n.c. P2 P1 1 2 3 4 5 20 XTAL 19 AS 18 SDA 17 SCL 16 P4 V CC1 1 RF1 2 RF2 3 BS 4 16 XTAL 15 AS 14 SDA 13 SCL TSA5522T V EE 5 V CC2 6 P2 7 P1 8 MLD225 TSA5522M 6 7 8 9 15 P5 14 P7 13 P6 12 V tune 11 CP MLD230 12 P6 11 V tune 10 CP 9 PO P0 10 Fig.2 Pin configuration (SO16). Fig.3 Pin configuration (SSOP20). 1996 Jan 23 5 Philips Semiconductors Product specification 1.4 GHz I2C-bus controlled synthesizer FUNCTIONAL DESCRIPTION The device is controlled via the two-wire For programming, there is one module address (7 bits) and the R/W bit for selecting the READ or the WRITE mode. I2C-bus mode WRITE MODE (R/W = 0); see Table 1 Data bytes can be sent to the device after the address transmission (first byte). Four data bytes are required to fully program the device. The bus transceiver has an auto-increment facility which permits the programming of the device within one single transmission (address + 4 data bytes). The device can also be partially programmed providing that the first data byte following the address is divider byte 1 (DB1) or control byte (CB). The bits in the data bytes are defined in Table 1. The first bit of the first data I2C-bus. TSA5522 byte transmitted indicates whether frequency data (first bit = 0) or control and ports data (first bit = 1) will follow. Until an I2C-bus STOP command is sent by the controller, additional data bytes can be entered without the need to re-address the device. The frequency register is loaded after the 8th clock pulse of the second divider byte (DB2), the control register is loaded after the 8th clock pulse of the control byte (CB) and the ports register is loaded after the 8th clock pulse of the ports byte (PB). I2C-BUS ADDRESS SELECTION The module address contains programmable address bits (MA1 and MA0) which offer the possibility of having several synthesizers (up to 3) in one system by applying a specific voltage on the AS input. The relationship between MA1 and MA0 and the input voltage on the AS input is given in Table 3. Table 1 I2C-bus data format BYTE MSB 1 0 N7 1 P7(1) 1 N14 N6 CP P6 0 N13 N5 T2 P5(1) DATA BYTE 0 N12 N4 T1 P4(1) 0 N11 N3 T0 X MA1 N10 N2 RSA P2 MA0 N9 N1 RSB P1 LSB 0 N8 N0 OS P0 COMMAND A A A A A Address byte (ADB) Divider byte 1 (DB1) Divider byte 2 (DB2) Control byte (CB) Ports byte (PB) Note 1. Not available on 16-pin devices. Table 2 Description of Table 1 DESCRIPTION programmable address bits (see Table 3) programmable divider bits N = N14 × 214 + N13 × 213 + ... + N1 × 2 + N0 charge-pump current; CP = 0 = 50 µA; CP = 1 = 250 µA test bits (see Table 4). For normal operation T2 = 0; T1 = 0; T0 = 1 reference divider ratio select bits (see Table 5) tuning amplifier control bit; for normal operation OS = 0 and tuning voltage is ON; when OS = 1 tuning voltage is OFF (high impedance) PNP band switch buffers control bits NPN open collector control bits when Pn = 0 output n is OFF; when Pn = 1 output n is ON don’t care SYMBOL MA1, MA0 N14 to N0 CP T2 to T0 RSA, RSB OS P2 to P0 P7 to P4 X 1996 Jan 23 6 Philips Semiconductors Product specification 1.4 GHz I2C-bus controlled synthesizer Table 3 Address selection MA1 0 0 1 1 MA2 0 1 0 1 READ MODE; R/W = 1 (see Table 7) TSA5522 VOLTAGE APPLIED ON AS INPUT 0 to 0.1VCC1 Always valid 0.4VCC1 to 0.6VCC1 0.9VCC1 to VCC1 Table 4 T2 0 0 1 1 1 1 T1 0 1 1 1 0 0 Test bits T0 1 X 0 1 0 1 DEVICE OPERATION normal mode charge-pump is OFF charge-pump is sinking current charge-pump is sourcing current fref is available at LOCK output 1⁄ f 2 div is available at LOCK output Data can be read from the device by setting the R/W bit to logic 1. After the slave address has been recognized, the device generates an acknowledge pulse and the first data byte (status byte) is transferred on the SDA line (MSB first). Data is valid on the SDA line during a HIGH level of the SCL clock signal. A second data byte can be read from the device if the microcontroller generates an acknowledge on the SDA line (master acknowledge). End of transmission will occur if no master acknowledge occurs. The device will then release the data line to allow the microcontroller to generate a STOP condition. When ports P4 to P7 are used as inputs, the corresponding bits must be logic 0 (high impedance state). The POR flag is set to logic 1 at power-on. The flag is reset when an end-of-data is detected by the device (end of a read sequence). Control of the loop is made possible with the in-lock flag (FL) which indicates when the loop is locked (FL = 1). The bits I2, to I0 represent the status of the I/O ports P7, P5 and P4 respectively. A logic 0 indicates a LOW level and a logic 1 indicates a HIGH level (see “Characteristics”). A built-in ADC is available at pin P6. This converter can be used to apply AFC information to the microcontroller from the IF section of the television. The relationship between the bits A2 to A0 is given in Table 8. Table 5 Ratio select bits RSB 0 1 1 Band switch output levels P1 1 0 0 P0 0 0 1 VOLTAGE ON BS OUTPUT 0.25 V 0.4VCC1 0.8VCC1 PHILIPS M/O BAND band A band B band C REFERENCE DIVIDER 640 1024 512 RSA X 0 1 Table 6 P2 0 1 0 Table 7 READ data format BYTE MSB 1 POR(2) 1 FL(3) 0 I2(4) DATA BYTE 0 I1(4) 0 I0(4) MA1 A2(5) MA0 A1(5) LSB 1 A0(5) COMMAND A(1) − Address byte (ADB) Status byte (SB) Notes 1. A = acknowledge. 2. POR = power-on-reset (POR = 1 at power-on). 3. FL = in-lock flag (FL = 1 when loop is locked). 4. I2 to I0 = digital levels for I/O ports P7, P5 and P4 respectively. 5. A2 to A0 = digital outputs of the 5-level ADC. 1996 Jan 23 7 Philips Semiconductors Product specification 1.4 GHz I2C-bus controlled synthesizer Table 8 ADC levels A2 1 0 0 0 0 A1 0 1 1 0 0 A0 0 1 0 1 0 TSA5522 VOLTAGE APPLIED ON PORT P6(1) 0.6VCC1 to 13.5V 0.45VCC1 to 0.6VCC1 0.3VCC1 to 0.45VCC1 0.15VCC1 to 0.3VCC1 0 to 0.15VCC1 Note 1. Accuracy is 0.02VCC1. LIMITING VALUES In accordance with the Absolute Maximum System (IEC 134) SYMBOL VCC1 VCC2 Vi(RF) Vo(BS) Vo(PNP) Io(PNP) VNPN INPN Vo(CP) Vo(tune) Vi(SCL) Vi/o(SDA) Io(SDA) Vi(AS) Vi(xtal) Tstg Tj tsc HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling bipolar devices. Every pin withstands the ESD test in accordance with MIL-STD-883C category B (2000 V). Every pin withstands the ESD test in accordance with Philips Semiconductors Machine Model 0 Ω, 200 pF (200 V). supply voltage +5 V supply voltage + 12 V prescaler input voltage band switch output voltage PNP band switch buffer output voltage PNP band switch buffers output current NPN open-collector output voltage NPN open-collector output current charge-pump output voltage output tuning voltage serial clock input voltage serial data input/output voltage serial data output current address selection input voltage crystal oscillator input voltage storage temperature range (IC) maximum junction temperature short circuit time; every pin to VCC1 or GND PARAMETER MIN. −0.3 −0.3 −0.3 −0.3 − 0.3 −1 −0.3 −1 −0.3 −0.3 −0.3 −0.3 −1 −0.3 −0.3 −40 − − 6.0 16 VCC1 VCC1 VCC2 25 16 25 VCC1 35 6.0 6.0 5 VCC1 VCC1 +150 +150 10 MAX V V V V V mA V mA V V V V mA V V °C °C s UNIT 1996 Jan 23 8 Philips Semiconductors Product specification 1.4 GHz I2C-bus controlled synthesizer THERMAL CHARACTERISTICS SYMBOL Rth j-a SO16 SSOP20 PARAMETER thermal resistance from junction to ambient in free air 110 120 MAX TSA5522 UNIT K/W K/W CHARACTERISTICS VCC1 = 4.5 to 5.5 V; VCC2 = VCC1 to 13.2 V; Tamb = −20 to 85 °C; unless otherwise specified; see note 1 SYMBOL VCC1 VCC2 ICC1 ICC2 fRF DR PARAMETER supply voltage (+5 V) supply voltage (+12 V) supply current supply current RF input frequency divider ratio 15-bit frequency word Rxtal = 25 to 300 Ω One band switch buffer is ON; Isource = 20 mA CONDITIONS MIN. 4.5 VCC1 − − 64 256 − − 22 27 − − TYP. MAX 5.5 13.5 30 32 1400 32767 V V mA mA MHz MHz UNIT Crystal oscillator fxtal Zxtal Prescaler Vi(RF) RF input level VCC1 = 4.5 to 5.5 V; see Fig.4; fi = 80 to 150 MHz VCC1 = 4.5 to 5.5 V; see Fig.4; fi = 150 to 1000 MHz VCC1 = 4.5 to 5.5 V; see Fig.4; fi = 1000 to 1400 MHz PNP band switch buffers outputs |ILO| Vo(sat) |ILO| Vo(sat) COL output leakage current output saturation voltage VCC2 = 13.5 V; Vo = 0 V Isource = 20 mA; note 1 VCC1 = 5.5 V; Vo = 13.5 V Isink = 20 mA; note 3 VOL = 13.5 V −10 − − − 0.2 − 0.2 − 0.5 µA V µA V nF −25 −28 −26 − − − 3 3 3 dB dB dB crystal oscillator input frequency 3.2 600 4 1200 4.48 − MHz Ω crystal oscillator input fi = 4 MHz impedance (absolute value) NPN open-collector outputs P4, P5, P6 and P7; see note 2 output leakage current output saturation voltage allowed capacitive loading on output pins 10 0.5 10 Input ports P7, P5 and P4; see note 2 VIL VIH IIH(AS) 1996 Jan 23 LOW level input voltage HIGH level input voltage − 3 − 9 − − − 1.5 − V V µA AS input (Address Selection) HIGH level input current VAS = VCC1 50 Philips Semiconductors Product specification 1.4 GHz I2C-bus controlled synthesizer TSA5522 SYMBOL IIL(AS) VIL VIH IIH IIL fclk PARAMETER LOW level input current CONDITIONS VAS = 0 V MIN. −50 − 3.0 − − − − − − TYP. − MAX UNIT µA SCL and SDA inputs LOW level input voltage HIGH level input voltage HIGH level input current LOW level input current input clock frequency VIH = 5.5 V; VCC1 = 0 V VIH = 5.5 V; VCC1 = 5.5 V VIL = 0 V; VCC1 = 5.5 V 1.5 5.5 10 10 − 400 V V µA µA µA kHz µA µA − − −10 − − − − 0.36VCC1 0.7VCC1 3.1 − − − −5 − 100 − − SDA output (I2C bus mode) IILO Vo Vo(BS) output leakage current output voltage VO = 5.5 V Isink = 3 mA band A; Isource = 20 µA band B; Isource = 20 µA band C; Isource = 20 µA band C; Isource = 50 µA Charge-pump output CP IICPH IICPL Vo(CP) ILI(off) HIGH charge pump current (absolute value) LOW charge pump current (absolute value) output voltage off-state leakage current CP = 1 CP = 0 in-lock; Tamb = +25 °C T2 = 0; T1 = 1 250 50 1.95 1 − − − − − − 15 µA µA V nA µA V mV 10 0.4 BS output (M/O band selection) output voltage 0.25 0.4VCC1 0.8VCC1 − 0.5 0.9VCC1 − V V V 0.43VCC1 V Tuning voltage output Vtune ILO(off) Vo Vripple(p-p) leakage current when switched-off output voltage when the loop is closed acceptable ripple voltage on VCC1 (peak-to-peak value) OS = 1; Vtune = 33 V 10 32.6 30 OS = 0; T2 = 0; T1 = 0; T0 = 1; 0.4 RL = 27 k Ω; Vtune = 33 V fripple = 300 Hz to 300 kHz − Notes 1. A single PNP band switch buffer is ON. 2. P4, P5 and P7 I/O ports are not available in 16-pin package. In 20-pin package, when a port is active, the collector voltage must not exceed 6 V. 3. A single NPN open-collector output is ON. 1996 Jan 23 10 Philips Semiconductors Product specification 1.4 GHz I2C-bus controlled synthesizer TSA5522 handbook, full pagewidth 12 MLD227 power (dBm) 0 12 24 36 48 0 200 400 600 800 1000 1200 1400 f i (MHz) 1600 Fig.4 Prescaler typical input sensitivity curve. 1996 Jan 23 11 Philips Semiconductors Product specification 1.4 GHz I2C-bus controlled synthesizer INTERNAL PIN CONFIGURATION TSA5522 handbook, full pagewidth 3 kΩ V CC1 300 µF VCC1 to presscaler divider V CC1 RF1 Vref AS V CC1 V CC1 RF2 V CC1 1 kΩ 1 kΩ VCC1 XTAL AS SDA V CC1 V CC1 BS 1 kΩ SCL V CC1 V CC1 P4 V EE VCC1 V CC1 P5 TSA5522 VCC2 VCC2 n.c. V CC1 V CC1 P7 P2 VCC2 V CC1 X4 V CC1 P6 P1 Vtune control VCC2 V CC1 down P0 up CP MLD228 Fig.5 Internal pin configuration. 1996 Jan 23 12 Philips Semiconductors Product specification 1.4 GHz I2C-bus controlled synthesizer APPLICATION INFORMATION Tuning amplifier The tuning amplifier is capable of driving the varicap voltage without an external transistor. The tuning voltage output must be connected to an external load of 27 kΩ which is connected to the tuning voltage supply rail. Figure 6 shows a possible loop filter. The component values depend on the oscillator characteristics and the selected reference frequency. Crystal oscillator TSA5522 The crystal oscillator uses a 4 MHz crystal connected in series with an 18 pF capacitor thereby operating in the series resonance mode. Connecting the oscillator to the supply voltage is preferred, but it can, however, also be connected to ground. handbook, full pagewidth 27 kΩ V tune 33 V UHF 39 nF P0 180 nF 22 kΩ CP V tune P6 SCL SDA AS P6 SCL SDA AS XTAL P2 VCC2 V EE BS 1 nF RF2 RF1 V CC1 1 nF 5V 10 nF MLD229 P1 VHF1 VHF3 12 V TSA5522T BS RF RF 4 MHz 18 pF Fig.6 Typical application (SO16). 1996 Jan 23 13 Philips Semiconductors Product specification 1.4 GHz I2C-bus controlled synthesizer Flock flag (FL) definition When the LOCK output is LOW the maximum frequency deviation (∆f) from stable frequency can be expressed as K VCO ( C1 + C2 ) follows: ∆ f = ± ------------- × I CP × ---------------------------( C1 × C2 ) KO where: Kvco = oscillator slope Hz/V ICP = charge-pump current (A) KO = 4 × 10E6 C1, C2 = loop filter capacitors. In the application: KVCO = 16 MHz/V (UHF band) ICP = 250 µA C1 = 180 nF, C2 = 39 nF ∆f = ±31.2 kHz. Table 9 LOCK output / FL flag setting DESCRIPTION CONDITION MIN. 1024 2048 1280 0 Fig.7 Loop filter. handbook, halfpage TSA5522 C2 C1 R MBE331 MAX. 1152 2304 1440 300 UNIT µs µs µs µs Time span between actual phase lock and LOCK bit is LOW RSA = 1; RSB = 1 (or FL flag = 1) RSA = 1; RSB = 1 RSB = 0 Time span between the loop losing lock and LOCK bit is HIGH or (FL flag = 0) 1996 Jan 23 14 Philips Semiconductors Product specification 1.4 GHz I2C-bus controlled synthesizer PACKAGE OUTLINES SO16: plastic small outline package; 16 leads; body width 3.9 mm TSA5522 SOT109-1 D E A X c y HE vMA Z 16 9 Q A2 A1 pin 1 index θ Lp 1 e bp 8 wM L detail X (A 3) A 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 0.069 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 10.0 9.8 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.050 HE 6.2 5.8 0.24 0.23 L 1.05 0.041 Lp 1.0 0.4 0.039 0.016 Q 0.7 0.6 0.028 0.020 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.7 0.3 0.028 0.012 θ 0.0098 0.057 0.0039 0.049 0.019 0.0098 0.39 0.014 0.0075 0.38 8 0o o Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07S JEDEC MS-012AC EIAJ EUROPEAN PROJECTION ISSUE DATE 91-08-13 95-01-23 1996 Jan 23 15 Philips Semiconductors Product specification 1.4 GHz I2C-bus controlled synthesizer TSA5522 SSOP20: plastic shrink small outline package; 20 leads; body width 4.4 mm SOT266-1 D E A X c y HE vM A Z 20 11 Q A2 pin 1 index A1 (A 3) θ Lp L A 1 e bp 10 detail X wM 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.5 A1 0.15 0 A2 1.4 1.2 A3 0.25 bp 0.32 0.20 c 0.20 0.13 D (1) 6.6 6.4 E (1) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1.0 Lp 0.75 0.45 Q 0.65 0.45 v 0.2 w 0.13 y 0.1 Z (1) 0.48 0.18 θ 10 0o o Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT266-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 90-04-05 95-02-25 1996 Jan 23 16 Philips Semiconductors Product specification 1.4 GHz I2C-bus controlled synthesizer SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all SO and SSOP packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. Wave soldering SO Wave soldering techniques can be used for all SO packages if the following conditions are observed: • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. • The longitudinal axis of the package footprint must be parallel to the solder flow. • The package footprint must incorporate solder thieves at the downstream end. SSOP TSA5522 Wave soldering is not recommended for SSOP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering cannot be avoided, the following conditions must be observed: • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. • The longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end. Even with these conditions, only consider wave soldering SSOP packages that have a body width of 4.4 mm, that is SSOP16 (SOT369-1) or SSOP20 (SOT266-1). METHOD (SO AND SSOP) During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 1996 Jan 23 17 Philips Semiconductors Product specification 1.4 GHz I2C-bus controlled synthesizer DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values TSA5522 This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1996 Jan 23 18 Philips Semiconductors Product specification 1.4 GHz I2C-bus controlled synthesizer NOTES TSA5522 1996 Jan 23 19 Philips Semiconductors – a worldwide company Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428) BUENOS AIRES, Tel. (541)786 7633, Fax. (541)786 9367 Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. (02)805 4455, Fax. (02)805 4466 Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213, Tel. (01)60 101-1236, Fax. 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