TZA1038HW

INTEGRATED CIRCUITS DATA SHEET TZA1038HW High speed advanced analog DVD signal processor and laser supply Product specification 2003 Sep 03 Philips Semiconductors Product specification High speed advanced analog DVD signal processor and laser supply CONTENTS 1 2 3 4 5 6 7 7.1 7.2 7.2.1 7.2.2 7.2.3 7.2.4 7.2.4.1 7.2.4.2 7.2.4.3 7.2.4.4 7.2.5 7.2.6 7.2.7 7.2.7.1 7.2.7.2 7.2.8 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6 7.3.7 7.3.8 7.3.9 7.3.10 7.3.11 7.3.12 7.3.13 7.3.14 FEATURES GENERAL DESCRIPTION ORDERING INFORMATION QUICK REFERENCE DATA BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION RF data processing Servo signal processing Servo signal path set-up Focus servo Radial servo Differential phase detection Drop-out concealment Push-pull and three-beam push-pull Enhanced push-pull (dynamic offset compensation for beam landing) Offset compensation Automatic dual laser supply Power-on reset and general power on Compatibility with TZA1033HL/V1 Software compatibility Hardware compatibility Interface to the system controller Control registers Register 0: power control Register 1: servo and RF modes Register 2: focus offset DAC Register 3: RF path gain Register 4: RF left and right, or sum offset compensation Register 5: RF sum offset compensation Register 6: servo gain and dynamic radial offset compensation factor Register 7: servo path gain and bandwidth and RF path bandwidth and pre-emphasis Register 8: RF channel selection Register 11: radial servo offset cancellation Register 12: central servo offset cancellation inputs A and B Register 13: central servo offset cancellation inputs C and D Register 14: RF filter settings Register 15: DPD filter settings 7.5.3 7.5.4 7.5.5 7.5.5.1 7.5.5.2 7.5.5.3 7.5.5.4 8 9 10 11 11.1 11.1.1 11.1.2 11.2 11.3 11.4 11.4.1 11.4.2 11.4.3 11.4.4 12 13 13.1 13.2 13.3 13.4 13.5 14 15 16 7.4 7.4.1 7.4.2 7.5 7.5.1 7.5.2 TZA1038HW Internal digital control, serial bus and external digital input signal relationships STANDBY mode RF only mode Signal descriptions Data path signals through pins A to D Data signal path through input pins RFSUMP and RFSUMN HF filtering Focus signals Radial signals DPD signals (DVD-ROM mode) with no drop-out concealment DPD signals (DVD-ROM mode) with drop-out concealment Three-beam push-pull (CD mode) Enhanced push-pull LIMITING VALUES THERMAL CHARACTERISTICS CHARACTERISTICS APPLICATION INFORMATION Signal relationships Data path Servo path Programming examples Energy saving Initial DC and gain setting strategy Electrical offset from pick-up Gain setting servo DC level in RF path Gain setting RF path PACKAGE OUTLINE SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS 2003 Sep 03 2 Philips Semiconductors Product specification High speed advanced analog DVD signal processor and laser supply 1 FEATURES 2 GENERAL DESCRIPTION TZA1038HW • Operates with DVD-ROM, DVD+RW, DVD-RW, CD-ROM and CD-RW • Operates up to 64 × CD-ROM and 12 × DVD-ROM • RF data amplifier with wide, fine pitch programmable noise filter and equalizer equivalent to 64 × CD or 12 × DVD • Programmable RF gain for DVD-ROM, CD-RW and CD-ROM applications (approximately 50 dB range to cover a large range of disc-reflectivity and OPUs) • Additional RF sum input • Balanced RF data signal transfer • Universal photodiode IC interface using internal conversion resistors and offset cancellation • Input buffers and amplifiers with low-pass filtering • Three different tracking servo strategies: – Conventional three-beam tracking for CD – Differential Phase Detection (DPD) for DVD-ROM, including option to emulate traditional drop-out detection: Drop-Out Concealment (DOC) – Advanced push-pull with dynamic offset compensation. • Enhanced signal conditioning in DPD circuit for optimal tracking performance under noisy conditions • Radial error signal for Fast Track Counting (FTC) • RF only mode: servo outputs can be set to 3-state, while RF data path remains active • Radial servo polarity switch • Flexible adaption to different light pen configurations • Two fully automatic laser controls for red and infrared lasers, including stabilization and an on/off switch • Automatic selection of monitor diode polarity • Digital interface with 3 and 5 V compatibility. The TZA1038HW is an analog preprocessor and laser supply circuit for DVD and CD read-only players. The device contains data amplifiers, several options for radial tracking and focus control. The preamplifier forms a versatile, programmable interface between single light path voltage output CD or DVD mechanisms to Philips digital signal processor family for CD and DVD (for example, Gecko, HDR65 or Iguana). A separate high-speed RFSUM input is available. The device contains several options for radial tracking: • Conventional three-beam tracking for CD • Differential phase detector for DVD • Push-pull with flexible left and right weighting to compensate dynamic offsets e.g. beam landing offset • A radial error signal to allow Fast Track Count (FTC) during track jumps. The dynamic range of this preamplifier and processor combination can be optimized for LF servo and RF data paths. The gain in both channels can be programmed separately and so guarantees optimal playability for all disc types. The RF path is fully DC coupled. The DC content compensation techniques provide fast settling after disc errors. The device can accommodate astigmatic, single foucault and double foucault detectors and can be used with P-type lasers with N-sub or P-sub monitor diodes. After an initial adjustment, the circuit will maintain control over the laser diode current. With an on-chip reference voltage generator, a constant stabilized output power is ensured and is independent of ageing. An internal Power-on reset circuit ensures a safe start-up condition. 2003 Sep 03 3 Philips Semiconductors Product specification High speed advanced analog DVD signal processor and laser supply 3 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TZA1038HW HTQFP48 DESCRIPTION plastic thermal enhanced thin quad flat package; 48 leads; body 7 × 7 × 1 mm; exposed die pad TZA1038HW VERSION SOT545-2 4 QUICK REFERENCE DATA SYMBOL PARAMETER ambient temperature CONDITIONS MIN. −40 4.5 2.7 4.5 without laser supply STANDBY mode note 1 − − 2.7 − 5.0 3.3 5.0 98 − 3.3 TYP. MAX. +85 UNIT °C V V V mA mA V Tamb Supplies VDDA1, VDDA2, VDDA3, VDDA4 VDDD3 VDDD5 IDD VI(logic) BLF(−3dB) IO(LF) VO(FTC)(p-p) BFTC VI(FTCREF) analog supply voltage 3 V digital supply voltage 5 V digital supply voltage supply current logic input compatibility −3 dB bandwidth of LF path output current FTC output voltage (peak-to-peak value) FTC bandwidth FTC reference input voltage FTCHBW = 0 FTCHBW = 1; note 2 focus servo output radial servo output 5.5 5.5 5.5 120 1 5.5 Servo signal processing 60 0 0 2.0 − − 1.25 75 − − − 600 1200 − 100 12 12 − − − 2.75 kHz µA µA V kHz kHz V RF data processing ARF linear current gain programmable gain RF channels RFSUM channels BRF(−3dB) f0(RF) td(RF) −3 dB bandwidth of RFP and RFN signal path noise filter and equalizer corner frequency flatness delay in RF data path input impedance of pins A to D RFEQEN = 0; RFNFEN = 0 BWRF = 0 BWRF = 127 equalizer on; flat from 0 to 100 MHz; BWRF = 127 6 −6 200 8 100 − − − 300 12.0 145 − 49 +31 − 14.5 182 0.5 dB dB MHz MHz MHz ns Zi 100 − − kΩ 2003 Sep 03 4 Philips Semiconductors Product specification High speed advanced analog DVD signal processor and laser supply SYMBOL Vi(RF)(FS) PARAMETER CONDITIONS MIN. TYP. TZA1038HW MAX. UNIT input voltage on at the appropriate signal pins A to D for full-scale at path gain setting output RF signal path − LF signal path − − differential input voltage on pins RFSUMP and RFSUMN DC input voltage range on pins RFSUMP and RFSUMN differential output voltage on pins RFP and RFN (peak-to-peak value) DC output voltage on pins RFP and RFN input reference voltage on pin RFREF for common mode output GRFSUM = −6 dB − − − 600 700 1800 mV mV mV Vi(SUM)(dif) VI(DC) with respect to VSS 1.3 − VDDA − 1.0 V Vo(RF)(dif)(p-p) − − 1.4 V VO(RF)(DC) Vi(RFREF)(CM) 0.35 0.8 − 1.2 VDDA − 1.9 2.1 V V Laser supply Io(laser)(max) Vi(mon) maximum current output to laser input voltage from laser monitor diode P-type monitor diode LOW level voltage HIGH level voltage N-type monitor diode LOW level voltage HIGH level voltage Notes 1. Input logic voltage level follows the supply voltage applied at pin VDDD3. 2. High FTC bandwidth is achieved when IS1 and IS2 > 1.5 µA. − − 0.155 0.185 − − V V − − VDDA4 − 0.155 − VDDA4 − 0.190 − V V −120 − − mA 2003 Sep 03 5 Philips Semiconductors Product specification High speed advanced analog DVD signal processor and laser supply 5 BLOCK DIAGRAM TZA1038HW handbook, full pagewidth VDDA1 5 1 2 VDDA2 43 VDDA3 37 VDDA4 32 RFREF 38 VDDD3 15 VDDD5 23 RFSUMP RFSUMN RF DATA PROCESSING MULTIPLEXER A to D OPUREF 5 VARIABLE GAIN STAGES 39 40 RFP RFN 4 TZA1038HW 36 A B C D E F OPUREF 8 9 10 11 3 4 12 PUSH-PULL OFFSET COMPENSATION 27 47 VOLTAGE AND CURRENT REFERENCES DUAL LASER SUPPLY 20 21 S1 S2 28 25 DPD SELECT; SWAP SERVO SIGNAL PROCESSING 4 3-BEAM TRACKING 35 34 33 30 29 OB OC OD S1 S2 OCENTRAL FTC OA FTC FTCREF VDDL REXT COP COM 44 CDMI CDLO DVDMI DVDLO 46 45 7 48 LASER 2 LASER 1 FTC COMPARATOR 22 COO SERIAL INTERFACE 14 26 6 42 VSSA2 41 VSSA3 31 VSSA4 19 VSSD 16 SIDA 17 SICL 18 MCE466 TM TDO VSSA1 SILD Fig.1 Block diagram. 2003 Sep 03 6 Philips Semiconductors Product specification High speed advanced analog DVD signal processor and laser supply 6 PINNING SYMBOL RFSUMP RFSUMN E F VDDA1 VSSA1 DVDMI A B C D OPUREF n.c. TM VDDD3 SIDA SICL SILD VSSD COP COM COO VDDD5 n.c. FTC TDO FTCREF OCENTRAL S2 S1 VSSA4 VDDA4 OD OC OB OA VDDA3 RFREF RFP RFN 2003 Sep 03 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 positive RF sum input negative RF sum input input E input F analog supply voltage 1 (RF input stage) analog ground 1 input signal from DVD laser monitor diode input A input B input C input D reference input from Optical Pick-Up (OPU) not connected test mode input (factory test only) DESCRIPTION TZA1038HW digital supply voltage (serial interface 3 V I/O pads and FTC comparator) serial host interface data input serial host interface clock input serial host interface load digital ground positive FTC comparator input inverting FTC comparator input FTC comparator output digital supply voltage (5 V digital core) not connected fast track count output test data output (factory test only) FTC reference input test pin for offset cancellation servo current output 2 for radial tracking servo current output 1 for radial tracking analog ground 4 analog supply voltage 4 (servo signal processing) servo current output for focus D servo current output for focus C servo current output for focus B servo current output for focus A analog supply voltage 3 (RF output stage) DC reference input for RF channel common mode output voltage positive RF output negative RF output 7 Philips Semiconductors Product specification High speed advanced analog DVD signal processor and laser supply SYMBOL VSSA3 VSSA2 VDDA2 REXT CDLO CDMI VDDL DVDLO PIN 41 42 43 44 45 46 47 48 analog ground 3 analog ground 2 analog supply voltage 2 (internal RF data processing) reference current input (connect via 12.1 kΩ to VSSA4) CD laser output input signal from CD laser monitor diode laser supply voltage DVD laser output DESCRIPTION TZA1038HW 48 DVDLO 43 VDDA2 45 CDLO 47 VDDL 44 REXT 46 CDMI 39 RFP handbook, full pagewidth 37 VDDA3 38 RFREF 42 VSSA2 41 VSSA3 40 RFN RFSUMP 1 36 OA 35 OB 34 OC 33 OD 32 VDDA4 RFSUMN 2 E3 F4 VDDA1 5 VSSA1 6 DVDMI 7 A8 B9 C 10 D 11 OPUREF 12 TZA1038HW 31 VSSA4 30 S1 29 S2 28 OCENTRAL 27 FTCREF 26 TDO 25 FTC n.c. 13 TM 14 VDDD3 15 SIDA 16 SICL 17 SILD 18 VSSD 19 COP 20 COM 21 COO 22 VDDD5 23 n.c. 24 MCE467 Fig.2 Pin configuration. 2003 Sep 03 8 Philips Semiconductors Product specification High speed advanced analog DVD signal processor and laser supply 7 7.1 FUNCTIONAL DESCRIPTION RF data processing TZA1038HW The RF data path is a fully DC-coupled, multi-stage amplifier (see Fig.3). The input signal for data can be selected from RF inputs A to D or from the summed RF inputs RFSUMP and RFSUMN. Switching between the two sets of signals is performed by an internal multiplexer. The signals are fully balanced internally to improve signal quality and reduce power supply interference. RF outputs RFP and RFN can be DC coupled to the Analog-to-Digital Converter (ADC) of the decoder. The RF input signals are from photodiodes and have a large DC content by nature. This DC component must be removed from the signals for good system performance. Built-in DACs, located after the input stages G1 and RFSUM, have the ability to do this. The DAC range and resolution is scaled with the gain setting of the first amplifier stage. When the DC content is removed, the RF signal can be DC coupled to the decoder. The main advantage of DC coupling is fast recovery from signal swings due to disc defects since there is no AC coupling capacitance to slow the recovery. When using DC coupling, both AC and DC content in the data signal is known. The Philips Iguana decoders have on-chip control loops to support Automatic Gain Control (AGC) and DC cancellation. Two separate DACs are available for cases where the left and right side DC conditions can be different. When it is not possible to have a DC connection between the TZA1038HW and the decoder, the signals on servo outputs OA to OD can be used as they contain the same LP-filtered and DC coupled information. Summing of the photodiode signals A to D is performed in the second amplifier stage G2. Each individual diode channel can be switched on, off or inverted with switches SW-A to SW-D. Switching between photodiode signals and RFSUM input is performed immediately before the third amplifier stage G3. This stage has a variable gain with fine resolution to allow automatic gain adjustment to be controlled by the decoder. The filter stage limits the bandwidth according to the maximum playback speed of the disc. This is to optimize the noise performance. The filter stage consists of an equalizer and a noise filter, both of which can be bypassed, also the boost factor of the equalizer can be set. The corner frequencies of the equalizer and noise filter are equal and can be programmed to a 7-bit resolution. The RF output signals RFP and RFN can be DC coupled to a decoder with a differential input pair (as with Philips Iguana decoders). The common mode output voltage can be set externally at pin RFREF. The signals for differential phase detection are tapped from the inputs A to D at the RF amplifier G1 stages. DC cancellation for the A to D and RFSUM signal paths can be set independently or simultaneously. 2003 Sep 03 9 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... andbook, full pagewidth 2003 Sep 03 RFSUMP RFSUMN 1 2 RFSUM RFOFFSS 12 OPUREF 8 G1 SW-A A DPD-A RFOFFSL SW-B 9 G1 DPD-B SW-C 10 G1 DPD-C RFOFFSR SW-D 11 G1 DPD-D Philips Semiconductors High speed advanced analog DVD signal processor and laser supply RFREF 38 39 G3 EQUALIZER NOISE FILTER 40 RFP RFN RF outputs TZA1038HW 10 RF inputs B G2 DPD 30 FILTER DOC 29 S1 S2 servo radial outputs C DPD-A DPD-D DPD-C DPD-B central aperture signal D TZA1038HW Product specification MCE468 Fig.3 RF data and DPD processing. Philips Semiconductors Product specification High speed advanced analog DVD signal processor and laser supply 7.2 Servo signal processing TZA1038HW The photodiode configurations and naming conventions are shown in Figs 4 and 5. handbook, halfpage left tangential direction right 7.2.1 SERVO SIGNAL PATH SET-UP A block diagram of the servo signal path is shown in Fig.6. In general, the servo signal path comprises: • A voltage-to-current converter with programmable offset voltage source VLFOFFS that is common to all inputs • A 4-bit DAC for each of the six channels to compensate for offset per channel • A variable gain stage to adapt the signal level to the specific pick-up and disc properties • Low-pass filtering and output stage for the photodiode current signals • Error output stage in the radial data path for fast track counting. Servo output signals OA to OD, S1 and S2 are unipolar current signals which represent the low-pass filtered photodiode signals. In DPD radial tracking, the S1 and S2 signals are the equivalent of the satellite signals commonly found in traditional CD systems. The servo output signals OA to OD, S1 and S2 are set to 3-state if bit RFonly = 1 (register 13, bit 11). Data = A + B + C + D Push-pull = A − D Focus = C − B DPD2 = phase (A, D) DPD4 not applicable A BC D MGW554 Fig.5 Foucault diode configuration. 7.2.2 FOCUS SERVO Focus information is reflected in the four outputs OA to OD. Gain and offset can be programmed. For optical pick-ups where only channels B and C are used for focus, channels A and D can be switched off (bit Focus_mode = 0). For initial alignment, a copy of the output currents can be made available on pin OCENTRAL. 7.2.3 RADIAL SERVO handbook, halfpage A B left tangential direction D C right MGW553 Data = A + B + C + D Push-pull = (A + B) − (C + D) Focus = (A + C) − (B + D) DPD2 = phase (A + B, C + D) DPD4 = phase (A,D) + phase (C,B) Radial information can be obtained from the two output signals S1 and S2, and the gain and offset can be programmed. The TZA1038HW provides differential phase detection, push-pull and three-beam push-pull for radial tracking. The signal FTC is made available for fast track counting and is primarily the voltage error signal derived from signals S1 or S2. The polarity of the radial loop can be reversed via the serial control bus (RAD_pol). Fig.4 Astigmatic diode configuration. 2003 Sep 03 11 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... andbook, full pagewidth 2003 Sep 03 A 8 Philips Semiconductors High speed advanced analog DVD signal processor and laser supply FTC DPD 26k 14k MUX 25 FTC 27 FTCREF V /I COFFSA B 9 α GLFR MUX SWAP 30 S1 servo radial outputs V /I 30k 14k 2−α GLFR 29 S2 COFFSB C RF inputs D 11 10 V /I 30k 14k GLFC CA 36 OA COFFSC V /I 30k 14k GLFC 35 OB servo focus outputs GLFC 34 OC 12 COFFSD E 3 V /I 15k ROFFSE F 4 V /I 15k GLFC 33 OD ROFFSF VLFOFFS OPUREF 12 LFOFFS MCE469 TZA1038HW FOFFS OCENTRAL 28 OCENTRAL TZA1038HW Product specification Fig.6 Servo signal path. Philips Semiconductors Product specification High speed advanced analog DVD signal processor and laser supply 7.2.4 DIFFERENTIAL PHASE DETECTION TZA1038HW The TZA1038HW provides differential phase detection to support DVD in various ways: • DPD2 with four channels programmed to be active gives DPD as required in the standard specification • Two of the four channels can be excluded from the DPD for pick-ups with an alternative photodiode arrangement • An increase in performance, dedicated for DVD+RW, can be obtained by using the DPD4 method. Then two truly separated phase detectors are active. After the phase detection of the two input pairs the result is summed. Input signals for DPD are taken from input pins A to D after the first gain stage G1 (see Fig.3). Pre-emphasis is applied by means of a programmable lead/lag filter. Additionally, a programmable low-pass filter is available to improve the signal quality under noisy signal conditions at lower speeds. For further signal improvements the DPD pulse stretcher can be programmed to higher values at lower speeds. The DPD signal is low-pass filtered by two internal capacitors. The signal is then fed to pins S1 and S2, or directed via the drop-out concealment circuit to the outputs (see Section 7.5). in a three-spot optical system with Three-Beam Push-Pull (TBPP). The built-in multiplexer gives a flexible method of dealing with many detector arrangements. For push-pull, the input signals are taken from channels A to D. There is also a command that switches off channels B and C, leaving channels A and D for push-pull (bits RT_mode[2:0]). For TBPP, the input signal is taken from channels E and F, irrespective of bit RFSUM setting. 7.2.4.3 Enhanced push-pull (dynamic offset compensation for beam landing) This option cancels offsets due to beam landing. A factor α can be programmed to re-balance the signal gain between channels S1 and S2. In a simplified form this can be described as: S1 = ALFR × α × input left S2 = ALFR × (2 − α) × input right. Factor α can be programmed in a range from 0.6 to 1.35, with 1.0 as the balanced condition (bits α[3:0]). 7.2.4.4 Offset compensation 7.2.4.1 Drop-out concealment A special function is built in for compatibility with drop-out detection strategies, based on level detection in the S1 and S2 signals. When using DPD in a fundamental way, there is no representation of mirror level information from the light pen. When the drop-out concealment function is enabled (bit DOCEN = 1), a portion of the Central Aperture (CA) signal is added to S1 and S2. Also, when the CA signal drops below the DOC threshold, the DPD signal is gradually attenuated. The DPD detection cannot work properly when the input signal becomes very small. The output of the DPD may then show a significant offset. The DOC may not conceal this offset completely because: • DOC is gradually controlled from the CA signal • The CA signal may not become 0 during disc-defect. For details see Section 7.5.5.2 A provision is made to compensate electrical offset from a light pen. The offset voltage from the light pen can be positive or negative. In general, the offset between any two channels is smaller than the absolute offsets. As negative input signals cannot be handled by the TZA1038HW internal servo channels, a two-step approach is adopted: • A coarse DAC, common to all the input channels, adds an offset that shifts the input signals in positive direction until all inputs are ≥0. The DAC used (LFOFFS) has a 2-bit resolution (bits LFOFF[1:0]). • A fine setting per channel is provided to cancel the remainder of the offset between the channels. This is achieved by DACs subtracting the DC component from the signals and bringing the inputs to approximately zero offset (within ≈ 1 mV). The DACs (registers 11 to 13) have a 4-bit resolution. The range of both DACs can be increased by a factor of three to compensate for higher offset values by means of control parameter bit SERVOOS. With a switched-off laser, the result of the offset cancellation can be observed at each corresponding output pin, OA to OD, S1 and S2, or via a built-in multiplexer to pin OCENTRAL (central channels only). See registers 11 to 13 for DAC and multiplexer control. 7.2.4.2 Push-pull and three-beam push-pull The TZA1038HW can also provide radial information by means of push-pull signals (from the photodiode inputs) or 2003 Sep 03 13 Philips Semiconductors Product specification High speed advanced analog DVD signal processor and laser supply 7.2.5 AUTOMATIC DUAL LASER SUPPLY 7.2.7 TZA1038HW COMPATIBILITY WITH TZA1033HL/V1 The TZA1038HW can control the output power of two lasers; it has an Automatic Laser Power Control (ALPC) that stabilizes the laser output power and compensates the effects of temperature and ageing of the laser. ALPC automatically detects if there is a P-type or N-type monitor diode in use in either of the laser circuits. The regulation loop formed by the ALPC, the laser, the monitor diode and the associated adjustment resistor will settle at the monitor input voltage. The monitor input voltage can be programmed to HIGH (≈ 180 mV) or LOW (≈ 150 mV), according to frequently-used pre-adjustments of the light pen. This set point can be set independently for both ALPCs. Bandwidth limitation and smooth switch-on behaviour is realized using an internal capacitor. A protection circuit is included to prevent laser damage due to dips in laser supply voltage VDDL. If a supply voltage dip occurs, the output can saturate and restrict the required laser current. Without the protection circuit, the ALPC would try to maximize the output power with destructive results for the laser when the supply voltage recovers. The protection circuit monitors the supply voltage and shuts off the laser when the voltage drops below a safe value. The ALPC recovers automatically after the dip has passed. Only one laser can be activated at the same time. An internal break-before-make circuit ensures safe start-up for the laser when a toggle situation between the two lasers is detected. When both lasers are programmed on, neither laser will be activated. 7.2.6 POWER-ON RESET AND GENERAL POWER ON 7.2.7.1 Software compatibility The TZA1038HW is highly software compatible with the TZA1033HL/V1. Provided that some conditions are met, the software of the TZA1038HW can be used as a successor with just minor modifications. This compatibility is achieved with the implementation of the TZA1038HW mode control bit (bit K2_Mode). When bit K2_Mode = 0, the TZA1038HW will act as a TZA1033HL/V1. When bit K2_Mode = 1, the TZA1038HW will act as a TZA1033HL/K2 and the new functions will be available (but require a software update). Other conditions or restrictions are: • Register bits of the TZA1038HW which were not defined are programmed to a logic 0. Registers 9, 10, 14 and 15 may be left undefined • The G4 stage high gain setting of the TZA1033HL/V1 is not available in the TZA1038HW; if this value was set to logic 0, there will be no difference • When bit K2_Mode = 0 the RF bandwidth will be fixed to the minimum value of 10 MHz (typical); bit K2_Mode = 1 to select a higher bandwidth; the bandwidth is now lower than using a TZA1033HL/V1. 7.2.7.2 Hardware compatibility The package is changed from LQFP64 for the TZA1033HL to LQFP48 for the TZA1038HW. The hardware differences are: • Input pins STB, HEADER and LAND of the TZA1033HL are not present • Input pins CD of TZA1033HL/V1 are not used; TZA1038HW has RFSUM inputs instead; the RFSUM inputs of TZA1038HW may be connected to ground when not used. When the supply voltage is switched on, bit PWRON is reset by the Power-On Reset (POR) signal. This concludes in a STANDBY mode at power up. POR is intended to prevent the lasers being damaged due to random settings. All other functions may be switched when power is on. The TZA1038HW becomes active when bit PWRON = 1. 2003 Sep 03 14 Philips Semiconductors Product specification High speed advanced analog DVD signal processor and laser supply 7.2.8 INTERFACE TO THE SYSTEM CONTROLLER TZA1038HW Programming the registers of TZA1038HW is done via a serial bus (see Fig.7). The circuitry is formed by a serial input shift register and a number of registers that store the data. The registers can always be programmed, irrespective of STANDBY mode. If required, the bus lines can be connected in parallel with an I2C-bus. The protocol needs no switching of the data line during SICL = HIGH. This means that other I2C-bus devices will not recognise any START or STOP commands. Control words addressed to TZA1038HW should go uniquely with the SILD signal. When SILD = HIGH, the TZA1038HW will not respond to any signal on SIDA or SICL. During a transmission, the serial data is first stored in an input shift register. At the rising edge of SILD, the content of the input register is copied into the addressed register. This is also the moment the programmed information becomes effective. The input pins have CMOS compatible threshold levels for both 3.3 and 5 V supplies. handbook, full pagewidth SICL SIDA D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 A0 A1 A2 A3 D0 D1 D2 D3 D4 A1 A2 A3 t load(H) SILD MGW496 Fig.7 Two word transmission. 7.3 Control registers The TZA1038HW is controlled by serial registers. To keep programming fast and efficient, the control bits are sent in 16-bit words. Four bits of the word are used for the address and for each address there are 12 data bits. Table 1 Overview of control parameters PARAMETER VALUES 0, 6 and 12 dB (1×, 2× and 4×) 6, 12, 18 and 24 dB (2×, 4×, 8× and 16×) 0 to 13 dB in steps of 0.8 dB (1× to 4×) REGISTER BITS SYMBOL Data path G1 (A1) G2 (A2) G3 (A3) GRFSUM (ARFSUM) BWRF gain of first RF amplifier stage (or linear amplification) gain of second RF amplifier stage (or linear amplification) gain of third RF amplifier stage (or linear amplification) 3 3 3 0 14 11 and 10 9 and 8 7 to 4 7 to 5 6 to 0 gain of RFSUM input stage (or −6, 0, 6, 12 and 18 dB linear amplification) (0.5×, 1×, 2×, 4× and 8×) bandwidth limitation in RF path f0(RF) = 12 to 145 MHz 2003 Sep 03 15 Philips Semiconductors Product specification High speed advanced analog DVD signal processor and laser supply SYMBOL RFOFFSL PARAMETER DC offset compensation in left RF input path VALUES RFSUM = 0; full range depends on G1 setting: G1 = 0 dB: 0 to 450 mV in 7.1 mV steps G1 = 6 dB: 0 to 225 mV in 3.6 mV steps G1 = 12 dB: 0 to 120 mV in 1.9 mV steps RFOFFSR DC offset compensation in right RF input path RFSUM = 0; full range depends on G1 setting: G1 = 0 dB: 0 to 450 mV in 7.1 mV steps G1 = 6 dB: 0 to 225 mV in 3.6 mV steps G1 = 12 dB: 0 to 120 mV in 1.9 mV steps RFOFFSS DC offset compensation in RFSUM path RFSUM = 1; full range depends on GRFSUM setting: GRFSUM = −6 dB; 0 to 1700 mV GRFSUM = 0 dB; 0 to 850 mV GRFSUM = 6 dB; 0 to 425 mV GRFSUM = 12 dB; 0 to 210 mV GRFSUM = 18 dB; 0 to 105 mV Servo radial path LFOFFS DC offset compensation for LF path (common for all servo inputs) CD satellite path input transresistance DVD push-pull signal transresistance DC offset compensation for radial servo path (input E) DC offset compensation for radial servo path (input F) dynamic radial offset compensation factor full scale DPD current, fixed value based on bandgap voltage across external resistor internally generated common mode DC reference current in DPD mode start frequency lead/lag filter of DPD block SERVOOS = 0: VLFOFFS = 0, 5, 10 or 15 mV SERVOOS = 1: VLFOFFS = 0, 15, 30 or 45 mV 15 kΩ fixed 30 kΩ fixed SERVOOS = 0: VROFFSE = 0 to 20 mV SERVOOS = 1: VROFFSE = 0 to 60 mV SERVOOS = 0: VROFFSF = 0 to 20 mV SERVOOS = 1: VROFFSF = 0 to 60 mV α = 0.6 to 1.35 in 15 steps of 0.05 DOCEN = 0: fixed value = 20 µA DOCEN = 1: fixed value = 6.6 µA 3.5 µA fixed TZA1038HW REGISTER 4 BITS 11 to 6 4 5 to 0 4 or 5 5 to 0 11 11 and 10 RLFR RLFPP ROFFSE ROFFSF α I(FS)(DPD), I(FS)(DPD)(DOC) − − 11 11 6 1 − − 7 to 4 3 to 0 3 to 0 5 IREFRAD(CM) − − fstart_DPD fstart_DPD = 1, 5 or 10 MHz (TZA1033HL/V1 compatible) fstart_DPD = 1, 5, 10, 18 or 24 MHz 7 15 1 and 0 5 to 3 2003 Sep 03 16 Philips Semiconductors Product specification High speed advanced analog DVD signal processor and laser supply SYMBOL GLFR (ALFR) PARAMETER VALUES TZA1038HW REGISTER 6 BITS 11 to 8 low frequency gain, radial path −15 to +9 dB in steps of 3 dB output stage (or linear (0.18× to 2.8×) amplification) gain of fast track count output 680 kΩ ±20% fixed for ±2 V (p-p) 14 kΩ fixed SERVOOS = 0: 0 to 20 mV SERVOOS = 1: 0 to 60 mV SERVOOS = 0: 0 to 20 mV SERVOOS = 1: 0 to 60 mV SERVOOS = 0: 0 to 20 mV SERVOOS = 1: 0 to 60 mV SERVOOS = 0: 0 to 20 mV SERVOOS = 1: 0 to 60 mV −15 to +9 dB in steps of 3 dB (0.18× to 2.8×) β = 0 to 31⁄32 RFTC Servo focus path RLFC COFFSA COFFSB COFFSC COFFSD GLFC (ALFC) − − 12 12 13 13 6 − − 7 to 4 3 to 0 7 to 4 3 to 0 7 to 4 LF path input transresistance DC offset compensation for central servo path A DC offset compensation for central servo path B DC offset compensation for central servo path C DC offset compensation for central servo path D low frequency gain, central path output stage (or linear amplification) focus offset compensation β FOFFSEN 2 2 4 to 0 10 full range offset compensation DAC enabled: IFOFFS = 400 nA (fixed) for focus DAC disabled: IFOFFS = 0 nA 7.3.1 Table 2 BIT REGISTER 0: POWER CONTROL Register address 0H 15 AD3 14 AD2 13 AD1 12 AD0 11 − 10 − 9 − 8 − SYMBOL BIT SYMBOL Table 3 BIT 15 to 12 11 to 8 7 to 5 − 7 GRF SUM2 6 GRF SUM1 5 GRF SUM0 4 DVD_ MILVL 3 CD_MILVL 2 DVD_ LDON 1 CD_LDON 0 PWRON Description of register bits (address 0H) SYMBOL AD[3:0] GRFSUM[2:0] 0000 = address 0H not used Gain of RFSUM input stage. 000 = −6 dB 001 = 0 dB 010 = 6 dB 011 = 12 dB 100 = 18 dB FUNCTION 4 DVD_MILVL DVD monitor input level. 0 = 150 mV; 1 = 180 mV. 17 2003 Sep 03 Philips Semiconductors Product specification High speed advanced analog DVD signal processor and laser supply BIT 3 2 1 0 7.3.2 Table 4 BIT SYMBOL SYMBOL CD_MILVL DVD_LDON CD_LDON PWRON FUNCTION CD monitor input level. 0 = 150 mV; 1 = 180 mV. DVD laser on. 0 = laser off; 1 = laser on. CD laser on. 0 = laser off; 1 = laser on. Power on. 0 = STANDBY mode; 1 = power on. TZA1038HW REGISTER 1: SERVO AND RF MODES Register address 1H 15 AD3 14 AD2 13 AD1 12 AD0 11 DPD_DCC 10 − 9 − 8 RAD_pol BIT SYMBOL Table 5 BIT 15 to 12 11 10 and 9 8 7 and 6 5 4 3 to 1 7 − 6 − 5 DOCEN 4 Focus_ mode 3 RT_mode2 2 RT_mode1 1 RT_mode0 0 RFSUM Description of register bits (address 1H) SYMBOL AD[3:0] DPD_DCC − RAD_pol − DOCEN Focus_mode RT_mode[2:0] 0001 = address 1H RF offset DAC for DPD signal control. 0 = DAC controlled by register 4, bits RFOFFSL[5:0]; 1 = DAC controlled by register 5, bits RFOFFSS[5:0]. not used Radial polarity switch. 0 = inverse; 1 = normal (default). not used Drop-out concealment enable. 0 = disable; 1 = enable. Focus mode. 0 = two-channel focus (channels B and C only); 1 = four-channel focus. Radial tracking mode. 000 = DPD2; DPD = phase (A,D) 001 = push-pull; channels A,D only 100 = DPD2; DPD = phase (A + C, B + D) 101 = push-pull; four channels 110 = DPD4; DPD = phase (A,D) + phase (C,B) X11 = TBPP channels E and F FUNCTION 0 RFSUM RF channel selection. 0 = diode inputs selected; 1 = RFSUM input selected. 2003 Sep 03 18 Philips Semiconductors Product specification High speed advanced analog DVD signal processor and laser supply 7.3.3 Table 6 BIT SYMBOL REGISTER 2: FOCUS OFFSET DAC Register address 2H 15 AD3 14 AD2 13 AD1 12 AD0 11 K2_Mode 10 FOFFSEN TZA1038HW 9 β4 8 β3 BIT SYMBOL Table 7 BIT 15 to 12 11 10 9 to 5 4 to 0 7.3.4 Table 8 BIT SYMBOL 7 β2 6 β1 5 β0 4 − 3 − 2 − 1 − 0 − Description of register bits (address 2H) SYMBOL AD[3:0] K2_Mode FOFFSEN β[4:0] − 0010 = address 2H K2 mode. 0 = disable; 1 = enable. Focus offset enable. 0 = enable; 1 = disable. Focus offset compensation. 0 0000 to 11111: β = 0 to β = 31⁄32. not used FUNCTION REGISTER 3: RF PATH GAIN Register address 3H 15 AD3 14 AD2 13 AD1 12 AD0 11 G11 10 G10 9 G21 8 G20 BIT SYMBOL Table 9 BIT 15 to 12 7 G33 6 G32 5 G31 4 G30 3 − 2 − 1 − 0 − Description of register bits (address 3H) SYMBOL AD[3:0] 0011 = address 3H First RF amplifier stage gain. 00 = 0 dB 01 = 6 dB 10 = 12 dB 11 = not used FUNCTION 11 and 10 G1[1:0] 9 and 8 G2[1:0] Second RF amplifier stage gain. 00 = 6 dB 01 = 12 dB 10 = 18 dB 11 = 24 dB 7 to 4 3 to 0 G3[3:0] − Third RF amplifier stage gain. 0000 to 1111: 0 to 13 dB in 0.8 dB steps. not used 2003 Sep 03 19 Philips Semiconductors Product specification High speed advanced analog DVD signal processor and laser supply 7.3.5 REGISTER 4: RF LEFT AND RIGHT, OR SUM OFFSET COMPENSATION TZA1038HW Table 10 Register address 4H BIT SYMBOL 15 AD3 14 AD2 13 AD1 12 AD0 11 RFOFFSL5 10 RFOFFSL4 9 RFOFFSL3 8 RFOFFSL2 BIT SYMBOL 7 6 5 RFOFFSR5/ RFOFFSS5 4 RFOFFSR4/ RFOFFSS4 3 RFOFFSR3/ RFOFFSS3 2 RFOFFSR2/ RFOFFSS2 1 RFOFFSR1/ RFOFFSS1 0 RFOFFSR0/ RFOFFSS0 RFOFFSL1 RFOFFSL0 Table 11 Description of register bits (address 4H) BIT 15 to 12 11 to 6 SYMBOL AD[3:0] RFOFFSL[5:0] 0100 = address 4H Left channel RF offset compensation definition. bit RFSUM = 0: left RF channel offset compensation value bit RFSUM = 1: not used 5 to 0 RFOFFSR[5:0] Right channel RF offset compensation definition. bit RFSUM = 0: right RF channel offset compensation value (symbol is RFOFFSR) bit RFSUM = 1 and bit DPD_DCC = 1: not used bit RFSUM = 1 and bit DPD_DCC = 0: the decoder controls DPD and RFSUM channels automatically, in parallel and with same values (symbol is RFOFFSS). 7.3.6 REGISTER 5: RF SUM OFFSET COMPENSATION FUNCTION Table 12 Register address 5H BIT SYMBOL 15 AD3 14 AD2 13 AD1 12 AD0 11 − 10 − 9 − 8 − BIT SYMBOL 7 − 6 − 5 RFOFFSS5 4 RFOFFSS4 3 RFOFFSS3 2 RFOFFSS2 1 RFOFFSS1 0 RFOFFSS0 Table 13 Description of register bits (address 5H) BIT 15 to 12 11 to 6 5 to 0 − RFOFFSS[5:0] SYMBOL AD[3:0] 0101 = address 5H not used RF offset compensation definition. bit RFSUM = 0: not used bit RFSUM = 1 and bit DPD_DCC = 0: not used bit RFSUM = 1 and bit DPD_DCC = 1: the decoder controls RFSUM channels; the DPD channels can be set independently from the microprocessor. FUNCTION 2003 Sep 03 20 Philips Semiconductors Product specification High speed advanced analog DVD signal processor and laser supply 7.3.7 REGISTER 6: SERVO GAIN AND DYNAMIC RADIAL OFFSET COMPENSATION FACTOR TZA1038HW Table 14 Register address 6H BIT SYMBOL 15 AD3 14 AD2 13 AD1 12 AD0 11 GLFR3 10 GLFR2 9 GLFR1 8 GLFR0 BIT SYMBOL 7 GLFC3 6 GLFC2 5 GLFC1 4 GLFC0 3 α3 2 α2 1 α1 0 α0 Table 15 Description of register bits (address 6H) BIT 15 to 12 11 to 8 7 to 4 3 to 0 SYMBOL AD[3:0] GLFR[3:0] GLFC[3:0] α[3:0] 0110 = address 6H Low frequency gain, radial path output stage. 0000 to 1000: −15 to +9 dB in 3 dB steps. Low frequency gain, central path output stage. 0000 to 1000: −15 to +9 dB in 3 dB steps. Dynamic radial offset compensation factor. 0000 to 1111: 0.60 to 1.35 in 0.05 steps; 1000 = balanced value (default). FUNCTION 7.3.8 REGISTER 7: SERVO PATH GAIN AND BANDWIDTH AND RF PATH BANDWIDTH AND PRE-EMPHASIS Definitions in register 7 are intended mainly for software compatibility with the TZA1033HL/V1. New features that require more bit-space to program are moved to registers 14 and 15. Only DPD stretch remains programmed in register 7. Some parameters are slightly modified. Table 16 Register address 7H BIT SYMBOL 15 AD3 14 AD2 13 AD1 12 AD0 11 DPDLPF1 10 DPDLPF0 9 DPD_ stretch2 1 fstart_DPD1 8 DPD_ stretch1 0 fstart_DPD0 BIT SYMBOL 7 DPD_ stretch0 6 5 4 EQRF2 3 EQRF1 2 EQRF0 DPD_ DVDALAS_ testmode mode Table 17 Description of register bits (address 7H) FUNCTION BIT 15 to 12 SYMBOL K2_Mode = 0 AD[3:0] 0111 = address 7H DPD low-pass filter. 0X : B−3dB = 50 MHz (equivalent to TZA1023) 1X : B−3dB = 10 MHz 11 and 10 DPDLPF[1:0] K2_Mode = 1 0111 = address 7H not applicable 2003 Sep 03 21 Philips Semiconductors Product specification High speed advanced analog DVD signal processor and laser supply FUNCTION BIT 9 to 7 SYMBOL K2_Mode = 0 DPD_stretch [2:0] DPD pulse stretcher (tP). 000 = 1.9 ns 001 = 3.8 ns (equivalent to TZA1023) 010 = 7.5 ns 011 = 15 ns 100 = 30 ns 101 = not used 6 5 DPD_ testmode DVDALAS_ mode For factory test purposes only. DVDALAS mode bit. 0 = disables control of bits 11 to 6 and creates behaviour equivalent to TZA1023; 1 = enables DPD low-pass filter and time stretcher equivalent to TZA1033HL/V1. RF channel low-pass filter (BRF). 001 = 10 MHz Start frequency lead/lag filter, DPD block. 00 = 1 MHz 01 = 5 MHz 10 = 10 MHz 11 = not used 7.3.9 REGISTER 8: RF CHANNEL SELECTION TZA1038HW K2_Mode = 1 DPD pulse stretcher (tP). 000 = 30 ns 001 = 15 ns 010 = 7.5 ns 011 = 3.8 ns 100 = 1.9 ns 101 = 1.2 ns For factory test purposes only. not applicable 4 to 2 1 and 0 EQRF[2:0] fstart_DPD[1:0] not applicable not applicable Table 18 Register address 8H BIT SYMBOL 15 AD3 14 AD2 13 AD1 12 AD0 11 − 10 − 9 − 8 − BIT 7 6 5 SW-Cmute 4 SW-Cinv 3 SW-Bmute 2 SW-Binv 1 SW-Amute 0 SW-Ainv SYMBOL SW-Dmute SW-Dinv Table 19 Description of register bits (address 8H) BIT 15 to 12 11 to 8 7 6 5 4 3 − SW-Dmute SW-Dinv SW-Cmute SW-Cinv SW-Bmute SYMBOL AD[3:0] 1000 = address 8H. not used 0 = pass D signal; 1 = mute D signal. 0 = pass D signal with no inversion; 1 = pass D signal with inversion. 0 = pass C signal; 1 = mute C signal. 0 = pass C signal with no inversion; 1 = pass C signal with inversion. 0 = pass B signal; 1 = mute B signal. FUNCTION 2003 Sep 03 22 Philips Semiconductors Product specification High speed advanced analog DVD signal processor and laser supply BIT 2 1 0 7.3.10 SYMBOL SW-Binv SW-Amute SW-Ainv FUNCTION TZA1038HW 0 = pass B signal with no inversion; 1 = pass B signal with inversion. 0 = pass A signal; 1 = mute A signal. 0 = pass A signal with no inversion; 1 = pass A signal with inversion. REGISTER 11: RADIAL SERVO OFFSET CANCELLATION Table 20 Register address BH BIT SYMBOL 15 AD3 14 AD2 13 AD1 12 AD0 11 LFOFFS1 10 LFOFFS0 9 SERVOOS 8 FTCHBW BIT SYMBOL 7 ROFFSE3 6 ROFFSE2 5 ROFFSE1 4 ROFFSE0 3 ROFFSF3 2 ROFFSF2 1 ROFFSF1 0 ROFFSF0 Table 21 Description of register bits (address BH) BIT 15 to 12 SYMBOL AD[3:0] 1011 = address BH DC offset compensation for LF path (VLFOFFS). Common for all servo inputs: SERVOOS = 0 00 = 0 mV 01 = 5 mV 10 = 10 mV 11 = 15 mV 9 8 7 to 4 3 to 0 SERVOOS FTCHBW ROFFSE[3:0] ROFFSF[3:0] SERVOOS = 1 00 = 0 mV 01 = 15 mV 10 = 30 mV 11 = 45 mV FUNCTION 11 and 10 LFOFFS[1:0] Servo offset scale (DACs ROFFSx, COFFSx and LFOFFS). 0 = normal range; 1 = triple range. FTC bandwidth. 0 = 600 kHz (approximately); 1 = 1.2 MHz (approximately.) Programmable DC offset compensation for radial servo path (E input). SERVOOS = 0: 0 to 20 mV; bit SERVOOS = 1: 0 to 60 mV. Programmable DC offset compensation for radial servo path (F input). SERVOOS = 0: 0 to 20 mV; bit SERVOOS = 1: 0 to 60 mV. 7.3.11 REGISTER 12: CENTRAL SERVO OFFSET CANCELLATION INPUTS A AND B Table 22 Register address CH BIT SYMBOL 15 AD3 14 AD2 13 AD1 12 AD0 D11 TSTDPDRF D10 TSTSRV2 D9 TSTSRV1 D8 TSTSRV0 BIT SYMBOL D7 COFFSA3 D6 COFFSA2 D5 COFFSA1 D4 COFFSA0 D3 COFFSB3 D2 COFFSB2 D1 COFFSB1 D0 COFFSB0 2003 Sep 03 23 Philips Semiconductors Product specification High speed advanced analog DVD signal processor and laser supply Table 23 Description of register bits (address CH) BIT 15 to 12 11 10 to 8 SYMBOL AD[3:0] TSTDPDRF TSTSRV[2:0] 1100 = address CH FUNCTION TZA1038HW DPD RF test bit. With this bit the DPD filter performance is checked. 0 = normal operation; 1 = RF signal filtered by the DPD block is connected to the RF output. Test matrix for servo signals to pin OCENTRAL. 000 = normal operation 001 = filter DAC current for test purposes 011 = CA (sum A to D) 100 = channel A 101 = channel B 110 = channel C 111 = channel D 7 to 4 3 to 0 COFFSA[3:0] COFFSB[3:0] Central servo input A offset cancellation. Bit SERVOOS = 0: 0 to 20 mV; bit SERVOOS = 1: 0 to 60 mV. Central servo input B offset cancellation. Bit SERVOOS = 0: 0 to 20 mV; bit SERVOOS = 1: 0 to 60 mV. 7.3.12 REGISTER 13: CENTRAL SERVO OFFSET CANCELLATION INPUTS C AND D Table 24 Register address DH BIT SYMBOL 15 AD3 14 AD2 13 AD1 12 AD0 11 RFonly 10 − 9 − 8 − BIT SYMBOL 7 COFFSC3 6 COFFSC2 5 COFFSC1 4 COFFSC0 3 COFFSC3 2 COFFSC2 1 COFFSC1 0 COFFSC0 Table 25 Description of register bits (address DH) BIT 15 to 12 11 10 to 8 7 to 4 3 to 0 SYMBOL AD[3:0] RFonly − COFFSC[3:0] COFFSD[3:0] 1101 = address DH Operation mode. 0 = normal operation; 1 = RF only mode (servo outputs OA to OD, S1 and S2 are 3-state). not used Central servo input C offset cancellation. Bit SERVOOS = 0: 0 to 20 mV; bit SERVOOS = 1: 0 to 60 mV. Central servo input D offset cancellation. Bit SERVOOS = 0: 0 to 20 mV; bit SERVOOS = 1: 0 to 60 mV. FUNCTION 2003 Sep 03 24 Philips Semiconductors Product specification High speed advanced analog DVD signal processor and laser supply 7.3.13 REGISTER 14: RF FILTER SETTINGS TZA1038HW Table 26 Register address EH BIT SYMBOL 15 AD3 14 AD2 13 AD1 12 AD0 11 − 10 − 9 RFNFEN 8 RFEQEN BIT SYMBOL 7 RFKEQ 6 BWRF6 5 BWRF5 4 BWRF4 3 BWRF3 2 BWRF2 1 BWRF1 0 BWRF0 Table 27 Description of register bits (address EH); bit K2_Mode = 1 BIT 15 to 12 9 8 7 6 to 0 7.3.14 11 and 10 − RFNFEN RFEQEN RFKEQ BWRF[6:0] SYMBOL AD[3:0] 1110 = address EH not used Noise filter enable. 0 = disable; 1 = enable. Equalizer enable. 0 = disable; 1 = enable. Boost factor. 0 = boost factor low; 1 = boost factor high. Bandwidth limitation in RF path. 000 0000 to 111 1111: f0(RF) = 12 to 145 MHz. FUNCTION REGISTER 15: DPD FILTER SETTINGS Table 28 Register address FH BIT SYMBOL 15 AD3 14 AD2 13 AD1 12 AD0 11 − 10 − 9 − 8 − BIT SYMBOL 7 − 6 − 5 DPD_LL2 4 DPD_LL1 3 DPD_LL0 2 DPD_LPF2 1 DPD_LPF1 0 DPD_LPF0 2003 Sep 03 25 Philips Semiconductors Product specification High speed advanced analog DVD signal processor and laser supply Table 29 Description of register bits (address FH); bit K2_Mode = 1 BIT 15 to 12 11 to 6 5 to 3 − DPD_LL[2:0] SYMBOL AD[3:0] 1111 = address FH not used DPD lead/lag filter start frequency (fstart). 000 = 1 MHz 001 = 5 MHz 010 = 10 MHz 011 = 18 MHz 100 = 24 MHz 2 to 0 DPD_LPF[2:0] DPD low-pass filter (f−3dB). 000 = 10 MHz 001 = 50 MHz 010 = 100 MHz 011 = 180 MHz 111 = 240 MHz 7.4 Internal digital control, serial bus and external digital input signal relationships 7.5 Signal descriptions FUNCTION TZA1038HW The settings of all internal switches, DACs and modes of operation can be programmed via the serial bus. There are also a few external digital signals which influence the programmed settings. 7.4.1 STANDBY MODE The variables A1 to A3, ARFSUM, ALFC and ALFR, are the linear equivalents of G1 to G3, GRFSUM, GLFC and GLFR. 7.5.1 DATA PATH SIGNALS THROUGH PINS A TO D With bit RFSUM = 0: (DVDRFP − DVDRFN) = A2 × 1/4 × [SW-A {(A − OPUREF) × A1 − RFOFFSL} + SW-B {(B − OPUREF) × A1 − RFOFFSL} + SW-C {(C − OPUREF) × A1 − RFOFFSR} + SW-D {(D − OPUREF) × A1 − RFOFFSR}] RFP = RFREF + 0.5 × A3 × (DVDRFP − DVDRFN) RFN = RFREF − 0.5 × A3 × (DVDRFP − DVDRFN) Thus: RFdif = A+B+C+D A3 × A2 × A1 ×  ----------------------------------- – OPUREF – RF OFFS   4 To ensure a safe start-up, the TZA1038HW has an internal Power-on reset that resets on bit PWRON. During STANDBY mode, most circuits, including laser supplies, are switched off. bit CD_LDON = 1 if CD laser is on and POWERON bit DVD_LDON = 1 if DVD laser is on and POWERON. 7.4.2 RF ONLY MODE The servo outputs can be disabled for easy interfacing in systems where two front-end signal processors are used. This mode will set the outputs OA to OD, S1 and S2 to 3-state. The RF data path remains active. 2003 Sep 03 26 Philips Semiconductors Product specification High speed advanced analog DVD signal processor and laser supply Switches SW-A to SW-D can be programmed 1, −1 or 0 (respectively pass, invert or not pass the signal) for each channel. In this way the data can be read by any combination of diode inputs. The first gain stage also carries the signals for DPD tracking. Therefore this stage will also be active when RFSUM input and DPD is selected. The DC offset cancellation is also active in this situation but left and right channels are controlled from a single DAC. Also in this situation, the A to D and RFSUM inputs are used simultaneously. Control of the DC offset DACs can be chosen to be from the same register or from two independent registers (registers 4 and 5). 7.5.2 DATA SIGNAL PATH THROUGH INPUT PINS RFSUMP AND RFSUMN TZA1038HW 1 1 H n ( s ) = -------------------------------------------- × ---------------------2 s s s 1 + -------------- + ------------ 1 + -----------ω 0RF 2ω 0RF ω 0RF The corner frequency ω0RF is equal to that of the equalizer filter. The noise filter is switched on with bit RFNFEN. 7.5.4 FOCUS SIGNALS Focus servo signals: 1 OA = ------------ × ALFC × (A − OPUREF + LFOFFS − COFFSA) R LFC + β × FOFFS 1 OB = ------------ × ALFC × (B − OPUREF + LFOFFS − COFFSB) R LFC + (1 − β) × FOFFS 1 OC = ------------ × ALFC × (C − OPUREF + LFOFFS − COFFSC) R LFC + β × FOFFS 1 OD = ------------ × ALFC × (D − OPUREF + LFOFFS − COFFSD) R LFC + (1 − β) × FOFFS The parameter β can be programmed via the serial bus. The focus offset DAC can be switched on with the control bit FOFFSEN. 7.5.5 RADIAL SIGNALS With bit RFSUM = 1: (DVDRFP − DVDRFN) = ARFSUM × [RFSUMP − RFSUMN − RFOFFSS] RFP = RFREF + 0.5 × A3 × (DVDRFP − DVDRFN) RFN = RFREF − 0.5 × A3 × (DVDRFP − DVDRFN) Thus: RFdif = ARFSUM × [RFSUMP − RFSUMN − RFOFFSS] 7.5.3 HF FILTERING The differential HF signal from the G3 stage is sent to a filter section that consists of an equalizer and a noise filter, which are controlled by bits BWRF, RFKEQ, RFEQEN and RFNFEN. The equalizer has a transfer function H1 (s) which is modelled after a target transfer function He (s): s 1 + k × -------------2 ω 0RF 1 H e ( s ) = ------------------------------------------------------- × -----------------------------2 s s s -----------1 + --------------- + α × ------------ 1 + τ × ω 2 0RF ω 0RF ω 0RF This represents a third-order equi-ripple phase filter with a good delay response. The boost factor k is programmable via the serial bus control bit RFKEQ. The corner frequency ω0RF = 2πf0RF is programmable via control parameter bit BWRF. The equalizer is switched on with control bit RFEQEN. The noise filter has a transfer function H2 (s) which is modelled after a third-order Butterworth low-pass filter with target transfer function Hn (s): 2 7.5.5.1 DPD signals (DVD-ROM mode) with no drop-out concealment DPD tracking can be activated with bits RT_mode[2:0] of register 1. Input signals are taken from the diode inputs A to D, through the input stage G1 and the DC offset cancellation DAC. When bit RFSUM = 0, the input stage is also used for the RF signal. When bit RFSUM = 1, the setting for G1 and DC offset control can be independent of the setting for the data signal which goes through RFSUM. ∆t S1DPD = I(FS)(DPD) × ------ + IREFRAD TP ∆t S2DPD = −I(FS)(DPD) × ------ + IREFRAD TP ∆t ------ is the time difference between the two input signals, TP relative to the period time TP of the input signal. I(FS)(DPD) is the full scale range. 2003 Sep 03 27 Philips Semiconductors Product specification High speed advanced analog DVD signal processor and laser supply The bandwidth of the DPD signal is limited by the 100 kHz phase detector integration filters and the bandwidth of the output stages (100 kHz for S1 and S2). The input signals used for DPD depend on the programmed radial tracking mode (bits RT_mode[2:0]): ∆t ∆t DPDmode = DPD2: ------ (A,D) or DPD2: ------ (A + C, B + D) TP TP ∆t ∆t DPDmode = DPD4: 0.5[ ------ (A,D) + ------ (C,B)] TP TP ∆t Range of ------ is from −0.5 to + 0.5. TP ∆t ------ > 0 if A,C phase leads with respect to D,B phase. TP FTC = (S1 − S2) × (RFTC + FTCREF) For S1 and S2 bit RAD_pol is assumed to be set to logic 1. Otherwise the signals appearing at S1 and S2 will be swapped. TZA1038HW For S1 and S2 bit RAD_pol is assumed to be set to logic 1. Otherwise the signals appearing at S1 and S2 will be swapped. The DPD detection can not work properly when the input signal becomes very small. The output of the DPD may then show a significant offset. The DOC may not conceal this offset completely because: • DOC is gradually controlled from the CA signal • The CA signal may not become 0 during disc-defect. 7.5.5.3 Three-beam push-pull (CD mode) When the three-beam system is used, the radial signals S1 and S2 can be composed from inputs E and F.  E – OPUREF + LF OFFS + R OFFSE  S1 PP = A LFR ×  ----------------------------------------------------------------------------------------  R LFR    F – OPUREF + LF OFFS – R OFFSF  S2 PP = A LFR ×  ---------------------------------------------------------------------------------------  R LFR   FTC = (S1 − S2) × RFTC + FTCREF (bandwidth limited to 600 kHz). For S1 and S2 bit RAD_pol is assumed to be set to logic 1. Otherwise the signals appearing at S1 and S2 will be swapped. 7.5.5.2 DPD signals (DVD-ROM mode) with drop-out concealment With bit DOCEN = 1, drop-out concealment is activated and the S1 and S2 outputs change: • The common mode level (IREFRAD) is now determined by the CA signal • The scaling changes. At low signal levels (SUM < DOCthreshold), the contribution ∆t of ------ is reduced smoothly. TP ∆t S1DPD = C × I(FS)(DPD)(DOC) × ------ + 0.25 × CA. TP ∆t S2DPD = −C × I(FS)(DPD)(DOC) × ------ + 0.25 × CA. TP Where: • I(FS)(DPD)(DOC) is the full scale range • C = concealment multiplier, C = 0 to 1 when CA is 0 to DOCthreshold • CA = OA + OB + OC + OD • DOCthreshold is typically 3 µA. 7.5.5.4 Enhanced push-pull Top hold push-pull method is supported but only in conjunction with a compatible decoder. The peak hold function is executed in the decoder, by measuring the mirror levels of the gap-zones in each header. The TZA1038HW will compensate for offset errors in two ways: • The DC offset from the pick-up can be compensated by means of a DAC (COFFSx) in each channel • The dynamic offsets can be compensated by means of the multiplier ratio α. The correction values must be calculated in the decoder and programmed via the serial bus. The method is called the enhanced push-pull method. For S1 and S2 bit RAD_pol is assumed to be set to logic 1. Otherwise the signals appearing at S1 and S2 will be swapped. 2003 Sep 03 28 Philips Semiconductors Product specification High speed advanced analog DVD signal processor and laser supply  A + B – 2 × OPUREF + 2 × LF OFFS – ( C OFFSA – C OFFSB )  S1 PP = A LFR × α ×  -----------------------------------------------------------------------------------------------------------------------------------------------------  R LFPP    C + D – 2 × OPUREF + 2 × LF OFFS – ( C OFFSC – C OFFSD )  S2 PP = A LFR × ( 2 – α ) ×  -------------------------------------------------------------------------------------------------------------------------------------------------------  R LFPP   or:  A – OPUREF + LF OFFS – C OFFSA  S1 PP = A LFR × α ×  ----------------------------------------------------------------------------------------  R LFPP    D – OPUREF + LF OFFS – C OFFSD  S2 PP = A LFR × ( 2 – α ) ×  ----------------------------------------------------------------------------------------  R LFPP   TZA1038HW The signals from the B and C channels can be switched off, depending on the photodiode configuration (bit RT_mode[2:0]). 2003 Sep 03 29 Philips Semiconductors Product specification High speed advanced analog DVD signal processor and laser supply 8 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOLS VDD Tamb Vesd PARAMETER supply voltage ambient temperature electrostatic discharge voltage Machine Model (MM); note 1 CONDITIONS − −40 Human Body Model (HBM); note 1 − − MIN. TZA1038HW MAX. 5.5 +85 2000 200 V UNIT °C V V Note 1. ESD behaviour is tested in accordance with JEDEC II standard: HBM is equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor. MM is equivalent to discharging a 200 pF capacitor through a 0.75 µH series inductor. 9 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient in free air CONDITIONS VALUE 27 UNIT K/W 10 CHARACTERISTICS VDDA = 5 V; VDDD3 = 3.3 V; VDDD5 = 5 V; VRFREF = 1.2 V; Tamb = 25 °C; RF inputs A to D are referred to pin OPUREF; f0(RF) = 50 MHz; Rext = 12.1 kΩ (pin REXT); RF output max. load on pins RFP and RFN is ZO(max): 5 pF parallel with 10 kΩ to VSS; unless otherwise specified. SYMBOL Tamb Supplies VDDA1, VDDA2, analog supply VDDA3, VDDA4 voltage VDDD3 VDDD5 VI(logic) VPOR IDD 3 V digital supply voltage 5 V digital supply voltage logic input compatibility Power-on reset voltage supply current without laser supply STANDBY mode note 1 4.5 2.7 4.5 2.7 3.3 − − 5.0 3.3 5.0 3.3 3.5 98 − 5.5 5.5 5.5 5.5 3.7 120 1 V V V V V mA mA PARAMETER ambient temperature CONDITIONS −40 MIN. − TYP. +85 MAX. UNIT °C 2003 Sep 03 30 Philips Semiconductors Product specification High speed advanced analog DVD signal processor and laser supply SYMBOL PARAMETER CONDITIONS MIN. TYP. TZA1038HW MAX. VDDA − 2 UNIT RF data path, input: pins A to D and OPUREF Vi(OPUREF) Vi(RF)(FS) input voltage on pin OPUREF input voltage on pins A to D for full-scale at output note 2 referred to VOPUREF G1 = 0 dB G1 = 6 dB G1 = 12 dB VI(DC) VRFOFFSL, VRFOFFSR ∆VRFOFFSL, ∆VRFOFFSR II(bias) Zi ARF(min) ARF(max) DC component of input voltage DC offset compensation voltage DC offset compensation voltage resolution input bias current on pins A to D input impedance of pins A to D minimum gain maximum gain G1 = 0 dB, G2 = 6 dB, G3 = 0 dB; note 3 G1 = 12 dB, G2 = 24 dB, G3 = 13 dB; note 3 G1 = 0 dB G1 = 6 dB G1 = 12 dB G1 = 0 dB G1 = 6 dB G1 = 12 dB − − − 1.8 350 175 90 − − − − 100 4 48 − − − 0.5VDDA 450 225 120 7.1 3.6 1.9 − − 6 49 600 300 150 VDDA − 1.4 550 275 160 − − − 5 − 8 52 mV mV mV V mV mV mV mV mV mV µA kΩ dB dB 1.5 0.5VDDA V TCgain ∆G1 ∆G2 gain temperature coefficient first RF amplifier stage gain step size second RF amplifier stage gain step size − 5 5 −0.025 6 6 − 7 7 dB/°C dB dB RF data path, input: pins RFSUMP and RFSUMN VI(DC) VI(SUM)(dif) DC input voltage differential input voltage with respect to VSS GRFSUM = −6 dB GRFSUM = 0 dB GRFSUM = 6 dB GRFSUM = 12 dB GRFSUM = 18 dB II(bias) ZI input bias current input impedance note 4 1.3 − − − − − − 50 − − − − − − 5 − VDDA − 1.0 1800 1400 700 350 175 − 600 V mV mV mV mV mV µA kΩ 2003 Sep 03 31 Philips Semiconductors Product specification High speed advanced analog DVD signal processor and laser supply SYMBOL VRFOFFSS PARAMETER DC offset compensation voltage CONDITIONS GRFSUM = −6 dB GRFSUM = 0 dB GRFSUM = 6 dB GRFSUM = 12 dB GRFSUM = 18 dB ∆VRFOFFSS DC offset compensation voltage resolution GRFSUM = −6 dB GRFSUM = 0 dB GRFSUM = 6 dB GRFSUM = 12 dB GRFSUM = 18 dB ARFSUM(min) ARFSUM(max) TCgain ∆GRFSUM minimum gain maximum gain gain temperature coefficient RFSUM amplifier stage gain step size notes 3 and 5 notes 3 and 5 − − − − − − − − − − −8 29 − 5 MIN. 850 425 210 105 27 13.5 6.7 3.4 1.7 −6 31 −0.02 6 TYP. 1700 TZA1038HW MAX. − − − − − − − − − − −4 33 − 7.5 UNIT mV mV mV mV mV mV mV mV mV mV dB dB dB/°C dB RF data path, filter and output Vn(o)(dif)(rms) differential RF output noise voltage (RMS value) diode input: BWRF = 127; f = 0 to 500 MHz; RFNFEN = 1; note 6 A = 12 + 24 + 6 dB; RFEQEN = 0 A = 12 + 6 + 6 dB; RFEQEN = 0 A = 12 + 6 + 6 dB; RFEQEN = 1; RFKEQ = 0 A = 12 + 6 + 6 dB; RFEQEN = 1; RFKEQ = 1 SUM input: BWRF = 127; f = 0 to 500 MHz; RFNFEN = 1; note 6 A = 12 + 6 + 6 dB; RFEQEN = 0 VOO(ref) DC output offset VI(RF) = 0 V; voltage with respect DVDOFFS = 0; note 7 to VRFREF VRFREF = 1.2 V − 12 − mV − − − 7 6 9 − − mV mV mV − 11 − mV − − − 60 100 mV mV VRFREF = 0.8 to 2.1 V − 2003 Sep 03 32 Philips Semiconductors Product specification High speed advanced analog DVD signal processor and laser supply SYMBOL Vo(dif)(p-p) PARAMETER differential output voltage on pins RFP and RFN (peak-to-peak value) DC output voltage on pins RFP and RFN input reference voltage for common mode output on pin RFREF output impedance on pins RFP and RFN third RF amplifier note 8 stage gain step size equalizer amplitude flatness between error f0 and 100 kHz noise filter amplitude error −3 dB bandwidth of RFP and RFN signal path noise filter and equalizer corner frequency noise filter and equalizer corner frequency step size flatness delay in RF data path flatness between f0 and 100 kHz RFEQEN = 0; RFNFEN = 0 BWRF = 0 BWRF = 127 ∆BWRF = 1; note 9 CONDITIONS − MIN. − TYP. TZA1038HW MAX. 1.4 UNIT V VO(RF)(DC) 0.35 − VDDA − 1.9 V Vi(RFREF)(CM) 0.8 1.2 2.1 V Ro − 100 − Ω ∆G3 ||h1| − |he|| ||h1| − |hn|| BRF(−3dB) − − − 200 0.85 − − 300 1.3 1.5 1.5 − dB dB dB MHz f0(RF) 8 100 0.73 12.0 145 1.06 14.5 182 1.32 MHz MHz MHz ∆f0(RF) td(RF) equalizer off; f = 0 to 150 MHz equalizer on; f = 0 to 100 MHz; BWRF = 127 equalizer and noise filter on; f = 0 to 0.7f0(RF) BWRF = 0 BWRF = 127 − − − − 0.1 0.5 ns ns − − − 1.125 1.18 − − − 1.25 1.31 3.5 0.6 0.5 1.375 1.44 ns ns µs tst(G3) α τ amplifier G3 gain note 10 change settling time equalizer parameter see Section 7.5.3 equalizer parameter see Section 7.5.3 2003 Sep 03 33 Philips Semiconductors Product specification High speed advanced analog DVD signal processor and laser supply SYMBOL k PARAMETER CONDITIONS RFKEQ = 0 RFKEQ = 1 LF servo path VI(LF) input voltage range path to focus servo outputs referred to VOPUREF path to radial servo outputs referred to VOPUREF VO(LF) VLFOFFS(CM) servo output voltage common mode offset compensation voltage DC offset voltage resolution offset voltage compensation DC offset voltage resolution FTC reference input reference voltage FTC output voltage (peak-to-peak value) output current focus servo outputs radial servo outputs IFOFFS ∆IFOFFS I(FS)(DPD) focus compensation from FOFFS DAC current compensation current resolution DPD full scale current f = 3 MHz; Vi = 100 mV (p-p) DOCEN = 0 DOCEN = 1 Ith(DOC) IREFRAD(CM) DOCEN threshold current common mode DC current in DPD mode SUM value DOCEN = 0 17 4.5 2.5 − 20 6.6 3 3.5 SERVOOS = 0 SERVOOS = 1 700 − 3.2 4.8 MIN. 4.0 6.0 TYP. TZA1038HW MAX. 4.8 7.2 − UNIT equalizer parameter see Section 7.5.3 mV 500 − − mv −0.2 − − − 15 45 VDD − 2.5 − − V mV mV ∆VLFOFFS VROFFS, VCOFFS ∆VROFFS, ∆VCOFFS VI(FTCREF) VO(FTC)(p-p) SERVOOS = 0 SERVOOS = 1 SERVOOS = 0 SERVOOS = 1 SERVOOS = 0 SERVOOS = 1 4.25 13 − − 1.0 3.0 1.25 2.0 5 15 20 60 1.3 4 − − 5.75 17 − − 1.6 4.8 2.75 − mV mV mV mV mV mV V V IO(LF) 0 0 310 − − − 390 12 12 12 480 − µA µA nA nA 23 8 3.5 − µA µA µA µA 2003 Sep 03 34 Philips Semiconductors Product specification High speed advanced analog DVD signal processor and laser supply SYMBOL RLFC RLFR PARAMETER LF path input transresistance CD satellite path input transresistance DVD push-pull transresistance fast track count transimpedance gain range central channels gain resolution gain range radial channels gain resolution −3 dB bandwidth of LF path FTC bandwidth dynamic radial left right matching channel pair matching FTCHBW = 0 FTCHBW = 1; note 12 LRM CPM α=1 GLF = 0 dB; note 13 VI(LF) = 96 mV; pairs OA, OD or OC, OB VI(LF) = 48 mV; pair S1 and S2 α dynamic radial offset compensation factor dynamic radial offset compensation factor resolution −2 −7 0.6 − − − CONDITIONS GLFC = 0 dB GLFR = 0 dB; α = 1 10.5 11 MIN. 14 15 TYP. TZA1038HW MAX. 16.5 18 UNIT kΩ kΩ RLFPP RFTC GLFC ∆GLFC GLFR ∆GLFR BLF(−3dB) BFTC GLFR = 0 dB; α = 1 note 11 23 510 −15.5 − −15.5 − 60 − − −7 30 650 − 3 − 3 75 600 1200 − 36 800 +8.5 − +8.5 − 100 − − +7 kΩ kΩ dB dB dB dB kHz kHz kHz % +2 +7 1.35 %FS %FS ∆α − 0.05 − ALPC Automatic Laser Power Control Vi(mon) input voltage from laser monitor diode P-type monitor diode LOW level voltage HIGH level voltage N-type monitor diode LOW level voltage HIGH level voltage VO(laser) Vprot laser output voltage low supply voltage protection level 35 0.145 0.175 − 3.6 0.155 0.185 − 3.8 0.17 0.2 VDDL − 0.5 4.0 V V V V VDDA4 − 0.140 VDDA4 − 0.155 VDDA4 − 0.170 V VDDA4 − 0.215 VDDA4 − 0.190 VDDA4 − 0.180 V 2003 Sep 03 Philips Semiconductors Product specification High speed advanced analog DVD signal processor and laser supply SYMBOL ∆Vprot PARAMETER low supply voltage protection hysteresis laser monitor diode input current maximum current output to laser laser switch on time CONDITIONS − MIN. 200 TYP. TZA1038HW MAX. − UNIT mV II(mon) Io(laser)(max) ton(laser) VI(CM) VOL VOH VIO ILI AV tr, tf tres VIH VIL IIH − −120 − 0 0 VDDD3 − 0.5 − − − CL = 15 pF VI(dif) = 200 mV (p-p) − − 0.7VDDD3 − input incorporates internal pull-down resistor pins SIDA, SICL and SILD − − − 3 − − − − − 200 250 200 − − − 200 − − 2.5 0.5 VDDD3 10 100 − − − − 0.3VDDD3 100 nA mA ms FTC comparator common mode input voltage LOW-level output voltage HIGH-level output voltage input offset voltage input leakage current voltage gain rise and fall time response time V V V mV nA V/mV ns ns Serial bus interface (see Fig.8) HIGH-level input voltage LOW-level input voltage HIGH-level input current on pin TM input current start set-up time data set-up time data hold time clock HIGH time clock LOW time clock period load pulse set-up time load pulse HIGH time V V µA II tsu(strt) tsu(D) th(D) tclk(H) tclk(L) Tclk tsu(load) tload(H) Notes − 0 5 20 10 10 30 30 10 − − − − − − − − − 100 − − − − − − − − nA ns ns ns ns ns ns ns ns 1. Level follows the applied supply voltage at pin VDDD3. 2003 Sep 03 36 Philips Semiconductors Product specification High speed advanced analog DVD signal processor and laser supply TZA1038HW 2. This range for the servo path is designed to be larger than for the data path so that the servo path can handle out-of-focus situations. 3. A = 10 ( G1 + G2 + G3 ) ---------------------------------------20 [dB] or A = 10 ( Gsum + G3 ) ---------------------------------20 [dB] (see Section 7.5). 4. Input impedance depends on gain setting. Highest gain has lowest input impedance. 5. The gain of the RF sum channel, when programmed to −6 dB, will be increased when the supply voltage is below 4.8 V and at an ambient temperature of −40 °C. 6. Noise figures depend on gain and filter settings, examples given here. V RFP + V RFN 7. VOO(ref) = --------------------------------- – V RFREF 2 8. Integral range for G3 from minimum to maximum gain is 13 dB (typical). 9. At the transition BWRF = 63 to 64 the ∆f may be between −0.2 and +1.7 MHz 10. Faster for small steps. 11. Overall gain from input to output is determined by RFTC/RLFR or RFTC/RLFPP, depending on radial tracking mode, three-beam push-pull (CD) or DVD push-pull. Gain FTC scales with GFRR. When DPD tracking is selected the FTC gain is fixed. 12. High FTC bandwidth is achieved when IS1 and IS2 > 1.5 µA. 13. Channel pair matching is defined in % of full scale (FS) output at half of the full scale level. handbook, full pagewidth SICL t clk(H) t h(D) t su(D) SIDA D0 A3 T clk t clk(L) t su(strt) SILD t su(load) MGW495 Fig.8 Single word transmission. 2003 Sep 03 37 Philips Semiconductors Product specification High speed advanced analog DVD signal processor and laser supply 11 APPLICATION INFORMATION 11.1 Signal relationships 11.1.2 SERVO PATH TZA1038HW Simplified relationships between signals are described in this section. In the simplification, all built-in options for DVD-ROM are omitted. The variables A1 to A3, ALFC and ALFR, are the linear equivalents of bits G1 to G3, GLFC and GLFR. 11.1.1 DATA PATH The current through output pins OA to OD represents the low-pass filtered input voltage of each individual pick-up segment. The gain from input to output can be programmed to adapt to different disc types or pick-ups (offset cancellation is omitted for simplicity): V Ix × A LFC I Ox = -------------------------14 k Ω ( V I(A) + V I(B) ) × A LFR I S1 = ---------------------------------------------------- (in DVD push-pull mode) 30 k Ω ( V I(C) + V I(D) ) × A LFR I S2 = ---------------------------------------------------- (in DVD push-pull mode) 30 k Ω or: V I(E) × A LFR I S1 = ----------------------------- (in CD three-beam push-pull mode) 15 k Ω V I(F) × A LFR I S2 = ----------------------------- (in CD three-beam push-pull mode) 15 k Ω or: I S1 = I DC + I FS × phase difference (in DPD mode) I S2 = I DC – I FS × phase difference (in DPD mode) Where: • ALFC and ALFR are the programmable gains in central and radial paths • Gain should be programmed such that maximum signal levels fit into the range of the servo processor ADC • VI(A); VI(B); VI(C) and VI(D) are defined as input voltages at pins A to D with respect to pin OPUREF • IDC is a DC current that keeps IS1 and IS2 unipolar • IFS is the sensitivity to relative phase difference. ∆φ [ degrees ] ∆t Phase difference = ----- = --------------------------------- ; 360 Tp −180° < φ < + 180°. Pins RFP and RFN carry the RF data signals in opposite phases with respect to each other. This allows an ADC with a balanced or differential input to be used in the decoder. Depending on the DC input ranges of the ADC, in many cases the connection between TZA1038HW and the decoder can be a DC pin to pin connection. The common mode DC level of pins RFP and RFN can be chosen independently by means of input pin RFREF. If bit RFSUM = 0 • VRFP = VRFREF + 0.5 × A3 × A2 × A1 × (VI − VRFOFFS) • VRFN = VRFREF − 0.5 × A3 × A2 × A1 × (VI − VRFOFFS) • VRFDIF = A3 × A2 × A1 × (VI − VRFOFFS). If bit RFSUM = 1 • VRFP = VRFREF + 0.5 × ARFSUM × A3 × (VRFSUMP − VRFSU MN − VRFOFFSS) • VRFN = VRFREF − 0.5 × ARFSUM × A3 × (VRFSUMP − VRFSU MN − VRFOFFSS) • VRFDIF = ARFSUM × A3 (VRFSUMP − VRFSUMN − VRFOFFSS). Where: • A1, A2, A3 and ARFSUM are programmed gain values • VI = average input voltage at pins A to D, with respect to the voltage at pin OPUREF • VRFOFFS is the programmed RFOFFS DAC voltage (register 4 and register 5) • VRFREF is the input voltage at pin RFREF. Correct settings for VRFREF and VRFOFFS are required to keep both VRFP and VRFN at the DC voltage levels specified for the TZA1038HW and the decoder. 2003 Sep 03 38 Philips Semiconductors Product specification High speed advanced analog DVD signal processor and laser supply 11.2 Programming examples TZA1038HW Table 30 Sample of register values and mode settings. REGISTER VALUE (HEX) REGISTER 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Note 1. Use RFSUM input. DVD; LOW GAIN 005 01D 800 800 − 820 000 338 200 000 000 000 000 000 000 335 022 DVD; HIGH GAIN(1) 045 01D 800 − 800 410 000 778 200 000 000 000 000 000 000 335 022 CD; HIGH GAIN(1) 043 007 800 800 − 410 000 778 000 000 000 000 000 000 000 335 000 set bits BWRF to 80 MHz; RFEQEN = 1; RFNFEN = 1 set bits DPD_LL to 24 MHz; set bits DPD_LPF to 100 MHz MODE SETTINGS switch on the laser power; Vmon = 150 mV; set GRFSUM select diode or SUM inputs and corresponding tracking method set K2 mode set low RF gain = 18 dB + G3 set G1 for DPD (G3 = 0 dB in this example) approximation for DVDOFFS DAC optional second RF offset setting GLFC = GLFR = −6 dB (low gain) or +6 dB (high gain); α=1 set bits DPD_stretch to 1.9 ns enable inputs A to D for RF not used not used set for electrical offset compensation from pick-up (see Section 11.4) 2003 Sep 03 39 Philips Semiconductors Product specification High speed advanced analog DVD signal processor and laser supply 11.3 Energy saving TZA1038HW Bit PWRON can be used to bring the TZA1038HW into STANDBY mode reducing the supply current to approximately 0.5 mA. 11.4 11.4.1 Initial DC and gain setting strategy ELECTRICAL OFFSET FROM PICK-UP The test pin OCENTRAL can be useful to follow this procedure. This pin can be programmed to output a copy of the signal OA to OD (see register 12). 11.4.2 GAIN SETTING SERVO It is useful to compensate for electrical offset, especially with pick-ups that give a low output signal. It is possible to compensate for each individual servo channel. Due to internal circuitry, the TZA1038HW servo channels can handle only signals positive with respect to the reference input OPUREF. Therefore the potentially negative offset from the pick-up must first be cancelled. The LFOFFS DAC can be programmed to do this, and will apply this to all six channels at the same time. The LFOFFS DAC can be set to 0, 5, 10 or 15 mV. As a second step, the offset between each channel can be compensated by connecting the DACs to each individual DAC (COFFSA to COFFSD, ROFFSE and ROFFSF). These DACs can be programmed between 0 and 20 mV with approximately 1.25 mV resolution. Where the LFOFFS DAC increases the outputs signal level, the individual DACs decrease the output signal. In this way the output signal can be set very close to zero. The range of DACs, LFOFFS, COFFS and ROFFS can be tripled with control bit SERVOOS. The output current of servo channel A is calculated by: [ ( V A – V OPUREF ) + V FLOFFS – V COFFSA ] × A LFC I OA = -----------------------------------------------------------------------------------------------------------------------14 k Ω In case the laser is switched off, the term (VA − VOPUREF) represents the electrical offset from the pick-up. The procedure to cancel the offset is: 1. Activate the pick-up and switch off the laser. 2. Set LFOFFS to its maximum value. 3. Measure the output currents off all relevant servo outputs. 4. If all outputs represent a signal >5 mV equivalent input voltage, decrease VLFOFFS then repeat step 3; if all outputs represent a signal