TZA3019BHT

INTEGRATED CIRCUITS DATA SHEET TZA3019 2.5 Gbits/s dual postamplifier with level detectors and 2 × 2 switch Preliminary specification File under Integrated Circuits, IC19 2000 Apr 10 Philips Semiconductors Preliminary specification 2.5 Gbits/s dual postamplifier with level detectors and 2 × 2 switch FEATURES • Dual postamplifier • Single 3.3 V power supply • Wideband operation from 50 kHz to 2.5 GHz (typical value) • Fully differential • Channels are delay matched • On-chip DC-offset compensations without external capacitor • Interfacing with positive or negative supplied logic • Switching possibility between channels • Positive Emitter Coupled Logic (PECL) or Current-Mode Logic (CML) compatible data outputs adjustable from 200 to 800 mV (p-p) single-ended • Power-down capability for unused outputs and detectors • Rise and fall times 80 ps (typical value) • Possibility to invert the output of each channel separately • Input level-detection circuits for Received Signal Strength Indicator (RSSI) or Loss Of Signal (LOS) detection, programmable from 0.4 to 400 mV (p-p) single-ended, with open-drain comparator output for direct interfacing with positive or negative logic • Reference voltage for output level and LOS adjustment • Automatic strongest input signal switch possibility (TZA3019 version B) • HTQFP32 or HBCC32 plastic package with exposed pad. APPLICATIONS TZA3019 • Postamplifier for Synchronous Digital Hierarchy and Synchronous Optical Network (SDH/SONET) transponder • SDH/SONET wavelength converter • Crosspoint or channel switch • PECL driver • Fibre channel arbitrated loop • Protection ring • Monitoring • Signal level detectors • Swing converter CML 200 mV (p-p) to PECL 800 mV (p-p) • Port bypass circuit • 2.5 GHz clock amplification. GENERAL DESCRIPTION The TZA3019 is a low gain postamplifier multiplexer with a dual RSSI and/or LOS detector that is designed for use in critical signal path control applications, such as loop-through, redundant channel switching or Wavelength Division Multiplexing (WDM). The signal path is unregistered, so no clock is required for the data inputs. The signal path is fully differential and delay matched. It is capable of operating from 50 kHz to 2.5 GHz. The TZA3019 HTQFP32 and HBCC32 packages can be delivered in three versions: • TZA3019AHT and TZA3019AV with two RSSI signals • TZA3019BHT and TZA3019BV with one RSSI and one LOS signal • TZA3019CHT and TZA3019CV with two LOS signals. ORDERING INFORMATION TYPE NUMBER TZA3019AHT TZA3019BHT TZA3019CHT TZA3019AV TZA3019BV TZA3019CV TZA3019U PACKAGE NAME HTQFP32 HTQFP32 HTQFP32 HBCC32 HBCC32 HBCC32 − DESCRIPTION plastic, heatsink thin quad flat package; 32 leads; body 5 × 5 × 1 mm plastic, heatsink thin quad flat package; 32 leads; body 5 × 5 × 1 mm plastic, heatsink thin quad flat package; 32 leads; body 5 × 5 × 1 mm plastic, heatsink bottom chip carrier; 32 terminals; body 5 × 5 × 0.65 mm plastic, heatsink bottom chip carrier; 32 terminals; body 5 × 5 × 0.65 mm plastic, heatsink bottom chip carrier; 32 terminals; body 5 × 5 × 0.65 mm bare die; 2.22 × 2.22 × 0.28 mm VERSION SOT547-2 SOT547-2 SOT547-2 SOT560-1 SOT560-1 SOT560-1 − 2000 Apr 10 2 Philips Semiconductors Preliminary specification 2.5 Gbits/s dual postamplifier with level detectors and 2 × 2 switch BLOCK DIAGRAM TZA3019 handbook, full pagewidth VEE1A LOSTH1 32 10 25 VEE1B LOS DETECTOR 1× offset 27 RSSI1 LEVEL1 INV1 S1 GND1A IN1 IN1Q GND1A 12 29 31 1 2 3 4 TZA3019AHT TZA3019AV level 24 SWITCH 23 22 A1A A1B 21 GND1B OUT1 OUT1Q GND1B TEST 15 DFT BAND GAP REFERENCE 14 Vref GND2A IN2Q IN2 GND2A S2 INV2 LEVEL2 8 7 6 5 30 28 13 level SWITCH A2A A2B 17 18 19 20 GND2B OUT2Q OUT2 GND2B offset LOS DETECTOR 11 9 1× 26 RSSI2 LOSTH2 VEE2A 16 VEE2B MGT028 Fig.1 Block diagram (TZA3019AHT and TZA3019AV). 2000 Apr 10 3 Philips Semiconductors Preliminary specification 2.5 Gbits/s dual postamplifier with level detectors and 2 × 2 switch TZA3019 handbook, full pagewidth VEE1A LOSTH1 32 10 25 VEE1B LOS DETECTOR offset 12 29 31 1 2 3 4 A1A A1B 5 kΩ 27 LOS1 TZA3019BHT TZA3019BV level LEVEL1 INV1 S1 GND1A IN1 IN1Q GND1A 24 SWITCH 23 22 21 GND1B OUT1 OUT1Q GND1B TEST 15 DFT BAND GAP REFERENCE 14 Vref GND2A IN2Q IN2 GND2A S2 INV2 LEVEL2 8 7 6 5 30 28 13 level SWITCH A2A A2B 17 18 19 20 GND2B OUT2Q OUT2 GND2B offset LOS DETECTOR 11 9 1× 26 RSSI2 LOSTH2 VEE2A 16 VEE2B MGT027 Fig.2 Block diagram (TZA3019BHT and TZA3019AV). 2000 Apr 10 4 Philips Semiconductors Preliminary specification 2.5 Gbits/s dual postamplifier with level detectors and 2 × 2 switch TZA3019 handbook, full pagewidth VEE1A LOSTH1 32 10 25 VEE1B LOS DETECTOR offset 12 29 31 1 2 3 4 A1A A1B 5 kΩ 27 LOS1 TZA3019CHT TZA3019CV level LEVEL1 INV1 S1 GND1A IN1 IN1Q GND1A 24 SWITCH 23 22 21 GND1B OUT1 OUT1Q GND1B TEST 15 DFT BAND GAP REFERENCE 14 Vref GND2A IN2Q IN2 GND2A S2 INV2 LEVEL2 8 7 6 5 30 28 13 level SWITCH A2A A2B 17 18 19 20 GND2B OUT2Q OUT2 GND2B LOS DETECTOR offset 5 kΩ 26 LOS2 LOSTH2 VEE2A 11 9 16 VEE2B MGS553 Fig.3 Block diagram (TZA3019CHT and TZA3019CV). 2000 Apr 10 5 Philips Semiconductors Preliminary specification 2.5 Gbits/s dual postamplifier with level detectors and 2 × 2 switch PINNING PIN SYMBOL TZA3019xHT/xV(1) A GND1A IN1 IN1Q GND1A n.c n.c GND2A IN2 IN2Q GND2A VEE2A LOSTH1 1 2 3 4 − − 5 6 7 8 9 10 B 1 2 3 4 − − 5 6 7 8 9 10 C 1 2 3 4 − − 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 11 12 S I I S − − S I I S S I ground for input 1 and LOS1 circuits PAD TYPE(2) DESCRIPTION TZA3019 differential circuit 1 input; complimentary to pin IN1Q; DC bias level is set internally at approximately −0.33 V differential circuit 1 input; complimentary to pin IN1; DC bias level is set internally at approximately −0.33 V ground for input 1 and LOS1 circuits not connected not connected ground for input 2 and LOS2 circuits differential circuit 2 input; complimentary to pin IN2Q; DC bias level is set internally at approximately −0.33 V differential circuit 2 input; complimentary to pin IN2; DC bias level is set internally at approximately −0.33 V ground for input 2 and LOS2 circuits negative supply voltage for input 2 and LOS2 circuits Input for level detector programming of input 1 circuit; threshold level is set by connecting external resistors between pins GND1A and Vref. When forced to VEE2A or not connected, the LOS1 circuit will be switched off. Input for level detector programming of input 2 circuit; threshold level is set by connecting external resistors between pins GND2A and Vref. When forced to VEE2A or not connected, the LOS2 circuit will be switched off. not connected Input for programming output level of output 1 circuit; output level is set by connecting external resistors between pins GND1A and Vref. When forced to GND1A or not connected, pins OUT1 and OUT1Q will be switched off. Input for programming output level of output 2 circuit; output level is set by connecting external resistors between pins GND2A and Vref. When forced to GND2A or not connected, pins OUT2 and OUT2Q will be switched off. reference voltage for level circuit and LOS threshold programming; typical value is −1.6 V; no external capacitor allowed for test purposes only; to be left open-circuit in the application negative supply voltage for output 2 circuit ground for output 2 circuit PECL or CML compatible differential circuit 2 output; complimentary to pin OUT2 LOSTH2 11 11 11 13 I n.c LEVEL1 − 12 − 12 − 12 14 15 − I LEVEL2 13 13 13 16 I Vref n.c TEST VEE2B GND2B OUT2Q 14 − 15 16 17 18 14 − 15 16 17 18 14 − 15 16 17 18 17 18 19 20 21 22 O − I S S O 2000 Apr 10 6 Philips Semiconductors Preliminary specification 2.5 Gbits/s dual postamplifier with level detectors and 2 × 2 switch PIN SYMBOL TZA3019xHT/xV(1) A OUT2 GND2B n.c n.c GND1B OUT1Q OUT1 GND1B VEE1B RSSI2 LOS2 RSSI1 LOS1 INV2 INV1 S2 S1 VEE1A VEEP Notes 1. The ‘x’ in TZA3019xHT/xV represents versions A, B and C. 19 20 − − 21 22 23 24 25 26 − 27 − 28 29 30 31 32 pad B 19 20 − − 21 22 23 24 25 26 − − 27 28 29 30 31 32 pad C 19 20 − − 21 22 23 24 25 − 26 − 27 28 29 30 31 32 pad 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 − O S − − S O O S S O PAD TYPE(2) DESCRIPTION TZA3019 PECL or CML compatible differential circuit 2 output; complimentary to pin OUT2Q ground for output 2 circuit not connected not connected ground for output 1 circuit PECL or CML compatible differential circuit 1 output; complimentary to pin OUT1 PECL or CML compatible differential circuit 1 output; complimentary to pin OUT1Q ground for output 1 circuit negative supply voltage for output 1 circuit output of received signal strength indicator of detector O-DRN output loss of signal detector 2; detection of input 2 signal; direct drive of positive or negative supplied logic via internal 5 kΩ resistor O output of received signal strength indicator of detector O-DRN output loss of signal detector 2; detection of input 2 signal; direct drive of positive or negative supplied logic via internal 5 kΩ resistor TTL TTL TTL TTL S S input to invert the signal of pins OUT2 and OUT2Q; directly positive (inverted) or negative supplied logic driven input to invert the signal of pins OUT1 and OUT1Q; directly of positive (inverted) or negative supplied logic driven input selector output 2 circuit; directly positive (inverted) or negative supplied logic driven input selector output 1 circuit; directly positive (inverted) or negative supplied logic driven negative supply voltage for input 1 and LOS1 circuits negative supply voltage pad (exposed die pad) 2. Pin type abbreviations: O = output, I = input, S = power supply, TTL = logic input and O-DRN = open-drain output. 2000 Apr 10 7 Philips Semiconductors Preliminary specification 2.5 Gbits/s dual postamplifier with level detectors and 2 × 2 switch TZA3019 handbook, full pagewidth 26 RSSI2/LOS2 27 RSSI1/LOS1 32 VEE1A GND1A IN1 IN1Q GND1A GND2A IN2 IN2Q GND2A 1 2 3 4 exposed pad 25 VEE1B 29 INV1 28 INV2 31 S1 30 S2 24 GND1B 23 OUT1 22 OUT1Q 21 GND1B TZA3019xHT 5 6 7 8 VEEP 20 GND2B 19 OUT2 18 OUT2Q 17 GND2B LOSTH2 11 LOSTH1 10 LEVEL1 12 LEVEL2 13 Vref 14 TEST 15 VEE2B 16 VEE2A 9 MGS554 Fig.4 Pin configuration HTQFP32. RSSI1/LOS1 handbook, full pagewidth RSSI2/LOS2 26 VEE1A INV1 GND1A IN1 IN1Q GND1A GND2A IN2 IN2Q GND2A 1 2 3 4 5 6 7 8 9 VEE2A 32 31 30 29 28 INV2 27 25 24 23 22 GND1B OUT1 OUT1Q GND1B GND2B OUT2 OUT2Q GND2B exposed pad TZA3019xV 21 20 19 VEEP 18 17 10 LOSTH1 11 LOSTH2 12 LEVEL1 13 LEVEL2 14 Vref 15 TEST 16 VEE2B VEE1B MGT029 S1 Fig.5 Pin configuration HBCC32. 2000 Apr 10 S2 8 Philips Semiconductors Preliminary specification 2.5 Gbits/s dual postamplifier with level detectors and 2 × 2 switch FUNCTIONAL DESCRIPTION The TZA3019 is a dual postamplifier with multiplexer and loss of signal detection see Figs 1, 2 and 3. The RF path starts with the multiplexer, which connects an amplifier to one of the two inputs. It is possible to invert the output for easy layout of the Printed-Circuit Board (PCB). The signal is amplified to a certain level. To guarantee this level with minimum distortion over the temperature range and level range, an active control part is added. The offset compensation circuit following the inverter minimizes the offset. The Received Signal Strength Indicator (RSSI) or the Loss Of Signal (LOS) detection uses a 7-stage ‘successive detection’ circuit. It provides a logarithmic output. The LOS is followed by a comparator with a programmable threshold. The input signal level-detection is implemented to check if the input signal voltage is above the user programmed level. This can insure that data will only be transmitted when the input signal-to-noise ratio is sufficient for low bit error rate system operation. A second offset compensation circuit minimizes the offset of the logarithmic amplifier. RF input circuit The input circuit contains internal 50 Ω resistors decoupled to ground via an internal common mode 12 pF capacitor (see Fig.6). The input pins are DC-biased at approximately −0.33 V by an internal reference generator. The TZA3019 can be DC-coupled, but AC-coupling is preferred. In case of DC-coupling, the driving source must operate within the allowable input range (−1.0 to +0.3 V). A DC-offset voltage of more than a few millivolts should be avoided, since the internal DC-offset compensation circuit has a limited correction range. When AC-coupling is used, if no DC-compatibility is required, the values of the coupling capacitors must be large enough to pass the lowest input frequency of interest. Capacitor tolerance and resistor variation must be included for an accurate calculation. Do not use signal frequencies around the low cut-off circuit frequencies (f−3dB(l) = 50 kHz for the postamplifiers and f−3dB(l) = 1 MHz for the LOS circuits). RF output circuit Matching the main amplifier outputs (see Fig.7) is not mandatory. In most applications, the transmission line receiving end will be properly matched, while very little reflections occur. Matching the transmitting end to absorb reflections is only recommended for very sensitive applications. 2000 Apr 10 9 Postamplifier level adjustment TZA3019 In such cases, pull-up resistors of 100 Ω should be connected as close as possible to the IC from pins OUT1 and OUT1Q, and pins OUT2 and OUT2Q to VEE1B and VEE2B respectively. These matching resistors are not needed in most applications. handbook, halfpage GND1A, GND2A 12 pF 420 Ω 50 Ω IN1, IN2 IN1Q, IN2Q 50 Ω MGS555 VEE1A, VEE2A Fig.6 RF input circuit. The postamplifier boosts the signal up to PECL levels. The output can be either CML- or PECL-level compatible, adjusted by means of the voltage on pins LEVEL1 and LEVEL2. The DC voltages of pins OUT1 and OUT1Q, and pins OUT2 and OUT2Q match with the DC-levels on pins LEVEL1 and LEVEL2, respectively. Due to the receiving end 50 Ω load resistance, it means that at the same level of Vo(p-p), VLEVEL1 and VLEVEL2 with AC-coupling are not equal to VLEVEL1 and VLEVEL2 with DC-coupling (see Figs 7 and 8). The postamplifier is in power-down state when pin LEVEL1 or LEVEL2 is connected to ground or not connected (see Fig.8). Postamplifier DC offset cancellation loop Offset control loops connected between the inputs of the buffers A1A and A2A and the outputs of the amplifiers A1B and A2B (see Figs 1, 2 and 3) will keep the input of both buffers at their toggle point during the absence of an input signal. The active offset compensation circuit is integrated, so no external capacitor is required. The loop time constant determines the lower cut-off frequency of the amplifier chain. The cut-off frequency of the offset compensations is fixed internally at approximately 5 kHz. Philips Semiconductors Preliminary specification 2.5 Gbits/s dual postamplifier with level detectors and 2 × 2 switch TZA3019 handbook, full pagewidth GND1A, GND2A R1 100 Ω 100 Ω GND1B, GND2B OUT1, OUT2 OUT1Q, OUT2Q 50 Ω 50 Ω Vo LEVEL1, LEVEL2 Vlevel R2 Vref REG 0 Vlevel Vo (V) Vo(se)(p-p) MGS556 Vlevel = 0.5 × Vo(se)(p-p). R1 V level = V ref × --------------------- . R1 + R2 Level detector in power-down mode: VLEVEL1 or VLEVEL2 = VGND. a. DC-coupling. handbook, full pagewidth GND1A, GND2A 100 Ω R1 100 Ω GND1B, GND2B OUT1, OUT2 OUT1Q, OUT2Q 50 Ω 50 Ω Vo LEVEL1, LEVEL2 Vlevel 0 R2 Vref REG Vlevel Vo (V) Vlevel = 1.5 × Vo(se)(p-p). R1 V level = V ref × --------------------- . R1 + R2 Level detector in power-down mode: VLEVEL1 or VLEVEL2 = VGND. Vo(se)(p-p) MGL811 b. AC-coupling. Fig.7 RF output configurations. 2000 Apr 10 10 Philips Semiconductors Preliminary specification 2.5 Gbits/s dual postamplifier with level detectors and 2 × 2 switch TZA3019 handbook, full pagewidth MGS557 1000 Vo(se)(p-p) (mV) 800 DC-coupled 600 AC-coupled 400 200 0 0 20 40 60 100 80 Vlevel (% of Vref) Fig.8 Output signal as a function of Vlevel. TTL logic input of selector and inverter The logic levels are differently defined for positive or negative logic (see Fig.9). It should be noted that positive logic levels are inverted if a negative supply voltage is used. Outputs as a function of switch input pins S1, S2, INV1 and INV2 See Tables 1, 2, 3 and 4. The default values for the switch input pins S1, S2, INV1 and INV2 if not connected, is zero. Table 1 S1 0 1 OUT1 and OUT1Q as function of input S1 Table 2 S2 0 1 Table 3 INV1 0 1 Table 4 INV2 OUT2 and OUT2Q as function of input S2 OUT2 IN2 IN1 OUT2Q IN2Q IN1Q OUT1 and OUT1Q as function of INV1 OUT1 IN1 or IN2 IN1Q or IN2Q OUT1Q IN1Q or IN2Q IN1 or IN2 OUT2 and OUT2Q as function of INV2 OUT2 IN1 or IN2 IN1Q or IN2Q OUT2Q IN1Q or IN2Q IN1 or IN2 OUT1 IN1 IN2 OUT1Q IN1Q IN2Q 0 1 2000 Apr 10 11 Philips Semiconductors Preliminary specification 2.5 Gbits/s dual postamplifier with level detectors and 2 × 2 switch TZA3019 handbook, full pagewidth logic level 1 MGS558 2.0 V 2.0 V (1) T TL 0.8 V 0 1.4 V VEE −4 −3 −2 −1 GND 0 +1 +2 VI (V) +3 1.4 V 0.8 V a. Negative circuit supply voltage VEE and negative logic supply voltage VEE. handbook, full pagewidth logic level 1 MGS559 2.0 V 2.0 V (1) T TL 0.8 V 0 1.4 V VEE −4 −3 −2 −1 GND 0 +1 +2 VI (V) +3 1.4 V VCC 0.8 V b. Negative circuit supply voltage VEE and positive logic supply voltage VCC. handbook, full pagewidth logic level 1 MGS560 2.0 V 2.0 V (1) T TL 0.8 V 0 1.4 V GND −1 0 +1 +2 VCC +3 +4 +5 VI (V) +6 1.4 V 0.8 V c. Positive circuit supply voltage VCC and positive logic supply voltage VCC. (1) Level not defined. Fig.9 Logic levels on pins S1, S2, INV1 and INV2 as a function of the input voltages. 2000 Apr 10 12 Philips Semiconductors Preliminary specification 2.5 Gbits/s dual postamplifier with level detectors and 2 × 2 switch RSSI and LOS detection The TZA3019 allows AC-signal level detection. This can prevent the outputs from reacting to noise during the absence of a valid input signal, and can insure that data only will be transmitted when the signal-to-noise ratio of the input signal is sufficient to insure low bit error rate system operation. The RSSI detection circuit uses seven limiting amplifiers in a ‘successive detection’ topology to closely approximate logarithmic response over a total range of 70 dB. The detectors provide full-wave rectification of the AC signals presented at each previous amplifier stage. Their outputs are current drivers. Each cell incorporates a low-pass filter, being the first step in recovering the average value of the demodulated signal of the input frequency. The summed detector output currents are converted to a voltage by an internal load resistor. This voltage is buffered and available in the A and B versions of the TZA3019. When VRSSI is used VLOSTH must be connected to GND to prevent the LOS comparator from switching to the standby mode. The LOS comparator detects an input signal above a fixed threshold, resulting in a LOW-level at the LOS circuit output.The threshold level is determined by the voltage on pins LOSTH1 or LOSTH2 (see Fig.10). A filter with a time constant of 1 µs nominal is included to prevent noise spikes from triggering the level detector. The comparator (with internal 3 dB hysteresis) drives an open-drain circuit with an internal resistor (5 kΩ) for direct interfacing to positive or negative logic (see Fig.11). Only available in the B and C versions of the TZA3019. The response is independent of the sign of the input signal because of the particular way the circuit has been built. This is part of the demodulating nature of the detector, which results in an alternating input voltage being transformed to a rectified and filtered quasi DC-output signal. For the TZA3019 the logarithmic voltage slope is ϕ = 1/13 dB/mV and is essentially temperature and supply independent through four feedback loops in the reference circuit. The internal LOS detector output voltage is based on Vref. The demodulator characteristic depends on the waveform and the response depends roughly on the input signal RMS value. This influences high frequencies, a square wave input of 2.4 GHz (LOS circuit bandwidth of 2.4 GHz) offsets the intercept voltage by 20%. VLOSTH can be calculated using the following formulae: V LOSTH = V RSSI = S × 20log where S = sensitivity. Example: a 200 mV (p-p) single-ended 1.2 GB/s PRBS signal has an RSSI from 1003 mV. 2000 Apr 10 13 ( Vi ⁄ 18 µ V ) TZA3019 handbook, halfpage3 10 MGS564 Vi(se)(p-p) (mV) 102 LOS1, LOS2 LOW-level (1) (2) 10 LOS1, LOS2 HIGH-level 1 (3) 10−1 10 20 40 50 60 30 70 VLOSTH1, VLOSTH2 (% of Vref) −0.16 −0.32 −0.48 −0.64 −0.8 −0.96 −1.12 VRSSI1, VRSSI2 (V) (1) PRBS pattern input signal with a frequency