TZA3044U

INTEGRATED CIRCUITS DATA SHEET TZA3044T; TZA3044U 1.25 Gbits/s Gigabit Ethernet postamplifiers Objective specification File under Integrated Circuits, IC19 1998 Jul 07 Philips Semiconductors Objective specification 1.25 Gbits/s Gigabit Ethernet postamplifiers FEATURES • Pin compatible with the NE/SA5224 and NE/SA5225 but with extended power supply range and less external component count • Wideband operation from 1.0 kHz to 1.25 GHz typical • Applicable in 1.25 Gbits/s Gigabit Ethernet receivers • Single supply voltage from 3.0 to 5.5 V • PECL (Positive Emitter Coupled Logic) compatible data outputs • Programmable input signal level-detection to be adjusted using a single external resistor • On-chip DC offset compensation without external capacitor • Fully differential for excellent PSRR. ORDERING INFORMATION TYPE NUMBER TZA3044T TZA3044U PACKAGE NAME SO16 naked die DESCRIPTION APPLICATIONS TZA3044T; TZA3044U • Digital fibre optic receiver for Gigabit Ethernet applications • Wideband RF gain block. GENERAL DESCRIPTION The TZA3044 is a high gain limiting amplifier that is designed to process signals from fibre optic preamplifiers like the TZA3043. It is pin compatible with the NE/SA5224 and NE/SA5225 but with extended power supply range, and needs less external components. Capable of operating at 1.25 Gbits/s, the chip has input signal level detection with a user-programmable threshold. The data and level-detection status outputs are differential outputs for optimum noise margin and ease of use. VERSION SOT109-1 − plastic small outline package; 16 leads; body width 3.9 mm die in waffle pack carriers; die dimensions 1.58 × 1.58 mm BLOCK DIAGRAM handbook, full pagewidth TEST 2 (2, 10, 15, 21, 26) DC-OFFSET COMPENSATION DIN DINQ 4 (7) 5 (8) A1 A2 A3 TZA3044 (24) 13 (23) 12 (16) 8 (18) 10 DOUT DOUTQ JAM ST STQ 25 kΩ RECTIFIER RSET Vref 16 (30) 15 (29) 1 kΩ A4 BAND GAP REFERENCE (17) 9 (3, 4, 6, 9) 3 AGND (1, 14) 1 (11, 12) 6 VCCA (13) 7 CF (19, 20, 22, 25) 11 (27, 28) 14 MGR240 SUB DGND VCCD The numbers in brackets refer to the pad numbers of the naked die version. Fig.1 Block diagram. 1998 Jul 07 2 Philips Semiconductors Objective specification 1.25 Gbits/s Gigabit Ethernet postamplifiers PINNING SYMBOL SUB TEST AGND DIN DINQ VCCA CF JAM PIN 1 2 3 4 5 6 7 8 TYPE substrate test pin ground analog input analog input supply analog input PECL input TZA3044T; TZA3044U DESCRIPTION substrate pin; must be at the same potential as AGND (pin 3) for test purpose only; to be left open in the application analog ground; must be at the same potential as DGND (pin 11) differential input; DC bias level is set internally at approximately 2.55 V; complimentary to DINQ (pin 5) differential input; DC bias level is set internally at approximately 2.55 V; complimentary to DIN (pin 4) analog supply voltage; must be at the same potential as VCCD (pin 14) filter capacitor for input signal level detector; capacitor should be connected between this pin and VCCA (pin 6) PECL-compatible input; controls the output buffers DOUT and DOUTQ (pins 13 and 12). When a LOW signal is applied, the outputs will follow the input signal. When a HIGH signal is applied, the DOUT and DOUTQ pins will latch into LOW and HIGH states, respectively. When left unconnected, this pin is actively pulled LOW (JAM OFF). PECL-compatible status output of the input signal level detector; when the input signal is below the user-programmed threshold level, this output is HIGH; complimentary to ST (pin 10) PECL-compatible status output of the input signal level detector; when the input signal is below the user-programmed threshold level, this output is LOW; complimentary to STQ (pin 9) digital ground; must be at the same potential as AGND (pin 3) PECL-compatible differential output; when JAM is HIGH, this pin will be forced into a HIGH condition; complimentary to DOUT (pin 13) PECL-compatible differential output; when JAM is HIGH, this pin will be forced into a LOW condition; complimentary to DOUTQ (pin 12) digital supply voltage; must be at the same potential as VCCA (pin 6) input signal level detector programming; nominal DC voltage is VCCA − 1.5 V; threshold level is set by connecting an external resistor between RSET and VCCA or by forcing a current into RSET; default value for this resistor is 180 kΩ which corresponds with approximately 4 mV (p-p) differential input signal STQ 9 PECL output ST 10 PECL output DGND DOUTQ DOUT VCCD Vref RSET 11 12 13 14 15 16 ground PECL output PECL output supply analog input analog output band gap reference voltage; typical value is 1.2 V; internal series resistor of 1 kΩ 1998 Jul 07 3 Philips Semiconductors Objective specification 1.25 Gbits/s Gigabit Ethernet postamplifiers TZA3044T; TZA3044U PAD CONFIGURATION Pad centre locations handbook, halfpage COORDINATES(1) SUB 1 TEST 2 AGND 3 DIN 4 16 RSET 15 Vref 14 VCCD 13 DOUT SYMBOL SUB TEST AGND AGND n.c. AGND DIN DINQ AGND TEST VCCA VCCA CF SUB TEST JAM STQ ST DGND DGND TEST DGND DOUTQ DOUT DGND TEST VCCD VCCD Vref RSET n.c. n.c. Note PAD x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 −235.7 −392.8 −532.8 −647.8 −647.8 −647.8 −647.8 −647.8 −647.8 −647.8 −647.8 −532.8 −392.8 −235.7 −78.6 +61.4 +218.5 +375.6 +532.7 +647.8 +647.8 +647.8 +647.8 647.8 647.8 647.8 647.8 532.7 392.7 235.6 78.5 −78.6 y +647.8 +647.8 +647.8 +507.1 +350.0 +210.0 +70.0 −70.0 −210.0 −350.0 −507.1 −647.8 −647.8 −647.8 −647.8 −647.8 −647.8 −647.8 −647.8 −507.1 −350.0 −210.0 −70.0 70.0 210.0 350.0 507.1 647.8 647.8 647.8 647.8 +647.8 TZA3044T DINQ 5 VCCA 6 CF 7 JAM 8 MGR241 12 DOUTQ 11 DGND 10 ST 9 STQ Fig.2 Pin configuration. 1. Coordinates represent the position of the centre of the pad, in µm, with respect to the centre of the die. 1998 Jul 07 4 Philips Semiconductors Objective specification 1.25 Gbits/s Gigabit Ethernet postamplifiers Bonding pad locations TZA3044T; TZA3044U AGND SUB 3 AGND n.c. AGND 1.58(1) mm DIN DINQ AGND TEST VCCA 4 5 6 7 8 9 10 11 12 VCCA 2 1 32 31 30 29 Vref handbook, full pagewidth 28 27 26 25 VCCD TEST DGND DOUT DOUTQ DGND TEST DGND VCCD RSET TEST n.c. n.c. x 0 0 y 24 23 22 21 20 TZA3044U 13 CF 14 SUB 15 TEST 16 JAM 17 STQ 18 ST 19 DGND MGR242 1.58 mm(1) (1) Typical value. Pad size: 90 × 90 µm. Fig.3 Bonding pad locations: TZA3044U. FUNCTIONAL DESCRIPTION The TZA3044 accepts up to 1.25 Gbits/s Gigabit Ethernet data streams, with amplitudes from 2 mV (p-p) up to 1 V (p-p) single-ended. The input signal will be amplified and limited to differential PECL output levels (see Fig.1). The input buffer A1 presents an impedance of approximately 4.5 kΩ to the data stream on the inputs DIN and DINQ. The input can be used both single-ended and differential, but differential operation is preferred for better performance. Because of the high gain of the postamplifier, a very small offset voltage would shift the decision level in such a way that the input sensitivity decreases drastically. Therefore a DC offset compensation circuit is implemented in the TZA3044, which keeps the input of buffer A3 at its toggle point in the absence of any input signal. An input signal level detection is implemented to check if the input signal is above the user-programmed level. The outcome of this test is available at the PECL outputs ST and STQ. This flag can also be used to prevent the PECL outputs DOUT and DOUTQ from reacting to noise in the absence of a valid input signal, by connecting the output STQ to the input JAM. This insures that data will only be transmitted when the input signal-to-noise ratio is sufficient for low bit error rate system operation. PECL logic The logic level symbol definitions for PECL are shown in Fig.4. Input biasing The input pins DIN and DINQ are DC biased at approximately 2.55 V by an internal reference generator (see Fig.5). The TZA3044 can be DC coupled, but AC coupling is preferred. In case of DC coupling, the driving source must operate within the allowable input signal range (2.0 V to VCCA + 0.5 V). Also a DC offset voltage of 1998 Jul 07 5 Philips Semiconductors Objective specification 1.25 Gbits/s Gigabit Ethernet postamplifiers more than a few millivolt should be avoided, since the internal DC offset compensation circuit has a limited correction range. If AC coupling is used to remove any DC compatibility requirement, the coupling capacitors must be large enough to pass the lowest input frequency of interest. For example, 1 nF coupling capacitors react with the internal 4.5 kΩ input bias resistors to yield a lower −3 dB frequency of 35 kHz. This then sets a limit on the maximum number of consecutive pulses that can be sensed accurately at the system data rate. Capacitor tolerance and resistor variation must be included for an accurate calculation. DC-offset compensation A control loop connected between the inputs of buffer A3 and amplifier A1 (see Fig.1) will keep the input of buffer A3 at its toggle point in the absence of any input signal. Because of the active offset compensation which is integrated in the TZA3044, no external capacitor is required. The loop time constant determines the lower cut-off frequency of the amplifier chain, which is set at approximately 850 Hz. Input signal level-detection The TZA3044 allows for user-programmable input signal level-detection and can automatically disable the switching of the PECL outputs if the input signal is below a set threshold. This prevents the outputs from reacting to noise in the absence of a valid input signal, and insures that data will only be transmitted when the signal-to-noise ratio of the input signal is sufficient for low bit-error-rate system operation. Complementary PECL flags (ST and STQ) indicate whether the input signal is above or below the programmed threshold level. The input signal is amplified and rectified before being compared to a programmable threshold reference. A filter is included to prevent noise spikes from triggering the level-detector. This filter has a nominal 1 µs time constant and additional filtering can be achieved by using an external capacitor between pin CF and VCCA (the internal driving impedance nominally is 25 kΩ). The resultant signal is then compared to a threshold current through pin RSET (see Fig.6). This current can be set by connecting an external resistor RDETECT between pin RSET and VCCA, or by forcing a current into pin RSET. The relationship between the threshold current and the detected input voltage is approximately: I RSET = 0.002 × ( V DIN – V DINQ ) [ A ] (1) TZA3044T; TZA3044U Since the voltage on pin RSET is held constant at 1.5 V below VCCA, the current flowing into this pin will be: 1.5 I RSET = ----------------------- [ A ] (2) R DETECT Combining these two formulas results in a general formula to calculate RDETECT for a given input signal level-detection: 750 (3) R DETECT = ----------------------------------------- [ Ω ] ( V DIN – V DINQ ) In this formula, VDIN and VDINQ are in V (p-p). Example: Detection should occur if the differential voltage of the input signals drops below 4 mV (p-p). In this case, a reference current of 0.002 × 0.004 = 8 µA should flow into pin RSET. This can be set using a current source or simply by connecting a resistor of the appropriate value. The resistor must be connected between VCCA and pin RSET. In this example the resistor would be: 750 R DETECT = ---------------- = 187.5 k Ω 0.004 The hysteresis is fixed internally at 3 dB electrical. In the example of above, a differential level below 4 mV (p-p) of the input signal will drive pin ST to LOW, and an input signal level above 5.7 mV (p-p) will drive pin ST to HIGH. Since a JAM function is provided which forces the data outputs to a predetermined state (DOUT = LOW and DOUTQ = HIGH), the pins STQ and JAM can be connected to automatically disable the signal transmission when the chip senses that the input signal is below the programmed threshold. Response time of the input signal level-detection circuit is determined by the time constant of the input capacitors, together with the filter time constant (1 µs internal plus the additional capacitor at pin CF). PECL output circuits The output circuit of ST and STQ is given in Fig.7 The output circuit of DOUT and DOUTQ is given in Fig.8. Some PECL termination schemes are given in Fig.9. 1998 Jul 07 6 Philips Semiconductors Objective specification 1.25 Gbits/s Gigabit Ethernet postamplifiers TZA3044T; TZA3044U handbook, full pagewidth VCC VO(max) VOQH VOH Vo(p-p) VOQL VOL VO(min) VOO MGR243 Fig.4 Logic level symbol definitions for PECL. handbook, full pagewidth VCC DIN DINQ 4.5 kΩ 4.5 kΩ 2.55 V 330 µA 330 µA MGR244 Fig.5 Data input circuit DIN and DINQ. 1998 Jul 07 7 Philips Semiconductors Objective specification 1.25 Gbits/s Gigabit Ethernet postamplifiers TZA3044T; TZA3044U handbook, halfpage VCC RSET 1.5 V MGR245 Fig.6 Level-detect input circuit RSET. handbook, halfpage VCC VHIGH VLOW ST, STQ 10 kΩ MGR246 Fig.7 PECL output circuit ST and STQ. VCC handbook, halfpage 105 Ω 105 Ω DOUT DOUTQ 0.5 mA 9 mA 0.5 mA MGR247 Fig.8 PECL output circuit DOUT and DOUTQ. 1998 Jul 07 8 Philips Semiconductors Objective specification 1.25 Gbits/s Gigabit Ethernet postamplifiers TZA3044T; TZA3044U handbook, full pagewidth VCC − 2 V R1 = 50 Ω VI VIQ VO Zo = 50 Ω VOQ MGR248 R1 = 50 Ω handbook, full pagewidth VCC = 3.3 V R1 = 127 Ω VI VIQ VO Zo = 50 Ω VOQ R2 = 82.5 Ω R2 = 82.5 Ω R1 = 127 Ω GND MGR249 handbook, full pagewidth VCC = 5.0 V R1 = 83.3 Ω VI VIQ VO Zo = 50 Ω VOQ R2 = 125 Ω R2 = 125 Ω R1 = 83.3 Ω GND MGR250 Fig.9 PECL output termination schemes. 1998 Jul 07 9 Philips Semiconductors Objective specification 1.25 Gbits/s Gigabit Ethernet postamplifiers LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VCC Vn supply voltage DC voltage pins 4 and 5 (7 and 8): DIN and DINQ pin 7 (13): CF pin 8 (16): JAM pins 9, 10, 12 and 13 (17, 18, 23 and 24): STQ, ST, DOUTQ and DOUT pin 15 (29): Vref pin 16 (30): RSET In DC current pin 4 and 5 (7 and 8): DIN and DINQ pin 7 (13): CF pin 8 (16): JAM pins 9, 10, 12 and 13 (17, 18, 23 and 24): STQ, ST, DOUTQ and DOUT pin 15 (29): Vref pin 16 (30): RSET Ptot Tstg Tj Tamb Note 1. The numbers in brackets refer to the pad numbers of the naked die version. THERMAL CHARACTERISTICS SYMBOL Rth(j-s) Rth(j-a) PARAMETER thermal resistance from junction to solder point thermal resistance from junction to ambient total power dissipation storage temperature junction temperature ambient temperature note 1 note 1 PARAMETER CONDITIONS TZA3044T; TZA3044U MIN. −0.5 −0.5 −0.5 −0.5 VCC − 2 −0.5 −0.5 −1 −1 −1 −25 −2 −2 − −65 − −40 MAX. +6 V UNIT VCC + 0.5 V VCC + 0.5 V VCC + 0.5 V VCC + 0.5 V +3.2 V VCC + 0.5 V +1 +1 +1 +10 +2.5 +2 tbf +150 150 +85 mA mA mA mA mA mA mW °C °C °C VALUE tbf tbf UNIT K/W K/W 1998 Jul 07 10 Philips Semiconductors Objective specification 1.25 Gbits/s Gigabit Ethernet postamplifiers TZA3044T; TZA3044U CHARACTERISTICS For typical values Tamb = 25 °C and VCC = 3.3 V; minimum and maximum values are valid over the entire ambient temperature range and supply voltage range; all voltages with respect to ground; unless otherwise specified. SYMBOL Supply VCC ICCD ICCA Ptot Tj Tamb Vi(se)(p-p) Vi(dif)(p-p) VI VIO(eq) VIO(cor) Ri Ci Vn(i)(rms) supply voltage digital supply current analog supply current total power dissipation junction temperature ambient temperature note 1 note 1 3 − − − −40 −40 3.3 18 15 110 − +25 − − 2.55 − − 4.5 − 115 5.5 27 22 270 +120 +85 V mA mA mW °C °C PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Inputs: DIN and DINQ input signal voltage single-ended (peak-to-peak) input signal voltage differential (peak-to-peak) absolute input signal voltage equivalent input signal offset voltage input offset voltage correction note 2 range input resistance input capacitance equivalent input RMS noise voltage single-ended single-ended note 3 0.002 0.004 2.1 − −5 2.9 − − 1.0 2.0 VCCA + 0.5 50 +5 7.6 2.5 145 V V V µV mV kΩ pF µV Input signal level-detect: RSET Iref Vref Vth(p-p) hys RF tF VOL VOH tr tf tw(p-p) f-3dB(l) f-3dB(h) reference current reference voltage programmability (single-ended, peak-to-peak) hysteresis filter resistance filter time constant CF = 0 RL = 50 Ω to VCC − 2 V RL = 50 Ω to VCC − 2 V 20% to 80% 80% to 20% note 4 referred to VCCA Vi = 200 kHz square wave electrically measured 5 −1.55 2 2 14 0.5 − −1.5 − 3 25 1.0 60 −1.45 12 4 41 2.0 µA V mV dB kΩ µs PECL outputs: DOUT and DOUTQ LOW-level output voltage HIGH-level output voltage rise time fall time pulse width distortion low frequency −3 dB point high frequency −3 dB point VCC − 1840 − VCC − 1100 − − − − − 1000 150 100 − 0.85 1300 VCC − 1620 mV VCC − 900 250 200 30 1.5 1600 mV ps ps ps kHz MHz 1998 Jul 07 11 Philips Semiconductors Objective specification 1.25 Gbits/s Gigabit Ethernet postamplifiers TZA3044T; TZA3044U SYMBOL PARAMETER CONDITIONS RL = 50 Ω to VCC − 2 V RL = 50 Ω to VCC − 2 V 20% to 80% 80% to 20% MIN. VCC − 1840 − VCC − 1100 − − − − − − − − TYP. MAX. UNIT PECL outputs: ST and STQ VOL VOH tr tf VIL VIH II(JAM) LOW-level output voltage HIGH-level output voltage rise time fall time VCC − 1620 mV VCC − 900 600 200 mV ns ns PECL input: JAM LOW-level input voltage HIGH-level input voltage JAM input current note 5 VCC − 1490 mV − +10 mV µA VCC − 1165 − −10 Reference voltage output: Vref Vref Notes 1. DOUT, DOUTQ, ST and STQ outputs are left unconnected. 2. If the input is DC coupled, the preceding amplifier’s output offset voltage should not exceed these limits, in order to avoid malfunctioning of the DC offset compensation circuit. 3. total output RMS noise Input RMS noise = ----------------------------------------------------------low frequency gain reference voltage note 6 1.165 1.20 1.235 V 4. The reference currents can be set by a resistor between VCCA and pin RSET. The corresponding input signal level-detect range is from 2 to 12 mV (p-p) single-ended. See section “Input signal level-detection” for detailed information. 5. Internal pull-down resistor of 500 kΩ to DGND. 6. Internal series resistor of 1 kΩ. 1998 Jul 07 12 Philips Semiconductors Objective specification 1.25 Gbits/s Gigabit Ethernet postamplifiers APPLICATION INFORMATION TZA3044T; TZA3044U handbook, full pagewidth VCC 100 nF VCCA 6 (11, 12) 10 nF DIN 4 (7) 180 kΩ RSET 16 (30) CF 7 (13) Vref 15 (29) VCCD 14 (27, 28) (24) 13 100 nF DOUT data out data in 10 nF DINQ 5 (8) (3, 4, 6, 9) (1, 14) 3 1 AGND SUB TZA3044 (23) 12 (16) 8 JAM (17) 9 STQ (18) (19, 20, 22, 25) 10 11 ST DGND DOUTQ level-detect status 1 kΩ 50 Ω 50 Ω MGR251 VCC − 2 V The numbers in brackets refer to the pad numbers of the naked die version. Fig.10 Application diagram. 1998 Jul 07 13 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... width 1998 Jul 07 VCC (1) Philips Semiconductors 1.25 Gbits/s Gigabit Ethernet postamplifiers 680 nF (1) (1) 22 nF VCC 8 DREF OUTQ 4 pF 6 OUT noise filter: 1-pole, 800 MHz GND 100 Ω 10 nF DINQ 10 nF DIN 100 nF VCCA 6 (11, 12) 7 4 (7) 180 kΩ RSET 16 (30) CF 7 (13) Vref 15 (29) VCCD 14 (27, 28) (24) 13 100 nF 1 DOUT data out TZA3043T IPhoto 3 TZA3044 5 (8) (3, 4, 6, 9) (1, 14) 3 1 AGND SUB (16) 8 JAM (17) 9 STQ (23) 12 (18) (19, 20, 22, 25) 10 11 ST DGND DOUTQ 14 2 GND 4 GND 5 level-detect status 1 kΩ 50 Ω 50 Ω VCC − 2 V MGR252 TZA3044T; TZA3044U Objective specification (1) ferrite bead e.g. Murata BLM31A601S. The numbers in brackets refer to the pad numbers of the naked die version. Fig.11 STM1 receiver using the TZA3043T and TZA3044. Philips Semiconductors Objective specification 1.25 Gbits/s Gigabit Ethernet postamplifiers PACKAGE OUTLINE SO16: plastic small outline package; 16 leads; body width 3.9 mm TZA3044T; TZA3044U SOT109-1 D E A X c y HE vMA Z 16 9 Q A2 A1 pin 1 index θ Lp 1 e bp 8 wM L detail X (A 3) A 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 10.0 9.8 E (1) 4.0 3.8 0.16 0.15 e 1.27 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 0.039 0.016 Q 0.7 0.6 0.028 0.020 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3 θ 0.010 0.057 0.069 0.004 0.049 0.019 0.0100 0.39 0.014 0.0075 0.38 0.244 0.050 0.041 0.228 0.028 0.004 0.012 8 0o o Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07S JEDEC MS-012AC EIAJ EUROPEAN PROJECTION ISSUE DATE 95-01-23 97-05-22 1998 Jul 07 15 Philips Semiconductors Objective specification 1.25 Gbits/s Gigabit Ethernet postamplifiers SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. Wave soldering TZA3044T; TZA3044U Wave soldering techniques can be used for all SO packages if the following conditions are observed: • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. • The longitudinal axis of the package footprint must be parallel to the solder flow. • The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 1998 Jul 07 16 Philips Semiconductors Objective specification 1.25 Gbits/s Gigabit Ethernet postamplifiers DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values TZA3044T; TZA3044U This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1998 Jul 07 17 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Al. 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No. 5, 80640 GÜLTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 Internet: http://www.semiconductors.philips.com For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 © Philips Electronics N.V. 1998 SCA60 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 425102/200/01/pp20 Date of release: 1998 Jul 07 Document order number: 9397 750 03816