UAA3202M

INTEGRATED CIRCUITS DATA SHEET UAA3202M Frequency Shift Keying (FSK) receiver Preliminary specification File under Integrated Circuits, IC01 1997 Aug 12 Philips Semiconductors Preliminary specification Frequency Shift Keying (FSK) receiver FEATURES • Low cost single-chip FSK receiver • Superheterodyne architecture with high integration level • Few external low cost components • Wide supply voltage range • Low power consumption • Wide frequency range, 150 to 450 MHz • High sensitivity • IF band determined by application • High selectivity • Very low spurious radiation, −60 dBm (meets FTZ 17TR2100) • Automotive temperature range • Power-down mode • SSOP20 package. Applications • Keyless entry systems • Car alarm systems • Remote control systems • Security systems • Telemetry systems • Wireless data transmission • Domestic appliances. QUICK REFERENCE DATA SYMBOL VCC ICC PARAMETER supply voltage supply current for operating mode on operating mode off Psens sensitivity VPWD = 0 V; R2 = 560 Ω VPWD = VCC fi = 433.92 MHz; fmod = 250 Hz square wave; ∆f = ±25 kHz; BER ≤ 3% 2.0 − − 3.4 3 − CONDITIONS MIN. 3.5 − TYP. GENERAL DESCRIPTION UAA3202M The UAA3202M is a fully integrated single-chip receiver, primarily intended for use in VHF and UHF systems employing direct Frequency Shift Keying (FSK) modulation. The UAA3202M incorporates a SAW stabilized local oscillator, balanced mixer, IF amplifier, limiter, Received Signal Strength Indicator (RSSI), RSSI comparator, FSK demodulator, data filter and data slicer. The device features a power-down mode in order to minimize the average receiver supply current. MAX. 6 4.7 30 −94 V UNIT mA µA dBm Tamb operating ambient temperature −40 − +85 °C ORDERING INFORMATION TYPE NUMBER UAA3202M PACKAGE NAME SSOP20 DESCRIPTION plastic shrink small outline package; 20 leads; body width 5.3 mm VERSION SOT339-1 1997 Aug 12 2 1997 Aug 12 LIN LFB RSSI DMOD CPC PWD DATA 19 18 PHASE SHIFT Vref BIAS 150 kΩ VCC LIMITER AMPLIFIER BUFFER 150 kΩ PHASE DETECTOR 30 kΩ 50 kΩ 17 16 15 14 13 12 11 BLOCK DIAGRAM Philips Semiconductors handbook, full pagewidth FA VEM MXIN 20 1.4 kΩ IF AMP 1.5 kΩ Frequency Shift Keying (FSK) receiver 3 RSSI Vref 1.5 kΩ MIXER UAA3202M OSCILLATOR 4 5 6 7 8 9 10 MHA797 1 2 3 MON MOP VCC OSC OSE VEO VEE COMP CPB CPA Preliminary specification UAA3202M Fig.1 Block diagram. Philips Semiconductors Preliminary specification Frequency Shift Keying (FSK) receiver PINNING SYMBOL MON MOP VCC OSC OSE VEO VEE COMP CPB CPA DATA PWD CPC DMOD RSSI LFB LIN MXIN VEM FA PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 DESCRIPTION negative mixer output positive mixer output positive supply voltage oscillator collector oscillator emitter negative supply voltage for oscillator negative supply voltage RSSI comparator output comparator input B comparator input A data output power-down control input comparator input C demodulator frequency adjustment RSSI current output limiter feedback limiter input mixer input negative supply voltage for mixer IF amplifier output handbook, halfpage UAA3202M MON 1 MOP 2 VCC 3 OSC 4 OSE 5 VEO 6 VEE 7 COMP 8 CPB 9 CPA 10 MHA796 20 FA 19 VEM 18 MXIN 17 LIN 16 LFB UAA3202M 15 RSSI 14 DMOD 13 CPC 12 PWD 11 DATA Fig.2 Pin configuration. 1997 Aug 12 4 Philips Semiconductors Preliminary specification Frequency Shift Keying (FSK) receiver FUNCTIONAL DESCRIPTION The device is based on the superheterodyne architecture incorporating a mixer, local oscillator, IF amplifier, limiter, RSSI, RSSI comparator, FSK demodulator, data filter, data slicer and power-down circuitry. The device employs a low IF frequency of typically 1 MHz in order to allow IF filtering by means of external low cost R, L and C components. If image rejection is required it can be achieved by applying a matching external front-end SAW filter. The device provides a wide IF range of 300 kHz in order to allow the use of a SAW stabilized oscillator. The on-chip local oscillator provides the injection signal for the mixer. Tuning of the on-chip local oscillator is not necessary. The oscillator frequency is determined by an external 1-port SAW resonator. The RF input signal is fed to the mixer and down converted to the IF frequency. After amplification and filtering the RF signal is applied to a limiter. The IF filter order and characteristics are determined by the external low cost R, L and C components. The limiter amplifier provides a RSSI signal which can be routed to an on-chip RSSI level comparator in order to derive a field strength indication for external use. The limited IF signal is fed to the FSK demodulator. The demodulator centre frequency is determined by an external capacitor. No alignment is necessary for the FSK demodulator. After filtering the demodulated data signal is fed to a data slicer and is made available at the data output. The data filter characteristics are determined by external capacitors. The data slicer employs an adaptive slice reference in order to track frequency offsets. The device is switched from power-down to operating mode and vice versa by means of a control input. Extremely low supply current is drawn when the device is in power-down mode. Measures are taken to allow fast receiver settling when the device is switched from power-down to operating mode. Mixer The mixer is a single balanced emitter coupled mixer with internal biasing. Matching of the RF source impedance to the mixer input requires an external matching network. Oscillator The oscillator consists of an on-chip transistor in common base configuration. An external tank and SAW resonator determines the oscillator frequency. Oscillator alignment is not necessary. Oscillator bias is controlled by an external resistor. Post mixer amplifier UAA3202M The Post Mixer Amplifier (PMA) is a differential input, single-ended output amplifier. It separates the first and second IF filters from each other. Amplifier gain is provided in order to reduce the influence of the limiter noise figure on the total noise figure. Limiter The limiter is a single-ended input multiple stage amplifier with high total gain. Amplifier stability is achieved by means of an external DC feedback capacitor, which is also used to determine the lower limiter cut-off frequency. An RSSI signal proportional to the limiter input signal is provided. IF filters IF filtering with high selectivity is realized by means of external low cost R, L and C components. The first IF filter is located directly following the mixer output. An external L/C network assembles a band-pass with low sensitivity in order to meet the bandwidth of an elliptic low-pass filter external to the device and is located in front of the limiter. The filter source impedance is determined by the drive impedance of the IF amplifier. In order to improve the IF filter selectivity below the pass-band a high-pass characteristic is added by means of a DC blocking capacitor in front of the limiter input and by means of the limiter DC feedback capacitor. RSSI The RSSI signal is a current proportional to the limiter input level (RF input power). By means of an external resistor the resulting RSSI voltage level is set in order to fit the application. The RSSI voltage is available to external circuits and is fed to the input of the RSSI level comparator. For RSSI filtering an external capacitor is connected. RSSI level comparator The RSSI level comparator compares the RSSI level with a fixed and independent internal reference voltage. If the RSSI level exceeds the internal reference voltage a logic HIGH signal is generated. The level comparator provides some hysteresis in order to avoid spurious oscillation. The output of the level comparator is designed as an open-collector with internal pull-up. 1997 Aug 12 5 Philips Semiconductors Preliminary specification Frequency Shift Keying (FSK) receiver FSK demodulator The limited IF signal is converted into baseband data by means of a quadrature FM demodulator consisting of an all-pass filter and a mixer stage. No alignment of the demodulator is necessary. The demodulator centre frequency is set by a capacitor external to the device. The demodulator provides a large audio bandwidth in order to allow high data rate applications. The demodulator can detect a small IF frequency deviation even if a relatively large IF frequency offset is encountered. Data filters After demodulation a two-stage data filtering circuit is provided in order to suppress unwanted frequency components. Two R/C low-pass filters with on-chip resistors are provided which are separated by a buffer stage. Data slicer Data detection is provided by means of a level comparator with adaptive slice reference. After the first data filter stage the pre-filtered data is split into two parts. One part passes the second data filter stage and is fed to the positive comparator input. UAA3202M The other path is fed to an integration circuit with a large time constant in order to derive the average value (DC component) as an adaptive slice reference which is presented to the negative comparator input. The adaptive reference enables the received data over a large range of demodulator frequency offsets to be detected. The integration circuit consists of a simple R/C low-pass filter with on-chip resistor. The level comparator output is designed as an open-collector with internal pull-up. Power-down circuitry The device provides a power-down mode. While in power-down mode the device disables the majority of the internal circuits and consumes extremely low current. Measures are taken to allow fast receiver settling when normal operation is resumed. Thus circuits with large time constants are only powered down partly or provide a high impedance during power-down in order to avoid the discharge of external capacitors as much as possible. Power-down mode is entered when the control input is active HIGH. The control input provides an internal pull-up resistor of high impedance. LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VCC Tamb Tstg Vesd PARAMETER supply voltage operating ambient temperature storage temperature electrostatic handling pins 4 and 5 pins 18 and 19 all other pins Note 1. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor. THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER thermal resistance from junction to ambient in free air VALUE 125 UNIT K/W note 1 −2000 −1500 −2000 +1500 +2000 +2000 V V V CONDITIONS MIN. −0.3 −40 −55 MAX. +8.0 +85 +125 V °C °C UNIT 1997 Aug 12 6 Philips Semiconductors Preliminary specification Frequency Shift Keying (FSK) receiver DC CHARACTERISTICS VCC = 3.5 V; Tamb = 25 °C; for application diagram see Fig.11; unless otherwise specified. SYMBOL Supplies VCC ICC supply voltage supply current for operating mode on operating mode off VPWD(on) VPWD(off) IPWD(on) IPWD(off) Oscillator VOSC(DC) Mixer VMXIN(DC) VMOP(DC) VMON(DC) VFA(DC) Limiter VLIN(DC) VLFB(DC) VRSSI(DC) VDMOD(DC) Data slicer VCPC(DC) VCPA(DC) VCPB(DC) VOH(DAT) VOL(DAT) VOH(RSSI) VOL(RSSI) Notes 1. The given values are valid for the whole temperature range from Tamb = −40 to +85 °C. 2. Tune RF input frequency until IF = 1 MHz. DC operating point pin 13 DC operating point pin 10 DC operating point pin 9 HIGH-level data output voltage LOW-level data output voltage HIGH-level comparator output voltage LOW-level comparator output voltage note 2 note 2 note 2 IDATA = −10 µA IDATA = 200 µA IRSSI = −10 µA IRSSI = 200 µA 1.43 1.43 1.43 0 1.93 1.93 1.93 − DC operating point pin 17 DC operating point pin 16 DC operating point pin 15 DC operating point pin 14 3.45 2.76 2.21 1.63 3.49 2.81 2.36 1.83 DC operating point pin 18 DC operating point pin 2 DC operating point pin 1 DC operating point pin 20 0.68 2.78 2.78 2.14 0.78 2.98 2.98 2.27 DC operating point pin 4 3.28 3.34 PWD voltage for operating mode ON PWD voltage for operating mode OFF PWD current for operating mode ON PWD current for operating mode OFF VPWD = 0 V VPWD = VCC note 1 VPWD = 0 V; R2 = 560 Ω VPWD = VCC 2.0 − 0 −30 − 3.4 3 − −10 1 3.5 − 6 PARAMETER CONDITIONS MIN. TYP. UAA3202M MAX. UNIT V mA µA mV V µA µA V V V V V V V V V V V V V V V V 4.7 30 300 VCC −3 3 3.40 0.88 3.18 3.18 2.40 3.50 2.86 2.51 2.03 2.43 2.43 2.43 VCC 0.6 VCC 0.6 VCC − 0.3 − Post mixer amplifier Demodulator VCC − 0.5 − RSSI comparator VCC − 0.5 − 0 − 1997 Aug 12 7 Philips Semiconductors Preliminary specification Frequency Shift Keying (FSK) receiver UAA3202M AC CHARACTERISTICS VCC = 3.5 V; Tamb = 25 °C; for application diagram see Fig.11; fi = 433.92 MHz; ∆f = ±25 kHz; fmod = 250 Hz square wave, i.e. 500 bits/s; unless otherwise specified. SYMBOL System performance Psens Pi(max) αrad tst BIF fD Mixer Gmix Ro(mix) IP3PMA GPMA P