UBA1706TS

INTEGRATED CIRCUITS DATA SHEET UBA1706 Cordless telephone line interface Objective specification Supersedes data of 1999 Mar 08 File under Integrated Circuits, IC17 1999 Jun 04 Philips Semiconductors Objective specification Cordless telephone line interface FEATURES Line interface • Low DC line voltage; operates down to 1.2 V (excluding polarity guard) • Voltage regulator with adjustable DC voltage • DC mask for voltage or current regulation (CTR21) • Line current limitation for protection • Electronic hook switch control input • Transmit amplifier with: – Symmetrical inputs – Fixed gain – Large signal handling capability. • Receive amplifier with fixed gain • Transmit and receive amplifiers Automatic Gain Control (AGC) for line loss compensation. General purpose switches Two switches with open-collector. 3-wire serial bus interface Allows control of: • DC mask (voltage or current regulation) • Receive amplifier mute function • AGC: – On/off – Slope – Istart line current. • The state of the general purpose switches • Global power-down mode. Supply Operates with external supply voltage from 3.0 to 5.5 V. ORDERING INFORMATION TYPE NUMBER UBA1706TS PACKAGE NAME SSOP24 DESCRIPTION plastic shrink small outline package; 24 leads; body width 5.3 mm APPLICATIONS • Cordless base stations UBA1706 • Mains or battery-powered telephone sets. GENERAL DESCRIPTION The UBA1706 is a BiCMOS integrated circuit intended for use in mains-powered telecom terminals. It performs all speech and line interface functions, DC mask for voltage or current regulation and electronic hook switch control. The device also includes general purpose switches. Most of the characteristics are programmable via a 3-wire serial bus interface. VERSION SOT340-1 1999 Jun 04 2 Philips Semiconductors Objective specification Cordless telephone line interface UBA1706 QUICK REFERENCE DATA Iline = 15 mA; VCC = 3.3 V; RSLPE = 10 Ω; AGC pin connected to GND; Zline = 600 Ω; ZSET = 619 Ω; EHI = HIGH; f = 1 kHz; Tamb = 25 °C; bit AGC at logic 1, all other configuration bits at logic 0; measured in the test circuit of Fig.14; unless otherwise specified. SYMBOL VCC ICC Iline VLN RREGC PARAMETER supply voltage current consumption from pin VCC line current operating range DC line voltage DC mask slope in current regulation mode voltage gain transmit amplifier from TXI to LN ∆Gv(trx) gain control range for transmit and receive amplifiers with respect to Iline = 15 mA VTXI = 50 mV (RMS) Iline = 90 mA 10.6 36.9 − 11.6 37.9 6.5 12.6 38.9 − dB dB dB receive amplifier from RXI to RXO VRXI = 2 mV (RMS) Iline > 35 mA (typical); RLVI = 1 MΩ; RRGL = 7.15 kΩ; bit CRC = 1 normal operation; bit PD = 0 power-down mode; bit PD = 1 normal operation with reduced performance CONDITIONS MIN. 3.0 − − 11 3 2.7 − TYP. − 2.2 110 − − 3.0 1.4 MAX. 5.5 3.2 150 140 11 3.3 − UNIT V mA µA mA mA V kΩ Gv(trx) 1999 Jun 04 3 Philips Semiconductors Objective specification Cordless telephone line interface BLOCK DIAGRAM UBA1706 handbook, full pagewidth VCC 21 UBA1706 19 GND RX PREAMP RXI 9 V 2Vd EHI TXI+ TXI− 15 14 V I I RXM LINE INTERFACE 7 2Vd 1 LN ZSET RXO LINE INTERFACE 300 mV 24 SLPE REG CREG RSLPE TX PREAMP RAGC2 RAGC1 2 AGC 8 AGC 2 EHI LOW VOLTAGE PART EHI SAGC, AGC CURRENT LIMITATION VCC SLPE 10 5 EHI LCC CST CCST VCC TPDARL D REG SWITCH DRIVER PROTECTION 600 mV 6 CRC RRGL 200 nA RGL 4 3 LVI RLVI TNSW TNON-HOOK 16, 20, 22, 23 n.c. GENERAL SWITCHES 2 9 SERIAL INTERFACE SUPPLY 18 17 SWI1 SWI2 SWC1, SWC2 PD 12 EN 13 CLK 11 DATA MBL039 Bit names are given in italics. Fig.1 Block diagram. 1999 Jun 04 4 Philips Semiconductors Objective specification Cordless telephone line interface PINNING SYMBOL LN REG LVI RGL LCC CST RXO AGC RXI EHI DATA EN CLK TXI− TXI+ n.c. SWI2 SWI1 GND n.c. VCC n.c. n.c. SLPE PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 DESCRIPTION positive line terminal line voltage regulator decoupling negative line voltage sense input reference for current regulation mode line current control output input for stability capacitor receive amplifier output automatic gain control/line loss compensation adjustment receiver amplifier input electronic hook switch control input serial bus data input programming serial bus enable input serial bus clock input inverted transmit amplifier input non-inverted transmit amplifier input not connected NPN open-collector output 2 NPN open-collector output 1 ground reference not connected supply voltage not connected not connected connection for slope resistor AGC RXI 8 9 LVI RGL LCC CST RXO 3 4 5 6 handbook, halfpage UBA1706 LN REG 1 2 24 SLPE 23 n.c. 22 n.c. 21 VCC 20 n.c. 19 GND UBA1706 7 18 SW1 17 SW2 16 n.c. 15 TXI+ 14 TXI13 CLK FCA031 EHI 10 DATA 11 EN 12 Fig.2 Pin configuration. 1999 Jun 04 5 Philips Semiconductors Objective specification Cordless telephone line interface FUNCTIONAL DESCRIPTION All data given in this chapter consists of typical values, except when otherwise specified. handbook, halfpage UBA1706 MGK706 8.5 Supply (pins VCC and GND; bit PD) The UBA1706 must be supplied with an external stabilized voltage source across pins VCC and GND. Without any signal and without any general purpose switch selected, the internal current consumption is 2.2 mA at VCC = 3.3 V. Each selected switch (pins SWI1 or SWI2) increases the current consumption by 600 µA. To drastically reduce current consumption, the UBA1706 is provided with a power-down mode controlled by bit PD. When bit PD is at logic 1, the current consumption from VCC becomes 110 µA. In the power-down mode, the serial interface is the only function which remains active. Line interface DC CHARACTERISTICS (PINS LN, SLPE, REG, CST, LVI, LCC, RGL AND GND; BIT CRC) The IC generates a stabilized reference voltage (Vref) across pins LN and SLPE. This reference voltage is equal to 2.9 V, is temperature compensated and can be adjusted by means of an external resistor (RVA). The reference voltage can be increased by connecting the RVA resistor between pins REG and SLPE (see Fig.3). The voltage at pin REG is used by the internal regulator to generate the stabilized reference voltage and is decoupled by a capacitor (CREG) which is connected to GND. This capacitor, converted to an equivalent inductance (see Section “Set impedance”) realizes the set impedance conversion from its DC value (RSLPE) to its AC value (ZSET in the audio frequency range). Figure 4 illustrates the reference voltage supply configuration. As can be seen from Fig.4, part of the line current flows into the ZSET impedance network and is not sensed by the UBA1706. Therefore, using the RVA resistor to change the value of the reference voltage will also modify all parameters related to the line current such as: • The AGC • The DC mask management • The low voltage area characteristics. In the same way, changing the value of ZSET also affects the characteristics. The IC has been optimized for Vref = 2.9 V and ZSET = 619 Ω. Vref (V) 7.5 6.5 5.5 4.5 (1) 3.5 (2) 2.5 103 104 105 RVA (Ω) 106 (1) Influence of RVA on Vref. (2) Vref without influence of RVA. Fig.3 Reference voltage adjustment with RVA. The IC regulates the line voltage at pin LN, which can be calculated as follows: V LN = V ref + R SLPE × I SLPE I SLPE = I line – I ZSET – I* ≅ I line – I ZSET Where: Iline = line current IZSET = current flowing through ZSET I* = current consumed between LN and GND (approximately 100 µA). The preferred value for RSLPE is 10 Ω. Changing RSLPE will affect more than the DC characteristics; it also influences the transmit gain, the gain control characteristics, the sidetone level and the maximum output swing on the line. Nevertheless, for compliance with CTR21, 8.66 Ω is the optimum value for RSLPE. 1999 Jun 04 6 Philips Semiconductors Objective specification Cordless telephone line interface UBA1706 handbook, full pagewidth LN+ ILN Rp 35 kΩ I* IZSET ZSET LN Iline UBA1706 619 Ω Vd Rd 4 kΩ REG CREG 4.7 µF ISLPE SLPE RSLPE 10 Ω GND FCA032 Fig.4 Reference voltage supply configuration. handbook, full pagewidth ILN Rp 35 kΩ Vref Vd Rd 4 kΩ REG CREG 4.7 µF GND ISLPE SLPE RSLPE 10 Ω HOOK SWITCH MANAGEMENT LCC EHI VEHI LN Iline LN+ Zline UBA1706 IZSET ZSET Rexch 619 Ω Vline Vexch TNSW VCE (TNSW) LN− FCA033 Fig.5 Line current settling simplified configuration. 1999 Jun 04 7 Philips Semiconductors Objective specification Cordless telephone line interface The DC line current flowing into the set is determined by the exchange supply voltage (Vexch), the feeding bridge resistance (Rexch), the DC resistors of the telephone line (Rline) and the set (RSET), the reference voltage (Vref) and the voltage introduced by the transistor (TNSW) used as line interrupter (see Fig.5). With a line current below Ilow (8 mA with ZSET = 619 Ω), the internal reference voltage (Vref) is automatically adjusted to a lower value. This means that several sets can operate in parallel with DC line voltages (excluding the polarity guard) down to 1.2 V. With a line current below Ilow, the circuit has limited transmit and receive levels. This is called the low voltage area. Figure 6 shows in more detail how the UBA1706, in association with some external components, manages the line interrupter (TNSW external transistor). In on-hook conditions (voltage at pin EHI is LOW), the voltage at pin LCC is pulled up to the supply voltage level (VCC) to turn off transistor TPDARL. As a result, because of resistor RPD, transistors TNSW and TNON-HOOK are switched off. Transistor TNON-HOOK disconnects resistor RLVI from the LN− line terminal to guarantee a high on-hook impedance. UBA1706 In off-hook conditions (voltage at pin EHI is HIGH), an operational amplifier drives (at pin LCC) the base of transistor TPDARL, which forms a current amplifier structure in association with TNSW. The line current flows through transistor TNSW. Transistor TNON-HOOK is forced into deep saturation. A virtual ground is created at pin LVI because of the operational amplifier. A DC current (ILVI) is sourced from pin LVI into the RLVI resistor to generate a voltage source. Thus, the voltage across pins GND and LN− becomes: VCE (TNSW) = RLVI × ILVI + VCE (TNON-HOOK) ≅ RLVI × ILVI The voltage Vline across line terminals LN+ and LN− can be calculated as follows: Vline ≅ Vref + RSLPE × (Iline − IZSET) + VCE (TNSW) Where: Iline = line current IZSET = current flowing through ZSET. 1999 Jun 04 8 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1999 Jun 04 Rp 35 kΩ LN ILN IZSET Iline ZSET LN+ Philips Semiconductors Cordless telephone line interface UBA1706 Vref Vd REG CREG 4.7 µF Rd EHI 4 kΩ 8.2 V 619 Ω SLPE RSLPE 10 Ω VCC ISLPE VEHI CURRENT REGULATION MODE MANAGEMENT ILVIV 200 nA ILVI CURRENT LIMITATION RPLU 150 kΩ LCC TPDARL Vline Bit names are given in italics. Fig.6 Line interrupter management and DC mask regulation configuration. handbook, full pagewidth 9 CRC RGL RRGL LVI CLVI 470 pF RLVI GND CST CCST 22 pF RON-HOOK TNON-HOOK 100 kΩ Dprot DSW TNSW 20 kΩ RPD Iline FCA034 7.15 kΩ 1 MΩ Objective specification LN− UBA1706 Philips Semiconductors Objective specification Cordless telephone line interface The UBA1706 offers the possibility to choose two kinds of regulations for the DC characteristic between line terminals LN+ and LN− (see Fig.7): • Voltage regulation mode • Current regulation mode. UBA1706 Therefore, VCE (TNSW) ≅ RLVI × ILVIV = 200 mV in a typical application (see Fig.15). The slope ∆Vline/∆Iline of the Vline, Iline characteristic is RREGV ≅ RSLPE. Current regulation mode In current regulation mode (bit CRC at logic 1), when the line current is lower than Iknee = 35 mA (with ZSET = 619 Ω), VCE (TNSW) is fixed by means of a 200 nA DC constant current ILVIV flowing through RLVI. When the line current is higher than 35 mA, an additional current (proportional to the line current) flows through RLVI. As a result, TNSW works as a DC voltage source increasing with the line current. VCE (TNSW) can be calculated as follows:  R SLPE  V CE ( TN SW ) ≅ R LVI ×  --------------- × ( I line – I knee ) + I LVIV   R RGL  Where: Iline = line current RRGL = resistor connected at pin RGL. In a typical application (see Fig.15), the slope ∆Vline/∆Iline of the Vline, Iline characteristic is determined by the ratio of the resistors connected at pins SLPE, LVI and RGL, as follows: R SLPE R REGC ≅ R SLPE + R LVI × --------------- = 1400 Ω . R RGL handbook, halfpage Vline (1) (2) (3) Iline Iprot (4) Ilow Iknee MGK710 (1) Low voltage area. (2) Small slope (determined by RSLPE). (3) Small slope (dashed line; determined by RSLPE) in voltage regulation mode. High slope (full line; determined by RSLPE, RLVI and RRGL) in current regulation mode. (4) Current limitation. Current limitation Whatever the selected mode is, the line current is limited to approximately 145 mA; this current is sensed on SLPE. For this purpose, the external Zener diode must be connected between pins LN and SLPE. The speech function no longer operates in this condition. ELECTRONIC HOOK SWITCH CONTROL (PIN EHI) The electronic hook switch input (EHI) controls the state of transistor TPDARL. When the voltage applied at pin EHI is LOW, transistor TPDARL is turned off. The voltage at pin LCC is pulled up to supply voltage (VCC). Transistors TNSW and TNON-HOOK are also turned off by means of a pull-down resistor (RPD). When the voltage applied at pin EHI is HIGH, transistor TPDARL is driven by the operational amplifier at pin LCC and the regulation mode selected is operating. An internal 165 kΩ pull-up resistor is connected between pins LCC and VCC. Fig.7 General form of the DC mask as a function of the regulation mode. The regulation mode is selected by bit CRC via the serial interface. The DC mask regulation is realised by adjusting the DC voltage VCE (TNSW) across pin GND and line terminal LN− as a function of the line current. Voltage regulation mode In the voltage regulation mode (bit CRC at logic 0), the VCE (TNSW) voltage is fixed by means of a 200 nA DC constant current ILVIV flowing through RLVI. 1999 Jun 04 10 Philips Semiconductors Objective specification Cordless telephone line interface Input EHI can also be used for pulse dialling or register recall (timed loop break). During line breaks (the voltage at pin EHI is LOW or open-circuit), the voltage regulator is switched off and the capacitor at pin REG is internally disconnected to prevent its discharge. As a result, the voltage stabilizer will have negligible switch-on delay after line interruptions. This minimizes the contribution of the IC to the current waveform during pulse dialling or register recall. When the UBA1706 is in power-down mode (bit PD at logic 1), transistor TPDARL is forced off whatever the voltage applied at pin EHI. SET IMPEDANCE In the audio frequency range, the dynamic impedance between pins LN and GND (illustrated in Fig.8) is mainly determined by the ZSET impedance. The impedance introduced by the external TNSW transistor connected between pins GND and LN− is negligible. TRANSMIT AMPLIFIER (PINS TXI+ AND TXI−) The UBA1706 has symmetrical transmit inputs TXI+ and TXI−. The input impedance between pins TXI+ or TXI− and GND is 21 kΩ. The voltage gain from pins TXI+ or TXI− to pin LN is set at 11.6 dB with 600 Ω line load (Zline) and 619 Ω set impedance. The inputs are biased at 2 × Vd ≅ 1.4 V, with Vd representing the diode voltage. AGC is provided on this amplifier for line loss compensation. RECEIVE AMPLIFIER (PINS RXI AND RXO; BIT RXM) The receive amplifier (see Fig.9) has one input (RXI) and one output (RXO). The input impedance between pins RXI and GND is 21 kΩ. SLPE RSLPE 10 Ω GND CREG 4.7 µF MGL215 UBA1706 The rail-to-rail output stage is designed to drive a 500 µA peak current. The output impedance at pin RXO is approximately 100 Ω. The voltage gain from pin RXI to pin RXO is set at 37.9 dB. This gain value compensates typically the attenuation of the anti-sidetone network (see Fig.10). The output and the input are biased at 2 × Vd ≅ 1.4 V. AGC is provided on this amplifier for line loss compensation. This amplifier can be muted by activating the receive mute function (bit RXM at logic 1). handbook, halfpage LN RP REG ZSET 619 Ω LEQ Vref Leq = CREG × RSLPE × RP RP = internal resistance = 35 kΩ. Fig.8 Equivalent impedance between pins LN and GND. handbook, full pagewidth RXI V 2Vd from AGC I RXM RXO I 2Vd V UBA1706 FCA035 Bit names are given in italics. Fig.9 Receive amplifier. 1999 Jun 04 11 Philips Semiconductors Objective specification Cordless telephone line interface SIDETONE SUPPRESSION The UBA1706 anti-sidetone network comprising ZSET//Zline, Rast1, Rast2, Rast3, RSLPE and Zbal (see Fig.10) suppresses the transmitted signal in the received signal. Maximum compensation is obtained when the following conditions are fulfilled: RSLPE × Rast1 = ZSET × (Rast2 + Rast3) ( R ast2 × ( R ast3 + R SLPE ) ) k = ------------------------------------------------------------------( R ast1 × R SLPE ) Zbal = k × Zline The scale factor ‘k’ is chosen to meet the compatibility with a standard capacitor from the E6 or E12 range for Zbal. In practice, Zline varies considerably with the line type and the line length. UBA1706 Therefore, the value chosen for Zbal should be for an average line length, which gives satisfactory sidetone suppression with short and long lines. The suppression also depends on the accuracy of the match between Zbal and the impedance of the average line. The anti-sidetone network for the UBA1706 (see Fig.15) attenuates the receiving signal from the line by 38 dB before it enters the receiving amplifier. The attenuation is almost constant over the whole audio frequency range. A Wheatstone bridge configuration (see Fig.11) may also be used. More information on the balancing of an anti-sidetone bridge can be obtained in our publication “Applications Handbook for Wired Telecom Systems, IC03b”. handbook, full pagewidth LN Zline ZSET Rast1 GND Im RXI ZRXI Rast2 RSLPE Rast3 SLPE Zbal MGL216 Fig.10 Equivalent circuit of UBA1706 anti-sidetone bridge. 1999 Jun 04 12 Philips Semiconductors Objective specification Cordless telephone line interface UBA1706 handbook, full pagewidth LN Zline ZSET Zbal GND Im RXI ZRXI RSLPE Rast1 RA SLPE MGL217 Fig.11 Equivalent circuit of an anti-sidetone network in a Wheatstone bridge configuration. AUTOMATIC GAIN CONTROL (PIN AGC; BITS RAGC1, RAGC2, SAGC AND AGC) The UBA1706 performs automatic line loss compensation. The AGC varies the gain of the transmit amplifier and the gain of the receive amplifier in accordance with the DC line current. The control range is 6.5 dB (which corresponds roughly to a line length of 5.5 km for a 0.5 mm diameter twisted-pair copper cable with a DC resistance of 176 Ω/km and an average attenuation of 1.2 dB/km). When the line current is greater than Istop, the voltage gains are minimum. When the line current is less than Istart, the voltage gains are maximum. When the AGC pin is connected to pin GND, the start line current (Istart) can be chosen between 22.5 and 29.5 mA via bits RAGC1 and RAGC2 through the serial interface. Two values for the Istop/Istart ratio (slope of the AGC) are possible via bit SAGC through the serial interface. When bit SAGC is at logic 0 then Istop = 2.7 × Istart (optimized for voltage regulation mode). When SAGC is at logic 1 then Istop = 1.9 × Istart (optimized for current regulation mode). An external resistor RAGC (connected between pins GND and AGC) enables the Istart and Istop line currents to be increased (the ratio between Istart and Istop is not affected by this external resistor). Therefore, internal and external adjustments of the AGC allow optimization of the IC for many configurations of exchange supply voltage and feeding bridge resistance. Part of the line current flows into the ZSET impedance network. The IC has been optimized for ZSET = 619 Ω. Changing this 619 Ω value slightly modifies Istop and Istart line currents as well as the value of the two AGC slopes. The AGC function can be disabled by setting the AGC bit to logic 0 via the serial interface or by leaving pin AGC open-circuit. In this case, both of the voltage gains are maximum. 1999 Jun 04 13 Philips Semiconductors Objective specification Cordless telephone line interface General purpose switches (pins SWI1 and SWI2; bits SWC1 and SWC2) The UBA1706 is equipped with two general purpose open-collector switches, which short circuit pins SWI1 and SWI2 to ground. These switches are controlled by bits SWC1 and SWC2, respectively, and have an operating voltage limited to 12 V. The outputs have to be current biased. For a bias current between 2 and 20 mA, the AC impedance is 30 Ω maximum. Serial interface (pins DATA, CLK and EN) A simple 3-wire unidirectional serial bus is used to program the circuit. The three wires of the bus are EN, CLK and DATA. The data sent to the device is loaded in bursts framed by EN. Programming clock edges (falling edges) and their appropriate data bits are ignored until EN goes HIGH. The programmed information is loaded into the addressed register when EN returns to LOW or left open-circuit. During normal operation, EN should be kept LOW. Only the last seven bits serially clocked into the device are retained within the programming register. UBA1706 Additional leading bits are ignored and no check is made on the number of clock pulses. New programming data can always be captured during global power-down (bit PD at logic 1). Data is entered with the most significant bit first. The leading six bits make up the data field (bits D0 to D5) while the trailing two bits are the address field (bits ADO and AD1). The first bit entered is D5, the last bit AD0. This organisation allows the transmission of only the number of bits of the addressed register. Figure 13 shows the serial timing diagram. Table 1 gives the list of registers. When the supply voltage VCC drops below 2.5 V, all register files are set to the initial state (see Table 1) defined by the power-up reset. At start-up, the circuit is in power-down mode. When the IC is used in a noisy environment, it is advised to periodically refresh the content of registers. 1999 Jun 04 14 Philips Semiconductors Objective specification Cordless telephone line interface Table 1 BIT NAME Register description; note 1 FUNCTION POLARITY DATA ADDRESS UBA1706 STATE AT POWER-UP RESET Register 0: general purpose switches state and DC mask regulation mode SWC1 SWC2 un un CRC SWI1 output connection SWI2 output connection unused unused current regulation mode 0: SWI1 switched-off 1: SWI1 switched-on 0: SWI2 switched-off 1: SWI2 switched-on must be set to logic 0 must be set to logic 0 0: voltage regulation 1: current regulation D0 D1 D2 D3 D4 (AD1, AD0) = (0,0) 0 0 0 0 0 Register 1: automatic gain control RAGC1 RAGC2 SAGC AGC Register 2 unused, in case of programming register 2 data must be set to: 000100 (D5; D0) Register 3: mute functions and power-down un RXM PD un Notes 1. For full software compatibility, the registers have the same addresses as for the UBA1707. 2. See Section “Automatic gain control (pin AGC; bits RAGC1, RAGC2, SAGC and AGC)”. unused receive amplifier mute reduced consumption mode unused must be set to logic 1 0: amplifier enabled 1: amplifier muted 0: normal operating mode 1: power-down mode must be set to logic 1 D0 D1 D2 D3 (AD1, AD0) = (1,1) 0 0 1 0 (AD1, AD0) = (1,0) − AGC range selection 1 AGC range selection 2 AGC slope selection line loss compensation mode D0 D1 D2 D3 (AD1, AD0) = (0,1) 0 0 0 0 0: 2.7 type slope; note 2 1: 1.9 type slope; note 2 0: AGC inhibited 1: AGC enabled 1999 Jun 04 15 Philips Semiconductors Objective specification Cordless telephone line interface LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VCC VLN supply voltage positive continuous line voltage on pin LN repetitive line voltage during switch-on or line interruption VSWIn Vn(max) ILN ISWIn Ptot Tstg Tamb Tj voltage on pins SWI1 and SWI2 maximum voltage on all other pins current sunk by pin LN continuous current sunk by pins SWI1 and SWI2 total power dissipation IC storage temperature ambient temperature junction temperature see Fig.12 bit SWCn = 1 continuous during switching PARAMETER CONDITIONS MIN. UBA1706 MAX. UNIT V V V V V V mA mA mW °C °C °C GND − 0.4 5.5 GND − 0.4 12.0 GND − 0.4 13.2 GND − 0.4 12.0 GND − 0.4 13.2 GND − 0.4 VCC + 0.4 − − 150 20 454 +125 +75 +125 Tamb = 75 °C; see Fig.12 − −40 −25 − THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER CONDITIONS VALUE 100 UNIT K/W thermal resistance from junction to ambient in free air 1999 Jun 04 16 Philips Semiconductors Objective specification Cordless telephone line interface UBA1706 handbook, full pagewidth 150 ILN (mA) 130 FCA036 110 (4) (3) (2) (1) 90 70 50 30 2 3 4 5 6 7 8 9 10 11 12. VLN - VSLPE (V) (1) Tamb = 45 °C; Ptot = 727 mW (2) Tamb = 55 °C; Ptot = 636 mW (3) Tamb = 65 °C; Ptot = 545 mW (4) Tamb = 75 °C; Ptot = 454 mW The line current value can be calculated from the ILN value as follows: I LN × ( R SET + R SLPE ) + V LN – V SLPE I line = --------------------------------------------------------------------------------------------- where RSET is the resistive part of ZSET. R SET Fig.12 Safe operating area. 1999 Jun 04 17 Philips Semiconductors Objective specification Cordless telephone line interface UBA1706 CHARACTERISTICS Iline = 15 mA; VCC = 3.3 V; RSLPE = 10 Ω; AGC pin connected to GND; Zline = 600 Ω; ZSET = 619 Ω; EHI = HIGH; f = 1 kHz; Tamb = 25 °C; bit AGC at logic 1, all other configuration bits at logic 0; measured in test circuit of Fig.14; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply (pins VCC and GND; bit PD) VCC ICC ICC(pd) supply voltage current consumption from pin VCC current consumption from pin VCC in power-down mode bit PD = 1 3.0 − − − 2.2 110 5.5 3.2 150 V mA µA Line interface (pins LN, SLPE and REG) DC CHARACTERISTICS Vref VLN stabilized voltage between pins LN and SLPE DC line voltage between pins LN and GND Iline = 11 to 140 mA Iline = 2 mA Iline = 4 mA Iline = 15 mA Iline = 140 mA VLN(Rext) DC line voltage between pins LN and GND with an external resistor RVA DC line voltage variation with temperature referenced to 25 °C RVA(SLPE−REG) = 8 kΩ 2.6 − − 2.7 − − 2.9 1.2 1.8 3.0 4.35 4.5 3.2 − − 3.3 − − V V V V V V ∆VLN(T) Tamb = −25 to +75 °C − 8.0 − mV Masks regulation (pins LCC, LVI, CST and RGL; bit CRC) DC CHARACTERISTICS ILCC(max) Rint(LCC) maximum current sunk by pin LCC internal resistance between pins VCC and LCC current sourced from pin LVI bit CRC = 0 500 − − 165 − − µA kΩ Voltage regulation mode ILVIV Iknee RREGC − − 200 − − − nA Current regulation mode start line current for current regulation mode DC mask slope in current regulation mode bit CRC = 1 35 1.4 mA kΩ Iline > Iknee; RLVI = 1 MΩ; − RRGL = 7.15 kΩ; bit CRC = 1 − Current limitation Iprot current limitation level 145 − mA 1999 Jun 04 18 Philips Semiconductors Objective specification Cordless telephone line interface UBA1706 SYMBOL PARAMETER CONDITIONS MIN. TYP. − 2 MAX. UNIT Electronic hook-switch control (pin EHI) VIH VIL Ibias Zi HIGH-level input voltage LOW-level input voltage input bias current VCC = 3.0 to 5.5 V input level = HIGH 2.3 1 − VCC + 0.4 0.3VCC 5 − − 12.6 − − V V µA kΩ kΩ dB dB dB GND − 0.4 − Transmit amplifier (pins TXI+, TXI− and LN) input impedance between pins TXI+ and GND or TXI− and GND VTXI = 50 mV (RMS) 21 36 11.6 ±0.3 ±0.3 between pins TXI+ and TXI− − Gv(TX) ∆Gv(TX)(f) ∆Gv(TX)(T) voltage gain from TXI+/TXI− to LN 10.6 − − voltage gain variation with f = 300 to 3400 Hz frequency referenced to 1 kHz voltage gain variation with temperature referenced to 25 °C common mode rejection ratio power supply rejection ratio Iline = 15 mA; THD = 2% Iline = 4 mA; THD = 10% Iline = 15 mA Iline = 90 mA Tamb = −25 to +75 °C CMRR PSRR − − 1.2 − − − − 65 36 1.4 0.26 0.35 0.75 −74 − − − − − − − dB dB V V V V dBmp VLN(max)(rms) maximum sending signal (RMS value) ViTX(max)(rms) maximum transmit input voltage (RMS value) for 2% THD on pin LN Vno(LN) noise output voltage at pin LN pins TXI+ and TXI− short-circuited through 200 Ω in series with 10 µF; psophometrically weighted (P53 curve) Receive amplifier (pins RXI and RXO; bit RXM) Zi Gv(RX) ∆Gv(RX)(f) ∆Gv(RX)(T) input impedance between pins RXI and GND voltage gain from RXI to RXO VRXI = 2 mV (RMS) voltage gain variation with f = 300 to 3400 Hz frequency referenced to 1 kHz voltage gain variation with temperature referenced to 25 °C power supply rejection ratio total harmonic distortion VRXI = 2 mV (RMS) VRXI = 12.5 mV (RMS) VRXI = 19.5 mV (RMS); Iline = 90 mA Tamb = −25 to +75 °C − 36.9 − − 21 37.9 ±0.2 ±0.3 − 38.9 − − kΩ dB dB dB PSRR THD − − − − 68 0.03 2 2 − − − − dB % % % 1999 Jun 04 19 Philips Semiconductors Objective specification Cordless telephone line interface UBA1706 SYMBOL PARAMETER CONDITIONS RXI open-circuit; psophometrically weighted (P53 curve) VRXI = 10 mV (RMS); bit RXM = 1 − MIN. TYP. −81 − MAX. UNIT dBVp Vno(RXO)(rms) noise output voltage at pin RXO (RMS value) ∆Gv(RX)(m) voltage gain reduction from pin RXI to RXO when muted − 80 − dB Automatic gain control (pin AGC; bits RAGC1, RAGC2, SAGC and AGC) ∆Gv(trx) gain control range for transmit Iline = 90 mA and receive amplifiers with respect to Iline = 15 mA highest line current for maximum gain bits RAGC1 = 1; RAGC2 = 1 bits RAGC1 = 1; RAGC2 = 0 bits RAGC1 = 0; RAGC2 = 1 bits RAGC1 = 0; RAGC2 = 0 Istop lowest line current for minimum gain when Istart = 23 mA gain variation for transmit and receive amplifiers when AGC is off bits SAGC = 0; RAGC1 = 1; RAGC2 = 1 bits SAGC = 1; RAGC1 = 1; RAGC2 = 1 bit AGC = 0; Iline = 15 to 140 mA − 6.5 − dB Istart − − − − − − − 22.5 25 27 29.5 62 43 − − − − − − − ±0.2 mA mA mA mA mA mA dB ∆Gv(trxoff) Switches (pins SWI1 and SWI2; bits SWC1 and SWC2) Zi(off) AC impedance between pins SWIn and GND when not selected AC impedance between pins SWIn and GND when selected bit SWCn = 0 700 − − kΩ Zi(on) 2 mA < ISWIn < 20 mA; bit SWCn = 1 − − 30 Ω Serial interface (pins DATA, CLK and EN) VIH VIL Ibias Ci HIGH-level input voltage LOW-level input voltage input bias current input capacitance at pins DATA, CLK and EN VCC = 3 to 5.5 V input level = HIGH 2.3 1 − − 2 4 VCC + 0.4 0.3VCC 5 − V V µA pF GND − 0.4 − 1999 Jun 04 20 Philips Semiconductors Objective specification Cordless telephone line interface SERIAL BUS TIMING CHARACTERISTICS VCC = 3.3 V; Tamb = 25 °C; unless otherwise specified. SYMBOL PARAMETER MIN. MAX. UBA1706 UNIT Serial programming clock; pin CLK fclk tSTART tEND tW(min) tSU; EN tSU; DATA tHD; DATA clock frequency 0 300 − − − − − − kHz µs µs µs µs µs µs Enable programming; pin EN delay to falling clock edge delay from last rising clock edge minimum inactive pulse width enable set-up time to next clock edge 1 0.1 1.5 0.1 Serial data; pin DATA input data to clock set-up time input data to clock hold time 2 2 handbook, full pagewidth tW tHD;DATA 1/fclk tSU;EN tSU;DATA CLK DATA D5 D4 AD1 AD0 EN tSTART tEND MGK716 Fig.13 Serial bus timing diagram. 1999 Jun 04 21 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1999 Jun 04 VLN from microcontroller LN 1 TXI+ Cline GND 19 SWI2 17 SWI1 18 EHI 10 DATA EN 11 12 CLK 13 RXI CRXI 220 nF VTXI TXI− 619 Ω ZSET CEMC 10 nF 7 RXO VRXI 15 9 100 µF 14 TEST AND APPLICATION INFORMATION Philips Semiconductors Cordless telephone line interface UBA1706 handbook, full pagewidth 22 Iline Zline 600 Ω CVCC 10 µF TNSW BUX86 ICC VCC 21 VVCC 5 LCC 6 CST 3 LVI 2 REG CREG 4.7 µF 8 AGC 4 RGL RRGL 24 SLPE RSLPE 10 Ω TPDARL MPSA92 CLCC 6.8 pF CCST 27 pF FCA037 RLVI CLVI 470 pF 1 MΩ 7.15 kΩ RON-HOOK DSW 1N4148 RPD 100 kΩ Dprot 1N4148 TNON-HOOK MPSA42 Objective specification 20 kΩ UBA1706 Fig.14 Test circuit. This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1999 Jun 04 VLN LN 1 CTXIP 100 nF 10 CTXIM ZSET 619 Ω CEMC(3) 10 nF 100 nF 12 ICC VCC EN TXI− 14 EHI M I C R O C O N T R O L L E R TXI+ 17 15 21 handbook, full pagewidth Philips Semiconductors Cordless telephone line interface Rast1 260 kΩ BZX79C8V2 Rast2 3.92 kΩ Zbal CRXI 100 nF CRXO SWI2 SWI1 18 9 RXI RXO 7 24 SLPE RSLPE 10 Ω Rast3 392 Ω UBA1706 11 DATA 13 CLK 23 BRIDGE 4 × BAS11 a/b BOD BR211-240 b/a CVCC 10 µF TNSW BUX86 (MPSA42 (1) VVCC 5 LCC 6 CST 3 LVI CLVI(2) 470 pF 2 REG CREG 4.7 µF 8 AGC 4 RGL RRGL 19 GND TPDARL MPSA92 CLCC(4) 6.8 pF CCST 27pF FCA038 RLVI 1 MΩ 7.15 kΩ RON-HOOK DSW 1N4148 RPD 20 kΩ 100 kΩ Dprot 1N4148 TNON-HOOK MPSA42 ) Objective specification (1) (2) (3) (4) In case of low line current in voltage regulation mode. Only required in current regulation mode. To improve EMC performance; necessary for stability. To improve stability only in current regulation mode. UBA1706 Fig.15 Typical application. Philips Semiconductors Objective specification Cordless telephone line interface PACKAGES OUTLINE SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm UBA1706 SOT340-1 D E A X c y HE vMA Z 24 13 Q A2 pin 1 index A1 (A 3) θ Lp L 1 e bp 12 wM detail X A 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.0 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 8.4 8.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 0.8 0.4 θ 8 0o o Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT340-1 REFERENCES IEC JEDEC MO-150AG EIAJ EUROPEAN PROJECTION ISSUE DATE 93-09-08 95-02-04 1999 Jun 04 24 Philips Semiconductors Objective specification Cordless telephone line interface SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. UBA1706 If wave soldering is used the following conditions must be observed for optimal results: • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 1999 Jun 04 25 Philips Semiconductors Objective specification Cordless telephone line interface Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE BGA, SQFP PLCC(3), SO, SOJ not suitable suitable(2) suitable not recommended(3)(4) not recommended(5) suitable suitable suitable suitable suitable HLQFP, HSQFP, HSOP, HTSSOP, SMS not LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes UBA1706 REFLOW(1) 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. 1999 Jun 04 26 Philips Semiconductors Objective specification Cordless telephone line interface NOTES UBA1706 1999 Jun 04 27 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 465008/02/pp28 Date of release: 1999 Jun 04 Document order number: 9397 750 05276