UBA2032T

INTEGRATED CIRCUITS DATA SHEET UBA2032 Full bridge driver IC Preliminary specification 2002 Oct 07 Philips Semiconductors Preliminary specification Full bridge driver IC FEATURES • Full bridge driver circuit • Integrated bootstrap diodes • Integrated high voltage level shift function • High voltage input for the internal supply voltage • 550 V maximum bridge voltage • Bridge disa‘ble function • Input for start-up delay • Adjustable oscillator frequency • Predefined bridge position during start-up • Adaptive non-overlap. APPLICATIONS • The UBA2032 can drive (via the MOSFETs) any kind of load in a full bridge configuration • The circuit is especially designed as a commutator for High Intensity Discharge (HID) lamps. ORDERING INFORMATION TYPE NUMBER UBA2032T UBA2032TS PACKAGE NAME SO24 SSOP28 DESCRIPTION plastic small outline package; 24 leads; body width 7.5 mm plastic shrink small outline package; 28 leads; body width 5.3 mm GENERAL DESCRIPTION UBA2032 The UBA2032 is a high voltage monolithic integrated circuit made in the EZ-HV SOI process. The circuit is designed for driving the MOSFETs in a full bridge configuration. In addition, it features a disable function, an internal adjustable oscillator and an external drive function with a high-voltage level shifter for driving the bridge. To guarantee an accurate 50% duty factor, the oscillator signal can be passed through a divider before being fed to the output drivers. VERSION SOT137-1 SOT341-1 2002 Oct 07 2 Philips Semiconductors Preliminary specification Full bridge driver IC BLOCK DIAGRAM UBA2032 handbook, full pagewidth −LVS 1 (1) EXTDR 2 (2) +LVS 3 (3) 14 (16) FSL GHL SHL FSR LOGIC SIGNAL GENERATOR HIGH VOLTAGE LEVEL SHIFTER HIGHER RIGHT DRIVER 24 (28) 22 (26) LOWER RIGHT DRIVER 20 (23) 18 (21) GHR SHR GLR PGND 5 (6) HV HIGHER LEFT DRIVER 13 (15) 15 (17) SGND 12 (14) STABILIZER UVLO 23 (27) 7 (9) VDD 11 (13) RC OSCILLATOR 2 8 (10) UBA2032T UBA2032TS SU 10 (12) BD 1.29 V bridge disable 9 (11) DD LOGIC LOW VOLTAGE LEVEL SHIFTER LOWER LEFT DRIVER 17 (20) GLL 4, 6, 16, 19, 21 (4, 5, 7, 8, 18, 19, 22, 24, 25) n.c. MGU542 Pin numbers refer to the UBA2032T. Pin numbers in brackets refer to the UBA2032TS. Fig.1 Block diagram. 2002 Oct 07 3 Philips Semiconductors Preliminary specification Full bridge driver IC PINNING PIN SYMBOL UBA2032T −LVS EXTDR +LVS n.c. n.c. HV n.c. n.c. VDD SU DD BD RC SGND GHL FSL SHL n.c. n.c. GLL PGND n.c. GLR n.c. n.c. SHR FSR GHR 1 2 3 4 − 5 6 − 7 8 9 10 11 12 13 14 15 16 − 17 18 19 20 21 − 22 23 24 UBA2032TS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 negative supply voltage (for logic input) oscillator signal input positive supply voltage (for logic input) not connected not connected high voltage supply input not connected not connected internal low voltage supply input signal for start-up delay divider disable input bridge disable control input RC input for internal oscillator signal ground gate of higher left MOSFET floating supply voltage left source of higher left MOSFET not connected not connected gate of lower left MOSFET power ground not connected gate of lower right MOSFET not connected not connected source of higher right MOSFET floating supply voltage right gate of higher right MOSFET DESCRIPTION UBA2032 2002 Oct 07 4 Philips Semiconductors Preliminary specification Full bridge driver IC UBA2032 handbook, halfpage −LVS 1 EXTDR +LVS n.c. HV n.c. VDD SU DD 2 3 4 5 6 handbook, halfpage 24 GHR 23 FSR 22 SHR 21 n.c. 20 GLR 19 n.c. −LVS 1 EXTDR 2 +LVS 3 28 GHR 27 FSR 26 SHR 25 n.c. 24 n.c. 23 GLR 22 n.c. n.c. 4 n.c. 5 HV 6 n.c. 7 UBA2032T 7 8 9 18 PGND 17 GLL 16 n.c. 15 SHL 14 FSL 13 GHL MGU543 UBA2032TS n.c. 8 VDD 9 SU 10 DD 11 BD 12 RC 13 SGND 14 MGU544 21 PGND 20 GLL 19 n.c. 18 n.c. 17 SHL 16 FSL 15 GHL BD 10 RC 11 SGND 12 Fig.2 Pin configuration (SO24). Fig.3 Pin configuration (SSOP28). FUNCTIONAL DESCRIPTION Supply voltage The UBA2032 is powered by a supply voltage applied to pin HV, for instance the supply voltage of the full bridge. The IC generates its own low supply voltage for the internal circuitry. Therefore an additional low voltage supply is not required. A capacitor has to be connected to pin VDD to obtain a ripple-free internal supply voltage. The circuit can also be powered by a low voltage supply directly applied to pin VDD. In this case pin HV should be connected to pin VDD or SGND. Start-up With an increasing supply voltage the IC enters the start-up state; the higher power transistors are kept off and the lower power transistors are switched on. During the start-up state the bootstrap capacitors are charged and the bridge output current is zero. The start-up state is defined until VDD = VDD(UVLO), where UVLO stands for Under Voltage Lock-out. The state of the outputs during the start-up phase is overruled by the bridge disable function. Release of the power drive At the moment the supply voltage on pin VDD or HV exceeds the level of release power drive the output voltage of the bridge depends on the control signal on pin EXTDR see Table 1. The bridge position after start-up, disable, or delayed start-up (via pin SU) depends on the status of the pins DD and EXTDR. If pin DD = LOW (divider enabled) the bridge will start in the pre-defined position pin GLR and pin GHL = HIGH and pin GLL and pin GHR = LOW. If pin DD = HIGH (divider disabled) the bridge position will depend on the status of pin EXTDR. If the supply voltage on pin VDD or HV decreases and drops below the reset level of power drive the IC enters the start-up state again. Oscillation At the point where the supply voltage on pin HV crosses the level of release power drive, the bridge begins commutating between the following two defined states: • Higher left and lower right MOSFETs on, higher right and lower left MOSFETs off • Higher left and lower right MOSFETs off, higher right and lower left MOSFETs on. 2002 Oct 07 5 Philips Semiconductors Preliminary specification Full bridge driver IC The oscillation can take place in three different modes: • Internal oscillator mode. In this mode the bridge commutating frequency is determined by the values of an external resistor (Rosc) and capacitor (Cosc). In this mode pin EXTDR must be connected to pin +LVS. To realize an accurate 50% duty factor, the internal divider should be used. The internal divider is enabled by connecting pin DD to SGND. Due to the presence of the divider the bridge frequency is half the oscillator frequency. The commutation of the bridge will take place at the falling edge of the signal on pin RC. To minimize the current consumption pins +LVS, −LVS and EXTDR can be connected together to either pin SGND or VDD. In this way the current source in the logic voltage supply circuit is shut off. • External oscillator mode without the internal divider. In the external oscillator mode the external source is connected to pin EXTDR and pin RC is short-circuited to pin SGND to disable the internal oscillator. If the internal divider is disabled (DD = VDD) the duty factor of the bridge output signal is determined by the external oscillator signal and the bridge frequency equals the external oscillator frequency. • External oscillator mode with the internal divider. The external oscillator mode can also be used with the internal divider function enabled (RC = DD = SGND). Due to the presence of the divider the bridge frequency is half the external oscillator frequency. The commutation of the bridge is triggered by the falling edge of the EXTDR signal with respect to V−LVS. If the supply voltage on pin VDD or HV drops below the reset level of power drive, the UBA2032 re-enters the start-up phase. The design equation for the bridge 1 oscillator frequency is: f bridge = -------------------------------------------------- . ( k osc × R osc × C osc ) Non-overlap time The non-overlap time is the time between turning off the conducting pair of MOSFETs and turning on the next pair. The non-overlap time is realized by means of an adaptive non-overlap circuit. With an adaptive non-overlap, the application determines the duration of the non-overlap and makes the non-overlap time optimal for each frequency. The non-overlap time is determined by the duration of the falling slope of the relevant half bridge voltage (see Fig.4). The occurrence of a slope is sensed internally. The minimum non-overlap time is internally fixed. Fig.4 V handbook, halfpage GHR VSHR 0 VGHL VSHL 0 Vhalf bridge left 0 Vhalf bridge right 0 UBA2032 t (sec) MGU545 Half bridge and higher/lower side driver output signals. Divider function If pin DD = SGND then the divider function is enabled/present. If the divider function is present there is no direct relation between the position of the bridge output and the status of pin EXTDR. Start-up delay Normally, the circuit starts oscillating as soon as pin VDD or HV reaches the level of release power drive. At this moment the gate drive voltage is equal to the voltage on pin VDD for the low side transistors and VDD − 0.6 V for the high side transistors. If this voltage is too low for sufficient drive of the MOSFETs the release of the power drive can be delayed via pin SU. A simple RC filter (R between pins VDD and SU; C between pins SU and SGND) can be used to make a delay, or a control signal from a processor can be used. Bridge disable The bridge disable function can be used to switch off all the MOSFETs as soon as the voltage on pin BD exceeds the bridge disable voltage (1.29 V). The bridge disable function overrules all the other states. 2002 Oct 07 6 Philips Semiconductors Preliminary specification Full bridge driver IC Table 1 Logic table; note 1 INPUTS (2) BD HIGH LOW Oscillation state HIGH LOW LOW LOW SU X X X LOW HIGH HIGH DD X X X X HIGH LOW(4) EXTDR X X X X HIGH LOW LOW LOW-to-HIGH HIGH HIGH-to-LOW(5) Notes 1. X = don’t care. 2. BD, SU and DD logic levels are with respect to SGND; EXTDR logic levels are with respect to V−LVS. 3. GHL logic levels are with respect to SHL; GHR logic levels are with respect to SHR; GLL and GLR logic levels are with respect to PGND. GHL LOW LOW LOW LOW LOW HIGH HIGH HIGH HIGH LOW UBA2032 DEVICE STATUS Start-up state OUTPUTS (3) GHR LOW LOW LOW LOW HIGH LOW LOW LOW LOW HIGH GLL LOW HIGH LOW HIGH HIGH LOW LOW LOW LOW HIGH GLR LOW HIGH LOW HIGH LOW HIGH HIGH HIGH HIGH LOW 4. If pin DD = LOW the bridge enters the state (oscillation state and pin BD = LOW and pin SU = HIGH) in the pre-defined position pin GHL and pin GLR = HIGH and pin GLL and pin GHR = LOW. 5. Only if the level of pin EXTDR changes from HIGH-to-LOW, the level of outputs GHL, GHR, GLL and GLR changes from LOW-to-HIGH or from HIGH-to-LOW. 2002 Oct 07 7 Philips Semiconductors Preliminary specification Full bridge driver IC UBA2032 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); all voltages are measured with respect to SGND; positive currents flow into the IC. SYMBOL VDD VHV VFSL VFSR VSHL VSHR VPGND V−LVS V+LVS PARAMETER supply voltage (low voltage) supply voltage (high voltage) floating supply voltage left floating supply voltage right source voltage for higher left MOSFETs source voltage for higher right MOSFETs power ground voltage positive supply voltage for logic input VSHL = VSHR = 550 V VSHL = VSHR = 0 V VSHL = VSHR = 550 V VSHL = VSHR = 0 V with respect to PGND and SGND with respect to SGND; t < 1 µs with respect to PGND and SGND with respect to SGND; t < 1 µs with respect to SGND VHV = 450 V; t < 1 s VHV = 0 V; DC value VHV = 0 V; transient at t < 0.1 µs Vi(EXTDR) Vi(RC) Vi(SU) Vi(BD) Vi(DD) SR Tj Tamb Tstg Vesd input voltage from external oscillator on pin EXTDR input voltage on pin RC input voltage on pin SU input voltage on pin BD input voltage on pin DD slew rate at output pins junction temperature ambient temperature storage temperature electrostatic discharge voltage on pins HV, +LVS, -LVS, EXTDR, FSL, GHL, SHL, SHR, GHR and FSR note 1 with respect to V−LVS DC value transient at t < 0.1 µs DC value transient at t < 0.1 µs DC value transient at t < 0.1 µs DC value transient at t < 0.1 µs repetitive DC value transient at t < 0.1 µs CONDITIONS 0 0 0 0 0 0 0 −3 −14 −3 −14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 −40 −40 −55 − MIN. MAX. 14 17 550 564 14 564 14 +550 − +550 − 5 464 464 14 17 V+LVS VDD 17 VDD 17 VDD 17 VDD 17 4 +150 +150 +150 900 V V V V V V V V V V V V V V V V V V V V V V V V V V/ns °C °C °C V UNIT negative supply voltage for logic input t < 1 s Note 1. In accordance with the Human Body Model (HBM): equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor. 2002 Oct 07 8 Philips Semiconductors Preliminary specification Full bridge driver IC THERMAL CHARACTERISTICS SYMBOL Rth(j-a) UBA2032T UBA2032TS QUALITY SPECIFICATION In accordance with “SNW-FQ-611D”. PARAMETER thermal resistance from junction to ambient CONDITIONS in free air 80 100 VALUE UBA2032 UNIT K/W K/W CHARACTERISTICS Tj = 25 °C; all voltages are measured with respect to SGND; positive currents flow into the IC; unless otherwise specified. SYMBOL High voltage IHV IFSL, IFSR IHV(drive) high voltage supply current high voltage floating supply current supply current on pins EXTDR and +LVS supply current on pin −LVS Start-up; powered via pin HV Ii(HV) VHV(rel) VHV(UVLO) VHV(hys) VDD HV input current level of release power drive voltage reset level of power drive voltage HV hysteresis voltage internal supply voltage VHV = 20 V VHV = 11 V; note 1 − 11 8.5 2.0 10.5 − 8.25 5.75 2.0 0.5 12.5 10 2.5 11.5 1.0 14 11.5 3.0 13.5 mA V V V V t < 0.5 s and VHV = 550 V t < 0.5 s and VFSL = VFSR = 564 V t < 0.5 s and VHV(drive) = 464 V t < 0.5 s and VHV(drive) = 450 V 0 0 0 0 − − − − 30 30 30 30 µA µA µA µA PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Start-up; powered via pin VDD Ii(DD) VDD(rel) VDD(UVLO) VDD(hys) VDD input current level of release power drive voltage reset level of power drive voltage hysteresis voltage VDD = 8.25 V; note 2 0.5 9.0 6.5 2.5 1.0 9.75 7.25 3.0 mA V V V 2002 Oct 07 9 Philips Semiconductors Preliminary specification Full bridge driver IC UBA2032 SYMBOL Output stage Ron(H) Roff(H) Ron(L) Roff(L) Io(source) Io(sink) Vdiode Tslope tno(min) VFSL VFSR IFSL IFSR DD input VIH VIL Ii(DD) SU input VIH VIL Ii(SU) VIH VIL Ii(EXTDR) fbridge I+LVS V+LVS Vref(dis) Ii(BD) PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Ω Ω Ω Ω mA mA V V/µs ns V V µA µA V V µA V V µA V V µA kHz µA V higher MOSFETs on resistance higher MOSFETs off resistance lower MOSFETs on resistance lower MOSFETs off resistance output source current output sink current bootstrap diode voltage drop minimum ∆V/∆T for adaptive non-overlap minimum non-overlap time HS lockout voltage left HS lockout voltage right FS supply current left FS supply current right VFSR = VFSL = 12 V; with respect to 15 SHR and SHL; Isource = 50 mA VFSR = VFSL = 12 V; with respect to 9 SHR and SHL; Isink = 50 mA VDD = 12 V; Isource = 50 mA VDD = 12 V; Isink = 50 mA VDD = VFSL = VFSR = 12 V; VGHR = VGHL = VGLR = VGLL = 0 V 15 9 130 21 14 21 14 180 200 1.0 15 900 4.0 4.0 4 4 − − − − − − − − − − 250 − 1.29 − 26 18 26 18 − − 1.2 25 1300 5.0 5.0 6 6 − 3 1 − 2 1 − 1.0 1 200 VDD = VFSL = VFSR = 12 V; 150 VGHR = VGHL = VGLR = VGLL = 12 V Idiode = 1 mA absolute values 0.8 5 600 3.0 3.0 VFSL = 12 V VFSR = 12 V VDD = 12 V 2 2 HIGH-level input voltage LOW-level input voltage input current into pin DD 6 − − HIGH-level input voltage LOW-level input voltage input current into pin SU VDD = 12 V 4 − − External drive input HIGH-level input voltage LOW-level input voltage input current into pin EXTDR bridge frequency note 3 with respect to V−LVS with respect to V−LVS 4.0 − − − Low voltage logic supply low voltage supply current low voltage supply voltage V+LVS = VEXTDR = 5.75 to 14 V with − respect to V−LVS with respect to V−LVS 5.75 500 14 Bridge disable circuit disable reference voltage disable input current 1.23 − 1.35 1 V µA 2002 Oct 07 10 Philips Semiconductors Preliminary specification Full bridge driver IC UBA2032 SYMBOL Internal oscillator fbridge ∆fosc(T) ∆fosc(VDD) kH kL kosc Rext Notes PARAMETER CONDITIONS MIN. − −10 −10 0.38 − 0.94 100 TYP. − 0 0 0.4 0.01 1.02 − MAX. UNIT bridge oscillating frequency oscillator frequency variation with respect to temperature oscillator frequency variation with respect to VDD high level trip point low level trip point oscillator constant external resistor to VDD note 3 fbridge = 250 Hz and Tamb = −40 to +150 °C fbridge = 250 Hz and VDD = 7.25 to 14 V VRC(high) = kH × VDD VRC(low) = kL × VDD fbridge = 250 Hz 100 +10 +10 0.42 − 1.10 − kHz % % kΩ 1. The current is specified without commutation of the bridge. The current into pin HV is limited by a thermal protection circuit. The current is limited to 11 mA at Tj = 150 °C. 2. The current is specified without commutation of the bridge and pin HV is connected to VDD. 3. The minimum frequency is mainly determined by the value of the bootstrap capacitors. 2002 Oct 07 11 Philips Semiconductors Preliminary specification Full bridge driver IC APPLICATION INFORMATION Basic application A basic full bridge configuration with an HID lamp is shown in Fig.5. The bridge disable, the start-up delay and the external drive functions are not used in this application. The pins −LVS, +LVS, EXTDR and BD are short-circuited to SGND. The internal oscillator is used and to realise a 50% duty cycle the internal divider function has to be used by connecting pin DD to SGND. The IC is powered by the high voltage supply. Because the internal oscillator is UBA2032 used, the bridge commutating frequency is determined by the values of Rosc and Cosc. The bridge starts oscillating when the HV supply voltage exceeds the level of release power drive (typically 12.5 V on pin HV). If the supply voltage on pin HV drops below the reset level of power drive (typically 10 V on pin HV), the UBA2032 enters the start-up state. handbook, fullhigh voltage pagewidth 550 V (max) R >100 Ω 1 2 3 5 7 8 9 10 11 12 24 23 22 GHR FSR SHR C1 R >100 Ω GLR PGND GLL SHL FSL GHL C2 LR IGNITOR LL R >100 Ω HR HL R >100 Ω −LVS EXTDR +LVS HV VDD Ci Rosc C3 SU DD BD RC SGND Cosc UBA2032T 20 18 17 15 14 13 GND MGU546 Fig.5 Basic configuration. 2002 Oct 07 12 Philips Semiconductors Preliminary specification Full bridge driver IC Application with external control Figure 6 shows an application containing a system ground-referenced control circuit. Pin +LVS can be connected to the same supply as the external oscillator control unit and pin −LVS is connected to SGND. Pin RC is UBA2032 short-circuited to SGND. The bridge commutation frequency is determined by the external oscillator. The bridge disable input (pin BD) can be used to immediately turn off all four MOSFETs in the full bridge. high full pagewidth handbook, voltage 550 V (max) R >100 Ω 1 2 3 5 7 8 9 10 11 12 24 23 22 GHR FSR SHR C1 R >100 Ω GLR PGND GLL SHL FSL GHL C2 LR IGNITOR LL R >100 Ω HR HL R >100 Ω low voltage −LVS EXTDR +LVS HV VDD SU DD BD RC C3 SGND UBA2032T 20 18 17 15 14 13 Ci EXTERNAL OSCILLATOR CONTROL CIRCUIT GND MGU547 Fig.6 External control configuration. 2002 Oct 07 13 Philips Semiconductors Preliminary specification Full bridge driver IC Car headlight application The life of an HID lamp depends of the rate of sodium migration through the quartz wall of the lamp. To minimize this, the lamp must operate negative with respect to the system ground. Figure 5 shows a full bridge with an HID lamp for a car headlight application, along with a control UBA2032 circuit referenced to the system ground and with a bridge voltage operating at high negative voltages with respect to the system ground. Pin +LVS and HV can be connected to the same supply as the control unit The output state of the bridge is related to the position of pin EXTDR. See also the timing diagram. handbook, full pagewidth + low voltage supply BRIDGE CONTROL UNIT system GND −LVS EXTDR +LVS HV VDD Ci SU DD BD C3 RC SGND R >100 Ω 1 2 3 6 9 10 11 12 13 14 23 GLR PGND GLL SHL FSL GHL MGU803 HR HL R >100 Ω 28 27 26 GHR FSR SHR C1 R >100 Ω LR IGNITOR LL R >100 Ω UBA2032TS 21 20 17 16 15 C2 high voltage − 450 V (max) Fig.7 Car headlight application. 2002 Oct 07 14 Philips Semiconductors Preliminary specification Full bridge driver IC Additional application information GATE RESISTORS At ignition of an HID lamp, a large EMC spark occurs. This can result in a large voltage transient or oscillation at the gates of the full bridge MOSFETs (LL, LR, HR and HL). When these gates are directly coupled to the gate drivers (pins GHR, GLR, GHL and GLL), voltage overstress of the driver outputs may occur. Therefore it is advised to add a resistor with a minimum value of 100 Ω in series with each gate driver to isolate the gate driver outputs from the actual power MOSFETs gate. UBA2032 GATE CHARGE AND SUPPLY CURRENT AT HIGH FREQUENCY USE The total gate current needed to charge the gates of the power MOSFETs equals: I gate = 4 × f bridge × Q gate . Where: Igate = gate current fbridge = bridge frequency Qgate = gate charge. This current is supplied via the internal low voltage supply (VDD). Since this current is limited to 11 mA (see table “Characteristics”, note 1), at higher frequencies and with MOSFETs having a relative high gate charge, this maximum VDD supply current may not be sufficient anymore. As a result the internal low voltage supply (VDD) and the gate drive voltage will drop resulting in an increase of the on resistance (Ron) of the full bridge MOSFETs. In this case an auxiliary low voltage supply is necessary. 2002 Oct 07 15 Philips Semiconductors Preliminary specification Full bridge driver IC PACKAGE OUTLINES SO24: plastic small outline package; 24 leads; body width 7.5 mm UBA2032 SOT137-1 D E A X c y HE vMA Z 24 13 Q A2 A1 pin 1 index Lp L 1 e bp 12 wM detail X (A 3) θ A 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.10 A1 0.30 0.10 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 15.6 15.2 0.61 0.60 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.050 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) θ 0.9 0.4 0.035 0.016 0.012 0.096 0.004 0.089 0.019 0.013 0.014 0.009 0.419 0.043 0.055 0.394 0.016 8o 0o Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT137-1 REFERENCES IEC 075E05 JEDEC MS-013 EIAJ EUROPEAN PROJECTION ISSUE DATE 97-05-22 99-12-27 2002 Oct 07 16 Philips Semiconductors Preliminary specification Full bridge driver IC UBA2032 SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm SOT341-1 D E A X c y HE vMA Z 28 15 Q A2 pin 1 index A1 (A 3) θ Lp L 1 e bp 14 wM detail X A 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.0 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 10.4 10.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.1 0.7 θ 8 0o o Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT341-1 REFERENCES IEC JEDEC MO-150 EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-04 99-12-27 2002 Oct 07 17 Philips Semiconductors Preliminary specification Full bridge driver IC SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 220 °C for thick/large packages, and below 235 °C for small/thin packages. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. UBA2032 If wave soldering is used the following conditions must be observed for optimal results: • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 2002 Oct 07 18 Philips Semiconductors Preliminary specification Full bridge driver IC Suitability of surface mount IC packages for wave and reflow soldering methods UBA2032 SOLDERING METHOD PACKAGE WAVE BGA, HBGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable REFLOW(1) suitable suitable suitable suitable suitable 2002 Oct 07 19 Philips Semiconductors Preliminary specification Full bridge driver IC DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development DEFINITION UBA2032 This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). II Preliminary data Qualification III Product data Production Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS Short-form specification  The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition  Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information  Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications  These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes  Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 2002 Oct 07 20 Philips Semiconductors Preliminary specification Full bridge driver IC NOTES UBA2032 2002 Oct 07 21 Philips Semiconductors Preliminary specification Full bridge driver IC NOTES UBA2032 2002 Oct 07 22 Philips Semiconductors Preliminary specification Full bridge driver IC NOTES UBA2032 2002 Oct 07 23 Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. © Koninklijke Philips Electronics N.V. 2002 SCA74 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 613502/01/pp24 Date of release: 2002 Oct 07 Document order number: 9397 750 09082 This datasheet has been download from: www.datasheetcatalog.com Datasheets for electronics components.