UM10430

D R A FT D R A FT D R A FT D R A FT D R A FT UM10430 Rev. 00.13 — 20 July 2011 D D D R A FT D D R A FT D FT R A R A FT LPC18xx ARM Cortex-M3 microcontroller D D R R R A FT D R R A FT D D R A FT R User manual A FT D R A FT D A FT A F R A FT D FT D R A D R A Document information Info Keywords Content LPC18xx, LPC1850, LPC1830, LPC1820, LPC1810, LPC1857, LPC1853, LPC1837, LPC1833, LPC1827, LPC1825, LPC1823, LPC1822, LPC1817, LPC1815, LPC1813, LPC1812, LPC1810, ARM Cortex-M3, SPIFI, SCT, USB, Ethernet LPC18xx User manual describing Rev ‘-’ and Rev ‘A’ version of parts LPC1850/30/20/10 (flashless parts). A preliminary description of parts LPC1857/53/37/33/27/25/23/22/17/15/13/12 (flash-based parts) is included. Abstract D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT D R A FT LPC18xx user manual D R A R A FT D R FT D Revision history Rev 0.13 Modifications: Date Description Preliminary LPC18xx User manual. R R A FT D R R A F D R A FT A FT A FT • • • • • • • • • • • • • • • • • • • • • • • • • • Location of C_CAN1 reset updated in the RGU (see Table 91, Table 93, Table 97). Pin P2_7 replaced by pin P2_9 as boot pin in Table 107 and Table 8. Pin P2_7 designated as ISP entry pin in Table 107. Boot ROM size increased to 64 kB. Editorial updates. ISP commands for flashless parts included in Chapter 40. Preliminary LPC18xx User manual. D D R A FT D R A 0.12 Modifications: All content relating to LPC1850/30/20/10 rev ‘-’ moved to Chapter 42. Repeater and plain input mode swapped in SFSP registers (see Section 42.7.4.1). Chapter 7 added. Use of divide-by-two clock for EMC added (Section 19.1). Bit description of RIT MASK register updated (Table 608). Overdrive mode removed in bits 1:0 of the PUMUCON register (see Table 32 and Table 918). Preliminary LPC18xx User manual. 0.11 Modifications: 0.10 Modifications: 0.09 Modifications: Chapter 5, Chapter 6, Chapter 7, Chapter 14, Chapter 35 added. Preliminary LPC18xx User manual. Chapter 14, Chapter 9, Chapter 13, Chapter 15 added. Preliminary LPC18xx User manual. Register bit description and functional description removed in Chapter 17. API calls to be added. Description of MSGVAL bit updated in Table 757. MAC_RWAKE_FRFLT register cannot used with bit-banding. See Table 413. Description of RMII and MII pins corrected in Table 401. Description of Ethernet function in pins P1_16 and PC_8 updated. AES description removed Chapter 4 “LPC18xx Security features”. CGU PLL0 output updated in Table 107. In Table 175, Pin PC_0: Change function 0 to n.c. and move ENET_RX_CLK to function 3. In Table 175, remove all SDIO functions. In Table 175, change CAN1_RD, CAN1_TD to CAN_RD, CAN_TD. Polarity of the ENABLE bit updated in Table 112 (1= power-down). WIC replaced by Event router throughout the manual. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 2 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT D R A FT LPC18xx user manual D R A R A FT D R FT Revision history …continued Rev 0.08 Modifications: Date Description Preliminary LPC18xx User manual. D R R A FT D R R A F D R A FT A FT A FT • • • • • • • • • • • • • • Updated the reference clock for the frequency monitor register (Section 12.6.1). Description of RTC calibration updated (Section 31.7.1). USB0 clock source description added to Table 294. USB1 clock source description added to Table 358. Boot source bit 3 (pin P2_7) and USB0/1 boot modes added to Table 7 and Table 8. Add SRAM control register ETBCFG in CREG block (Table 36). RTC initialization steps updated (Section 31.2). Access of LCD controller to SRAM updated (Section 23.7.1.1 and Section 23.7.1.2). ADC measurement range corrected (Section 38.3). D GPDMA, CxCONTROL register: bits TRANSFERSIZE are given in number of transfers (Table 214). Chapter 4 “LPC18xx Security features” added. Pin configuration updated (Table 175). Flash parts added (see Chapter 1 “Introductory information” and Chapter 2 “LPC18xx Memory mapping”. Chapter 40 “LPC18xx flash programming interface” added. Preliminary LPC18xx User manual. D R A FT D R A 0.07 Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 3 of 1164 D R A FT D R A FT D R A FT D R A FT D R A FT UM10430 Chapter 1: Introductory information Rev. 00.13 — 20 July 2011 D D D R A FT D D R A FT D R A FT D R A R A FT D R A R A FT D R A FT D R A F R A FT D R R D User manual FT D R A FT FT A FT 1.1 Introduction D The LPC18xx are ARM Cortex-M3 based microcontrollers for embedded applications. The ARM Cortex-M3 is a next generation core that offers system enhancements such as low power consumption, enhanced debug features, and a high level of support block integration. The LPC18xx operate at CPU frequencies of up to 150 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branching. The LPC18xx include up to 200 kB of on-chip SRAM data memory (flashless parts) or up to 136 kB of on-chip SRAM and up to 1 MB of flash (parts with on-chip flash), a quad SPI Flash Interface (SPIFI), a State Configurable Timer (SCT) subsystem, two High-speed USB controllers, Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals. Remark: This user manual describes the Rev ‘-’ and Rev ‘A’ versions of parts LPC1850/30/20/10 (flashless parts) and provides a preliminary description of the flash-based LPC18xx parts. The following peripherals are available on LPC1350/30/20/10 Rev ‘A’ only: D R A FT D R A • • • • • I2S1 C_CAN1 GPIO pin interrupts GPIO group interrupt 0/1 Global Input Multiplexer Array (GIMA) 1.2 Features • Processor core – ARM Cortex-M3 processor, running at frequencies of up to 150 MHz. – ARM Cortex-M3 built-in Memory Protection Unit (MPU) supporting eight regions. – ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC). – Non-maskable Interrupt (NMI) input. – JTAG and Serial Wire Debug, serial trace, eight breakpoints, and four watch points. – ETM and ETB support. – System tick timer. • On-chip memory (flashless parts LPC1850/30/20/10) – Up to 200 kB SRAM total for code and data use. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 4 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 1: Introductory information FT D R R A – Two 32 kB SRAM blocks with separate bus access. Both SRAM blocks can be powered down individually. A FT D – 64 kB ROM containing boot code and on-chip software drivers. – 32-bit One-Time Programmable (OTP) memory for general-purpose customer use. D R A D R A R A FT D R FT D R A F R D A FT D R A FT R A FT • On-chip memory (parts with on-chip flash) – Up to 1 MB total dual bank flash memory with flash accelerator. – In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software. – Up to 136 kB SRAM for code and data use. – Two 32 kB SRAM blocks with separate bus access. Both SRAM blocks can be powered down individually. – 32 kB ROM containing boot code and on-chip software drivers. FT D R A – 32-bit One-Time Programmable (OTP) memory for general-purpose customer use. • Clock generation unit – Crystal oscillator with an operating range of 1 MHz to 25 MHz. – 12 MHz internal RC oscillator trimmed to 1 % accuracy. – Ultra-low power RTC crystal oscillator. – Three PLLs allow CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. The second PLL is dedicated to the High-speed USB, the third PLL can be used as audio PLL. – Clock output. • Serial interfaces: – Quad SPI Flash Interface (SPIFI) with four lanes and data rates of up to 40 MB per second total. – 10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high throughput at low CPU load. Support for IEEE 1588 time stamping/advanced time stamping (IEEE 1588-2008 v2). – One High-speed USB 2.0 Host/Device/OTG interface with DMA support and on-chip PHY. – One High-speed USB 2.0 Host/Device interface with DMA support, on-chip full-speed PHY and ULPI interface to external high-speed PHY. – USB interface electrical test software included in ROM USB stack. – Four 550 UARTs with DMA support: one UART with full modem interface; one UART with IrDA interface; three USARTs support synchronous mode and a smart card interface conforming to ISO7816 specification. – Two C_CAN 2.0B controllers with one channel each. – Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA support. – One Fast-mode Plus I2C-bus interface with monitor mode and with open-drain I/O pins conforming to the full I2C-bus specification. Supports data rates of up to 1 Mbit/s. – One standard I2C-bus interface with monitor mode and standard I/O pins. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 5 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 1: Introductory information FT D R R A – Two I2S interfaces with DMA support, each with one input and one output. A D R A R A FT D R FT D R A F R A FT FT • Digital peripherals: D – External Memory Controller (EMC) supporting external SRAM, ROM, NOR flash, and SDRAM devices. A FT – LCD controller with DMA support and a programmable display resolution of up to 1024H  768V. Supports monochrome and color STN panels and TFT color panels; supports 1/2/4/8 bpp CLUT and 16/24-bit direct pixel mapping. – SD/MMC card interface. – Eight-channel General-Purpose DMA (GPDMA) controller can access all memories on the AHB and all DMA-capable AHB slaves. – Up to 80 General-Purpose Input/Output (GPIO) pins with configurable pull-up/pull-down resistors and open-drain modes. – GPIO registers are located on the AHB for fast access. GPIO ports have DMA support. – State Configurable Timer (SCT) subsystem on AHB. – Four general-purpose timer/counters with capture and match capabilities. – One motor control PWM for three-phase motor control. – One Quadrature Encoder Interface (QEI). – Repetitive Interrupt timer (RI timer). – Windowed watchdog timer. – Ultra-low power Real-Time Clock (RTC) on separate power domain with 256 bytes of battery powered backup registers. – Alarm timer; can be battery powered. D R D R A FT D A FT D R A R • Digital peripherals available on flash-based parts LPC18xx only: – • Analog peripherals: – One 10-bit DAC with DMA support and a data conversion rate of 400 kSamples/s. – Two 10-bit ADCs with DMA support and a data conversion rate of 400 kSamples/s. • Security: – Hardware-based AES security engine programmable through an on-chip API. – Two 128-bit secure OTP memories for AES key storage and customer use. – Unique ID for each device. • Power: – Single 3.3 V (2.2 V to 3.6 V) power supply with on-chip internal voltage regulator for the core supply and the RTC power domain. – RTC power domain can be powered separately by a 3 V battery supply. – Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down. – Processor wake-up from Sleep mode via wake-up interrupts from various peripherals. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 6 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 1: Introductory information FT D R R A – Wake-up from Deep-sleep, Power-down, and Deep power-down modes via external interrupts and interrupts generated by battery powered blocks in the RTC power domain. R A – Brownout detect with four separate thresholds for interrupt and forced reset. – Power-On Reset (POR). and 256-pin LBGA packages. • Available as 100-pin, 144-pin, and 208-pin LQFP packages and as 100-pin, 180-pin, 1.3 Ordering information (flashless parts LPC1850/30/20/10) Table 1. Ordering information Package Name LPC1850FET256 LPC1850FET180 LPC1830FET256 LPC1830FET180 LPC1830FET100 LPC1820FET100 LBGA256 Description Plastic low profile ball grid array package; 256 balls; body 17  17  1 mm Plastic low profile quad flat package; 208 leads; body 28 x 28 x 1.4 mm Plastic low profile ball grid array package; 256 balls; body 17  17  1 mm Version sot740-2 sot570-3 sot459-1 sot740-2 sot570-3 sot926-1 sot486-1 sot926-1 sot486-1 sot407-1 sot926-1 Type number D R A R A FT D R FT D R A A FT D R A R A FT F FT D R A FT D FT D D R A TFBGA180 Thin fine-pitch ball grid array package; 180 balls LBGA256 LPC1850FBD208 LQFP208 TFBGA180 Thin fine-pitch ball grid array package; 180 balls TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9 x 9 x 0.7 mm Plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm Plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm Plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9 x 9 x 0.7 mm LPC1830FBD144 LQFP144 LPC1820FBD144 LQFP144 LPC1820FBD100 LQFP100 LPC1810FET100 Table 2. TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9 x 9 x 0.7 mm Ordering options Total SRAM 200 kB 200 kB 200 kB 200 kB 200 kB 168 kB LCD yes yes yes no no no no no no no no Ethernet yes yes yes yes yes yes yes no no no no USB0 (Host, Device, OTG) yes yes yes yes yes yes yes yes yes yes no USB1 (Host, Device) yes yes yes yes yes yes yes no no no no GPIO 164 118 164 164 118 49 83 49 83 49 49 Package LBGA256 TFBGA180 LQFP208 LBGA256 TFBGA180 TFBGA100 LQFP144 TFBGA100 LQFP144 LQFP100 TFBGA100 Type number LPC1850FET256 LPC1850FET180 LPC1830FET256 LPC1830FET180 LPC1830FET100 LPC1820FET100 LPC1850FBD208 200 kB LPC1830FBD144 200 kB LPC1820FBD144 168 kB LPC1820FBD100 168 kB LPC1810FET100 136 kB All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 7 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 1: Introductory information FT D R A D R A R A FT D R FT 1.4 Ordering information (parts with on-chip flash) Table 3. Ordering information (parts with on-chip flash) Package Name LPC1857FET256 LPC1857 LPC1857 LPC1837FET256 LPC1837 LPC1837 LPC1827 LPC1827FET100 LPC1825 LPC1825FET100 LPC1823 LPC1823FET100 LPC1822 LPC1822FET100 LPC1817 LPC1817FET100 LPC1815 LPC1815FET100 LPC1813 LPC1813FET100 LPC1811 LPC1811FET100 Table 4. Type LBGA256 LQFP208 BGA180 LBGA256 LQFP208 BGA180 LQFP144 BGA100 LQFP144 BGA100 LQFP144 BGA100 LQFP144 BGA100 LQFP144 BGA100 LQFP144 BGA100 LQFP144 BGA100 LQFP144 BGA100 Description Type number D R plastic low profile ball grid array package; 256 balls; body 17  17  1 mm plastic low profile ball grid array package; 256 balls; body 17  17  1 mm R A FT R A F D A FT R R D A FT D R A A FT D FT D R A Version sot740-2 sot740-2 Ordering options (parts with on-chip flash) SRAM total Flash total Flash bank A Flash bank B LCD Ethernet USB0 (Host, Device, OTG) yes yes yes yes yes yes yes yes USB1 (Host, Device) yes yes yes yes no no no no Packages LPC1857 LPC1853 LPC1837 LPC1833 LPC1827 LPC1825 LPC1823 LPC1822 136 kB 136 kB 136 kB 136 kB 136 kB 136 kB 104 kB 104 kB 1 MB 512 kB 1 MB 512 kB 1 MB 768 kB 512 kB 512 kB 512 kB 256 kB 512 kB 256 kB 512 kB 384 kB 256 kB 512 kB 512 kB 256 kB 512 kB 256 kB 512 kB 384 kB 256 kB 0 yes yes no no no no no no yes yes yes yes no no no no LBGA256; BGA180; LQFP208 LBGA256; BGA180; LQFP208 LBGA256; BGA180; LQFP208 LBGA256; BGA180; LQFP208 LQFP144; BGA100 LQFP144; BGA100 LQFP144; BGA100 LQFP144; BGA100 © NXP B.V. 2011. All rights reserved. All information provided in this document is subject to legal disclaimers. User manual Rev. 00.13 — 20 July 2011 8 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 1: Introductory information FT D R A D R A R A FT D R FT Table 4. Type Ordering options (parts with on-chip flash) SRAM total Flash total Flash bank A Flash bank B LCD Ethernet USB0 (Host, Device, OTG) no no no no USB1 (Host, Device) no no no no Packages D R R A FT D R R A F D R A FT A FT A FT D R D LPC1817 LPC1815 LPC1813 LPC1812 136 kB 136 kB 104 kB 104 kB 1 MB 768 kB 512 kB 512 kB 512 kB 384 kB 256 kB 512 kB 512 kB 384 kB 256 kB 0 no no no no no no no no LQFP144; BGA100 LQFP144; BGA100 LQFP144; BGA100 LQFP144; BGA100 A FT D R A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 9 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 1: Introductory information FT D R A D R A R A FT D R FT 1.5 Block diagram (flashless parts LPC1850/30/20/10) SWD/TRACE PORT/JTAG D R LPC1850/30/20/10 HIGH-SPEED PHY R A FT D R R A F D R A FT A FT A FT D R A D FT D R A TEST/DEBUG INTERFACE GPDMA ARM CORTEX-M3 I-code bus BRIDGE 0 WWDT USART0 UART1 SSP0 TIMER0 TIMER1 SCU GPIO interrupts GPIO GROUP0 interrupt GPIO GROUP1 interrupt D-code bus system bus ETHERNET(1) 10/100 MAC IEEE 1588 HIGHSPEED USB0(1) HOST/ DEVICE/ OTG USB1(1) HOST/ DEVICE LCD(1) SD/ MMC masters slaves AHB MULTILAYER MATRIX slaves SPIFI EMC 64 kB ROM BRIDGE 1 BRIDGE 2 BRIDGE 3 BRIDGE BRIDGE MOTOR CONTROL PWM(1) I2C0 I2S0 I2S1 C_CAN1 RI TIMER USART2 USART3 TIMER2 TIMER3 SSP1 I2C1 10-bit DAC C_CAN0 10-bit ADC0 10-bit ADC1 CGU CCU1 CCU2 RGU ALARM TIMER BACKUP REGISTERS POWER MODE CONTROL CONFIGURATION REGISTERS EVENT ROUTER OTP MEMORY 64/96 kB LOCAL SRAM 40 kB LOCAL SRAM 16/32 kB AHB SRAM 16 kB + 16 kB AHB SRAM(1) AES HS GPIO SCT QEI(1) RTC GIMA 12 MHz IRC RTC POWER DOMAIN RTC OSC = connected to GPDMA 002aaf218 Fig 1. LPC18xx Block diagram (flashless parts) All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 10 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 1: Introductory information FT D R R A D R A R A FT D R FT D R A R A FT FT D R A FT D R A D A F R A FT D FT D R A TEST/DEBUG INTERFACE ARM CORTEX-M3 tem bus I-code bus D-code bus 0 GPDMA 1 ETHERNET(1) USB0(1) USB1(1) LCD(1) SD/ MMC masters slaves 64 kB ROM 64/96 kB LOCAL SRAM 40 kB LOCAL SRAM Fig 2. LPC18xx AHB multilayer matrix connections (flashless parts) All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 11 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 1: Introductory information FT D R A D R A R A FT D R FT 1.6 Block diagram (parts with on-chip flash) D R R A FT D R R A F D R A FT A FT A FT SWD/TRACE PORT/JTAG D D R A FT D LPC185x/3x/2x/1x HIGH-SPEED PHY R A TEST/DEBUG INTERFACE GPDMA ARM CORTEX-M3 I-code bus BRIDGE 0 WWDT USART0 UART1 SSP0 TIMER0 TIMER1 SCU D-code bus system bus ETHERNET(1) 10/100 MAC IEEE 1588 HIGHSPEED USB0(1) HOST/ DEVICE/ OTG USB1(1) HOST/ DEVICE LCD(1) SD/ MMC(1) masters slaves AHB MULTILAYER MATRIX slaves 512 kB FLASH(1) 512 kB FLASH(1) 32 kB LOCAL SRAM(1) 40 kB LOCAL SRAM BRIDGE 1 BRIDGE 2 BRIDGE 3 BRIDGE BRIDGE MOTOR CONTROL PWM I2C0 I2S0 I2S1 C_CAN1 RI TIMER USART2 USART3 TIMER2 TIMER3 SSP1 I2C1 10-bit DAC C_CAN0 10-bit ADC0 10-bit ADC1 CGU CCU1 CCU2 RGU ALARM TIMER BACKUP REGISTERS POWER MODE CONTROL CONFIGURATION REGISTERS EVENT ROUTER OTP MEMORY 32 kB ROM 32 kB AHB SRAM 16 +16 kB AHB SRAM SCT EMC HS GPIO AES SPI QEI RTC RTC OSC 12 MHz IRC SGPIO = connected to GPDMA RTC POWER DOMAIN SPIFI (1) Not available on all parts (see Table 4). Fig 3. LPC185x/3x/2x/1x block diagram (parts with on-chip flash) All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 12 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 1: Introductory information FT D R R A D R A R A FT D R FT D R A R A FT FT D D A F TEST/DEBUG INTERFACE R R A FT D R A FT D ARM CORTEX-M3 System bus I-code bus D-code bus 0 A GPDMA 1 ETHERNET(1) USB0(1) USB1(1) LCD(1) SD/ MMC(1) FT masters D R A slaves 512 kB FLASH(1) 512 kB FLASH(1) 32 kB ROM 32 kB LOCAL SRAM(1) 40 kB LOCAL SRAM 32 kB AHB SRAM 16 kB + 16 kB AHB SRAM EXTERNAL MEMORY CONTROLLER AHB MULTILAYER MATRIX AHB REGISTER INTERFACES, APB, RTC DOMAIN PERIPHERALS = master-slave connection (1) Not available on all parts (see Table 4). Fig 4. AHB multilayer matrix master and slave connections All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 13 of 1164 D R A FT D R A FT D R A FT D R A FT D R A FT UM10430 Chapter 2: LPC18xx Memory mapping Rev. 00.13 — 20 July 2011 D D D R A FT D D R A FT D R A FT D R A R A FT D R A R A FT D R A FT D R A F R A FT D R R D User manual FT D R A FT FT A FT 2.1 How to read this chapter The available peripherals and their memories vary for different parts. D D R A FT D R A • • • • • Ethernet: available on LPC185x/3x. USB0: available on LPC185x/3x/2x. USB1: available on LPC185x/3x. SRAM: see Table 5. Flash: see Table 6. The registers and memory regions corresponding to unavailable peripheral and memory blocks are reserved. The following memory blocks are available on LPC1350/30/20/10 Rev ‘A’ only: • • • • • I2S1 at address 0x400A 3000. C_CAN1 at address 0x400A 4000. GPIO pin interrupts 0x4008 7000. GPIO group interrupt 0/1 at addresses 0x4008 8000 and 0x4008 9000. High-speed GPIO at address 0x400F 4000 (on parts LPC1850/30/20/10 Rev ‘-’ parts, the GPIO block resides at address 0x400F 0000). • Global Input Multiplexer Array (GIMA) at address 0x400C 7000. 2.2 Basic configuration In the CREG block (see Table 36), select the interface to access the 16 kB block of RAM located at address 0x2000 C000. This RAM memory block can be accessed either by the ETB (this is the default) or be used as normal SRAM on the AHB bus. 2.3 Memory configuration 2.3.1 On-chip static RAM The LPC18xx support up to 136 kB SRAM (parts with on-chip flash) or up to 200 kB SRAM (flashless parts LPC1850/30/20/10) with separate bus master access for higher throughput and individual power control for low power operation. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 14 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 2: LPC18xx Memory mapping FT D R A D R A R A FT D R FT D Table 5. Part LPC185x/3x/2x/1x SRAM configuration Local SRAM Local SRAM Local SRAM 0x1000 0000 0x1001 0000 0x1008 0000 Local SRAM 0x1008 8000 AHB SRAM 0x2000 0000 AHB SRAM 0x2000 8000 AHB SRAM 0x2000 C000 R R A FT D R R A F D R A FT A FT A FT D R A D FT D R A LPC1850 LPC1830 LPC1820 LPC1810 LPC1857 LPC1853 LPC1837 LPC1833 LPC1827 LPC1825 LPC1823 LPC1822 LPC1817 LPC1815 LPC1813 LPC1812 64 kB 64 kB 64 kB 64 kB 32 kB 32 kB 32 kB 32 kB 32 kB 32 kB 32 kB 8 kB 8 kB 8 kB 8 kB 32 kB 32 kB 16 kB 16 kB 16 kB 16 kB 16 kB 16 kB 16 kB 16 kB Figure 5 Figure 5 Figure 5 Figure 5 Figure 7 Figure 7 Figure 7 Figure 7 Figure 7 Figure 7 Figure 7 Figure 7 Figure 7 Figure 7 Figure 7 Figure 7 2.3.2 On-chip flash The available flash configuration for the LPC185x/3x/2x/1x is shown in Table 6. A flash accelerator maximizes performance for use with the two fast AHB buses. Table 6. Part LPC185x/3x/2x/1x Flash configuration Flash bank A 256 kB 0x1A00 0000 LPC1857 LPC1853 LPC1837 LPC1833 LPC1827 LPC1825 LPC1823 LPC1822 LPC1817 yes yes yes yes yes yes yes yes yes Flash bank A 128 kB 0x1A04 000 yes no yes no yes yes no yes yes Flash bank A 128 kB 0x1A0 6000 yes no yes no yes no no yes yes Flash bank B 256 kB 0x1B00 0000 yes yes yes yes yes yes yes no yes Flash bank B 128 kB 0x1B04 000 yes no yes no yes yes no no yes Flash bank B 128 kB 0x1B0 6000 yes no yes no yes no no no yes All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 15 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 2: LPC18xx Memory mapping FT D R A D R A R A FT D R FT Table 6. Part LPC185x/3x/2x/1x Flash configuration Flash bank A 256 kB 0x1A00 0000 yes yes yes Flash bank A 128 kB 0x1A04 000 yes no yes Flash bank A 128 kB 0x1A0 6000 no no yes Flash bank B 256 kB 0x1B00 0000 yes yes no Flash bank B 128 kB 0x1B04 000 yes no no D R Flash bank B 128 kB 0x1B0 6000 no no no R A FT D R R A F D R A FT D A FT D A FT LPC1815 LPC1813 LPC1812 R A FT D R A 2.3.3 Bit banding Remark: Bit banding can not be used with the MAC_RWAKE_FRFLT register (see Section 22.6.10). 2.4 General description All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 16 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 2: LPC18xx Memory mapping FT D R A D R A R A FT D R FT 2.5 Memory map (flashless parts LPC1850/30/20/10) 4 GB reserved D R 0xFFFF FFFF 0xE010 0000 ARM private bus reserved SPIFI data 256 MB dynamic external memory DYCS3 256 MB dynamic external memory DYCS2 reserved peripheral bit band alias region reserved reserved reserved reserved high-speed GPIO reserved AES reserved APB peripherals #3 reserved APB peripherals #2 2000 0000 F00 0000 E00 0000 D00 0000 C00 0000 16 MB static external memory CS3 16 MB static external memory CS2 16 MB static external memory CS1 16 MB static external memory CS0 reserved 1800 0000 1400 0000 64 MB SPIFI data 1 GB reserved 1041 0000 1040 0000 008 A000 64 kB ROM reserved 32 kB + 8 kB local SRAM (LPC1850/30/20/10) reserved 32 kB local SRAM (LPC1850/30/20) 64 kB local SRAM (LPC1850/30/20/10) 1000 0000 reserved 0x2400 0000 32 MB AHB SRAM bit banding 0x2200 0000 reserved 0x2001 0000 16 kB AHB SRAM (LPC1850/30/20/10) 16 kB AHB SRAM (LPC1850/30) 16 kB AHB SRAM (LPC1850/30) 16 kB AHB SRAM (LPC1850/30/20/10) local SRAM/ external static memory banks 0 GB 256 MB shadow area 0x2000 C000 0x2000 8000 0x2000 4000 0x2000 0000 0x1000 0000 0x0000 0000 002aaf228 0xE000 0000 0x8800 0000 0x8000 0000 0x7000 0000 0x6000 0000 0x4400 0000 0x4200 0000 0x4010 2000 0x4010 1000 0x4010 0000 0x400F 8000 0x400F 4000 0x400F 2000 0x400F 1000 0x400F 0000 0x400E 0000 0x400D 0000 0x400C 0000 0x400B 0000 0x400A 0000 0x4009 0000 0x4008 0000 0x4006 0000 R A FT D R R A F D R A FT A FT A FT D R A D FT D R A reserved APB peripherals #1 reserved APB peripherals #0 reserved clocking/reset peripherals RTC domain peripherals reserved 0x4005 0000 0x4004 0000 0x4001 2000 AHB peripherals 256 MB dynamic external memory DYCS1 128 MB dynamic external memory DYCS0 0x4000 0000 0x3000 0000 0x2800 0000 1008 0000 1001 8000 1001 0000 Fig 5. System memory map - flashless parts LPC1850/30/20/10 (see Figure 6 for detailed addresses of all peripherals) All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 17 of 1164 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx User manual Rev. 00.13 — 20 July 2011 18 of 1164 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. NXP Semiconductors 0x400F 0000 0x400E 5000 0x400E 4000 0x400E 3000 0x400E 2000 0x400E 1000 0x400E 0000 0x400C 8000 0x400C 7000 0x400C 6000 0x400C 5000 0x400C 4000 0x400C 3000 0x400C 2000 0x400C 1000 0x400C 0000 0x400B 0000 0x400A 5000 0x400A 4000 0x400A 3000 0x400A 2000 0x400A 1000 0x400A 0000 0x4008 A000 0x4008 9000 0x4008 8000 0x4008 7000 0x4008 6000 0x4008 5000 0x4008 4000 0x4008 3000 0x4008 2000 0x4008 1000 0x4008 0000 reserved ADC1 ADC0 C_CAN0 DAC I2C1 GIMA QEI SSP1 timer3 timer2 USART3 USART2 RI timer reserved C_CAN1 I2S1 I2S0 I2C0 motor control PWM GPIO GROUP1 interrupt GPIO GROUP0 interrupt GPIO interrupts SCU timer1 timer0 SSP0 UART1 w/ modem USART0 WWDT LPC1850/30/20/10 0xFFFF FFFF APB3 peripherals external memories and ARM private bus 0x6000 0000 reserved peripheral bit band alias region reserved reserved reserved APB2 peripherals reserved 0x400F 8000 high-speed GPIO reserved AES reserved APB3 peripherals reserved APB1 peripherals APB2 peripherals reserved APB1 peripherals reserved APB0 peripherals reserved clocking/reset peripherals RTC domain peripherals APB0 peripherals reserved 0x4001 2000 AHB peripherals 0x4000 0000 SRAM memories external memory banks 0x0000 0000 002aaf229 reserved 0x4400 0000 0x4200 0000 0x4010 2000 0x4010 1000 0x4010 0000 reserved RTC OTP controller RTC domain peripherals event router CREG power mode control backup registers alarm timer ethernet reserved LCD USB1 USB0 AHB peripherals EMC SD/MMC SPIFI DMA reserved SCT clocking reset control peripherals RGU CCU2 CCU1 CGU 0x4006 0000 0x4005 4000 0x4005 3000 0x4005 2000 0x4005 1000 0x4005 0000 0x400F 4000 0x400F 2000 0x400F 1000 0x400F 0000 0x400E 0000 0x400D 0000 0x400C 0000 0x400B 0000 0x400A 0000 0x4009 0000 0x4008 0000 0x4006 0000 0x4005 0000 0x4004 0000 0x4004 7000 0x4004 6000 0x4004 5000 0x4004 4000 0x4004 3000 0x4004 2000 0x4004 1000 0x4004 0000 0x4001 2000 0x4001 0000 0x4000 9000 0x4000 8000 0x4000 7000 0x4000 6000 0x4000 5000 0x4000 4000 0x4000 3000 0x4000 2000 0x4000 1000 0x4000 0000 D D D D D R R R R R A A A A A FT FT FT FT FT D D D D R R R R A A A A F F F T T T Chapter 2: LPC18xx Memory mapping FT D D D D R R R R A A A UM10430 FT D R Fig 6. Memory map with peripherals - flashless parts LPC1850/30/20/10 (see Figure 5 for detailed addresses of memory blocks) A FT D R A FT D R A FT D R A FT A R R D A FT D R D FT FT A D F D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 2: LPC18xx Memory mapping FT D R A D R A R A FT D R FT D R 2.6 Memory map (parts with on-chip flash) LPC185x/3x/2x/1x 4 GB reserved 0xFFFF FFFF 0xE010 0000 ARM private bus reserved SPIFI data 256 MB dynamic external memory DYCS3 256 MB dynamic external memory DYCS2 reserved peripheral bit band alias region reserved reserved reserved reserved 0x2000 0000 0x1F00 0000 0x1E00 0000 0x1D00 0000 0x1C00 0000 16 MB static external memory CS3 16 MB static external memory CS2 16 MB static external memory CS1 16 MB static external memory CS0 reserved 0x1B08 0000 0x1B06 0000 0x1B04 0000 0x1B00 0000 0x1A08 0000 0x1A06 0000 0x1A04 0000 0x1A00 0000 128 kB flash bank B 128 kB flash bank B 256 kB flash bank B clocking/reset peripherals reserved 128 kB flash bank A 128 kB flash bank A 256 kB flash bank A 1 GB AHB peripherals 256 MB dynamic external memory DYCS1 128 MB dynamic external memory DYCS0 reserved 0x1040 8000 0x1040 0000 0x1008 A000 0x1008 0000 0x1000 8000 0x1000 0000 32 kB ROM reserved 32 kB + 8 kB local SRAM reserved 32 kB local SRAM(1) 32 MB AHB SRAM bit banding 0x2200 0000 reserved 0x2001 0000 16 kB AHB SRAM 16 kB AHB SRAM 16 kB AHB SRAM 16 kB AHB SRAM local SRAM/dual flash banks/ external static memory banks 0 GB 256 MB shadow area 0x2000 C000 0x2000 8000 0x2000 4000 0x2000 0000 0x1000 0000 0x0000 0000 002aaf228wFlash 0xE000 0000 0x8800 0000 0x8000 0000 0x7000 0000 0x6000 0000 0x4400 0000 0x4200 0000 0x4010 2000 0x4010 1000 0x4010 0000 0x400F 2000 0x400F 1000 0x400F 0000 0x400E 0000 0x400D 0000 0x400C 0000 0x400B 0000 0x400A 0000 0x4009 0000 0x4008 0000 0x4006 0000 0x4005 0000 0x4004 0000 0x4001 2000 0x4000 0000 0x3000 0000 0x2800 0000 0x2400 0000 R A FT D R R A F D R A FT A FT A FT D R A D FT D R A AES high-speed GPIO APB peripherals #3 reserved APB peripherals #2 reserved APB peripherals #1 reserved APB peripherals #0 reserved RTC domain peripherals reserved reserved (1) Not available on all parts (see Table 4). Fig 7. System memory map - parts with on-chip flash (overview) All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 19 of 1164 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx User manual Rev. 00.13 — 20 July 2011 20 of 1164 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. NXP Semiconductors 0x400F 0000 0x400E 5000 0x400E 4000 0x400E 3000 0x400E 2000 0x400E 1000 0x400E 0000 0x400D 0000 0x400C 7000 0x400C 6000 0x400C 5000 0x400C 4000 0x400C 3000 0x400C 2000 0x400C 1000 0x400C 0000 0x400B 0000 0x400A 5000 0x400A 4000 0x400A 3000 0x400A 2000 0x400A 1000 0x400A 0000 0x4009 0000 0x4008 7000 0x4008 6000 0x4008 5000 0x4008 4000 0x4008 3000 0x4008 2000 0x4008 1000 0x4008 0000 reserved SCU timer1 timer0 SSP0 UART1 w/ modem USART0 WWDT reserved QEI SSP1 timer3 timer2 USART3 USART2 RI timer reserved C_CAN1 I2S1 I2S0 I2C0 motor control PWM reserved ADC1 ADC0 C_CAN0 DAC I2C1 LPC185x/3x/2x/1x APB3 peripherals 0xFFFF FFFF external memories and ARM private bus 0x6000 0000 reserved peripheral bit band alias region reserved reserved 0x4400 0000 0x4200 0000 0x4010 2000 0x4010 1000 0x4010 0000 0x400F 2000 0x400F 1000 0x400F 0000 0x400E 0000 0x400D 0000 0x400C 0000 0x400B 0000 0x400A 0000 0x4009 0000 0x4008 0000 0x4006 0000 0x4005 0000 0x4004 0000 0x4001 2000 AHB peripherals 0x4000 0000 SRAM memories external memory banks 0x0000 0000 AHB peripherals ethernet(1) reserved LCD(1) USB1(1) USB0(1) EMC SD/MMC(1) SPIFI DMA reserved SCT RTC domain peripherals reserved RTC OTP controller event router CREG power mode control backup registers alarm timer reserved clocking and reset control peripherals RGU CCU2 CCU1 CGU 0x4006 0000 0x4005 4000 0x4005 3000 0x4005 2000 0x4005 1000 0x4005 0000 APB2 peripherals reserved reserved AES high-speed GPIO APB peripherals #3 reserved APB peripherals #2 reserved 0x4004 7000 0x4004 6000 0x4004 5000 0x4004 4000 0x4004 3000 0x4004 2000 0x4004 1000 0x4004 0000 0x4001 2000 0x4001 0000 0x4000 9000 0x4000 8000 0x4000 7000 0x4000 6000 0x4000 5000 0x4000 4000 0x4000 3000 0x4000 2000 0x4000 1000 0x4000 0000 002aaf229wFlash APB1 peripherals APB peripherals #1 reserved APB peripherals #0 reserved clocking/reset peripherals RTC domain peripherals reserved D D D D D R R R R R A A A A A FT FT FT FT FT D D D D R R R R A A A A F F F T T T Chapter 2: LPC18xx Memory mapping FT D D D D R R R R A A A APB0 peripherals UM10430 (1) Not available on all parts (see Table 4). FT D R Fig 8. Memory mapping - parts with on-chip flash (peripherals) A FT D R A FT D R A FT D R A D A FT A F R R D A FT D R D FT FT D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 2: LPC18xx Memory mapping FT D R R A D R A R A FT D R FT D R A R A FT FT D R A FT D R A D A F R A FT D FT D R A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 21 of 1164 D R A FT D R A FT D R A FT D R A FT D R A FT UM10430 Chapter 3: LPC18xx Boot ROM Rev. 00.13 — 20 July 2011 D D D R A FT D D R A FT D R A FT D R A R A FT D R A R A FT D R A FT D R A F R A FT D R R D User manual FT D R A FT FT A FT 3.1 How to read this chapter This chapter applies to flashless parts LPC1850/30/20/10 only. D D R A FT D R A 3.2 Features The boot ROM memory includes the following features: • ROM memory size is 64 kB. • Supports booting from UART interfaces and external static memory such as NOR flash, SPI flash, quad SPI flash. • Includes APIs for power control and OTP programming. • Includes SPIFI and USB drivers. • ISP mode for loading data to on-chip SRAM and execute code from on-chip SRAM. AES capable parts also support: • CMAC authentication on the boot image. • Secure booting from an encrypted image. • Supports development mode for booting from a plain text image. Development mode is terminated by programming the AES key. • API for AES programming. 3.3 Functional description The internal ROM memory is used to store the boot code. After a reset, the ARM processor will start its code execution from this memory. The ARM core is configured to start executing code, upon reset, with the program counter being set to the value 0x0000 0000. The LPC18xx contains a shadow pointer that allows areas of memory to be mapped to address 0x0000 0000. The default value of the shadow pointer is 0x1040 0000, ensuring that the code contained in the boot ROM is executed at reset. Several boot modes are available depending on the values of the OTP bits BOOT_SRC. If the OTP memory is not programmed or the BOOT_SRC bits are all zero, the boot mode is determined by the states of the boot pins p2_8, P2_8, P1_2, and P1_1. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 22 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 3: LPC18xx Boot ROM FT D R A D R A R A FT D R FT D Table 7. Boot mode when OTP BOOT_SRC bits are programmed BOOT_SRC BOOT_SRC BOOT_SRC bit 3 bit 2 bit 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 BOOT_SRC Description bit 0 0 1 0 1 0 1 0 1 0 1 R R A FT R A F A FT Boot mode Boot pins UART SPIFI EMC 8-bit EMC 16-bit EMC 32-bit USB0 USB1 SPI (SSP) USART3 [1] D Boot source is defined by the reset state of P1_1, P1_2, and P2_8 pins. See Table 8. Boot from device connected to USART0 using pins P2_0 and P2_1. Boot from Quad SPI flash connected to the SPIFI interface using pins P3_3 to P3_8. Boot from external static memory (such as NOR flash) using CS0 and an 8-bit data bus. Boot from external static memory (such as NOR flash) using CS0 and a 16-bit data bus. Boot from external static memory (such as NOR flash) using CS0 and a 32-bit data bus. Boot from USB0. Boot from USB1. Boot from SPI flash connected to the SSP0 interface on P3_3, P3_6, P3_7 and P3_8[1]. Boot from device connected to USART3 using pins P2_3 and P2_4. D R A FT D R A FT D A FT D R A R The boot loader programs the appropriate pin function at reset to boot using either SSP0 or SPIFI. Table 8. USART0 SPIFI EMC 8-bit EMC 16-bit EMC 32-bit USB0 USB1 SPI (SSP) USART3 [1] Boot mode when OPT BOOT_SRC bits are zero P2_9 LOW LOW LOW LOW LOW LOW LOW LOW HIGH P2_8 LOW LOW LOW LOW HIGH HIGH HIGH HIGH LOW P1_2 LOW LOW HIGH HIGH LOW LOW HIGH HIGH LOW P1_1 LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW Description Boot from device connected to USART0 using pins P2_0 and P2_1. Boot from Quad SPI flash connected to the SPIFI interface on P3_3 to P3_8[1]. Boot from external static memory (such as NOR flash) using CS0 and an 8-bit data bus. Boot from external static memory (such as NOR flash) using CS0 and a 16-bit data bus. Boot from external static memory (such as NOR flash) using CS0 and a 32-bit data bus. Boot from USB0. Boot from USB1. Boot from SPI flash connected to the SSP0 interface on P3_3, P3_6, P3_7 and P3_8[1]. Boot from device connected to USART3 using pins P2_3 and P2_4. Boot mode The boot loader programs the appropriate pin function at reset to boot using either SSP0 or SPIFI. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 23 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 3: LPC18xx Boot ROM FT D R A D R A R A FT D R FT 3.3.1 AES capable devices D R AES capable products will normally always boot from a secure (encrypted) image and use CMAC authentication. However a special development mode allows booting from a plain text image. This development mode is active when the AES key has not been programmed. In this case the AES key consists of all zeros. Once the key is programmed (to a non-zero value), the development mode is terminated. D R A FT D R A FT R A F D R A FT D FT D R A R A A FT 3.3.2 Boot process The top level boot process is illustrated in Figure 9. The boot starts after Reset is released. The IRC is selected as CPU clock and the Cortex-M3 starts by executing boot ROM. By default the JTAG access to the chip is disabled at reset. When the part is non-AES capable or it is AES capable but the AES key has not been programmed then JTAG access is enabled. As shown in Figure 9, the boot ROM determines the boot mode based on the OTP BOOT_SRC value or reset state of the pins P1_1, P1_2, P2_8, and P2_9. The boot ROM copies the image to internal SRAM at location 0x1000 0000 and jumps to that location (sets ARM's shadow pointer to 0x1000 0000) after image verification. Hence the images for LPC18xx should be compiled with entry point at 0x0000 0000. On AES capable LPC18xx with a programmed AES key the image and header are authenticated using the CMAC algorithm. If authentication fails the device is reset. On AES capable LPC18xx in development mode and non-AES capable LPC18xx, the image and header are not authenticated. If the image is not preceded by a header then the image is not copied to SRAM but assumed to be executable as-is. In that case the shadow pointer is set to the first address location of the external boot memory. The header-less images for LPC18xx should be compiled with entry point at 0x0000 0000, the same as for an image with header. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 24 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 3: LPC18xx Boot ROM FT D R R A D R A R A FT D R FT D R A R A FT FT D R A FT D R A D A F R A FT D LPC18xx RESET CPU clock = IRC 12MHz disable IRQ & MPU AES capable and key>0? yes load AES key FT D no R A enable JTAG CPU clock = PLL1 96 MHz =1 =0 check pins P2_9,P2_8,P1_2, P1_1 =1..4,7 >9 check BOOT SRC _ =6..7,9 >10 =2..5,8 =0 BOOT_ SRC =1 or pins =0 BOOT _SRC = 9 or pins = 8 BOOT _ SRC= 8 or pins = 7 BOOT _ SRC= 2 or pins = 1 BOOT _ SRC= 3 or pins = 2 BOOT_ SRC =4 or pins =3 BOOT _ SRC =5 or pins =4 BOOT _SRC = 6 or pins = 5 BOOT _SRC = 7 or pins = 6 SPI boot SPIFI boot EMC 8 b boot EMC 16b boot EMC 32b boot UART 0 boot UART 3 boot USB 1 boot USB 2 boot read Header read Header valid Header ? yes no yes valid Header ? no AES capable and CMAC active? yes copy image to SRAM and calculate CMAC tag no no development mode ? yes no valid tag ? yes decrypt image in SRAM copy image to SRAM 60s timeout toggle pin P1_1 set Shadow Pointer = boot address 4 of set Shadow Pointer = 0x 1000 0000 set Shadow Pointer = 0x1000 0000 Reset Fig 9. Boot process All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 25 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 3: LPC18xx Boot ROM FT D R A D R A R A FT D R FT 3.3.3 Boot image format D R AES capable products with a programmed AES key will always boot from a secure image and use CMAC authentication. A secure image should always include a header. D R A FT D Non-AES capable products may boot from an image with header or execute directly from the boot source (when the boot source is memory mapped; SPIFI or EMC). When no valid header is found then the CPU will try to execute code from the first location of the memory mapped boot source. The user should take care that this location contains executable code, otherwise a hard fault exception will occur. This exception jumps to a while(1) loop. The image must be preceded by a header that has the layout described in Table 9. Non-encrypted images may omit the header. Table 9. Address 5:0 Image header Name AES_ACTIVE[1] Description AES encryption active 0x25 (100101): AES encryption active 0x1A (011010): AES encryption not active else: invalid image 7:6 HASH_ACTIVE[1] Indicates whether a hash is used: 00: CMAC hash is used, value is HASH_VALUE 01: reserved 10: reserved 11: no hash is used 13:8 15:14 reserved AES_CONTROL 11...11 (binary) 6 These 2 bits can be set to a value such that 2 when AES encryption is active, that the AES_ACTIVE field, after AES encryption, is not equal to the value 0x1A (AES encryption not active) Size of the part of the image over which the hash value is calculated in number of 512 Byte frames. Also size of image copied to internal SRAM at boot time. Hash size = 16[2] + HASH_SIZE x 512 Byte. 95:32 HASH_VALUE CMAC hash value calculated over the first bytes of the image (starting right from the header) as indicated by HASH_SIZE. The value is truncated to the 64 MSB. 11...11 (binary) 64 16 2 size [bits] 6 R A FT R A F D R A FT D R A FT D R A A FT 31:16 HASH_SIZE[3] 127:96 [1] [2] [3] reserved 32 Can only be active if device is AES capable, else is considered an invalid image. 16 extra bytes are required for the header bytes. The image size should be set to no more than the size of the SRAM located at 0x1000 0000. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 26 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 3: LPC18xx Boot ROM FT D R A D R A R A FT D R FT 3.3.4 Boot image creation 3.3.4.1 CMAC D R The CMAC algorithm is used to calculate a tag which is used for image authentication. The tag is stored in the header field HASH_VALUE. The authentication process is as follows: 1. Use the CMAC algorithm to generate the 128-bit tag. Truncate the tag to 64 MSB and insert this truncated tag in the header. 2. At boot time the tag is recalculated. Authentication passes when the calculated tag is equal to the received tag in the image header. To generate an l-bit CMAC tag T of message M using a 128-bit block cipher AES and secret key K, the CMAC tag generation process is as follows: 1. Generate sub key K1: – Calculate a temporary value K0 = AESK(0). – If msb(K0) = 0 then K1 = (K0 100 kB. When booting without header then the image should configure extra address pins beyond the initially configured EXTBUS_A[13:0]. Setup Pin Configuration EXTBUS_A[13:0] EXTBUS_CS0 Read Image Header Image size > 16384-16 yes Extend address bus no see main boot flow Fig 13. EMC boot process All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 30 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 3: LPC18xx Boot ROM FT D R A D R A R A FT D R FT 3.3.4.5 SPI boot mode The boot uses SSP0 in SPI mode. The SPI clock is 18 MHz. D R Figure 14 details the boot-flow steps of the SPI flash boot mode. The execution of this mode happens only if the boot mode is set accordingly (see boot modes Table 7 and Table 8). R A FT D R R A F D R A FT A FT A FT D R A D FT D R A Setup clock SSP0_SCK= 18MHz Setup Pin Configuration P3_3, P3_6..P3_8 see main boot flow Fig 14. SPI boot process 3.3.5 Boot process timimg The following paramters describe the timing of the boot process: Table 10. Parameter t_a t_b t_c Boot process timing parameters Description Check boot selection pins Initialize device Copy image to embedded SRAM If part is executing from external flash with no copy If the image is encrypted or must be copied < 1 s to 10000 s depending on the size of the image and the speed of the boot memory Value < 1 s 250 s < 0.3 s All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 31 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 3: LPC18xx Boot ROM FT D R R A D R A R A FT D R FT D R A R A A IRC12 starts IRC12 stable FT D R R A A F FT D IRC12 FT D R A FT FT D RESET VDDREG GND 22 µs supply ramp up 0 .5µs; IRC stability count boot time user code ta µs tb µs initialise device tc µs copy image to embedded SRAM valid threshold D R A processor status check boot selection pins Fig 15. Boot process timing 3.3.6 ISP In-System programming (ISP) is programming or re-programming the on-chip SRAM memory, using the boot loader software and the USART0 serial port. This can be done when the part resides in the end-user board. ISP allows to load data into on-chip SRAM and execute code from on-chip SRAM. For details, see Chapter 40. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 32 of 1164 D R A FT D R A FT D R A FT D R A FT D R A FT UM10430 Chapter 4: LPC18xx Security features Rev. 00.13 — 20 July 2011 D D D R A FT D D R A FT D R A FT D R A R A FT D R A R A FT D R A FT D R A F R A FT D R R D User manual FT D R A FT FT A FT 4.1 How to read this chapter All LPC18xx parts support AES decoding. D D R A FT D R A 4.2 Features • • • • • Decoding of external image data. Secure storage of decoding keys. Support for CMAC hash calculation to authenticate data. AES engine performance of 1 byte/clock cycle. AES engine supports: – ECB decode mode with 128-bit key. – CBC decode mode with 128-bit key. – CMAC hash calculation. 4.3 General description The LPC18xx uses an external image to store instruction code and data. If customers want to protect the external image content, then the LPC18xx offers hardware to accelerate processing for data decoding, data integrity and proof of origin. The hardware consists of: • One-time programmable (OTP) non-volatile memories to store the AES key. Two instances (OTP1/2) are offered to store two keys. A 3rd OTP (OTP3) is used by the LPC18xx for storing other data. • An AES engine to perform the AES decoding. This engine supports an external GPDMA module to read and write data. The engine uses a 128-bit key and processes blocks of 128-bit. The key can use a dedicated hardware interface that is not visible to software or a software interface. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 33 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 4: LPC18xx Security features FT D R R A D R A R A FT D R FT D R A R A FT FT A F Vpp 3V3 Vdd 1V2 OTP0 OTP1 OTP2 D D R A FT D R A FT D A FT D R A R RNG AES_key JTAG OTP controller AES engine Control Data AHB2APB CPU AHB GPDMA Fig 16. AES engine 4.4 AES API calls 4.4.1 Security API The security API controls the AES block. Table 11. Function Security API calls Offset relative to Description the API entry point 0x00 Defines AES engine operation mode Parameter: unsigned cmd with values: 0 - Reserved. Do not use. 1 - AES_API_CMD_DECODE_ECB 2 - Reserved. Do not use. 3 - AES_API_CMD_DECODE_CBC AES_API_Set_Mode Return - unsigned: see general error codes. AES_API_Load_Key_1 0x04 Loads 128 bit AES user key 1 Parameter - void Return - void AES_API_Load_Key_2 0x08 Loads 128 bit AES user key 2 Parameter - void Return - void AES_API_Load_Key_RNG 0x0C Loads randomly generated key in AES engine. Parameter - void Return - void All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 34 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 4: LPC18xx Security features FT D R A D R A R A FT D R FT Table 11. Function Security API calls Offset relative to Description the API entry point 0x10 D R R A FT D R R A F D R A FT A FT A FT AES_API_Load_Key_SW Loads 128 bit AES software defined user key Parameter - unsigned char *key(16 bytes) Return - void D D R A FT D R A AES_API_Load_IV_SW 0x14 Loads 128 bit AES init vector Parameter - unsigned char *iv(16 bytes) Return - void AES_API_Load_IV_IC 0x18 Loads 128 bit AES IC specific init vector, which is used to decode a boot image. Parameter - void Return - void AES_API_Operate 0x1C Performs an operation pre-selected by the selected mode and therefore a key. A previously loaded iv is used. Data_out=AES_OP(data_in*size, key, [iv]) Parameter 1 - unsigned char *data_out Parameter 2 - unsigned char *data_in Parameter 3 - unsigned size (128 bits word 16 bytes) Return - unsigned: see general error codes. AES_API_Program_Key_1 0x20 Programs 128 bit AES key in OTP. Parameter: unsigned char *key (16 bytes) Return - unsigned: see general error codes. AES_API_Program_Key_2 0x24 Programs 128 bit AES key in OTP. Parameter: unsigned char *key (16 bytes) Return - unsigned: see general error codes. 4.4.2 OTP memory The virgin OTP state is all zeros. This implies that a zero value can be overwritten by a one value, but a one value cannot be changed. Programming the OTP requires a higher voltage than reading. The read voltage is generated internally. The programming voltage is supplied via pin VPP. If this pin is not connected, then the OTP can not be programmed. The OTP controller automatically selects the correct voltage. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 35 of 1164 D R A FT D R A FT D R A FT D R A FT D R A FT UM10430 Chapter 5: LPC18xx NVIC Rev. 00.13 — 20 July 2011 D D D R A FT D D R A FT D R A FT D R A R A FT D R A R A FT D R A FT D R A F R A FT D R R D User manual FT D R A FT FT A FT 5.1 How to read this chapter D Remark: This chapter describes the NVIC connections of parts LPC1850/30/20/10 Rev ‘A’. The available NVIC interrupt sources vary for different parts. D R A FT D R A • Ethernet interrupt: available on LPC1850/30. • USB0 interrupt: available on LPC1850/30/20. • USB1 interrupt: available on LPC1850/30. 5.2 Basic configuration The NVIC is part of the ARM Cortex-M3 core. 5.3 Features • • • • • • • • Nested Vectored Interrupt Controller that is an integral part of the ARM Cortex-M3 Tightly coupled interrupt controller provides low interrupt latency Controls system exceptions and peripheral interrupts On the LPC18xx, the NVIC supports 32 vectored interrupts 32 programmable interrupt priority levels, with hardware priority level masking Relocatable vector table Non-Maskable Interrupt Software interrupt generation 5.4 General description The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M3. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts. Refer to the Cortex-M3 User Guide for details of NVIC operation. 5.5 Pin description Table 12. Function NMI NVIC pin description Direction I Description External Non-Maskable Interrupt (NMI) input All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 36 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 5: LPC18xx NVIC FT D R A D R A R A FT D R FT 5.6 Interrupt sources D R Table 13 lists the interrupt sources for each peripheral function. Each peripheral device may have one or more interrupt lines to the Vectored Interrupt Controller. Each line may represent more than one interrupt source, as noted. Exception numbers relate to where entries are stored in the exception vector table. Interrupt numbers are used in some other contexts, such as software interrupts. R A FT In addition, the NVIC handles the Non-Maskable Interrupt (NMI). In order for NMI to operate from an external signal, the NMI function must be connected to the related device pin (P4_0 or PE_4). When connected, a logic one on the pin will cause the NMI to be processed. For details, refer to the Cortex-M3 User Guide. Table 13. Connection of interrupt sources to the NVIC Function DAC DMA Ethernet SD/MMC LCD USB0 USB1 SCT RI timer Timer0 Timer1 Timer2 Timer3 Motor control PWM ADC0 I2C0 I2C1 ADC1 SSP0 SSP1 USART0 UART1 USART2 USART3 I2S0 © NXP B.V. 2011. All rights reserved. R A FT D R A F D R A FT D A FT D R A R A FT D Interrupt Exception Vector ID Number Offset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Flag(s) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 Reserved Reserved Reserved Ethernet interrupt sbd_intr_o OTG interrupt OTG interrupt SCT combined interrupt Reserved UART and modem interrupt USART and IrDA interrupt All information provided in this document is subject to legal disclaimers. User manual Rev. 00.13 — 20 July 2011 37 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 5: LPC18xx NVIC FT D R A D R A R A FT D R FT Table 13. Connection of interrupt sources to the NVIC Function I2S1 SPIFI GPIO pin interrupt 0 GPIO pin interrupt 1 GPIO pin interrupt 2 GPIO pin interrupt 3 GPIO pin interrupt 4 GPIO pin interrupt 5 GPIO pin interrupt 6 GPIO pin interrupt 7 GPIO group interrupt 0 GPIO group interrupt 1 Event router C_CAN1 interrupt Reserved Reserved ATIMER Reserved Reserved WWDT Reserved C_CAN0 QEI Reserved Flag(s) D R R A R A A Interrupt Exception Vector ID Number Offset 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 0xB4 0xB8 0xBC 0xC0 0xC4 0xC8 0xCC 0xD0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC 0x100 FT D R R A A FT D R A FT F Combined interrupt from the event router sources FT D FT D D R A 5.7 Register description The following table summarizes the registers in the NVIC as implemented in the LPC18xx. The Cortex-M3 User Guide provides a functional description of the NVIC. Table 14. Name ISER0 ISER1 ICER0 Register overview: NVIC (base address 0xE000 E000) Access Address offset RW RW RW 0x100 0x104 0x180 Description Interrupt Set-Enable Register 0. This register allows enabling interrupts and reading back the interrupt enables for specific peripheral functions. Interrupt Set-Enable Register 1. This register allows enabling interrupts and reading back the interrupt enables for specific peripheral functions. Interrupt Clear-Enable Register 0. This register allows disabling interrupts and reading back the interrupt enables for specific peripheral functions. All information provided in this document is subject to legal disclaimers. Reset value 0 0 0 © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 38 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 5: LPC18xx NVIC FT D R A D R A R A FT D R FT Table 14. Name ICER1 ISPR0 Register overview: NVIC (base address 0xE000 E000) …continued Access Address offset RW RW 0x184 0x200 Description D R Interrupt Clear-Enable Register 1. This register allows disabling interrupts and reading back the interrupt enables for specific peripheral functions. Interrupt Set-Pending Register 0. This register allows changing the interrupt state to pending and reading back the interrupt pending state for specific peripheral functions. Interrupt Set-Pending Register 1. This register allows changing the interrupt state to pending and reading back the interrupt pending state for specific peripheral functions. Interrupt Clear-Pending Register 0. This register allows changing the interrupt state to not pending and reading back the interrupt pending state for specific peripheral functions. Interrupt Clear-Pending Register 0. This register allows changing the interrupt state to not pending and reading back the interrupt pending state for specific peripheral functions. Interrupt Active Bit Register 0. This register allows reading the current interrupt active state for specific peripheral functions. Interrupt Active Bit Register 1. This register allows reading the current interrupt active state for specific peripheral functions. Interrupt Priority Registers 0. This register allows assigning a priority to each interrupt. Each register contains the 5-bit priority fields for 4 interrupts. Interrupt Priority Registers 1 This register allows assigning a priority to each interrupt. Each register contains the 5-bit priority fields for 4 interrupts. Interrupt Priority Registers 2. This register allows assigning a priority to each interrupt. Each register contains the 5-bit priority fields for 4 interrupts. Interrupt Priority Registers 3. This register allows assigning a priority to each interrupt. Each register contains the 5-bit priority fields for 4 interrupts. Interrupt Priority Registers 4. This register allows assigning a priority to each interrupt. Each register contains the 5-bit priority fields for 4 interrupts. Interrupt Priority Registers 5. This register allows assigning a priority to each interrupt. Each register contains the 5-bit priority fields for 4 interrupts. Interrupt Priority Registers 6. This register allows assigning a priority to each interrupt. Each register contains the 5-bit priority fields for 4 interrupts. Interrupt Priority Registers 7. This register allows assigning a priority to each interrupt. Each register contains the 5-bit priority fields for 4 interrupts. R A FT D 0 0 R A F D R A FT D R A FT D R A Reset value A FT D R A FT ISPR1 RW 0x204 0 ICPR0 RW 0x280 0 ICPR1 RW 0x284 0 IABR0 IABR1 IPR0 IPR1 IPR2 IPR3 IPR4 IPR5 IPR6 IPR7 STIR RO RO RW RW RW RW RW RW RW RW WO 0x300 0x304 0x400 0x404 0x408 0x40C 0x410 0x414 0x418 0x41C 0xF00 0 0 0 0 0 0 0 0 0 0 Software Trigger Interrupt Register. This register allows software to generate an 0 interrupt. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 39 of 1164 D R A FT D R A FT D R A FT D R A FT D R A FT UM10430 Chapter 6: LPC18xx Event router Rev. 00.13 — 20 July 2011 D D D R A FT D D R A FT D R A FT D R A R A FT D R A R A FT D R A FT D R A F R A FT D R R D User manual FT D R A FT FT A FT 6.1 How to read this chapter Remark: This chapter applies to parts LPC1850/30/30/10 Rev ‘A’ only. D Remark: The event router controls the wake-up process and various event inputs to the NVIC. The available event router sources vary for different parts. D R A FT D R A • Ethernet: available on LPC1850/30. • USB0: available on LPC1850/30/20. • USB1: available on LPC1850/30. 6.2 Basic configuration • See Table 15 for clocking. • An event created in the event router can be output on the RTC_ALARM pin (see Table 31). • The event router is connected to interrupt #42 in the NVIC (see Table 13). Table 15. Event router clocking and power control Base clock Clock to event router BASE_M3_CLK Branch clock Maximum frequency CLK_M3_BUS 150 MHz 6.3 General description The event router is used to process wake-up events such as certain interrupts and external or internal inputs for wake-up from any of the low power modes (Sleep, Deep-sleep, Power-down, and Deep power-down modes). The event router has multiple event inputs from various peripherals. When the proper edge detection is set in the EDGE configuration register, the event router can wake up the part or can raise an interrupt in the NVIC. Each event input to the event router can be configured to trigger an output signal on rising or falling edges or on HIGH or LOW levels. The event router combines all events to an output signal which is used as follows: • Create an interrupt if the event router interrupt is enabled in the NVIC. • Send a wake-up signal to the power management unit to wake up from Deep-sleep, Power-down, and Deep power-down modes. • Send a wake-up signal to CCU1 and CCU2 for waking up from Sleep mode (see Section 14.5.3). All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 40 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 6: LPC18xx Event router FT D R A D R A R A FT D R FT 6.4 Event router inputs Table 16. Event # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 Event router inputs Source WAKEUP0 WAKEUP1 WAKEUP2 WAKEUP3 Alarm timer RTC BOD trip level 1 WWDT Ethernet USB0 USB1 SD/MMC C_CAN0/1 GIMA output 25 Notes WAKEUP0 pin WAKEUP1 pin WAKEUP2 pin WAKEUP3 pin Alarm timer interrupt RTC interrupt D R BOD interrupt; wake-up from low power mode WWDT interrupt Wake-up packet indicator Wake-up request signal ahb_needclk signal SD/MMC interrupt ORed C_CAN0 and C_CAN1 interrupt Output 2 of the combined timer (ORed output of SCT output 2 and the match channel 2 of timer 0). See Table 134. Output 6 of the combined timer (ORed output of SCT output 6 and the match channel 2 of timer 1). See Table 134. QEI interrupt Output 14 of the combined timer (ORed output of SCT output 14 and the match channel 2 of timer 3). See Table 134. Reserved Reserved Reserved R A FT D R R A F D R A FT A FT A FT D R A D FT D R A 14 GIMA output 26 15 16 QEI GIMA output 27 17 18 19 20 25-21 Reset BOD trip level 2 - 6.5 Pin description Table 17. Pin WAKEUP0/1/2/3 Event router pin description Direction I Description External wake-up input; can raise an interrupt and can cause wake-up from any of the low power modes. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 41 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 6: LPC18xx Event router FT D R A D R A R A FT D R FT 6.6 Register description Table 18. Name HILO EDGE CLR_EN SET_EN STATUS ENABLE CLR_STAT SET_STAT Register overview: Event router (base address 0x4004 4000) Access R/W R/W W W R R W W Address offset 0x000 0x004 0x008 0xFD4 0xFD8 0xFDC 0xFE0 0xFE4 0xFE8 0xFEC Description Level configuration register Edge configuration Reserved Event clear enable register Event set enable register Status register Enable register Clear register Set register D R R A FT D R 0x0 0x0 0x0 0x0 0x0 0x0 R A F D R A FT A FT A Reset Value 0x000 0x000 FT D R A D FT D R A 6.6.1 Level configuration register This register works in combination with the edge configuration register EDGE (see Table 21) to configure the level and edge detection for each input to the event router. Table 19. Bit 0 Level configuration register (HILO - address 0x4004 4000) bit description Value Description Level detect mode for WAKEUP0 event. 0 1 1 WAKEUP1_L 0 1 2 WAKEUP2_L 0 1 3 WAKEUP3_L 0 1 Detect LOW level if bit 0 in the EDGE register is 0. Detect falling edge if bit 0 in the EDGE register is 1. Detect HIGH level if bit 0 in the EDGE register is 0. Detect rising edge if bit 0 in the EDGE register is 1. Level detect mode for WAKEUP1 event. The corresponding bit in the EDGE register must be 0. Detect LOW level if bit 1 in the EDGE register is 0. Detect HIGH level if bit 1 in the EDGE register is 0. Detect rising edge if bit 1 in the EDGE register is 1. Level detect mode for WAKEUP2 event. Detect LOW level if bit 2 in the EDGE register is 0. Detect falling edge if bit 2 in the EDGE register is 1. Detect HIGH level if bit 2 in the EDGE register is 0. Detect rising edge if bit 2 in the EDGE register is 1. Level detect mode for WAKEUP3 event. Detect LOW level if bit 3 in the EDGE register is 0. Detect falling edge if bit 3 in the EDGE register is 1. Detect HIGH level if bit 3 in the EDGE register is 0. Detect rising edge if bit 3 in the EDGE register is 1. 0 0 0 Reset value 0 Symbol WAKEUP0_L All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 42 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 6: LPC18xx Event router FT D R A D R A R A FT D R FT Table 19. Bit 4 Level configuration register (HILO - address 0x4004 4000) bit description D R R R A A A Symbol ATIMER_L Value Description Level detect mode for alarm timer event. 0 1 Reset value 0 FT D R A F Detect LOW level if bit 4 in the EDGE register is 0. Detect falling edge if bit 4 in the EDGE register is 1. Detect HIGH level if bit 4 in the EDGE register is 0. Detect rising edge if bit 4 in the EDGE register is 1. Level detect mode for RTC event. 0 Detect LOW level if bit 5 in the EDGE register is 0. Detect falling edge if bit 5 in the EDGE register is 1. Detect HIGH level if bit 5 in the EDGE register is 0. Detect rising edge if bit 5 in the EDGE register is 1. Level detect mode for BOD event. 0 Detect LOW level if bit 6 in the EDGE register is 0. Detect falling edge if bit 6 in the EDGE register is 1. Detect HIGH level if bit 6 in the EDGE register is 0. Detect rising edge if bit 6 in the EDGE register is 1. Level detect mode for WWDTD event. 0 Detect LOW level if bit 7 in the EDGE register is 0. Detect falling edge if bit 7 in the EDGE register is 1. Detect HIGH level if bit 7 in the EDGE register is 0. Detect rising edge if bit 7 in the EDGE register is 1. 0 Detect LOW level if bit 8 in the EDGE register is 0. Detect falling edge if bit 8 in the EDGE register is 1. Detect HIGH level if bit 8 in the EDGE register is 0. Detect rising edge if bit 8 in the EDGE register is 1. 0 Detect LOW level if bit 9 in the EDGE register is 0. Detect falling edge if bit 9 in the EDGE register is 1. Detect HIGH level if bit 9 in the EDGE register is 0. Detect rising edge if bit 9 in the EDGE register is 1. 0 Detect LOW level if bit 10 in the EDGE register is 0. Detect falling edge if bit 10 in the EDGE register is 1. Detect HIGH level if bit 10 in the EDGE register is 0. Detect rising edge if bit 10 in the EDGE register is 1. Reserved. Level detect mode for C_CAN event. 0 Detect LOW level if bit 12 in the EDGE register is 0. Detect falling edge if bit 12 in the EDGE register is 1. Detect HIGH level if bit 12 in the EDGE register is 0. Detect rising edge if bit 12 in the EDGE register is 1. FT D R A FT D R A FT D FT D R A 5 RTC_L 0 1 6 BOD_L 0 1 7 WWDT_L 0 1 8 ETH_L 0 1 9 USB0_L 0 1 10 USB1_L 0 1 11 12 CAN_L 0 1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 43 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 6: LPC18xx Event router FT D R A D R A R A FT D R FT Table 19. Bit 13 Level configuration register (HILO - address 0x4004 4000) bit description D R R R A A A Symbol TIM2_L Value Description Level detect mode for combined timer output 2 event. 0 1 Reset value FT D R A F Detect LOW level if bit 13 in the EDGE register is 0. Detect falling edge if bit 13 in the EDGE register is 1. Detect HIGH level if bit 13 in the EDGE register is 0. Detect rising edge if bit 13 in the EDGE register is 1. Level detect mode for combined timer output 6 event. 0 Detect LOW level if bit 14 in the EDGE register is 0. Detect falling edge if bit 14 in the EDGE register is 1. Detect HIGH level if bit 14 in the EDGE register is 0. Detect rising edge if bit 14 in the EDGE register is 1. Level detect mode for QEI event. 0 Detect LOW level if bit 15 in the EDGE register is 0. Detect falling edge if bit 15 in the EDGE register is 1. Detect HIGH level if bit 15 in the EDGE register is 0. Detect rising edge if bit 15 in the EDGE register is 1. Level detect mode for combined timer output 14 event. 0 Detect LOW level if bit 16 in the EDGE register is 0. Detect falling edge if bit 16 in the EDGE register is 1. Detect HIGH level if bit 16 in the EDGE register is 0. Detect rising edge if bit 16 in the EDGE register is 1. Reserved. . 0 Detect LOW level if bit 17 in the EDGE register is 0. Detect falling edge if bit 17 in the EDGE register is 1. Detect HIGH level if bit 17 in the EDGE register is 0. Detect rising edge if bit 17 in the EDGE register is 1. Reserved. FT D R 0 A FT D R A FT D FT D R A 14 TIM6_L 0 1 15 QEI_L 0 1 16 TIM14_L 0 1 18:17 19 RESET_L 0 1 31:20 - - 6.6.2 Edge configuration register This register works in combination with the level configuration register HILO (see Table 19) to configure the level or edge detection for each input to the event router. The EDGE configuration register determines whether the event router responds to a level change (EDGEn=1), or a constant level (EDGEn=0). The HILOn bit determines a response to a rising edge (HILOn=1) or a falling edge (HILOn=0). Table 20. HILOn 0 0 1 1 EDGE and HILO combined register settings EDGEn 0 1 0 1 Description Detect LOW level Detect falling edge Detect HIGH level Detect rising edge All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 44 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 6: LPC18xx Event router FT D R R A When a HIGH level detect is active, the event router status bits cannot be cleared until the signal is LOW. When a rising edge detect is active, the event router status bit can be cleared right after the event has occurred. R A A FT D R A FT Table 21. Bit 0 Edge configuration register (EDGE - address 0x4004 4004) bit description Value Description Edge detect mode for WAKEUP0 event. 0 1 Level detect. Edge detect. Detect falling edge if bit 0 in the HILO register is 0. Detect rising edge if bit 0 in the HILO register is 1. Edge/level detect mode for WAKEUP1 event. The corresponding bit in the EDGE register must be 0. 0 1 Level detect. Edge detect. Detect falling edge if bit 1 in the HILO register is 0. Detect rising edge if bit 1 in the HILO register is 1. Edge/level detect mode for WAKEUP2 event. The corresponding bit in the EDGE register must be 0. 0 1 Level detect. Edge detect. Detect falling edge if bit 2 in the HILO register is 0. Detect rising edge if bit 2 in the HILO register is 1. Edge/level detect mode for WAKEUP3 event. The corresponding bit in the EDGE register must be 0. 0 1 Level detect. Edge detect. Detect falling edge if bit 30 in the HILO register is 0. Detect rising edge if bit 3 in the HILO register is 1. Edge/level detect mode for alarm timer event. The corresponding bit in the EDGE register must be 0. 0 1 Level detect. Edge detect. Detect falling edge if bit 4 in the HILO register is 0. Detect rising edge if bit 4 in the HILO register is 1. Edge/level detect mode for RTC event. The corresponding bit in the EDGE register must be 0. 0 1 Level detect. Edge detect. Detect falling edge if bit 5 in the HILO register is 0. Detect rising edge if bit 5 in the HILO register is 1. Edge/level detect mode for BOD event. The corresponding bit in the EDGE register must be 0. 0 1 Level detect. Edge detect. Detect falling edge if bit 6 in the HILO register is 0. Detect rising edge if bit 6 in the HILO register is 1. 0 0 0 0 0 0 D R A R A FT D R FT D R A F R A FT D D FT R D Symbol WAKEUP0_E Reset value 0 A FT D R A 1 WAKEUP1_E 2 WAKEUP2_E 3 WAKEUP3_E 4 ATIMER_E 5 RTC_E 6 BOD_E All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 45 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 6: LPC18xx Event router FT D R A D R A R A FT D R FT Table 21. Bit 7 Edge configuration register (EDGE - address 0x4004 4004) bit description D R R R A A A Symbol WWDT_E Value Description Edge/level detect mode for WWDTD event. The corresponding bit in the EDGE register must be 0. 0 1 Level detect. Edge detect. Detect falling edge if bit 7 in the HILO register is 0. Detect rising edge if bit 7 in the HILO register is 1. Reset value 0 FT D R A R A FT F FT D R A FT D FT D D R A 8 ETH_E 0 1 The corresponding bit in the EDGE register must be 0. Level detect. Edge detect. Detect falling edge if bit 8 in the HILO register is 0. Detect rising edge if bit 8 in the HILO register is 1. The corresponding bit in the EDGE register must be 0. 0 1 Level detect. Edge detect. Detect falling edge if bit 9 in the HILO register is 0. Detect rising edge if bit 9 in the HILO register is 1. The corresponding bit in the EDGE register must be 0. 0 1 Level detect. Edge detect. Detect falling edge if bit 10 in the HILO register is 0. Detect rising edge if bit 10 in the HILO register is 1. Reserved. Edge/level detect mode for C_CAN event. The corresponding bit in the EDGE register must be 0. 0 1 Level detect. Edge detect. Detect falling edge if bit 12 in the HILO register is 0. Detect rising edge if bit 12 in the HILO register is 1. Edge/level detect mode for combined timer output 2 event. The corresponding bit in the EDGE register must be 0. 0 1 Level detect. Edge detect. Detect falling edge if bit 13 in the HILO register is 0. Detect rising edge if bit 13 in the HILO register is 1. Edge/level detect mode for combined timer output 6 event. The corresponding bit in the EDGE register must be 0. 0 1 Level detect. Edge detect. Detect falling edge if bit 14 in the HILO register is 0. Detect rising edge if bit 14 in the HILO register is 1. 0 9 USB0_E 0 10 USB1_E 0 11 12 CAN_E - 0 13 TIM2_E 0 14 TIM6_E 0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 46 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 6: LPC18xx Event router FT D R A D R A R A FT D R FT Table 21. Bit 15 Edge configuration register (EDGE - address 0x4004 4004) bit description D R R R A A A Symbol QEI_E Value Description Edge/level detect mode for QEI interrupt signal. The corresponding bit in the EDGE register must be 0. 0 1 Level detect. Edge detect. Detect falling edge if bit 15 in the HILO register is 0. Detect rising edge if bit 15 in the HILO register is 1. Reset value 0 FT D R A R A FT F FT D R A FT D FT D D R A 16 TIM14_E Edge/level detect mode for combined timer output 14 event. The corresponding bit in the EDGE register must be 0. 0 1 Level detect. Edge detect. Detect falling edge if bit 16 in the HILO register is 0. Detect rising edge if bit 16 in the HILO register is 1. Reserved. . The corresponding bit in the EDGE register must be 0. 0 1 Level detect. Edge detect. Detect falling edge if bit 19 in the HILO register is 0. Detect rising edge if bit 19 in the HILO register is 1. Reserved. 0 18:17 19 RESET_E - 0 31:20 - - 6.6.3 Interrupt clear enable register Table 22. Bit 0 1 2 3 4 5 6 7 8 9 Interrupt clear enable register (CLR_EN - address 0x4004 4FD8) bit description Description Reset value Symbol WAKEUP0_CLREN Writing a 1 to this bit clears the event enable bit 0 in the ENABLE register. WAKEUP1_CLREN Writing a 1 to this bit clears the event enable bit 1 in the ENABLE register. WAKEUP2_CLREN Writing a 1 to this bit clears the event enable bit 2 in the ENABLE register. WAKEUP3_CLREN Writing a 1 to this bit clears the event enable bit 3 in the ENABLE register. ATIMER_CLREN RTC_CLREN BOD_CLREN WWDT_CLREN ETH_CLREN USB0_CLREN Writing a 1 to this bit clears the event enable bit 4 in the ENABLE register. Writing a 1 to this bit clears the event enable bit 5 in the ENABLE register. Writing a 1 to this bit clears the event enable bit 6 in the ENABLE register. Writing a 1 to this bit clears the event enable bit 7 in the ENABLE register. Writing a 1 to this bit clears the event enable bit 8 in the ENABLE register. Writing a 1 to this bit clears the event enable bit 9 in the ENABLE register. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 47 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 6: LPC18xx Event router FT D R A D R A R A FT D R FT Table 22. Bit 10 11 12 13 14 15 16 Interrupt clear enable register (CLR_EN - address 0x4004 4FD8) bit description D R R R A A A Symbol USB1_CLREN CAN_CLREN TIM2_CLREN TIM6_CLREN QEI_CLREN TIM14_CLREN Description Reset value FT D R A F Writing a 1 to this bit clears the event enable bit 10 in the ENABLE register. Reserved. Writing a 1 to this bit clears the event enable bit 12 in the ENABLE register. Writing a 1 to this bit clears the event enable bit 13 in the ENABLE register. Writing a 1 to this bit clears the event enable bit 14 in the ENABLE register. Writing a 1 to this bit clears the event enable bit 15 in the ENABLE register. Writing a 1 to this bit clears the event enable bit 16 in the ENABLE register. Reserved. Writing a 1 to this bit clears the event enable bit 19 in the ENABLE register. Reserved. FT D R - A FT D R A FT D FT D R A 18:17 19 RESET_CLREN 31:20 - 6.6.4 Event set enable register Table 23. Bit 0 1 2 3 4 5 6 7 8 9 10 11 Event set enable register (SET_EN - address 0x4004 4FDC) bit description Description Writing a 1 to this bit sets the event enable bit 0 in the ENABLE register. Writing a 1 to this bit sets the event enable bit 1 in the ENABLE register. Writing a 1 to this bit sets the event enable bit 2 in the ENABLE register. Writing a 1 to this bit sets the event enable bit 3 in the ENABLE register. Writing a 1 to this bit sets the event enable bit 4 in the ENABLE register. Writing a 1 to this bit sets the event enable bit 5 in the ENABLE register. Writing a 1 to this bit sets the event enable bit 6 in the ENABLE register. Writing a 1 to this bit sets the event enable bit 7 in the ENABLE register. Writing a 1 to this bit sets the event enable bit 8 in the ENABLE register. Writing a 1 to this bit sets the event enable bit 9 in the ENABLE register. Writing a 1 to this bit sets the event enable bit 10 in the ENABLE register. Reserved. All information provided in this document is subject to legal disclaimers. Symbol WAKEUP0_SETEN WAKEUP1_SETEN WAKEUP2_SETEN WAKEUP3_SETEN ATIMER_SETEN RTC_SETEN BOD_SETEN WWDT_SETEN ETH_SETEN USB0_SETEN USB1_SETEN - Reset value © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 48 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 6: LPC18xx Event router FT D R A D R A R A FT D R FT Table 23. Bit 12 13 14 15 16 18:17 19 31:20 Event set enable register (SET_EN - address 0x4004 4FDC) bit description D R R R A A A Symbol CAN_SETEN TIM2_SETEN TIM6_SETEN QEI_SETEN TIM14_SETEN RESET_SETEN - Description Reset value FT D R A F Writing a 1 to this bit sets the event enable bit 12 in the ENABLE register. Writing a 1 to this bit sets the event enable bit 13 in the ENABLE register. Writing a 1 to this bit sets the event enable bit 14 in the ENABLE register. Writing a 1 to this bit sets the event enable bit 15 in the ENABLE register. Writing a 1 to this bit sets the event enable bit 16 in the ENABLE register. Reserved. Writing a 1 to this bit sets the event enable bit 19 in the ENABLE register. Reserved. FT D - R A FT D R A FT D FT D R A 6.6.5 Event status register Table 24. Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18:17 19 31:20 Interrupt status register (STATUS - address 0x4004 4FE0) bit description Description Reset value Symbol WAKEUP0_ST A 1 in this bit shows that the WAKEUP0 event has been raised. WAKEUP1_ST A 1 in this bit shows that the WAKEUP1 event has been raised. WAKEUP2_ST A 1 in this bit shows that the WAKEUP2 event has been raised. WAKEUP3_ST A 1 in this bit shows that the WAKEUP3 event has been raised. ATIMER_ST RTC_ST BOD_ST WWDT_ST ETH_ST USB0_ST USB1_ST CAN_ST TIM2_ST TIM6_ST QEI_ST TIM14_ST RESET_ST A 1 in this bit shows that the ATIMER event has been raised. A 1 in this bit shows that the RTC event has been raised. A 1 in this bit shows that the BOD event has been raised. A 1 in this bit shows that the WWDT event has been raised. A 1 in this bit shows that the USB0 event has been raised. A 1 in this bit shows that the USB1 event has been raised. Reserved. A 1 in this bit shows that the C_CAN event has been raised. - A 1 in this bit shows that the ETHERNET event has been raised. - A 1 in this bit shows that the combined timer 2 output event has been raised. A 1 in this bit shows that the combined timer 6 output event has been raised. A 1 in this bit shows that the QEI event has been raised. A 1 in this bit shows that the combined timer 14 output event has been raised. Reserved. A 1 in this bit shows that the event has been raised. Reserved. © NXP B.V. 2011. All rights reserved. All information provided in this document is subject to legal disclaimers. User manual Rev. 00.13 — 20 July 2011 49 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 6: LPC18xx Event router FT D R A D R A R A FT D R FT 6.6.6 Event enable register Table 25. Bit 0 Symbol Description D R Event enable register (ENABLE - address 0x4004 4FE4) bit description WAKEUP0_EN A 1 in this bit shows that the WAKEUP0 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register. WAKEUP1_EN A 1 in this bit shows that the WAKEUP1 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register. WAKEUP2_EN A 1 in this bit shows that the WAKEUP2 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register. WAKEUP3_EN A 1 in this bit shows that the WAKEUP3 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register. ATIMER_EN R A FT D 0 R A F D R A A FT Reset value R A FT D R FT D A FT D R A 1 0 2 0 3 0 4 A 1 in this bit shows that the ATIMER event has been enabled. 0 This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register. A 1 in this bit shows that the RTC event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register. A 1 in this bit shows that the BOD event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register. A 1 in this bit shows that the WWDT event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register. A 1 in this bit shows that the ETHERNET event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register. A 1 in this bit shows that the USB0 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register. A 1 in this bit shows that the USB1 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register. Reserved. A 1 in this bit shows that the CAN event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register. A 1 in this bit shows that the TIM2 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register. A 1 in this bit shows that the TIM6 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register. 0 5 RTC_EN 6 BOD_EN 0 7 WWDT_EN 0 8 ETH_EN 0 9 USB0_EN 0 10 USB1_EN 0 11 12 CAN_EN 0 13 TIM2_EN 0 14 TIM6_EN 0 15 QEI_EN A 1 in this bit shows that the QEI event has been enabled. This 0 event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 50 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 6: LPC18xx Event router FT D R A D R A R A FT D R FT Table 25. Bit 16 Event enable register (ENABLE - address 0x4004 4FE4) bit description D R R R A A A Symbol TIM14_EN Description Reset value FT D R A F A 1 in this bit shows that the TIM14 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register. FT D 0 R A FT D R A FT D FT 18:17 19 RESET_EN A 1 in this bit shows that the RESET event has been enabled. 0 This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register. Reserved. - D R A 31:20 - 6.6.7 Clear status register Table 26. Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Interrupt clear status register (CLR_STAT - address 0x4004 4FE8) bit description Description Writing a 1 to this bit clears the STATUS event bit 0 in the STATUS register. Writing a 1 to this bit clears the STATUS event bit 1 in the STATUS register. Writing a 1 to this bit clears the STATUS event bit 2 in the STATUS register. Writing a 1 to this bit clears the STATUS event bit 3 in the STATUS register. Writing a 1 to this bit clears the STATUS event bit 4 in the STATUS register. Writing a 1 to this bit clears the STATUS event bit 5 in the STATUS register. Writing a 1 to this bit clears the STATUS event bit 6 in the STATUS register. Writing a 1 to this bit clears the STATUS event bit 7 in the STATUS register. Writing a 1 to this bit clears the STATUS event bit 8 in the STATUS register. Writing a 1 to this bit clears the STATUS event bit 9 in the STATUS register. Writing a 1 to this bit clears the STATUS event bit 10 in the STATUS register. Reserved. Writing a 1 to this bit clears the STATUS event bit 12 in the STATUS register. Writing a 1 to this bit clears the STATUS event bit 13 in the STATUS register. Writing a 1 to this bit clears the STATUS event bit 14 in the STATUS register. Writing a 1 to this bit clears the STATUS event bit 15 in the STATUS register. Reset value Symbol WAKEUP0_CLRST WAKEUP1_CLRST WAKEUP2_CLRST WAKEUP3_CLRST ATIMER_CLRST RTC_CLRST BOD_CLRST WWDT_CLRST ETH_CLRST USB0_CLRST USB1_CLRST CAN_CLRST TIM2_CLRST TIM6_CLRST QEI_CLRST All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 51 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 6: LPC18xx Event router FT D R A D R A R A FT D R FT Table 26. Bit 16 18:17 19 31:20 Interrupt clear status register (CLR_STAT - address 0x4004 4FE8) bit description D R R R A A A Symbol TIM14_CLRST RESET_CLRST - Description Reset value FT D R A F Writing a 1 to this bit clears the STATUS event bit 16 in the STATUS register. Writing a 1 to this bit clears the STATUS event bit 19 in the STATUS register. Reserved. - FT D R A FT D R A FT D FT D R A 6.6.8 Set status register Table 27. Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Interrupt set status register (SET_STAT - address 0x4004 4FEC) bit description Description Writing a 1 to this bit sets the STATUS event bit 0 in the STATUS register. Writing a 1 to this bit sets the STATUS event bit 1 in the STATUS register. Writing a 1 to this bit sets the STATUS event bit 2 in the STATUS register. Writing a 1 to this bit sets the STATUS event bit 3 in the STATUS register. Writing a 1 to this bit sets the STATUS event bit 4 in the STATUS register. Writing a 1 to this bit sets the STATUS event bit 5 in the STATUS register. Writing a 1 to this bit sets the STATUS event bit 6 in the STATUS register. Writing a 1 to this bit sets the STATUS event bit 7 in the STATUS register. Writing a 1 to this bit sets the STATUS event bit 8 in the STATUS register. Writing a 1 to this bit sets the STATUS event bit 9 in the STATUS register. Writing a 1 to this bit sets the STATUS event bit 10 in the STATUS register. Reserved. Writing a 1 to this bit sets the STATUS event bit 12 in the STATUS register. Writing a 1 to this bit sets the STATUS event bit 13 in the STATUS register. Writing a 1 to this bit sets the STATUS event bit 14 in the STATUS register. Writing a 1 to this bit sets the STATUS event bit 15 in the STATUS register. Writing a 1 to this bit sets the STATUS event bit 16 in the STATUS register. Reset value Symbol WAKEUP0_SETST WAKEUP1_SETST WAKEUP2_SETST WAKEUP3_SETST ATIMER_SETST RTC_SETST BOD_SETST WWDT_SETST ETH_SETST USB0_SETST USB1_SETST CAN_SETST TIM2_SETST TIM6_SETST QEI_SETST TIM14_SETST All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 52 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 6: LPC18xx Event router FT D R A D R A R A FT D R FT Table 27. Bit 18:17 19 31:20 Interrupt set status register (SET_STAT - address 0x4004 4FEC) bit description D R R R A A A Symbol RESET_SETST - Description Reserved. Reset value FT D R A F Writing a 1 to this bit sets the STATUS event bit 19 in the STATUS register. Reserved. - FT D R A FT D R A FT D FT D R A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 53 of 1164 D R A FT D R A FT D R A FT D R A FT D R A FT UM10430 Rev. 00.13 — 20 July 2011 D D Chapter 7: LPC18xx Configuration Registers (CREG) D R A FT D D R A FT D R A FT D R A FT D R A FT D R A R FT D A FT R A R A FT D R A FT D R A F R A FT D FT R User manual 7.1 How to read this chapter Remark: This chapter applies to LPC1850/30/20/10 Rev ‘A’ only. The available peripherals vary for different parts. D D R A FT D R A • Ethernet: available on LPC1850/30. • USB0: available on LPC1850/30/20. • USB1: available on LPC1850/30. If a peripheral is not available, the corresponding bits in the CREG registers are reserved. 7.2 Basic configuration The CREG block is configured as follows: • See Table 28 for clocking and power control. • The CREG block can not be reset by software. Table 28. CREG CREG clocking and power control Base clock BASE_M3_CLK Branch clock CLK_M3_CREG Maximum frequency 150 MHz 7.3 Features The following settings are controlled in the configuration register block: • • • • • • • BOD trip settings Oscillator output DMA-to-peripheral muxing Ethernet mode Memory mapping Timer/UART inputs In addition, the Creg block contains the part id and the part configuration information. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 54 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 7: LPC18xx Configuration Registers (CREG) FT D R A D R A R A FT D R FT 7.4 Register description Table 29. Name IRCTRM CREG0 PMUCON M3MEMMAP CREG1 CREG2 CREG3 CREG4 CREG5 DMAMUX ETBCFG CREG6 CHIPID R/W RO RO RO RO R/W R/W R/W R/W RO Register overview: Configuration registers (base address 0x4004 3000) Access RO R/W Address Description offset 0x000 0x004 0x008 0x008 0x0FC 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x1FC 0x200 0x204 0x2FC 0x300 0x304 0x308 LOCKREG 0x30C 0xEFC 0xF00 Reserved Lock register; blocks write access to CREG registers Reserved Part ID Reserved IRC trim register Chip configuration register 32 kHz oscillator output and BOD control register. Power mode control register. Reserved ARM Cortex-M3 memory mapping Reserved Chip configuration register 1 Chip configuration register 2 Chip configuration register 3 Chip configuration register 4 Chip configuration register 5. Controls JTAG access. DMA muxing control Reserved ETB RAM configuration - D R Reset value 0x000F F2BC 0x0000 0000 - 0x0000 0000 R A FT D R R A F D R A FT A FT A FT D R A D FT D R A 7.4.1 IRC trim register Table 30. Bit 11:0 19:12 31:20 IRC trim register (IRCTRM, address 0x4004 3000) bit description Description IRC trim value Reserved Reserved Reset value 0x2BC 0xFF Access R R Symbol TRM - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 55 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 7: LPC18xx Configuration Registers (CREG) FT D R A D R A R A FT D R FT 7.4.2 CREG0 control register Table 31. Bit 0 CREG0 register (CREG0, address 0x4004 3004) bit description Value Description Enable 1 kHz output. 0 1 1 EN32KHZ 0 1 2 RESET32KHZ 0 1 3 32KHZPD 0 1 4 5 USB0PHY 0 1 7:6 ALARMCTRL 0x0 0x1 0x2 0x3 9:8 BODLVL1 0x0 0x1 0x2 0x3 11:10 BODLVL2 0x0 0x1 0x2 0x3 31:12 1 kHz output disabled. 1 kHz output enabled. Enable 32 kHz output 32 kHz output disabled. 32 kHz output enabled. 32 kHz oscillator reset 32 kHz power control. 32 kHz oscillator powered. 32 kHz oscillator powered-down. Reserved USB0 PHY power control. USB0 PHY powered. USB0 PHY powered down. RTC_ALARM pin output control RTC alarm. Event router event. Event router or . Inactive. BOD trip level to generate an interrupt. 2.75 V 2.85 V 2.95 V 3.05 V BOD trip level to generate a reset. 1.70 V 1.80 V 1.90 V 2.00 V Reserved 11 11 1 1 0 Symbol EN1KHZ D R R A FT D R Reset value 0 R/W R/W R/W R/W R/W R/W R/W R/W - R A F D R A FT A FT A FT D R A Access D FT D R A 7.4.3 Power mode control register For details on power mode selection, see Section 8.2. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 56 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 7: LPC18xx Configuration Registers (CREG) FT D R A D R A R A FT D R FT D Table 32. Bit 1:0 Power mode control register (PMUCON, address 0x4004 3008) bit description R R R A A A FT FT F Symbol PMUCON Value Description Controls power mode. Reset value 0 Access R/W D D R A FT D R A FT D 0x0 0x1 0x2 0x3 31:2 - Normal Low-power Reserved Normal Reserved - R A FT D R A 7.4.4 ARM Cortex-M3 memory mapping register Table 33. Bit 11:0 31:12 M3MAP Memory mapping register (M3MEMMAP, address 0x4004 3100) bit description Description Reserved Shadow address when accessing memory at address 0x0000 0000 Reset value 0x000 0x1040 0000 Access R/W Symbol 7.4.5 CREG5 control register Table 34. Bit 4:0 5 6 7 8 31:9 CREG5 control register (CREG5, address 0x4004 3118) bit description Description Reserved. Reserved. Reserved. Reserved. Reserved. Reset Access value 0 0 0 0 R/W Symbol M3TAPSEL - 7.4.6 DMA muxing register This register controls which set of peripherals is connected to the DMA controller (see Table 195). Table 35. Bit 1:0 DMA muxing register (DMAMUX, address 0x4004 311C) bit description Value Description Select DMA to peripheral connection for DMA peripheral 0. 0x0 0x1 0x2 0x3 SPIFI SCT match 2 Reserved T3 match 1 Reset Access value 0 R/W Symbol DMAMUXCH0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 57 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 7: LPC18xx Configuration Registers (CREG) FT D R A D R A R A FT D R FT Table 35. Bit 3:2 DMA muxing register (DMAMUX, address 0x4004 311C) bit description …continued D R R R A A A Symbol DMAMUXCH1 Value Description Select DMA to peripheral connection for DMA peripheral 1 Reset Access value FT D R A F FT D R A 0 R/W FT D R A FT D 0x0 0x1 0x2 0x3 5:4 DMAMUXCH2 0x0 0x1 0x2 0x3 7:6 DMAMUXCH3 0x0 0x1 0x2 0x3 9:8 DMAMUXCH4 0x0 0x1 0x2 0x3 11:10 DMAMUXCH5 0x0 0x1 0x2 0x3 13:12 DMAMUXCH6 0x0 0x1 0x2 0x3 15:14 DMAMUXCH7 0x0 0x1 0x2 0x3 Timer 0 match 0 USART0 transmit Reserved AES input Select DMA to peripheral connection for DMA peripheral 2. Timer 0 match 1 USART0 receive Reserved AES output Select DMA to peripheral connection for DMA peripheral 3. Timer 1 match 0 UART1 transmit I2S1 channel 0 SSP1 transmit Select DMA to peripheral connection for DMA peripheral 4. Timer 1 match 1 UART1 receive I2S1 channel 1 SSP1 receive Select DMA to peripheral connection for DMA peripheral 5. Timer 2 match 0 USART2 transmit SSP1 transmit Reserved Selects DMA to peripheral connection for DMA peripheral 6. Timer 2 match 1 USART2 receive SSP1 receive Reserved Selects DMA to peripheral connection for DMA peripheral 7. Timer 3 match l 0 USART3 transmit SCT match output 0 Reserved 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W FT D R A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 58 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 7: LPC18xx Configuration Registers (CREG) FT D R A D R A R A FT D R FT Table 35. Bit 17:16 DMA muxing register (DMAMUX, address 0x4004 311C) bit description …continued D R R R A A A Symbol DMAMUXCH8 Value Description Select DMA to peripheral connection for DMA peripheral 8. Reset Access value FT D R A F FT D R A 0 R/W FT D R A FT D 0x0 0x1 0x2 0x3 19:18 DMAMUXCH9 0x0 0x1 0x2 0x3 21:20 DMAMUXCH10 0x0 0x1 0x2 0x3 23:22 DMAMUXCH11 0x0 0x1 0x2 0x3 25:24 DMAMUXCH12 0x0 0x1 0x2 0x3 27:26 DMAMUXCH13 0x0 0x1 0x2 0x3 29:28 DMAMUXCH14 0x0 0x1 0x2 0x3 Timer 3 match 1 USART3 receive SCT match output 1 Reserved Select DMA to peripheral connection for DMA peripheral 9. SSP0 receive I2S0 channel 0 SCT match output 1 Reserved Select DMA to peripheral connection for DMA peripheral 10. SSP0 transmit I2S0 channel 1 SCT match output 0 Reserved Selects DMA to peripheral connection for DMA peripheral 11. SSP1 receive Reserved USART0 transmit Reserved Select DMA to peripheral connection for DMA peripheral 12. SSP1 transmit Reserved USART0 receive Reserved Select DMA to peripheral connection for DMA peripheral 13. ADC0 AES input SSP1 receive USART3 receive Select DMA to peripheral connection for DMA peripheral 14. ADC1 AES output SSP1 transmit USART3 transmit 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W FT D R A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 59 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 7: LPC18xx Configuration Registers (CREG) FT D R A D R A R A FT D R FT Table 35. Bit 31:30 DMA muxing register (DMAMUX, address 0x4004 311C) bit description …continued D R R R A A A Symbol DMAMUXCH15 Value Description Select DMA to peripheral connection for DMA peripheral 15. Reset Access value FT D R A F FT D R A 0 R/W FT D R A FT D 0x0 0x1 0x2 0x3 DAC SCT match output 3 Reserved Timer 3 match 0 FT D R A 7.4.7 ETB SRAM configuration register This register selects the interface that is used to the 16 kB block of RAM located at address 0x2000 C000. This RAM memory block can be accessed either by the ETB or be used as normal SRAM on the AHB bus. Note that by default, this memory area will be accessed by the ETB. Table 36. Bit 0 ETB SRAM configuration register (ETBCFG, address 0x4004 3128) bit description Value Description Select SRAM interface 0 1 31:1 ETB accesses SRAM at address 0x2000 C000. AHB accesses SRAM at address 0x2000 C000. Reserved. Reset value 0 Access R/W Symbol ETB 7.4.8 CREG6 control register This register controls various aspects of the LPC18xx: • Bits 2:0 control the Ethernet PHY interface. The ethernet block reads this register during set-up, and therefore the ethernet must be reset after changing the PHY interface. • Bits 12:15 control the I2S connections. • Bit 16 controls the external memory controller clocking. Table 37. Bit 2:0 CREG6 control register (CREG6, address 0x4004 312C) bit description Value Description Selects the Ethernet mode. Reset the ethernet after changing the PHY interface. All other settings are reserved. 0x0 0x4 3 4 TIMCTRL 0 1 Symbol ETHMODE Reset Access value R/W MII RMII Reserved. © NXP B.V. 2011. All rights reserved. R/W 0 R/W All information provided in this document is subject to legal disclaimers. User manual Rev. 00.13 — 20 July 2011 60 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 7: LPC18xx Configuration Registers (CREG) FT D R A D R A R A FT D R FT Table 37. Bit 11: 5 12 CREG6 control register (CREG6, address 0x4004 312C) bit description …continued D R R R A A A Symbol I2S0_TX_SCK_IN_ SEL Value Description Reserved. I2S0_TX_SCK input select 0 1 I2 S clock selected as defined by the I2S transmit mode register Table 744. Audio PLL for I2S transmit clock MCLK input and MCLK output. The I2S must be configured in slave mode. I2S0_RX_SCK input select I2 S clock selected as defined by the I2S receive mode register Table 745. Audio PLL for I2S receive clock MCLK input and MCLK output. The I2S must be configured in slave mode. I2S1_TX_SCK input select 0 1 I2 S clock selected as defined by the I2S transmit mode register Table 744. Audio PLL for I2S transmit clock MCLK input and MCLK output. The I2S must be configured in slave mode. I2S1_RX_SCK input select I2 S clock selected as defined by the I2S receive mode register Table 745. Audio PLL for I2S receive clock MCLK input and MCLK output. The I2S must be configured in slave mode. EMC_CLK divided clock select (see Section 19.1). 0 1 EMC_CLK_DIV not divided. EMC_CLK_DIV divided by 2. Reserved. Reset Access value FT D R A F FT D R A 0 - FT D R A FT D R A R/W FT D 13 I2S0_RX_SCK_IN_ SEL 0 1 0 R/W 14 I2S1_TX_SCK_IN_ SEL 0 R/W 15 I2S1_RX_SCK_IN_ SEL 0 1 0 R/W 16 EMC_CLK_SEL 0 R/W 31: 17 - - - 7.4.9 Part ID register Table 38. Bit 31:0 Part ID register (CHIPID, address 0x4004 3200) bit description Description Reset value Access Symbol ID All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 61 of 1164 D R A FT D R A FT D R A FT D R A FT D R A FT UM10430 Rev. 00.13 — 20 July 2011 D D Chapter 8: LPC18xx Power Management Controller (PMC) D R R A A FT FT D D R A FT D R A FT D R A FT D FT D R A D R A FT R A R A FT D R A FT D R A F R A FT D FT R User manual 8.1 How to read this chapter The power management controller is identical on all LPC18xx parts. D D R A FT D R A 8.2 General description The PMC implements the control sequences to enable transitioning between different power modes and controls the power state of each peripheral. In addition, wake-up from a low-power mode based on hardware events is supported. Low-power modes can be reached from Active mode only, and transitions between low-power modes are not allowed. The PMC supports the following low-power modes: Deep-sleep, Power-down, and Deep power-down. The wake-up from a low-power mode will always result in the Active mode. The LPC18xx supports five power modes in order from highest to lowest power consumption: 1. Active mode 2. Sleep mode (controlled by the ARM Cortex-M3 core) 3. Deep-sleep mode (controlled by the ARM Cortex-M3 core) 4. Power-down mode (controlled by the ARM Cortex-M3 core) 5. Deep power-down mode 8.2.1 Active mode By default, the LPC18xx is in Active mode, which means that every peripheral can perform a functional operation at nominal operating conditions. The other low-power modes are standby modes in which the peripheral clocks are disabled and operating conditions are adapted to achieve further power savings. The peripheral clocks are enabled again at wake-up. In Active (or Sleep mode), three operating modes are supported. • Low-power mode: The CPU and core logic operate slower and the core supply voltage is reduced. • Normal mode: The CPU operates at the nominal supply voltage. The operating modes are programmable through a power API and through the PMUCON register in the CREG block (see Table 32). 8.2.2 Sleep mode In Sleep mode the CPU clock is shut down to save power; the peripherals can still remain active and fully functional. The Sleep mode is entered by a WFI or WFE instruction if the SLEEPDEEP bit in the ARM Cortex-M3 system control register is set to 0. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 62 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 8: LPC18xx Power Management Controller (PMC) FT D R A As in active mode, low-power and normal modes can be selected. D R A R A FT D R FT D R R A FT D R A F D A FT 8.2.3 Deep-sleep mode R In Deep-sleep mode the CPU clock and peripheral clocks are shut down to save power; logic states and SRAM memory are maintained. All analog blocks and the BOD control circuit are powered down. The Deep-sleep mode is entered by a WFI or WFE instruction if the SLEEPDEEP bit in the ARM Cortex-M3 system control register is set to 1 and the PD0_SLEEP0_MODE register (see Table 41) is programmed with the Deep-sleep mode value. D When the LPC18xx wakes up from Deep-sleep mode, the 12 MHz IRC is used as the clock source for all base clocks. Remark: Before entering Deep-sleep mode, program the CGU as follows: R A FT R A FT D FT D R A A • Switch the clock source of all base clocks to the IRC. • Put the PLLs in power-down mode. Reprogramming the CGU avoids any undefined or unlocked PLL clocks at wake-up and minimizes power consumption during Deep-sleep mode. 8.2.4 Power-down mode In Power-down mode the CPU clock and peripheral clocks are shut down but logic states are maintained. All SRAM memory except for the upper 8 kB of the local SRAM located at 0x1008 0000, all analog blocks, and the BOD control circuit are powered down.The Power-down mode is entered by a WFI or WFE instruction if the SLEEPDEEP bit in the ARM Cortex-M3 system control register is set to 1 and the PD0_SLEEP0_MODE register (see Table 41) is programmed with the Power-down mode value. When the LPC18xx wakes up from Power-down mode, the 12 MHz IRC is used as the clock source for all base clocks. Remark: Before entering Power-down mode, program the CGU as follows: • Switch the clock source of all base clocks to the IRC. • Put the PLLs in power-down mode. Reprogramming the CGU avoids any undefined or unlocked PLL clocks at wake-up and minimizes power consumption during Power-down mode. 8.2.5 Deep power-down In Deep power-down mode the entire core logic is powered down. Only the logic in the RTC power domain remains active. The Deep power-down mode is entered by a WFI or WFE instruction if the SLEEPDEEP bit in the ARM Cortex-M3 system control register is set to 1 and the PD0_SLEEP0_MODE register (see Table 41) is programmed with the Deep power-down value. When the LPC18xx wakes up from Deep power-down mode, the boot loader configures the PLL1 as the clock source running at 72 MHz. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 63 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 8: LPC18xx Power Management Controller (PMC) FT D R A D R A R A FT D R FT 8.3 Register description Table 39. Name PD0_SLEEP0_HW_ENA PD0_SLEEP0_MODE Access Address Description offset R/W R/W 0x000 0x004 0x018 0x01C Hardware sleep event enable register Reserved Sleep power mode register D R Register overview: Power Mode Controller (PMC) (base address 0x4004 2000) Reset value 8.3.1 Hardware sleep event enable register PD0_SLEEP0_HW_ENA Table 40. Bit 0 31:1 Hardware sleep event enable register (PD0_SLEEP0_HW_ENA - address 0x4004 2000) bit description Description Writing a 1 enables any sleep modes for Cortex-M3. Reset Access value 1 R/W - R A FT D R - R A F D R A FT D A FT A FT D R A FT D R A 0x0000 0001 Symbol ENA_EVENT0 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 8.3.2 Sleep power mode register PD0_SLEEP0_MODE The PD0_SLEEP0_MODE register controls which of the three reduced power modes, Deep-sleep, Power-down, or Deep power-down is entered when an ARM WFE/WFI instruction is issued and the SLEEPDEEP bit is set to 1. Remark: Only the three values listed in Table 41 are allowed settings for the PD0_SLEEP0_MODE register. Table 41. Bit 31:0 Sleep power mode register (PD0_SLEEP0_MODE - address 0x4004 201C) bit description Description Selects between Deep-sleep, Power-down, and Deep power-down modes. Only one of the following three values can be programmed in this register: 0x003F 00AA = Deep-sleep mode 0x003F FCBA = Power-down mode 0x003F FF7F = Deep power-down mode Reset value Access R/W Symbol PWR_STATE All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 64 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 8: LPC18xx Power Management Controller (PMC) FT D R A D R A R A FT D R FT 8.4 Functional description 8.4.1 Run-time programming D R The PD0_SLEEP0_MODE register can be programmed at run-time to change the default power state of the LPC18xx after the next transition to a reduced-power state. The default state is Deep power-down corresponding to a reset value of the PD0_SLEEP0_MODE register of 0x003F FF7F. D Table 42. Typical settings for PMC power modes PD0_SLEEP0_MODE Description register bit settings 0x0030 00AA CPU, peripherals, analog, USB PHY, and retention supplies in retention mode; all SRAM supplies in active mode; IO pads powered [1], BOD in power-down mode. CPU, peripherals, analog supplies in retention mode; USB PHY in power-down mode; retention in retention mode; SRAM1 in active mode; all other SRAMs in power-down mode; IO pads powered[1], BOD in power-down mode. CPU, peripherals, analog, USB PHY in power-down mode; all SRAMs, IO pads powered[1], BOD in power-down mode. R A FT D R R A F D R A FT A FT A FT R A D FT D R A Power mode Deep-sleep Power-down 0x0030 FC3A Deep power-down 0x0030 FF7F [1] When the IO pads are off, the external IO supply should be removed. Pin RTC_ALARM can be used to indicate when the event router and the core become active and when the IO should be powered on. 8.4.2 Power API All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 65 of 1164 D R A FT D R A FT D R A FT D R A FT D R A FT UM10430 Rev. 00.13 — 20 July 2011 D D Chapter 9: LPC18xx Clock Generation Unit (CGU) D R D R A FT D R A FT D R A FT FT D R A A FT D R A R A FT D R A FT D R A F R A FT D R R D User manual FT D R A FT A FT 9.1 How to read this chapter D Remark: This chapter describes the clock generation of parts LPC1850/30/20/10 Rev ‘A’ and parts LPC18xx (with on-chip flash). Note that register clocks and clock control registers are specific to parts LPC1850/30/20/10 rev “A” and parts LPC18xx (with on-chip flash). For a description of the CGU of parts LPC1850/30/20/10 Rev ‘-’, see Section 42.4. Ethernet, USB0, USB1, and LCD related clocks are not available on all packages. See Section 1.3. The corresponding clock control registers are reserved. D R A FT D R A 9.2 Basic configuration The CGU is configured as follows: • See Table 43 for clocking and power control. • Do not reset the CGU during normal operation. Table 43. CGU CGU clocking and power control Base clock BASE_M3_CLK Branch clock CLK_M3_BUS Maximum frequency 150 MHz 9.3 Features • • • • PLL control Oscillator control Clock generation and clock source multiplexing Five integer dividers 9.4 General description The CGU generates multiple independent clocks for the core and the peripheral blocks of the LPC18x. Each independent clock is called a base clock and itself is one of the inputs to the two Clock Control Units (CCUs) which control the branch clocks to the individual peripherals (see Chapter 10). All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 66 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 9: LPC18xx Clock Generation Unit (CGU) FT D R R A D R A R A FT D R FT D R A R A FT FT A F CGU D D PLL0 (USB0) R R BASE_SAFE_CLK IDIVA /4 IDIVB /16 IDIVC /16 OUTCLK1, 3 - 6, 9 - 10 (BASE_xxx_CLK) WWDT A A FT D FT D 12 MHz IRC 7 PLL0 (AUDIO) CCU1 branch clocks to core and peripherals R A FT D RTCX1 RTCX2 XTAL1 32 kHz OSC R OUTCLK12 - 19 (BASE_xxx_CLK) 8 CCU2 branch clocks to peripherals A CRYSTAL OSC XTAL2 ENET_RX_CLK ENET_TX_CLK GP_CLK PLL1 IDIVC /16 OUTCLK7 ENET_RX_CLK IDIVE /256 OUTCLK8 ENET_TX_CLK OUTCLK11 LCD_CLK OUTCLK20 CLKOUT OUTCLK25 APLL OUTCLK26 CGU_OUT0 OUTCLK27 CGU_OUT1 Fig 17. CGU and CCU0/1 block diagram The CGU selects the inputs to the clock generators from multiple clock sources, controls the clock generation, and routes the outputs of the clock generators through the clock source bus to the output stages. Each output stage provides an independent clock source and corresponds to one of the base clocks for the LPC18xx. See Table 44 for a description of each base clock and Table 46 for the possible clock sources for each base clock. The CGU contains four types of clock generators: 1. External clock inputs and internal clocks: The external clock inputs are the Ethernet PHY clocks and the general purpose input clock GP_CLKIN. The clocks from the internal oscillators are the IRC and the 32 kHz oscillator output clocks. These clock generators have no selectable inputs from the clock source bus and provide one clock output each to the clock source bus. 2. Crystal oscillator: The crystal oscillator is controlled by the CGU. The input to the crystal oscillator are the XTAL pins. The crystal oscillator creates one output to the clock source bus. 3. PLLs: PLL0 (USB0), PLL0 (audio), and PLL1 are controlled by the CGU. Each PLL can select one input from the clock source bus and provides one output to the clock source bus. The input to the PLLs can be selected from all external and internal clocks and oscillators, from the other PLLs, and from the outputs of any of the integer dividers (see Table 45). One PLL0 cannot select the other PLL0 as input. 4. Integer dividers: Each of the five integer dividers can select one input from the clock source bus and creates one divided output clock to the clock source bus. The input to all integer dividers can be selected from all external and internal clocks and oscillators, and from all three PLLs. In addition, the output of the first integer divider can be selected as an input to all other integer dividers (see Table 45). All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 67 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 9: LPC18xx Clock Generation Unit (CGU) FT D R A – Integer divider A: maximum division factor = 4 (see Table 62). – Integer divider E: maximum division factor = 256 (see Table 64). – Integer dividers B, C, D: maximum division factor = 16 (see Table 63). The output stages select a clock source from the clock source bus for each base clock (see Table 46). Except for the base clocks to the WWDT (BASE_SAFE_CLK) and USB0 (BASE_USB0_CLK), the clock source for each output stage can be any of the external and internal clocks and oscillators directly or one of the PLL outputs or any of the outputs of the integer dividers. D Table 44. CGU0 base clocks Frequency [1] D R A R A FT D R FT D R R A FT D R R A F D R A FT A FT A FT R A D FT D R A Number Name 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21-24 25 26 27 [1] Description Base safe clock (always on) for WDT Base clock for USB0 Reserved Base clock for USB1 System base clock for ARM Cortex-M3 core and APB peripheral blocks #0 and #2 Base clock for SPIFI Reserved Base clock for Ethernet PHY Rx Base clock for Ethernet PHY Tx Base clock for APB peripheral block # 1 Base clock for APB peripheral block # 3 Base clock for LCD Base clock for Base clock for SD/MMC Base clock for SSP0 Base clock for SSP1 Base clock for UART0 Base clock for UART1 Base clock for UART2 Base clock for UART3 Base clock for CLKOUT pin Reserved Base clock for audio PLL Base clock for CGU_OUT0 clock output Base clock for CGU_OUT1 clock output BASE_SAFE_CLK BASE_USB0_CLK BASE_USB1_CLK BASE_M3_CLK BASE_SPIFI_CLK BASE_PHY_RX_CLK BASE_PHY_TX_CLK BASE_APB1_CLK BASE_APB3_CLK BASE_LCD_CLK BASE_ENET_CSR_CLK BASE_SDIO_CLK BASE_SSP0_CLK BASE_SSP1_CLK BASE_UART0_CLK BASE_UART1_CLK BASE_UART2_CLK BASE_UART3_CLK BASE_OUT_CLK BASE_APLL_CLK BASE_CGU_OUT0_CLK BASE_CGU_OUT1_CLK 12 MHz 480 MHz 150 MHz 150 MHz 150 MHz 150 MHz 75 MHz 75 MHz 150 MHz 150 MHz 150 MHz 150 MHz 150 MHz 150 MHz 150 MHz 150 MHz 150 MHz 150 MHz 150 MHz 150 MHz 150 MHz 150 MHz Maximum frequency that guarantees stable operation of the LPC18xx. Table 45 shows all available input clock sources for each clock generator. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 68 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 9: LPC18xx Clock Generation Unit (CGU) FT D R A D R A R A FT D R FT D Table 45. Available clock sources for clock generators with selectable inputs Clock generators PLL0 (USB) yes yes yes yes yes yes no no yes yes yes yes yes yes PLL0 (audio) yes yes yes yes yes yes no no yes yes yes yes yes yes PLL1 yes yes yes yes yes yes yes yes no yes yes yes yes yes IDIVA /4 yes yes yes yes yes yes yes yes yes no no no no no IDIVB /16 yes yes yes yes yes yes no yes yes yes no no no no IDIVC /16 yes yes yes yes yes yes no yes yes yes no no no no R R A FT D R R A F D R A FT Clock sources 32 kHz oscillator IRC 12 MHz ENET_RX_CLK ENET_TX_CLK GP_CLKIN Crystal oscillator PLL0 (USB) PLL0 (audio) PLL1 IDIVA IDIVB IDIVC IDIVD IDIVE Table 46. IDIVD /16 yes yes yes yes yes yes no yes yes yes no no no no IDIVE /256 yes yes yes yes yes yes no yes yes yes no no no no A A FT D R A FT D R A FT D Clock sources for output stages Output stages (d = default clock source, y = yes (clock source available), n = no (clock source not available)) BASE_CGU_OUT0_CLK y d y y y y y y BASE_CGU_OUT1_CLK y d y y y y y y BASE_ENETCSR_CLK BASE_PHY_RX_CLK BASE_PHY_TX_CLK Clock sources BASE_USB0_CLK BASE_USB1_CLK BASE_SAFE_CLK BASE_SPIFI_CLK BASE_M3_CLK BASE_UART0_CLK BASE_UART1_CLK BASE_UART2_CLK BASE_UART3_CLK BASE_APB1_CLK BASE_APB3_CLK 32 kHz n oscillator IRC 12 MHz d n n n n n n d n y d y y y y y y y d y y y y n y y d y y y y n y y d y y y y n y y d y y y y n y y d y y y y n y y d y y y y n y y d y y y y n y y d y y y y n y y d y y y y n y y d y y y y n y y d y y y y n y y d y y y y n y y d y y y y n y y d y y y y n y y d y y y y n y y d y y y y n y y d y y y y y y y d y y y y n y ENET_ n RX_CLK ENET_ n TX_CLK GP_ CLKIN n Crystal n oscillator PLL0 (USB) PLL0 (audio) n n All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 BASE_APLL_CLK BASE_SSP0_CLK BASE_SSP1_CLK BASE_SDIO_CLK BASE_OUT_CLK BASE_LCD_CLK Reserved 69 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 9: LPC18xx Clock Generation Unit (CGU) FT D R A D R A R A FT D R FT Table 46. Clock sources for output stages Output stages (d = default clock source, y = yes (clock source available), n = no (clock source not available)) BASE_ENETCSR_CLK BASE_PHY_RX_CLK BASE_PHY_TX_CLK D R R A FT D R R A F D R A A FT A BASE_CGU_OUT0_CLK BASE_CGU_OUT1_CLK Clock sources BASE_USB0_CLK BASE_USB1_CLK BASE_SAFE_CLK BASE_SPIFI_CLK BASE_M3_CLK FT D FT D R BASE_UART0_CLK BASE_UART1_CLK BASE_UART2_CLK BASE_UART3_CLK A BASE_APB1_CLK BASE_APB3_CLK BASE_APLL_CLK BASE_SSP0_CLK BASE_SSP1_CLK FT BASE_SDIO_CLK BASE_OUT_CLK BASE_LCD_CLK D R A PLL1 IDIVA IDIVB IDIVC IDIVD IDIVE n n n n n n n n n n n n y y y y y y y y y y y y y y y y y y y y y y y y Reserved y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y Oscillators, clock inputs PLLs Integer dividers Output generators BASE_SAFE_CLK BASE_USB0_CLK 12 MHz IRC RTCX1 RTCX2 XTAL1 32 kHz OSC OUTCLK_20 CRYSTAL OSC CLKOUT XTAL2 PLL0 ENET_RX_CLK IDIVA /4 IDIVB /16 18 ENET_TX_CLK PLL1 IDIVC /16 OUTCLK_2 - 19 (BASE_xxx_CLK) GP_CLKIN IDIVD /16 IDIVE /256 5 Fig 18. CGU block diagram All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 70 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 9: LPC18xx Clock Generation Unit (CGU) FT D R A D R A R A FT D R FT 9.5 Pin description Table 47. CGU pin description Direction I O I O I I I O O O Description Crystal oscillator input Crystal oscillator output RTC 32 kHz oscillator input RTC 32 kHz oscillator output General purpose input clock Ethernet PHY transmit clock Ethernet PHY receive clock Clock output pin CGU spare output 0 CGU spare output 1 Pin name/ function name XTAL1 XTAL2 RTCX1 RTCX2 GP_CLKIN ENET_TX_CLK ENET_RX_CLK CLKOUT CGU_OUT0 CGU_OUT1 D R R A FT D R R A F D R A FT A FT A FT D R A D FT D R A 9.6 Register description The register addresses of the CGU are shown in Table 48. Remark: The CGU is configured by the boot loader at reset and when waking up from Deep power-down to produce a 72 MHz clock using PLL1. Note that this configuration is not reflected in the reset values given in Table 48. Table 48. Name FREQ_MON XTAL_OSC_CTRL PLL0USB_STAT PLL0USB_CTRL PLL0USB_MDIV PLL0USB_NP_DIV PLL0AUDIO_STAT PLL0AUDIO_CTRL PLL0AUDIO_MDIV PLLAUDIO_FRAC PLL1_STAT PLL1_CTRL Register overview: CGU (base address 0x4005 0000) Access Address offset R R R R R/W R/W R R/W R/W R/W R R/W R/W R/W R R/W 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 0x024 0x028 0x02C 0x030 0x034 0x038 0x03C 0x040 0x044 Description Reserved Reserved Reserved Reserved Reserved Frequency monitor register Crystal oscillator control register PLL0 (USB) status register PLL0 (USB) control register PLL0 (USB) M-divider register PLL0 (USB) N/P-divider register PLL0 (audio) status register PLL0 (audio) control register PLL0 (audio) M-divider register PLL0 (audio) N/P-divider register PLL0 (audio) PLL1 status register PLL1 control register Reset value 0x0110 0106 0x0010 0500 0x1C00 0000 0x0000 0000 0x0000 0000 0x0000 0005 0x0100 0000 0x0100 0003 0x05F8 5B6A 0x000B 1002 0x0100 0000 0x0100 4003 0x05F8 5B6A 0x000B 1002 0x0020 0000 0x0100 0000 0x0100 0003 © NXP B.V. 2011. All rights reserved. PLL0AUDIO_NP_DIV R/W All information provided in this document is subject to legal disclaimers. User manual Rev. 00.13 — 20 July 2011 71 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 9: LPC18xx Clock Generation Unit (CGU) FT D R A D R A R A FT D R FT Table 48. Name Register overview: CGU (base address 0x4005 0000) Access Address offset R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0x048 0x04C 0x050 0x054 0x058 0x05C 0x060 0x064 0x068 0x06C 0x070 0x074 0x078 0x07C 0x080 0x084 0x088 0x08C Description Integer divider A control register Integer divider B control register Integer divider C control register Integer divider D control register Integer divider E control register Output stage 0 control register for base clock BASE_SAFE_CLK Output stage 1 control register for base clock BASE_USB0_CLK Reserved Output stage 3 control register for base clock BASE_USB1_CLK Output stage 4 control register for base clock BASE_M3_CLK Output stage 5 control register for base clock BASE_SPIFI_CLK Reserved Output stage 7 control register for base clock BASE_PHY_RX_CLK Output stage 8 control register for base clock BASE_PHY_TX_CLK Output stage 9 control register for base clock BASE_APB1_CLK D R Reset value R A FT D R R A F D R A A FT A IDIVA_CTRL IDIVB_CTRL IDIVC_CTRL IDIVD_CTRL IDIVE_CTRL OUTCLK_0_CTRL OUTCLK_1_CTRL OUTCLK_3_CTRL OUTCLK_4_CTRL OUTCLK_5_CTRL OUTCLK_7_CTRL OUTCLK_8_CTRL OUTCLK_9_CTRL OUTCLK_10_CTRL OUTCLK_11_CTRL OUTCLK_12_CTRL 0x0100 0000 0x0100 0000 0x0100 0000 0x0100 0000 0x0100 0000 0x0100 0000 0x0700 0000 0x0100 0000 0x0100 0000 0x0100 0000 0x0100 0000 0x0100 0000 0x0100 0000 0x0100 0000 FT D R A FT D R A Output stage 10 control register for 0x0100 0000 base clock BASE_APB3_CLK Output stage 11 control register for 0x0100 0000 base clock BASE_LCD_CLK Output stage 11 control register for 0x0100 0000 base clock BASE_ENET_CSR_CLK Output stage 13 control register for 0x0100 0000 base clock BASE_SDIO_CLK Output stage 14 control register for 0x0100 0000 base clock BASE_SSP0_CLK Output stage 15 control register for 0x0100 0000 base clock BASE_SSP1_CLK Output stage 16 control register for 0x0100 0000 base clock BASE_UART0_CLK Output stage 17 control register for 0x0100 0000 base clock BASE_UART1_CLK Output stage 18 control register for 0x0100 0000 base clock BASE_UART2_CLK Output stage 19 control register for 0x0100 0000 base clock BASE_UART3_CLK FT D OUTCLK_13_CTRL OUTCLK_14_CTRL OUTCLK_15_CTRL OUTCLK_16_CTRL OUTCLK_17_CTRL OUTCLK_18_CTRL OUTCLK_19_CTRL R/W R/W R/W R/W R/W R/W R/W 0x090 0x094 0x098 0x09C 0x0A0 0x0A4 0x0A8 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 72 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 9: LPC18xx Clock Generation Unit (CGU) FT D R A D R A R A FT D R FT Table 48. Name Register overview: CGU (base address 0x4005 0000) Access Address offset R/W R/W 0x0AC 0x0B0 to 0x0BC 0x0C0 0x0C4 Description D R Reset value R A FT D R R A F D R A A FT A OUTCLK_20_CTRL OUTCLK_21_CTRL to OUTCLK_24_CTRL OUTCLK_25_CTRL OUTCLK_26_CTRL Output stage 20 control register for 0x0100 0000 base clock BASE_OUT_CLK Reserved output stages - FT D R A FT D R A FT D R/W R/W Output stage 25 control register for base clock BASE_APLL_CLK Output stage 26 control register for base clock BASE_CGU_OUT0_CLK Output stage 27 control register for base clock BASE_CGU_OUT1_CLK OUTCLK_27_CTRL R/W 0x0C8 9.6.1 Frequency monitor register The CGU can report the relative frequency of any operating clock. The clock to be measured must be selected by software, while the fixed-frequency IRC clock fref is used as the reference frequency. A 14-bit counter then counts the number of cycles of the measured clock that occur during a user-defined number of reference-clock cycles. When the MEAS bit is set, the measured-clock counter is reset to 0 and counts up, while the 9-bit reference-clock counter is loaded with the value in RCNT and then counts down towards 0. When either counter reaches its terminal value both counters are disabled and the MEAS bit is reset to 0. The current values of the counters can then be read out and the selected frequency obtained by the following equation: Qselected fselected = -------------------------------------------------------------------------  fref  Qref  initial  – Qref  final   If RCNT is programmed to a value equal to the core clock frequency in kHz and reaches 0 before the FCNT counter saturates, the value stored in FCNT would then show the measured clock’s frequency in kHz without the need for any further calculation. Note that the accuracy of this measurement can be affected by several factors: 1. Quantization error is noticeable if the ratio between the two clocks is large (e.g. 100 kHz vs. 1 kHz), because one counter saturates while the other still has only a small count value. 2. Due to synchronization, the counters are not started and stopped at exactly the same time. 3. The measured frequency can only be to the same level of precision as the reference frequency. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 73 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 9: LPC18xx Clock Generation Unit (CGU) FT D R A D R A R A FT D R FT D Table 49. Bit 8:0 22:9 23 FREQ_MON register (FREQ_MON, address 0x4005 0014) bit description R R R A A A FT D FT D F Symbol RCNT FCNT MEAS Value Description 9-bit reference clock-counter value 14-bit selected clock-counter value Measure frequency Reset value 0 0 0 Access R/W R R/W R R A A FT D R A FT D FT D R A 0 1 28:24 CLK_SEL 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 31:29 - RCNT and FCNT disabled Frequency counters started Clock-source selection for the clock to be 0 measured. All other values are reserved. 32 kHz oscillator (default) IRC ENET_RX_CLK ENET_TX_CLK GP_CLKIN Reserved Crystal oscillator PLL0 (USB) PLL0 (audio) PLL1 Reserved Reserved IDIVA IDIVB IDIVC IDIVD IDIVE Reserved R/W 9.6.2 Crystal oscillator control register The register XTAL_OSC_CONTROL contains the control bits for the crystal oscillator. Table 50. Bit 0 XTAL_OSC_CTRL register (XTAL_OSC_CTRL, address 0x4005 0018) bit description Value Description Reset Access value R/W Symbol ENABLE Oscillator-pad enable. Do not change the BYPASS 1 and ENABLE bits in one write-action: this will result in unstable device operation! 0 1 Enable Power-down (default) All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 74 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 9: LPC18xx Clock Generation Unit (CGU) FT D R A D R A R A FT D R FT Table 50. Bit 1 XTAL_OSC_CTRL register (XTAL_OSC_CTRL, address 0x4005 0018) bit description D R R R A A A FT F FT Symbol BYPASS Value Description Configure crystal operation or external-clock input pin XTAL1. Do not change the BYPASS and ENABLE bits in one write-action: this will result in unstable device operation! 0 1 Operation with crystal connected (default). Bypass mode. Use this mode when an external clock source is used instead of a crystal. Select frequency range 0 Oscillator low-frequency mode (crystal or external clock source 1 to 20 MHz). Between 15 MHz to 20 MHz, the state of the HF bit is don’t care. Oscillator high-frequency mode; crystal or external clock source 15 to 25 MHz. Between 15 MHz to 20 MHz, the state of the HF bit is don’t care (default) Reserved Reset Access value D D R R A A FT FT 0 R/W D D R A FT D R A 2 HF 1 R/W 1 31:3 - - - 9.6.3 PLL0 (for USB) registers The PLL0 provides a dedicated clock to the High-speed USB0 interface and to USB1. See Section 9.7.4.5 for instructions on how to set up the PLL0. 9.6.3.1 PLL0 (for USB) status register Table 51. Bit 0 1 31:2 PLL0USB status register (PLL0USB_STAT, address 0x4005 001C) bit description Symbol LOCK FR Description PLL0 lock indicator PLL0 free running indicator Reserved Reset value 0 0 Access R R - 9.6.3.2 PLL0 (for USB) control register Table 52. Bit 0 PLL0USB control register (PLL0USB_CTRL, address 0x4005 0020) bit description Symbol PD 0 1 1 BYPASS 0 1 2 Value Description PLL0 power down PLL0 enabled PLL0 powered down Input clock bypass control CCO clock sent to post-dividers. Use this in normal operation. PLL0 input clock sent to post-dividers (default). PLL0 direct input Reset value 1 Access R/W 1 R/W DIRECTI 0 R/W All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 75 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 9: LPC18xx Clock Generation Unit (CGU) FT D R A D R A R A FT D R FT Table 52. Bit 3 4 5 6 7 8 9 10 11 PLL0USB control register (PLL0USB_CTRL, address 0x4005 0020) bit description D R R R A A A …continued FT F FT Symbol DIRECTO CLKEN FRM AUTOBLOCK Value Description PLL0 direct output PLL0 clock enable Reserved Free running mode Reserved Reserved. Reads as zero. Do not write one to this register. Reserved. Reads as zero. Do not write one to this register. Reserved. Reads as zero. Do not write one to this register. Reset value 0 0 0 0 0 0 0 Access D D - R R/W R/W R/W R/W R/W R/W R/W R/W R A A FT D R A FT D FT D R A Block clock automatically during frequency 0 change 0 1 Autoblocking disabled Autoblocking enabled Reserved Clock source selection. All other values are reserved. 0x00 0x01 0x02 0x03 0x04 0x06 0x09 0x0C 0x0D 0x0E 0x0F 0x10 32 kHz oscillator IRC (default) ENET_RX_CLK ENET_TX_CLK GP_CLKIN Crystal oscillator PLL1 IDIVA IDIVB IDIVC IDIVD IDIVE Reserved 0x01 23:12 28:24 CLK_SEL R/W 31:29 - - 9.6.3.3 PLL0 (for USB) M-divider register Table 53. PLL0USB M-divider register (PLL0USB_MDIV, address 0x4005 0024) bit description Symbol MDEC Description Reset value Access R/W Bit 16:0 Decoded M-divider coefficient value. Select values for 0x5B6A the M-divider between 1 and 131071. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 76 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 9: LPC18xx Clock Generation Unit (CGU) FT D R A D R A R A FT D R FT Table 53. PLL0USB M-divider register (PLL0USB_MDIV, address 0x4005 0024) bit description D R R R A A A FT F FT …continued D D R R A Bit 21:17 27:22 31:28 Symbol SELP SELI SELR Description Bandwidth select P value Bandwidth select I value Bandwidth select R value Reset value 11100 010111 0000 Access R/W R/W R/W A FT D A FT D R A FT D R 9.6.3.4 PLL0 (for USB) NP-divider register Table 54. PLL0USB NP-divider register (PLL0USB_NP_DIV, address 0x4005 0028) bit description Symbol PDEC NDEC Description Decoded P-divider coefficient value Reserved Decoded N-divider coefficient value Reserved Reset value 000 0010 Access R/W - Bit 6:0 11:7 21:12 31:22 1011 0001 R/W 9.6.4 PLL0 (for audio) registers See Section 9.7.4.5 for instructions on how to set up the PLL0. 9.6.4.1 PLL0 (for audio) status register Table 55. Bit 0 1 31:2 PLL0AUDIO status register (PLL0AUDIO_STAT, address 0x4005 002C) bit description Symbol LOCK FR Description PLL0 lock indicator PLL0 free running indicator Reserved Reset value 0 0 Access R R - 9.6.4.2 PLL0 (for audio) control register Table 56. PLL0AUDIO control register (PLL0AUDIO_CTRL, address 0x4005 0030) bit description Symbol PD 0 1 1 BYPASS 0 1 Value Description PLL0 power down PLL0 enabled PLL0 powered down Input clock bypass control CCO clock sent to post-dividers. Use this in normal operation. PLL0 input clock sent to post-dividers (default). © NXP B.V. 2011. All rights reserved. Bit 0 Reset value 1 Access R/W 1 R/W All information provided in this document is subject to legal disclaimers. User manual Rev. 00.13 — 20 July 2011 77 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 9: LPC18xx Clock Generation Unit (CGU) FT D R A D R A R A FT D R FT Table 56. PLL0AUDIO control register (PLL0AUDIO_CTRL, address 0x4005 0030) bit description D R R R A A A FT F FT …continued D D R R A Bit 2 3 4 5 6 7 8 9 10 11 Symbol DIRECTI DIRECTO CLKEN FRM AUTOBLOCK Value Description PLL0 direct input PLL0 direct output PLL0 clock enable Reserved Free running mode Reserved Reserved. Reads as zero. Do not write one to this register. Reserved. Reads as zero. Do not write one to this register. Reserved. Reads as zero. Do not write one to this register. Reset value 0 0 0 0 0 0 0 0 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W A FT D A FT D R A FT D R Block clock automatically during frequency 0 change 0 1 Autoblocking disabled Autoblocking enabled Fractional PLL word write request SD modulator bypass SD modulator power-down 0 1 SD modulator enabled SD modulator powered down Reserved Clock source selection. All other values are reserved. 0x00 0x01 0x02 0x03 0x04 0x06 0x09 0x0C 0x0D 0x0E 0x0F 0x10 32 kHz oscillator IRC (default) ENET_RX_CLK ENET_TX_CLK GP_CLKIN Crystal oscillator PLL1 IDIVA IDIVB IDIVC IDIVD IDIVE Reserved 0x01 0 0 1 12 13 14 PLLFRAQ_ REQ SEL_EXT MOD_PD R/W R/W R/W 23:15 28:24 CLK_SEL R/W 31:29 - - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 78 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 9: LPC18xx Clock Generation Unit (CGU) FT D R A D R A R A FT D R FT 9.6.4.3 PLL0 (for audio) M-divider register Table 57. D R PLL0AUDIO M-divider register (PLL0AUDIO_MDIV, address 0x4005 0034) bit description R A FT D R R A F D R A FT D A FT D R A FT Bit 16:0 21:17 27:22 31:28 Symbol MDEC SELP SELI SELR Description Reset value Access R/W R/W R/W R/W A FT D Decoded M-divider coefficient value. Select values for 0x5B6A the M-divider between 1 and 131071. Bandwidth select P value Bandwidth select I value Bandwidth select R value 11100 010111 0000 R A 9.6.4.4 PLL0 (for audio) NP-divider register Table 58. PLL0 AUDIO NP-divider register (PLL0AUDIO_NP_DIV, address 0x4005 0038) bit description Symbol PDEC NDEC Description Decoded P-divider coefficient value Reserved Decoded N-divider coefficient value Reserved Reset value 000 0010 Access R/W - Bit 6:0 11:7 21:12 31:22 1011 0001 R/W 9.6.4.5 PLL0 (for audio) fractional divider register Table 59. PLL0AUDIO fractional divider register (PLL0AUDIO_FRAC, address 0x4005 003C) bit description Symbol PLLFRACT_CTRL Description PLL fractional divider control word Reserved Reset value 000 0000 Access R/W - Bit 21:0 31:22 9.6.5 PLL1 registers The PLL1 is used for the core and all peripheral blocks. 9.6.5.1 PLL1 status register Table 60. Bit 0 31:1 PLL1 status register (PLL1_STAT, address 0x4005 0040) bit description Symbol LOCK Description PLL1 lock indicator Reserved Reset value 0 Access R - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 79 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 9: LPC18xx Clock Generation Unit (CGU) FT D R A D R A R A FT D R FT 9.6.5.2 PLL1 control register Table 61. Bit 0 D R PLL1_CTRL register (PLL1_CTRL, address 0x4005 0044) bit description Symbol PD 0 1 Value Description PLL1 power down PLL1 enabled PLL1 powered down Input clock bypass control 0 1 CCO clock sent to post-dividers. Use for normal operation. PLL1 input clock sent to post-dividers (default). Reserved. Do not write one to this bit. Reserved. Do not write one to these bits. PLL feedback select (see Figure 20 “PLL1 block diagram”). 0 1 CCO output is used as feedback divider input clock. PLL output clock (clkout) is used as feedback divider input clock. Use for normal operation. PLL direct CCO output 0 1 Disabled Enabled Post-divider division ratio. The value applied is 2xP. 0x0 0x1 0x2 0x3 1 2 (default) 4 8 Reserved Block clock automatically during frequency change 0 1 Autoblocking disabled Autoblocking enabled Pre-divider division ratio 0x0 0x1 0x2 0x3 1 2 3 (default) 4 Reserved 10 0 01 0 0 0 1 Reset Access value 1 R/W R A FT D R R A F D R A FT A FT A FT D R A D FT D R A 1 BYPASS R/W 2 5:3 6 FBSEL R/W R/W 7 DIRECT R/W 9:8 PSEL[ R/W 10 11 AUTOBLOCK R/W 13:12 NSEL R/W 15:14 - - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 80 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 9: LPC18xx Clock Generation Unit (CGU) FT D R A D R A R A FT D R FT Table 61. Bit 23:16 PLL1_CTRL register (PLL1_CTRL, address 0x4005 0044) bit description D R R R A A A …continued FT F FT Symbol MSEL Value Description Feedback-divider division ratio (M) 00000000 = 1 00000001 = 2 ... 11111111 = 256 Reset Access value 11000 R/W D D R R A A FT D A FT D R A FT D R 27:24 CLK_SEL 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F Clock-source selection. 32 kHz oscillator IRC (default) ENET_RX_CLK ENET_TX_CLK GP_CLKIN Reserved crystal oscillator PLL0 Reserved Reserved Reserved IDIVA IDIVB IDIVC IDIVD IDIVE Reserved 0x01 R/W 31:28 - - - 9.6.6 Integer divider register A Table 62. Bit 0 IDIVA control register (IDIVA_CTRL, address 0x4005 0048) bit description Symbol PD 0 1 1 3:2 IDIV 0x0 0x1 0x2 0x3 10:4 Value Description Integer divider A power down IDIVA enabled (default) power-down Reserved Integer divider A divider values (1/(IDIV + 1)) 1 (default) 2 3 4 Reserved Reset value 0 Access R/W 00 R/W - - - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 81 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 9: LPC18xx Clock Generation Unit (CGU) FT D R A D R A R A FT D R FT Table 62. Bit 11 IDIVA control register (IDIVA_CTRL, address 0x4005 0048) bit description D R R R A A A …continued FT F FT Symbol AUTOBLOCK Value Description Reset value Access D D R R A A FT FT Block clock automatically during frequency 0 change 0 1 Autoblocking disabled Autoblocking enabled Reserved Clock source selection. All other values are reserved. 0x00 0x01 0x02 0x03 0x04 0x06 0x07 0x08 0x09 32 kHz oscillator IRC (default) ENET_RX_CLK ENET_TX_CLK GP_CLKIN Crystal oscillator PLL0 (for USB) PLL0 (for audio) PLL1 Reserved 0x01 R/W D D R A FT D R A 23:12 28:24 CLK_SEL R/W 31:29 - - 9.6.7 Integer divider register B, C, D Table 63. Bit 0 IDIVB/C/D control registers (IDIVB_CTRL, address 0x4005 004C; IDIVC_CTRL, address 0x4005 0050; IDIVC_CTRL, address 0x4005 0054) bit description Symbol PD 0 1 1 5:2 IDIV Value Description Integer divider power down IDIV enabled (default) power-down Reserved Integer divider B, C, D divider values (1/(IDIV + 1)) 0000 = 1 (default) 0001 = 2 ... 1111 = 16 10:6 11 AUTOBLOCK 0 1 23:12 Reserved R/W Block clock automatically during frequency 0 change Autoblocking disabled Autoblocking enabled Reserved 0000 R/W Reset value 0 Access R/W All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 82 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 9: LPC18xx Clock Generation Unit (CGU) FT D R A D R A R A FT D R FT Table 63. Bit 28:24 IDIVB/C/D control registers (IDIVB_CTRL, address 0x4005 004C; IDIVC_CTRL, address 0x4005 0050; IDIVC_CTRL, address 0x4005 0054) bit description D R R R A A A FT F FT Symbol CLK_SEL Value Description Clock-source selection. All other values are reserved. Reset value 0x01 Access R/W D D R R A A FT D R A FT D FT 0x00 0x01 0x02 0x03 0x04 0x06 0x08 0x09 0x0C 31:29 - 32 kHz oscillator IRC (default) ENET_RX_CLK ENET_TX_CLK GP_CLKIN Crystal oscillator PLL0 (for audio) PLL1 IDIVA Reserved - D R A 9.6.8 Integer divider register E Table 64. Bit 0 IDIVE control register (IDIVE_CTRL, address 0x4005 0058) bit description Symbol PD 0 1 1 9:2 IDIV Value Description Integer divider power down IDIV enabled (default) power-down Reserved Integer divider E divider values (1/(IDIV + 1)) 00000000 = 1 (default) 00000001 = 2 ... 111111111 = 256 10 11 AUTOBLOCK 0 1 23:12 Reserved R/W Block clock automatically during frequency 0 change Autoblocking disabled Autoblocking enabled Reserved 000000 00 R/W Reset value 0 Access R/W All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 83 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 9: LPC18xx Clock Generation Unit (CGU) FT D R A D R A R A FT D R FT Table 64. Bit 27:24 IDIVE control register (IDIVE_CTRL, address 0x4005 0058) bit description D R R R A A A Symbol CLK_SEL Value Description Reset value Access FT D R A F FT D R A R/W Clock-source selection. All other values are 0x01 reserved. 0x00 0x01 0x02 0x03 0x04 0x06 0x08 0x09 0x0C 32 kHz oscillator IRC (default) ENET_RX_CLK ENET_TX_CLK GP_CLKIN Crystal oscillator PLL0 (for audio) PLL1 IDIVA Reserved - FT D R A FT D R A FT D 31:28 - - 9.6.9 Output stage 0 control register This register controls the BASE_SAFE_CLK to the watchdog oscillator. The only possible clock source for this base clock is the IRC. Table 65. Bit 0 Output stage 0 control register (OUTCLK_0_CTRL, address 0x4005 005C) bit description Symbol PD 0 1 10:1 11 AUTOBLOCK 0 1 23:12 28:24 CLK_SEL 0x01 31:29 Value Description Output stage power down Output stage enabled (default) power-down Reserved R/W Block clock automatically during frequency 0 change Autoblocking disabled Autoblocking enabled Reserved Clock source selection. All other values are reserved. IRC (default) Reserved 0x01 R/W Reset value 0 Access R/W 9.6.10 Output stage 1 control register This register controls the BASE_USB0_CLK to the High-speed USB0. The only possible clock source for this base clock is the PLL0 (USB) output. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 84 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 9: LPC18xx Clock Generation Unit (CGU) FT D R A D R A R A FT D R FT D Table 66. Bit 0 Output stage 1 control register (OUTCLK_1_CTRL, address 0x4005 0060) bit description R R R A A A FT D F FT D Symbol PD Value Description Output stage power down Reset value 0 Access R/W R R A A FT D R A FT D 0 1 10:1 11 AUTOBLOCK 0 1 23:12 28:24 31:29 CLK_SEL 0x07 - Output stage enabled (default) power-down Reserved Block clock automatically during frequency change Autoblocking disabled Autoblocking enabled Reserved Clock-source selection. PLL0 (for USB, default) Reserved 0x07 R/W 0 R/W FT D R A 9.6.11 Output stage 3 control register These registers control base clocks 3 (USB1). Table 67. Bit 0 Output stage 3 control register (OUTCLK_3_CTRL, address 0x4005 0068) bit description Symbol PD 0 1 10:1 11 AUTOBLOCK 0 1 23:12 Value Description Output stage power down Output stage enabled (default) power-down Reserved R/W Block clock automatically during frequency 0 change Autoblocking disabled Autoblocking enabled Reserved Reset value 0 Access R/W All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 85 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 9: LPC18xx Clock Generation Unit (CGU) FT D R A D R A R A FT D R FT Table 67. Bit 28:24 Output stage 3 control register (OUTCLK_3_CTRL, address 0x4005 0068) bit description …continued D R R R A A A FT F FT Symbol CLK_SEL Value Description Reset value Access D D R R A A FT FT Clock source selection. All other values are 0x01 reserved. 0x00 0x01 0x02 0x03 0x04 0x06 0x07 0x08 0x09 0x0C 0x0D 0x0E 0x0F 0x10 32 kHz oscillator IRC (default) ENET_RX_CLK ENET_TX_CLK GP_CLKIN Crystal oscillator PLL0 (for USB) PLL0 (for audio) PLL1 IDIVA IDIVB IDIVC IDIVD IDIVE Reserved - R/W D D R A FT D R A 31:29 - - 9.6.12 Output stage 4 to 19 control registers These registers control base clocks 4 to 19. Table 68. Bit 0 Output stage 4 to 19 control registers (OUTCLK_4_CTRL to OUTCLK_19_CTRL, address 0x4005 006C to 0x4005 00A8) bit description Symbol PD 0 1 10:1 11 AUTOBLOCK 0 1 23:12 Value Description Output stage power down Output stage enabled (default) power-down Reserved R/W Block clock automatically during frequency 0 change Autoblocking disabled Autoblocking enabled Reserved Reset value 0 Access R/W All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 86 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 9: LPC18xx Clock Generation Unit (CGU) FT D R A D R A R A FT D R FT Table 68. Bit 28:24 Output stage 4 to 19 control registers (OUTCLK_4_CTRL to OUTCLK_19_CTRL, address 0x4005 006C to 0x4005 00A8) bit description …continued D R R R A A A FT F FT Symbol CLK_SEL Value Description Reset value Access D D R R A A FT FT Clock source selection. All other values are 0x01 reserved. 0x00 0x01 0x02 0x03 0x04 0x06 0x08 0x09 0x0C 0x0D 0x0E 0x0F 0x10 32 kHz oscillator IRC (default) ENET_RX_CLK ENET_TX_CLK GP_CLKIN Crystal oscillator PLL0 (for audio) PLL1 IDIVA IDIVB IDIVC IDIVD IDIVE Reserved - R/W D D R A FT D R A 31:29 - - 9.6.13 Output stage 20 register This register controls the clock output to the CLKOUT pin. All clock generator outputs can be monitored through this pin. Table 69. Bit 0 Output stage 20 control register (OUTCLK_20_CTRL, addresses 0x4005 00AC) bit description Symbol PD 0 1 10:1 11 AUTOBLOCK 0 1 23:12 Value Description Output stage power down Output stage enabled (default) power-down Reserved R/W Block clock automatically during frequency 0 change Autoblocking disabled Autoblocking enabled Reserved Reset value 0 Access R/W All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 87 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 9: LPC18xx Clock Generation Unit (CGU) FT D R A D R A R A FT D R FT Table 69. Bit 27:24 Output stage 20 control register (OUTCLK_20_CTRL, addresses 0x4005 00AC) bit description …continued D R R R A A A FT F FT Symbol CLK_SEL Value Description Clock-source selection. Reset value 0x01 Access R/W D D R R A A FT D R A FT D 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0C 0x0D 0x0E 0x0F 0x10 31:28 - 32 kHz oscillator IRC (default) ENET_RX_CLK ENET_TX_CLK GP_CLKIN Reserved Crystal oscillator PLL0 (for USB) PLL0 (for audio) PLL1 IDIVA IDIVB IDIVC IDIVD IDIVE Reserved - FT D R A 9.6.14 Output stage 25 register This register controls the clock output to the . Table 70. Bit 0 Output stage 25 control register (OUTCLK_25_CTRL, addresses 0x4005 00C0) bit description Symbol PD 0 1 10:1 11 AUTOBLOCK 0 1 23:12 Value Description Output stage power down Output stage enabled (default) power-down Reserved R/W Block clock automatically during frequency 0 change Autoblocking disabled Autoblocking enabled Reserved Reset value 0 Access R/W All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 88 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 9: LPC18xx Clock Generation Unit (CGU) FT D R A D R A R A FT D R FT Table 70. Bit 27:24 Output stage 25 control register (OUTCLK_25_CTRL, addresses 0x4005 00C0) bit description …continued D R R R A A A FT F FT Symbol CLK_SEL Value Description Clock-source selection. Reset value 0x01 Access R/W D D R R A A FT D R A FT D 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0C 0x0D 0x0E 0x0F 0x10 31:28 - 32 kHz oscillator IRC (default) ENET_RX_CLK ENET_TX_CLK GP_CLKIN Reserved Crystal oscillator Reserved PLL0 (for audio) PLL1 IDIVA IDIVB IDIVC IDIVD IDIVE Reserved - FT D R A 9.6.15 Output stage 26 to 27 register This register controls the clock output to the spare CGU outputs pins CGU_OUT0 and CGU_OUT1. All clock generator outputs can be monitored through this pin. Table 71. Bit 0 Output stage 26 to 27 control register (OUTCLK_26_CTRL to OUTCLK_27_CTRL, addresses 0x4005 00C4 to 0x4005 00C8) bit description Symbol PD 0 1 10:1 11 AUTOBLOCK 0 1 23:12 Value Description Output stage power down Output stage enabled (default) power-down Reserved R/W Block clock automatically during frequency 0 change Autoblocking disabled Autoblocking enabled Reserved Reset value 0 Access R/W All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 89 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 9: LPC18xx Clock Generation Unit (CGU) FT D R A D R A R A FT D R FT Table 71. Bit 27:24 Output stage 26 to 27 control register (OUTCLK_26_CTRL to OUTCLK_27_CTRL, addresses 0x4005 00C4 to 0x4005 00C8) bit description …continued D R R R A A A FT F FT Symbol CLK_SEL Value Description Clock-source selection. Reset value 0x01 Access R/W D D R R A A FT D R A FT D 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0C 0x0D 0x0E 0x0F 0x10 31:28 - 32 kHz oscillator IRC (default) ENET_RX_CLK ENET_TX_CLK GP_CLKIN Reserved Crystal oscillator PLL0 (for USB) PLL0 (for audio) PLL1 IDIVA IDIVB IDIVC IDIVD IDIVE Reserved - FT D R A 9.7 Functional description 9.7.1 32 kHz oscillator The 32 kHz oscillator output is controlled by the CREG block (see Table 31). The RTC and the Alarm timer are connected directly to the 32 kHz oscillator. 9.7.2 IRC The IRC is a trimmed 12 MHz internal oscillator. Although it's part of the CGU, the CGU has no control over this clock source. The IRC is put into power down depending on the power saving mode. 9.7.3 Crystal oscillator The crystal oscillator is controlled by the XTAL_OSC_CTRL register in the CGU (see Table 50). 9.7.4 PLL0 (for USB and audio) 9.7.4.1 Features • Input frequency: 14 kHz to 150 MHz. The input from an external crystal is limited to 25 MHz. • CCO frequency: 275 MHz to 550 MHz. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 90 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 9: LPC18xx Clock Generation Unit (CGU) FT D R A D R A R A FT D R FT • Output clock range: 4.3 MHz to 550 MHz. • Programmable dividers: – Pre-divider N (N, 1 to 28) – Feedback-divider 2 x M (M, 1 to 215) – Post-divider P x 2 (P, 1 to 25). D R • Programmable bandwidth (integrating action, proportional action, high frequency pole). • • • • • • On-the-fly adjustment of the clock possible (dividers with handshake control). Positive edge clocking. Frequency limiter to avoid hang-up of the PLL. Lock detector. Power-down mode. Free running mode Remark: Both PLL0 blocks are functionally identical. The PLL0 for audio applications (PLL0 for audio) supports an additional fractional divider stage (see Section 9.7.5). R A FT D R R A F D R A FT A FT A FT D R A D FT D R A 9.7.4.2 PLL0 description The block diagram of the PLL is shown in Figure 19. The clock input has to be fed to pin clkin. Pin clkout is the PLL clock output. The analog part of the PLL consists of a Phase Frequency Detector (PFD), filter and a Current Controlled Oscillator (CCO). The PFD has two inputs, a reference input from the (divided) external clock and one input from the divided CCO output clock. The PFD compares the phase/frequency of these input signals and generates a control signal if they don’t match. This control signal is fed to a filter which drives the CCO. Direct Output PLL0_CTRL [3] Bypass PLL0_CTRL [1] 32kHz IRC ENET_RX_CLK ENET_TX_CLK GP_CLKIN CRYSTAL PLL1 IDIVA IDIVB IDIVC IDIVD IDIVE CLKOUT Q N-DIVIDER CLKIN “1” PFD Filter CCO P-DIVIDER /2 D PLL0 NPDIV[21:12] Direct Input PLL0_CTRL[2] Bandwidth Select P,I,R PLL0_MDIV[31:17] M-DIVIDER /2 PLL0_NPDIV[6:0] PLL0_CTRL[27:24] CLKEN PLL0_CTRL[4] PLL0_MDIV[16:0] Fig 19. PLL0 block diagram The PLL contains three programmable dividers: pre-divider (N), feedback-divider (M) and post-divider (P). The PLL contains a lock detector which measures the phase difference between the rising edges of the input and feedback clocks. Only when this difference is All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 91 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 9: LPC18xx Clock Generation Unit (CGU) FT D R R A smaller than the so called “lock criterion” for more than seven consecutive input clock periods, the lock output switches from low to high. A single too large phase difference immediately resets the counter and causes the lock signal to drop (if it was high). Requiring seven phase measurements in a row to be below a certain figure ensures that the lock detector will not indicate lock until both the phase and frequency of the input and feedback clocks are very well aligned. This effectively prevents false lock indications, and thus ensures a glitch free lock signal. R A A FT D R A FT D To avoid frequency hang-up the PLL contains a frequency limiter. This feature is built in to prevent the CCO from running too fast, this can occur if e.g. a wrong feedback-divider (M) ratio is applied to the PLL. D R A R A FT D R FT D R A F R A FT D FT D R A D FT R A 9.7.4.3 Use of PLL0 operating modes Table 72. Mode 1: Normal 3: Power Down PLL operating modes PLL0_Mode bit settings: PD 0 1 CLKEN 1 x BYPASS 0 x DIRECTI 1/0 x DIRECTO 1/0 x FRM 0 x 9.7.4.3.1 Normal Mode Mode 1 is the normal operating mode. The pre- and post-divider can be selected to give: • • • • mode 1a: Normal operating mode without post-divider and without pre-divider mode 1b: Normal operating mode with post-divider and without pre-divider mode 1c: Normal operating mode without post-divider and with pre-divider mode 1d: Normal operating mode with post-divider and with pre-divider To get at the output of the PLL (clkout) the best phase-noise and jitter performance, the highest possible reference clock (clkref) at the PFD has to be used. Therefore mode 1a and 1b are recommended, when it is possible to make the right output frequency without pre-divider. By using the post-divider the clock at the output of the PLL (clkout) the divider ratio is always even because the divide-by-2 divider after the post-divider. Table 73. Mode 1a 1b 1c 1d DIRECTL and DIRECTO bit settings in HP0/1_Mode register DIRECTI 1 1 0 0 DIRECTO 1 0 1 0 9.7.4.3.2 Mode 1a: Normal operating mode without post-divider and without pre-divider In normal operating mode 1a the post-divider and pre-divider are bypassed. The operating frequencies are: All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 92 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 9: LPC18xx Clock Generation Unit (CGU) FT D R R A Fout = Fcco = 2 x M x Fin (275 MHz Fcco 550 MHz, 4 kHz  Fin 150 MHz) A D R A R A FT D R FT D R A F R A FT FT The feedback divider ratio is programmable: D D R A R A • Feedback-divider M (M, 1 to 215) 9.7.4.3.3 Mode 1b: Normal operating mode with post-divider and without pre-divider FT D R A FT D R A In normal operating mode 1b the pre-divider is bypassed. The operating frequencies are: Fout = Fcco /(2 x P) = (M / P) x Fin  (275 MHz Fcco 550 MHz, 4 kHz Fin  150 MHz) The divider ratios are programmable: FT D • Feedback-divider M (M, 1 to 215) • Post-divider P (P, 1 to 32) 9.7.4.3.4 Mode 1c: Normal operating mode without post-divider and with pre-divider In normal operating mode 1c the post-divider with divide-by-2 divider is bypassed. The operating frequencies are: Fout = Fcco = 2 x M x Fin / N  (275 MHz Fcco 550 MHz, 4 kHz Fin/N 150 MHz) The divider ratios are programmable: • Pre-divider N (N, 1 to 256) • Feedback-divider M (M, 1 to 215) 9.7.4.3.5 Mode 1d: Normal operating mode with post-divider and with pre-divider In normal operating mode 1d none of the dividers are bypassed. The operating frequencies are: Fout = Fcco /(2 x P) = M x Fin /(N x P)  (275 MHz Fcco 550 MHz, 4 kHz Fin/N 150 MHz) The divider ratios are programmable: • Pre-divider N (N, 1 to 256) • Feedback-divider M (M, 1 to 215) • Post-divider P (P, 1 to 32) 9.7.4.3.6 Mode 3: Power down mode (pd) In this mode (pd = '1'), the oscillator will be stopped, the lock output will be made low, and the internal current reference will be turned off. During pd it is also possible to load new divider ratios at the input buses (msel, psel, nsel). Power-down mode is ended by making pd low, causing the PLL to start up. The lock signal will be made high once the PLL has regained lock on the input clock. 9.7.4.4 Settings for USB0 Table 74 shows the divider settings used for configuring a certain output frequency Fout for USB0. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 93 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 9: LPC18xx Clock Generation Unit (CGU) FT D R A D R A R A FT D R FT D Table 74. System PLL divider ratio settings for 12 MHz FCCo (MHz) Ndec Mdec Pdec SELR R R A FT R A F A FT Fout (MHz) SELI SELP D D R R A A FT D FT D 9.7.4.5 Usage notes In order to set up the PLL0, follow these steps: 1. Power down the PLL0 by setting bit 1 in the PLL0_CTRL register to 1. This step is only needed if the PLL0 is currently enabled. 2. Configure the PLL0 m, n, and p divider values in the PLL0_M and PLL0_NP registers. 3. Power up the PLL0 by setting bit 1 in the PLL0_CTRL register to 0. 4. Wait for the PLL0 to lock by monitoring the LOCK bit in the PLL0_STAT register. 5. Enable the PLL0 clock output in the PLL0_CTRL register. R A FT D R A 9.7.5 Fractional divider for the PLL0 (for audio) The PLL0 for audio applications (PLL0 (for audio)) includes an additional fractional divider. 9.7.6 PLL1 9.7.6.1 Features • 1 MHz to 50 MHz input frequency. The input from an external crystal is limited to 25 MHz. • • • • 9.75 MHz to 320 MHz selectable output frequency with 50% duty cycle. 156 MHz to 320 MHz Current Controlled Oscillator (CCO) frequency. Power-down mode. Lock detector. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 94 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 9: LPC18xx Clock Generation Unit (CGU) FT D R A D R A R A FT D R FT 9.7.6.2 PLL1 description D R R A FT D R R A F D R A FT A FT A FT FCLKIN CCO D D R /N 2 NSEL PFD pd LOCK DETECT LOCK FCCO PSEL 2 0 1 BYPASS analog section pd A FT D R cd A /2P 0 1 DIRECT FCLKOUT FCLKIN pd cd /M 8 MSEL 0 1 FBSEL Fig 20. PLL1 block diagram The block diagram of this PLL is shown in Figure 20. The input frequency range is 10 MHz to 25 MHz. The input clock is fed directly to the Phase-Frequency Detector (PFD). This block compares the phase and frequency of its inputs, and generates a control signal when phase and/ or frequency do not match. The loop filter filters these control signals and drives the current controlled oscillator (CCO), which generates the main clock. The CCO frequency range is 156 MHz to 320 MHz.These clocks are either divided by 2xP by the programmable post divider to create the output clocks, or are sent directly to the outputs. The main output clock is then divided by M by the programmable feedback divider to generate the feedback clock. The output signal of the phase-frequency detector is also monitored by the lock detector, to signal when the PLL has locked on to the input clock. 9.7.6.3 Lock detector The lock detector measures the phase difference between the rising edges of the input and feedback clocks. Only when this difference is smaller than the so called “lock criterion” for more than eight consecutive input clock periods, the lock output switches from low to high. A single too large phase difference immediately resets the counter and causes the lock signal to drop (if it was high). Requiring eight phase measurements in a row to be below a certain figure ensures that the lock detector will not indicate lock until both the phase and frequency of the input and feedback clocks are very well aligned. This effectively prevents false lock indications, and thus ensures a glitch free lock signal. 9.7.6.4 Power-down control To reduce the power consumption when the PLL clock is not needed, a Power-down mode has been incorporated. In this mode, the internal current reference will be turned off, the oscillator and the phase-frequency detector will be stopped and the dividers will enter a reset state. While in Power-down mode, the lock output will be low to indicate that All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 95 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 9: LPC18xx Clock Generation Unit (CGU) FT D R R A the PLL is not in lock. When the Power-down mode is terminated, the PLL will resume its normal operation and will make the lock signal high once it has regained lock on the input clock. R A A FT D R A FT D R A R A FT D R FT D R A F R A FT D FT 9.7.6.5 Selectable feedback divider clock D To allow a trade-off to be made between functionality and power consumption, the feedback divider can be connected to either the CCO clock by setting FBSEL to 0 or to the output clock by setting FBSEL to 1. If the post-divider is used to divide down the CCO clock the current consumption of the feedback divider can be reduced by making it run on the lower output clock instead of the CCO clock, but doing so will limit the relation between output and phase detector clock frequencies to integer values. D R A FT D R A 9.7.6.6 Direct output mode In normal operating mode (with DIRECT set to 0) the CCO clock is divided by 2, 4, 8 or 16 depending on the value of PSEL[1:0], automatically giving an output clock with a 50% duty cycle. If a higher output frequency is needed, the CCO clock can be sent directly to the output by setting DIRECT to 1. Since the CCO was designed to directly generate a clock with a 50% duty cycle, the output clock duty cycle will also be 50% in direct mode. 9.7.6.7 Divider ratio programming Pre-divider The pre-divider’s division ratio is controlled by the NSEL[1:0] input. The division ratio between PLL’s input clock and the phase detector clock is the decimal value on NSEL[1:0] plus one. Post-divider The division ratio of the post divider is controlled by the PSEL bits. The division ratio is two times the value of P selected by PSEL bits. This guarantees an output clock with a 50% duty cycle. Feedback divider The feedback divider’s division ratio is controlled by the MSEL bits. The division ratio between the PLL’s output clock and the input clock is the decimal value on MSEL bits plus one. Changing the divider values Changing the divider ratio while the PLL is running is not recommended. As there is no way to synchronize the change of the NSEL, MSEL, and PSEL values with the dividers, the risk exists that the counter will read in an undefined value, which could lead to unwanted spikes or drops in the frequency of the output clock. The recommended way of changing between divider settings is to power down the PLL, adjust the divider settings and then let the PLL start up again. 9.7.6.8 Frequency selection The PLL frequency equations use the following parameters (also see Figure 20): Integer mode In this mode the post divider is enabled and the feedback divider is set to run on the PLL output clock, giving the following frequency relations: All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 96 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 9: LPC18xx Clock Generation Unit (CGU) FT D R R A D R A (1) FT R A FT D R FT D R A R FT A A F FCLKIN FCLKOUT = M  ---------------------N D D R A FT D R A FT D FT D R A R A (2) FCLKIN FCCO = 2  P  FCLKOUT = 2  P  M  --------------------N Non-integer mode In this mode the post-divider is enabled and the feedback divider is set to run directly on the CCO clock, which gives the following frequency dividers: (3) M FCLKIN FCCO FCLKOUT = ---------------- = ------------  ---------------------2P N 2P (4) FCLKIN FCCO = M  --------------------N Direct mode In this mode, the post-divider is disabled and the CCO clock is sent directly to the output, leading to the following frequency equation: (5) FCLKIN FCLKOUT = FCCO = M  --------------------N Power-down mode In this mode, the internal current reference will be turned off, the oscillator and the phase-frequency detector will be stopped and the dividers will enter a reset state. While in Power-down mode, the lock output will be low, to indicate that the PLL is not in lock. When the Power-down mode is terminated, the PLL will resume its normal operation and will make the lock signal high once it has regained lock on the input clock. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 97 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 9: LPC18xx Clock Generation Unit (CGU) FT D R A D R A R A FT D R FT 9.8 Example CGU configurations D R 9.8.1 Programming the CGU for Deep-sleep and Power-down modes Before the LPC18xx enters Deep-sleep or Power-down mode, the IRC must be programmed as the clock source in the control registers for all output stages (OUTCLK_0 to OUTCLK_27). In addition, the PLLs must be in Power-down mode. When the LPC18xx wakes up from Deep-sleep or Power-down mode, the IRC is used as the clock sources for all output stages. Also see and . D 9.8.2 Programming the CGU for using I2S at peripheral clock rate of 30 MHz In this example the peripheral clock of the I2S interface is set to 30 MHz. The peripheral I2S clock is a branch of the BASE_APB1_CLK. Using a crystal of 12 MHz as clock source, a PLL1 multiplier of 10, and an integer divider of 4 provide the desired clock rate. R A FT D R R A F D R A FT A FT A FT R A D FT D R A XTAL_OSC 12MHz PLL1 x 10 120MHz DIVA / 4 30MHz BASE_APB1_CLK For this example, program the CGU as follows: 1. Enable the crystal oscillator in the XTAL_OSC_CTRL register (Table 50). 2. Wait for the crystal to stabilize. 3. Select the crystal oscillator as input to the PLL1 and set up the divider in the PLL1_CTRL register (see Table 61): – Set bits CLK_SEL in the PLL1_CTRL register to 0x6. – Set MSEL = 9. – Set NSEL = 0. – Set PSEL = 1. – Set FBSEL = 1. – Set BYPASS = 0, DIRECT = 0. 4. Wait for the PLL1 to lock. 5. Select the PLL1 as clock source of the integer divider A (IDIVA) in the IDIVA register and set AUTOBLOCK = 1 (see Table 61). 6. Select IDIVA as clock source of the base clock BASE_APB1_CLK and set AUTOBLOCK = 1 (see Table 62). 7. Ensure that the I2S branch clock CLK_APB1_I2S is enabled in the CCU (see Table 78). All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 98 of 1164 D R A FT D R A FT D R A FT D R A FT D R A FT UM10430 Rev. 00.13 — 20 July 2011 D D Chapter 10: LPC18xx Clock Control Unit (CCU) D R A FT D D R A FT D R A FT D R A R A FT D R A R A FT D R A FT D R A F R A FT D R R D User manual FT D R A FT FT A FT 10.1 How to read this chapter Remark: This chapter applies to parts LPC1850_30_20_10 rev “A”. Remark: The VADC is not available on parts LPC1850_30_10_10 rev “A”. D Ethernet, USB0, USB1, and LCD related clocks are not available on all packages. See Table 4. D R A FT D R A 10.2 Basic configuration The CCU1/2 are configured as follows: • See Table 75 for clocking and power control. • Do not reset the CCUs during normal operation. • The output clock for the EMC clock divider (Table 84) must be configured together with bit 16 in the CREG6 register (Table 37). Table 75. CCU1 CCU2 CCU clocking and power control Base clock BASE_M3_CLK BASE_M3_CLK Branch clock CLK_M3_BUS CLK_M3_BUS Maximum frequency 150 MHz 150 MHz 10.3 Features The CCUs switch the clocks to individual peripherals on or off. • Auto mode activates the AHB disable protocol before switching off the branch clock. • Wake-up mode allows to select clocks to run automatically after a wake-up event. 10.4 General description Each CGU base clock has several clock branches which can be turned on or off independently by the Clock Control Units CCU1 or CCU2. The branch clocks are distributed between CCU1 and CCU2. Table 76. CCU1 branch clocks Branch clock CLK_APB3_I2C1 CLK_APB3_DAC Description APB3 bus clock. Clock to the I2C1 register interface and I2C1 peripheral clock. Clock to the DAC register interface. Base clock BASE_APB3_CLK CLK_APB3_BUS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 99 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 10: LPC18xx Clock Control Unit (CCU) FT D R A D R A R A FT D R FT Table 76. CCU1 branch clocks Branch clock CLK_APB3_ADC0 CLK_APB3_ADC1 CLK_APB3_CAN0 Description D R R A R A A Base clock FT D R R A A FT D R A FT F Clock to the ADC0 register interface and ADC0 peripheral clock. Clock to the ADC1 register interface and ADC1 peripheral clock. Clock to the C_CAN0 register interface and C_CAN0 peripheral clock. APB1 bus clock. Clock to the PWM Motor control block and PWM Motocon peripheral clock. Clock to the I2C0 register interface and I2C0 peripheral clock. Clock to the I2S0 and I2S1 register interfaces and I2S0 and I2S1 peripheral clock. Clock to the C_CAN1 register interface and C_CAN1 peripheral clock. clock for the SPIFI SCKI clock input. M3 bus clock. Clock to the SPIFI register interface. Clock to the GPIO register interface Clock to the LCD register interface. Clock to the Ethernet register interface. Clock to the USB0 register interface. Clock to the External memory controller. Clock to the SD/MMC register interface. Clock to the DMA register interface. Clock to the Cortex-M3 core Clock to the AES register interface. Clock to the SCT register interface. Clock to the USB1 register interface. Clock to the EMC with clock divider. Clock to the VADC. Clock to the WWDT register interface. Clock to the USART0 register interface. Clock to the UART1 register interface. Clock to the SSP0 register interface. Clock to the timer0 register interface and timer0 peripheral clock. Clock to the timer1 register interface and timer1 peripheral clock. Clock to the System control unit register interface. Clock to the CREG register interface. Clock to the RI timer register interface and RI timer peripheral clock. FT D FT D D R A BASE_APB1_CLK CLK_APB1_BUS CLK_APB1_MOTOCON CLK_APB1_I2C0 CLK_APB1_I2S CLK_APB1_CAN1 BASE_SPIFI_CLK BASE_M3_CLK CLK_SPIFI CLK_M3_BUS CLK_M3_SPIFI CLK_M3_GPIO CLK_M3_LCD CLK_M3_ETHERNET CLK_M3_USB0 CLK_M3_EMC CLK_M3_SDIO CLK_M3_DMA CLK_M3_M3CORE CLK_M3_AES CLK_M3_SCT CLK_M3_USB1 CLK_M3_EMC_DIV CLK_M3_VADC CLK_M3_WWDT CLK_M3_UART0 CLK_M3_UART1 CLK_M3_SSP0 CLK_M3_TIMER0 CLK_M3_TIMER1 CLK_M3_SCU CLK_M3_CREG CLK_M3_RITIMER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 100 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 10: LPC18xx Clock Control Unit (CCU) FT D R A D R A R A FT D R FT Table 76. CCU1 branch clocks Branch clock CLK_M3_UART2 CLK_M3_UART3 CLK_M3_TIMER2 CLK_M3_TIMER3 Description D R R A R A A Base clock FT D F Clock to the UART2 register interface. Clock to the UART3 register interface. Clock to the timer2 register interface and timer2 peripheral clock. Clock to the timer3 register interface and timer3 peripheral clock. Clock to the QEI register interface and QEI peripheral clock. USB0 peripheral clock. USB1 peripheral clock. Reserved. VADC clock. FT D R A R A FT D R A FT D R A D FT BASE_M3_CLK CLK_M3_SSP1 CLK_M3_QEI BASE_USB0_CLK CLK_USB0 BASE_USB1_CLK CLK_USB1 BASE_ENET_CSR CLK_VADC _CLK Table 77. CCU2 branch clocks Branch clock CLK_APLL CLK_APB2_UART3 CLK_APB2_UART2 CLK_APB0_UART1 CLK_APB0_UART0 CLK_APB2_SSP1 CLK_APB0_SSP0 CLK_SDIO Base clock BASE_APLL_CLK BASE_UART3_CLK BASE_UART2_CLK BASE_UART1_CLK BASE_UART0_CLK BASE_SSP1_CLK BASE_SSP0_CLK BASE_SDIO_CLK Description Audio PLL clock USART3 peripheral clock. USART2 peripheral clock. UART1 peripheral clock. USART0 peripheral clock. SSP1 peripheral clock. SSP0 peripheral clock. SD/MMC peripheral clock. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 101 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 10: LPC18xx Clock Control Unit (CCU) FT D R A D R A R A FT D R FT 10.5 Register description Table 78. Name PM BASE_STAT CLK_APB3_BUS_CFG CLK_APB3_BUS_STAT CLK_APB3_I2C1_CFG CLK_APB3_I2C1_STAT CLK_APB3_DAC_CFG CLK_APB3_DAC_STAT CLK_APB3_ADC0_CFG CLK_APB3_ADC0_STAT CLK_APB3_ADC1_CFG CLK_APB3_ADC1_STAT CLK_APB3_CAN0_CFG CLK_APB3_CAN0_STAT CLK_APB1_BUS_CFG CLK_APB1_BUS_STAT CLK_APB1_MOTOCONPWM_CFG CLK_APB1_MOTOCONPWM_STAT CLK_APB1_I2C0_CFG CLK_APB1_I2C0_STAT CLK_APB1_I2S_CFG CLK_APB1_I2S_STAT CLK_APB1_CAN1_CFG CLK_APB1_CAN1_STAT CLK_SPIFI_CFG CLK_SPIFI_STAT CLK_M3_BUS_CFG CLK_M3_BUS_STAT CLK_M3_SPIFI_CFG CLK_M3_SPIFI_STAT D R R A FT D R A F D A FT Register overview: CCU1 (base address 0x4005 1000) Access R/W R R/W R R/W R R/W R R/W R R/W R R/W R R/W R R/W R R/W R R/W R R/W R R/W R R/W R R/W R Address Description offset 0x000 0x004 CCU1 power mode register CCU1 base clocks status register R Reset value 0x0000 0000 0x0000 0FFF 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 © NXP B.V. 2011. All rights reserved. R A FT D R A FT D A FT D R A 0x008 to Reserved 0x0FC 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C CLK_APB3_BUS clock configuration register CLK_APB3_BUS clock status register CLK_APB3_I2C1 configuration register CLK_APB3_I2C1v status register CLK_APB3_DAC configuration register CLK_APB3_DAC status register CLK_APB3_ADC0 configuration register CLK_APB3_ADC0 status register CLK_APB3_ADC1 configuration register CLK_APB3_ADC1 status register CLK_APB3_CAN0 configuration register CLK_APB3_CAN0 status register 0x130 to Reserved 0x1FC 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 CLK_APB1_BUS configuration register CLK_APB1_BUS status register CLK_APB1_MOTOCON configuration register CLK_APB1_MOTOCON status register CLK_APB1_I2C0 configuration register CLK_APB1_I2C0 status register CLK_APB1_I2S configuration register CLK_APB1_I2S status register CLK_APB3_CAN1 configuration register CLK_APB3_CAN1 status register 0x220 to Reserved 0x2FC 0x300 0x304 CLK_SPIFI configuration register CLK_SPIFI status register 0x308 to Reserved 0x3FC 0x400 0x404 0x408 0x40C CLK_M3_BUS configuration register CLK_M3_BUS status register CLK_M3_SPIFI configuration register CLK_M3_SPIFI status register All information provided in this document is subject to legal disclaimers. User manual Rev. 00.13 — 20 July 2011 102 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 10: LPC18xx Clock Control Unit (CCU) FT D R A D R A R A FT D R FT Table 78. Name Register overview: CCU1 (base address 0x4005 1000) Access R/W R R/W R R/W R R/W R R/W R R/W R R/W R R/W R R/W R R/W R R/W R R/W R R/W R R/W R R/W R R/W R R/W R R/W R R/W Address Description offset 0x410 0x414 0x418 0x41C 0x420 0x424 0x428 0x42C 0x430 0x434 0x438 0x43C 0x440 0x444 0x448 0x44C CLK_M3_GPIO configuration register CLK_M3_GPIO status register CLK_M3_LCD configuration register CLK_M3_LCD status register CLK_M3_ETHERNET status register CLK_M3_USB0 configuration register CLK_M3_USB0 status register CLK_M3_EMC configuration register CLK_M3_EMC status register CLK_M3_SDIO configuration register CLK_M3_SDIO status register CLK_M3_DMA configuration register CLK_M3_DMA status register CLK_M3_M3CORE configuration register CLK_M3_M3CORE status register D R Reset value R A FT D R R A F D R A A FT A CLK_M3_GPIO_CFG CLK_M3_GPIO_STAT CLK_M3_LCD_CFG CLK_M3_LCD_STAT CLK_M3_ETHERNET_CFG CLK_M3_ETHERNET_STAT CLK_M3_USB0_CFG CLK_M3_USB0_STAT CLK_M3_EMC_CFG CLK_M3_EMC_STAT CLK_M3_SDIO_CFG CLK_M3_SDIO_STAT CLK_M3_DMA_CFG CLK_M3_DMA_STAT CLK_M3_M3CORE_CFG CLK_M3_M3CORE_STAT CLK_M3_AES_CFG CLK_M3_AES_STAT CLK_M3_SCT_CFG CLK_M3_SCT_STAT CLK_M3_USB1_CFG CLK_M3_USB1_STAT CLK_M3_EMCDIV_CFG CLK_M3_EMCDIV_STAT CLK_M3_WWDT_CFG CLK_M3_WWDT_STAT CLK_M3_USART0_CFG CLK_M3_USART0_STAT CLK_M3_UART1_CFG CLK_M3_UART1_STAT CLK_M3_SSP0_CFG CLK_M3_SSP0_STAT CLK_M3_TIMER0_CFG CLK_M3_TIMER0_STAT CLK_M3_TIMER1_CFG CLK_M3_TIMER1_STAT CLK_M3_SCU_CFG 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 FT D R A FT D R A CLK_M3_ETHERNET configuration register 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 © NXP B.V. 2011. All rights reserved. FT D 0x450 to Reserved 0x45C 0x460 0x464 0x468 0x46C 0x470 0x474 0x478 0x47C CLK_M3_AES configuration register CLK_M3_AES status register CLK_M3_SCT configuration register CLK_M3_SCT status register CLK_M3_USB1 configuration register CLK_M3_USB1 status register CLK_M3_EMCDIV configuration register CLK_M3_EMCDIV status register 0x480 to Reserved 0x4FC 0x500 0x504 0x508 0x50C 0x510 0x514 0x518 0x51C 0x520 0x524 0x528 0x52C 0x530 CLK_M3_WWDT configuration register CLK_M3_WWDT status register CLK_M3_UART0 configuration register CLK_M3_UART0 status register CLK_M3_UART1 configuration register CLK_M3_UART1 status register CLK_M3_SSP0 configuration register CLK_M3_SSP0 status register CLK_M3_TIMER0 configuration register CLK_M3_TIMER0 status register CLK_M3_TIMER1 configuration register CLK_M3_TIMER1 status register CLK_M3_SCU configuration register All information provided in this document is subject to legal disclaimers. User manual Rev. 00.13 — 20 July 2011 103 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 10: LPC18xx Clock Control Unit (CCU) FT D R A D R A R A FT D R FT Table 78. Name Register overview: CCU1 (base address 0x4005 1000) Access R R/W R R/W R R/W R R/W R R/W R R/W R R/W R R/W R R/W R/W R/W R R/W R R/W R Address Description offset 0x534 0x538 0x53C CLK_M3_SCU status register CLK_M3_CREG configuration register CLK_M3_CREG status register D R Reset value R A FT D R R A F D R A A FT A CLK_M3_SCU_STAT CLK_M3_CREG_CFG CLK_M3_CREG_STAT CLK_M3_RITIMER_CFG CLK_M3_RITIMER_STAT CLK_M3_USART2_CFG CLK_M3_USART2_STAT CLK_M3_USART3_CFG CLK_M3_USART3_STAT CLK_M3_TIMER2_CFG CLK_M3_TIMER2_STAT CLK_M3_TIMER3_CFG CLK_M3_TIMER3_STAT CLK_M3_SSP1_CFG CLK_M3_SSP1_STAT CLK_M3_QEI_CFG CLK_M3_QEI_STAT CLK_USB0_CFG CLK_USB0_STAT CLK_USB1_CFG CLK_USB1_STAT CLK_VADC_CFG CLK_VADC_STAT Table 79. Name PM BASE_STAT CLK_APLL_CFG 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 FT D R A FT D R FT D 0x540 to Reserved 0x5FC 0x600 0x604 0x608 0x60C 0x610 0x614 0x618 0x61C 0x620 0x624 0x628 0x62C 0x630 0x634 CLK_M3_RITIMER configuration register CLK_M3_RITIMER status register CLK_M3_UART2 configuration register CLK_M3_UART2 status register CLK_M3_UART3 configuration register CLK_M3_UART3 status register CLK_M3_TIMER2 configuration register CLK_M3_TIMER2 status register CLK_M3_TIMER3 configuration register CLK_M3_TIMER3 status register CLK_M3_SSP1 configuration register CLK_M3_SSP1 status register CLK_M3_QEI configuration register CLK_M3_QEI status register A 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x638 to Reserved 0x6FC 0x700 to Reserved 0x7FC 0x800 0x804 CLK_USB0 configuration register CLK_USB0 status register 0x808 to Reserved 0x8FC 0x900 0x904 CLK_USB1 configuration register CLK_USB1 status register 0x908 to Reserved 0x9FC 0xA00 0xA04 CLK_VADC configuration register CLK_VADC status register Register overview: CCU2 (base address 0x4005 2000) Access R/W R R/W Address Description offset 0x000 0x004 0x008 to 0x0FC 0x100 CCU2 power mode register CCU2 base clocks status register Reserved CLK_APLL configuration register Reset value 0x0000 0000 0x0000 0FFF 0x0000 0001 © NXP B.V. 2011. All rights reserved. All information provided in this document is subject to legal disclaimers. User manual Rev. 00.13 — 20 July 2011 104 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 10: LPC18xx Clock Control Unit (CCU) FT D R A D R A R A FT D R FT Table 79. Name Register overview: CCU2 (base address 0x4005 2000) Access R R/W R R/W R R/W R R/W R R/W R R/W R R/W R Address Description offset 0x104 0x108 to 0x1FC 0x200 0x204 0x208 to 0x2FC 0x300 0x304 0x308 to 0x3FC 0x400 0x404 0x408 to 0x4FC 0x500 0x504 0x508 to 0x5FC 0x600 0x604 0x608 to 0x6FC 0x700 0x704 0x708 to 0x7FC 0x800 0x804 CLK_APLL status register Reserved CLK_APB2_UART3 configuration register CLK_APB2_UART3 status register Reserved CLK_APB2_UART2 configuration register CLK_APB2_UART2 status register Reserved CLK_APB0_UART1 configuration register CLK_APB0_UART1 status register Reserved CLK_APB0_UART0 configuration register CLK_APB0_UART0 status register Reserved CLK_APB2_SSP1 configuration register CLK_APB2_SSP1 status register Reserved CLK_APB0_SSP0 configuration register CLK_APB0_SSP0 status register Reserved CLK_SDIO configuration register CLK_SDIO status register D R Reset value R A FT D R R A F D R A A FT A CLK_APLL_STAT CLK_APB2_USART3_CFG CLK_APB2_USART3_STAT CLK_APB2_USART2_CFG CLK_APB2_USART2_STAT CLK_APB0_UART1_CFG CLK_APB0_UART1_STAT CLK_APB0_USART0_CFG CLK_APB0_USART0_STAT CLK_APB2_SSP1_CFG CLK_APB2_SSP1_STAT CLK_APB0_SSP0_CFG CLK_APB0_SSP0_STAT CLK_SDIO_CFG CLK_SDIO_STAT 0x0000 0001 0x0000 0001 FT D R A FT D R A 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 FT D 10.5.1 Power mode register This register contains a single bit, PD, that when set will disable all output clocks with Wake-up enabled (i.e. W = 1 in the CCU branch clock configuration registers, Section 10.5.3). Clocks disabled by writing to this register will be reactivated when a wake-up interrupt is detected or when a 0 is written into the PD bit. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 105 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 10: LPC18xx Clock Control Unit (CCU) FT D R A D R A R A FT D R FT D Table 80. Bit 0 CCU1/2 power mode register (CCU1_PM, address 0x4005 1000 and CCU2_PM, address 0x4005 2000) bit description R R R A A A FT D F FT D Symbol PD Value Description Initiate power-down mode Reset value 0 Access R/W R R A A FT D R A FT D 0 1 31:1 - Normal operation. Clocks with wake-up mode enabled (W = 1) are disabled. Reserved. - FT D R A 10.5.2 Base clock status register Each bit in this register indicates if the specified base clock can be safely switched off. A logic zero indicates that all branch clocks generated from this base clock are disabled. Hence, the base clock can also be switched off. A logic one value indicates that there is still at least one branch clock running. Remark: The base clock must be reactivated before writing to the configuration register of the branch clock. Table 81. Bit 0 CCU1 base clock status register (CCU1_BASE_STAT, address 0x4005 1004) bit description Description Base clock indicator for BASE_APB3_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running. 1 BASE_APB1_ CLK_IND BASE_SPIFI_ CLK_IND BASE_M3_ CLK_IND BASE_USB0_ CLK_IND BASE_USB1_ CLK_IND Base clock indicator for BASE_APB1_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running. 2 Base clock indicator for BASE_SPIFI_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running. 3 Base clock indicator for BASE_M3_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running. 6:4 7 Reserved Base clock indicator for BASE_USB0_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running. 8 Base clock indicator for BASE_USB1_CLK 0 = All branch clocks switched off. 1 = at least one branch clock running. 31:9 Reserved 1 R 1 R 1 R 1 R 1 R Reset value 1 Access R Symbol BASE_APB3_ CLK_IND All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 106 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 10: LPC18xx Clock Control Unit (CCU) FT D R A D R A R A FT D R FT D Table 82. Bit 0 1 CCU2 base clock status register (CCU2_BASE_STAT, address 0x4005 2004) bit description R R R A A A FT D F FT D Symbol BASE_UART3_ CLK BASE_UART2_ CLK BASE_UART1_ CLK BASE_UART0_ CLK BASE_SSP1_ CLK BASE_SSP0_ CLK - Description Reserved. Base clock indicator for BASE_UART3_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running. Base clock indicator for BASE_UART2_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running. Base clock indicator for BASE_UART1_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running. Base clock indicator for BASE_UART0_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running. Base clock indicator for BASE_SSP1_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running. Base clock indicator for BASE_SSP0_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running. Reserved. Reserved. Reset value 1 Access R R A A FT R FT D R A FT D R A D 2 1 R 3 1 R 4 1 R 5 1 R 6 1 R 7 31:8 - - 10.5.3 CCU1/2 branch clock configuration registers Each generated output clock from the CCU has a configuration register. They all follow the format as described in Table 83 and Table 85. On the LPC18xx, all branch clocks are in Run mode after reset. Auto and wake-up features are disabled. The clock can be configured to run in the following modes described by the bits RUN, AUTO, and WAKEUP in the CLK_XXX_CFG registers: RUN — The WAKEUP, PD, and AUTO control bits determine the activation of the branch clock. If register bit AUTO is set the AHB disable protocol must complete before the clock is switched off. The PD bit is set in Table 80. AUTO — Enable auto (AHB disable mechanism). The PMU initiates the AHB disable protocol before switching the clock off. This protocol ensures that all AHB transactions have been completed before turning the clock off. WAKEUP — The branch clock is wake-up enabled when the PD bit in the Power Mode register (seeTable 80) is set and clocks which are wake-up enabled are switched off. These clocks will be switched on if a wake-up event is detected or if the PD bit is cleared. If register bit AUTO is set, the AHB disable protocol must complete before the clock is switched off. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 107 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 10: LPC18xx Clock Control Unit (CCU) FT D R R A Remark: In order to safely disable any of the branch clocks, use two separate writes to the CLK_XXX_CFG register: first set the AUTO bit, and then on the next write, disable the clock by setting the RUN bit to zero. R A A FT D R A FT Table 83. Bit 0 CCU1 branch clock configuration register (CLK_XXX_CFG, addresses 0x4005 1100, 0x4005 1104,..., 0x4005 1A00) bit description Symbol RUN 0 1 1 AUTO 0 1 2 WAKEUP 0 1 31:3 Value Description Run enable Clock is disabled. Clock is enabled. Auto (AHB disable mechanism) enable Auto is disabled. Auto is enabled. Wake-up mechanism enable Wake-up is disabled. Wake-up is enabled. Reserved 0 R/W 0 R/W Reset value 1 Remark: The output clock for the EMC clock divider (Table 84) must be configured together with bit 16 in the CREG6 register (Table 37). Table 84. Bit 0 CCU1 branch clock configuration register (CLK_EMCDIV_CFG, addresses 0x4005 1478) bit description Symbol RUN 0 1 1 AUTO 0 1 2 WAKEUP 0 1 3 4 7:5 DIV 0x0 0x1 0x2 0x3 0x4 31:8 Value Description Run enable Clock is disabled. Clock is enabled. Auto (AHB disable mechanism) enable Auto is disabled. Auto is enabled. Wake-up mechanism enable Wake-up is disabled. Wake-up is enabled. Reserved Reserved Clock divider value No division (divide by 1). Divide by 2. Reserved Reserved Reserved Reserved 0 R/W 0 R/W 0 R/W Reset value 1 Access R/W D R A R A FT D R FT D R A F R A FT D FT D R A D Access R/W FT R A D All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 108 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 10: LPC18xx Clock Control Unit (CCU) FT D R A D R A R A FT D R FT D Table 85. Bit 0 CCU2 branch clock configuration register (CLK_XXX_CFG, addresses 0x4005 2100, 0x4005 2200,..., 0x4005 2800) bit description R R R A A A FT D F FT D Symbol RUN Value Description Run enable Reset value 1 Access R/W R R A A FT D R A FT D 0 1 1 AUTO 0 1 2 WAKEUP 0 1 31:3 - Clock is disabled. Clock is enabled. Auto (AHB disable mechanism) enable Auto is disabled. Auto is enabled. Wake-up mechanism enable Wake-up is disabled. Wake-up is enabled. Reserved 0 R/W 0 R/W FT D R A 10.5.4 CCU1/2 branch clock status registers Like the Configuration Register, each generated output clock from the CCU has a status register. When the configuration register of an output clock is written into, the value of the actual hardware signals may not be updated immediately because of the Auto or Wake-up mechanism. The Status Register shows the current value of these signals. All output clock Status Registers follow the format as described in Table 86 and Table 87. Table 86. Bit 0 CCU1 branch clock status register (CLK_XXX_STAT, addresses 0x4005 1104, 0x4005 110C,..., 0x4005 1A04) bit description Symbol RUN Description Run enable status 0 = clock is disabled. 1 = clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. 2 WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. 31:3 Reserved 0 R 0 R Reset value 1 Access R All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 109 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 10: LPC18xx Clock Control Unit (CCU) FT D R A D R A R A FT D R FT D Table 87. Bit 0 CCU2 branch clock status register (CLK_XXX_STAT, addresses 0x4005 2104, 0x4005 2204,..., 0x4005 2804) bit description R R R A A A FT D F FT D Symbol RUN Description Run enable status 0 = clock is disabled 1 = clock is enabled Reset value 1 Access R R R A A FT D R A FT D FT D R A 1 AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled 1 = Auto is enabled 0 R 2 WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled 1 = Wake-up is enabled 0 R 31:3 - Reserved - - 10.6 Functional description All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 110 of 1164 D R A FT D R A FT D R A FT D R A FT D R A FT UM10430 Rev. 00.13 — 20 July 2011 D D Chapter 11: LPC18xx Reset Generation Unit (RGU) D R A FT D D R A FT D R A FT D R A FT D R R A FT D R A FT D A FT R A R A FT D R A FT D R A F R A FT D FT R User manual 11.1 How to read this chapter The C_CAN1 reset (#54) is available on parts LPC1850_30_20_10 Rev ‘A’ only. D D R A FT D R A 11.2 Basic configuration Table 88. RGU clocking and power control Base clock RGU RGU delay clocks BASE_M3_CLK BASE_SAFE_CLK Branch clock CLK_M3_BUS Maximum frequency 150 MHz 12 MHz The RGU is reset by a BUS_RST (reset #8). Remark: Support for the ARM Cortex-M3 SYSRESETREQ is not implemented on the LPC18xx. 11.3 General description The RGU allows generation of independent reset signals for various blocks and peripherals on the LPC18xx. Each reset signal is asserted by a reset generator with one output (the reset signal) and one or more inputs, which link the reset generators together and create a reset hierarchy. RGU RESET BOD reset WWDT reset CORE_RST GENERATOR WWDT CREG; RTC domain peripherals; PMC Bus bridges, memory controllers PERIPH_RST GENERATOR 24 APB peripherals, GPIO Cortex-M3 core MASTER_RST GENERATOR 7 AHB peripherals (USB0/1, LCD, Ethernet, GPDMA, SDIO, AES) Fig 21. RGU Block diagram All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 111 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 11: LPC18xx Reset Generation Unit (RGU) FT D R A D R A R A FT D R FT D Table 89. Reset output configuration Reset output # 0 Reset source R R A FT R A F A FT Reset output generator CORE_RST Parts of the device reset when activated D external reset, BOD reset, WWDT time-out reset CORE_RST PERIPH_RST CORE_RST CORE_RST Entire chip including peripherals in the battery-powered domain: CGU, power management controller, general purpose registers, alarm timer, parts of the CREG block, and RTC. All peripherals with reset source PERIPH_RST and MASTER_RST All peripherals with reset source MASTER_RST WWDT. No software reset. D R A FT D R A FT D A FT D R A R PERIPH_RST MASTER_RST Reserved WWDT_RST CREG_RST 1 2 3 4 5 Configuration register block, Event router, backup registers, RTC, alarm timer. No software reset. Buses; RGU, CCU, and CGU registers; memory controllers; bus bridges. Do not use during normal operation. System control unit Cortex-M3 system reset LCD controller reset USB0 reset USB1 reset DMA reset SDIO reset External memory controller reset Ethernet reset AES reset GPIO reset Timer0 reset Timer1 reset Timer2 reset Timer3 reset Repetitive Interrupt timer reset State Configurable Timer reset Motor control PWM reset QEI reset © NXP B.V. 2011. All rights reserved. Reserved BUS_RST 6-7 8 PERIPH_RST SCU_RST Reserved M3_RST Reserved Reserved LCD_RST USB0_RST USB1_RST DMA_RST SDIO_RST EMC_RST ETHERNET_RST AES_RST Reserved GPIO_RST Reserved TIMER0_RST TIMER1_RST TIMER2_RST TIMER3_RST RITIMER_RST SCT_RST QEI_RST 9 10 - 12 13 14 15 16 17 18 19 20 21 22 23 24 - 27 28 29 - 31 32 33 34 35 36 37 39 PERIPH_RST MASTER_RST MASTER_RST MASTER_RST MASTER_RST MASTER_RST MASTER_RST MASTER_RST MASTER_RST MASTER_RST PERIPH_RST PERIPH_RST PERIPH_RST PERIPH_RST PERIPH_RST PERIPH_RST PERIPH_RST PERIPH_RST PERIPH_RST MOTOCONPWM_RST 38 All information provided in this document is subject to legal disclaimers. User manual Rev. 00.13 — 20 July 2011 112 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 11: LPC18xx Reset Generation Unit (RGU) FT D R A D R A R A FT D R FT Table 89. Reset output configuration …continued Reset output # 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 59 - 63 Reset source D R R A R A A Reset output generator ADC0_RST ADC1_RST DAC_RST Reserved UART0_RST UART1_RST UART2_RST UART3_RST I2C0_RST I2C1_RST SSP0_RST SSP1_RST I2S_RST SPIFI_RST CAN1_RST CAN0_RST Reserved Reserved Reserved Parts of the device reset when activated FT D R R A FT A F FT D FT PERIPH_RST PERIPH_RST PERIPH_RST PERIPH_RST PERIPH_RST PERIPH_RST PERIPH_RST PERIPH_RST PERIPH_RST PERIPH_RST PERIPH_RST PERIPH_RST PERIPH_RST PERIPH_RST PERIPH_RST - ADC0 reset (ADC register interface and analog block) ADC1 reset (ADC register interface and analog block) DAC reset (DAC register interface and analog block) USART0 reset UART1 reset USART2 reset USART3 reset I2C0 reset I2C1 reset SSP0 reset SSP1 reset I2S0 and I2S1 reset SPIFI reset C_CAN1 reset C_CAN0 reset - D D R A FT D R A The RGU also monitors the reset cause for each reset output. The reset cause can be retrieved with two levels of granularity. The first level is monitored by the RESET_STATUS0 to 3 registers and indicates one of the following reset causes (see Table 94 to Table 97): • No reset has taken place. • Reset generated by software (using the registers RESET_CTRL0 and RESET_CTRL1). • Reset generated by any of the reset sources. The second level of granularity is monitored by one individual register for each reset output (RESET_EXT_STATUSn) in which the detailed reset cause is indicated, that is whether or not any of the possible inputs to each reset generator are activated. The following lists all inputs, but note that only a subset of inputs are connected to each reset generator: • • • • External reset (from external reset pin) CORE_RST output PERIPH_RST output MASTER_RST output All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 113 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 11: LPC18xx Reset Generation Unit (RGU) FT D R A D R A R A FT D R FT • BOD reset signal • WWDT time-out signal 11.3.1 Reset hierarchy The hierarchy is as follows (see Table 90): D R 1. External reset, BOD reset signal, WWDT time-out, and reset signal from the PMU 2. CORE_RST (inputs are the external reset pin, BOD reset, and the WWDT time-out reset); resets the whole chip including the WWDT and the configuration register block CREG. 3. PERIPH_RST (input is the CORE_RST); resets all APB peripherals and the ARM core, but not the WWDT and the CREG block. 4. MASTER_RST (input is the PERIPH_RST); resets the ARM Cortex-M3 core and the AHB peripherals (DMA, USB0/1, LCD, SDIO, EMC, AES). Table 90. Reset priority WWDT CREG/ RTC/ Event router yes yes no no ABP Cortex- AHB RGU EMC GPIO SRAM peripherals M3 Core peripherals controllers R A FT D R R A F D R A FT A FT A FT D R A D FT D R A Priority Reset input 1 2 3 4 External reset pin, yes BOD, WWDT CORE_RST PERIPH_RST MASTER_RST yes no no yes yes yes no yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes TRSTn TRSTn_loc ext_rst_an(0) bod_rst_an(4) core_rst_out_n wwdt_rst_an(5) pmc_rst_an delay=1 core_rst_an(1) delay=1 no sw delay=1 no sw delay=3 wwdt_rst_out_n creg_rst_out_n periph_rst_out_n periph_rst_an(2) spi,etc .... delay=0 master_rst_out_n delay=3 master_rst_an(3) m3,usb,lcd,etc... delay=0 Fig 22. RGU Reset structure All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 114 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 11: LPC18xx Reset Generation Unit (RGU) FT D R A D R A R A FT D R FT 11.4 Register overview Table 91. Name RESET_CTRL0 RESET_CTRL1 RESET_STATUS0 RESET_STATUS1 RESET_STATUS2 RESET_STATUS3 Register overview: RGU (base address: 0x4005 3000) Access W W R/W R/W R/W R/W Address Description offset 0x100 0x104 0x110 0x114 0x118 0x11C 0x150 0x154 0x400 0x404 0x408 0x40C 0x410 0x414 0x418 0x41C 0x420 0x424 0x428 0x42C 0x430 0x434 0x438 0x43C 0x440 0x444 0x448 0x44C Reset control register 0 Reset control register 1 Reset status register 0 Reset status register 1 Reset status register 2 Reset status register 3 Reset active status register 0 Reset active status register 1 Reset external status register 0 for CORE_RST Reset external status register 1 for PERIPH_RST Reset external status register 2 for MASTER_RST Reserved Reset external status register 4 for WWDT_RST Reset external status register 5 for CREG_RST Reserved Reserved Reset external status register 8 for BUS_RST Reset external status register 9 for SCU_RST Reserved Reserved Reserved Reset external status register 13 for M3_RST Reserved Reserved Reset external status register 16 for LCD_RST Reset external status register 17 for USB0_RST Reset external status register 18 for USB1_RST Reset external status register 19 for DMA_RST Reset value - D R Reference see Table 92 see Table 93 0x5555 0050 see Table 94 0x5555 5555 see Table 95 0x5555 5555 see Table 96 0x5555 5555 see Table 97 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 see Table 103 see Table 104 see Table 105 see Table 105 see Table 106 see Table 106 see Table 106 see Table 106 see Table 106 see Table 98 see Table 99 see Table 100 see Table 101 see Table 102 R A FT D R R A F D R A FT A FT A FT D R A D FT D R A RESET_ACTIVE_STATUS0 R RESET_ACTIVE_STATUS1 R RESET_EXT_STAT0 RESET_EXT_STAT1 RESET_EXT_STAT2 RESET_EXT_STAT3 RESET_EXT_STAT4 RESET_EXT_STAT5 RESET_EXT_STAT6 RESET_EXT_STAT7 RESET_EXT_STAT8 RESET_EXT_STAT9 RESET_EXT_STAT10 RESET_EXT_STAT11 RESET_EXT_STAT12 RESET_EXT_STAT13 RESET_EXT_STAT14 RESET_EXT_STAT15 RESET_EXT_STAT16 RESET_EXT_STAT17 RESET_EXT_STAT18 RESET_EXT_STAT19 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 115 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 11: LPC18xx Reset Generation Unit (RGU) FT D R A D R A R A FT D R FT Table 91. Name Register overview: RGU (base address: 0x4005 3000) …continued Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Address Description offset 0x450 0x454 0x458 0x45C 0x460 0x464 0x468 0x46C 0x470 0x474 0x478 0x47C 0x480 0x484 0x488 0x48C 0x490 0x494 0x498 0x49C 0x4A0 0x4A4 0x4A8 0x4AC 0x4B0 0x4B4 Reset external status register 20 for SDIO_RST Reset external status register 21 for EMC_RST Reset external status register 22 for ETHERNET_RST Reset external status register 23 for AES_RST Reserved Reserved Reserved Reserved Reset external status register 28 for GPIO_RST Reserved Reserved Reserved Reset external status register 32 for TIMER0_RST Reset external status register 33 for TIMER1_RST Reset external status register 34 for TIMER2_RST Reset external status register 35 for TIMER3_RST Reset external status register 36 for RITIMER_RST Reset external status register 37 for SCT_RST Reset external status register 38 for MOTOCONPWM_RST Reset external status register 39 for QEI_RST Reset external status register 40 for ADC0_RST Reset external status register 41 for ADC1_RST Reset external status register 42 for DAC_RST Reserved Reset external status register 44 for UART0_RST Reset external status register 45 for UART1_RST Reset value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 D R Reference R A FT D R R A F D R A A FT A RESET_EXT_STAT20 RESET_EXT_STAT21 RESET_EXT_STAT22 RESET_EXT_STAT23 RESET_EXT_STAT24 RESET_EXT_STAT25 RESET_EXT_STAT26 RESET_EXT_STAT27 RESET_EXT_STAT28 RESET_EXT_STAT29 RESET_EXT_STAT30 RESET_EXT_STAT31 RESET_EXT_STAT32 RESET_EXT_STAT33 RESET_EXT_STAT34 RESET_EXT_STAT35 RESET_EXT_STAT36 RESET_EXT_STAT37 RESET_EXT_STAT38 RESET_EXT_STAT39 RESET_EXT_STAT40 RESET_EXT_STAT41 RESET_EXT_STAT42 RESET_EXT_STAT43 RESET_EXT_STAT44 RESET_EXT_STAT45 see Table 106 see Table 106 see Table 106 see Table 106 see Table 105 see Table 105 see Table 105 see Table 105 see Table 105 see Table 105 see Table 105 see Table 105 see Table 105 see Table 105 see Table 105 see Table 105 see Table 105 see Table 105 FT D R A FT D R A FT D All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 116 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 11: LPC18xx Reset Generation Unit (RGU) FT D R A D R A R A FT D R FT Table 91. Name Register overview: RGU (base address: 0x4005 3000) …continued Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Address Description offset 0x4B8 0x4BC 0x4C0 0x4C4 0x4C8 0x4CC 0x4D0 0x4D4 0x4D8 0x4DC 0x4E0 0x4E4 0x4E8 0x4EC 0x4F0 0x4F4 0x4F8 0x4FC Reset external status register 46 for UART2_RST Reset external status register 47 for UART3_RST Reset external status register 48 for I2C0_RST Reset external status register 49 for I2C1_RST Reset external status register 50 for SSP0_RST Reset external status register 51 for SSP1_RST Reset external status register 52 for I2S_RST Reset external status register 53 for SPIFI_RST Reset external status register 54 for CAN1_RST Reset external status register 55 for CAN0_RST Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reset value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 - D R Reference R A FT D R R A F D R A A FT A RESET_EXT_STAT46 RESET_EXT_STAT47 RESET_EXT_STAT48 RESET_EXT_STAT49 RESET_EXT_STAT50 RESET_EXT_STAT51 RESET_EXT_STAT52 RESET_EXT_STAT53 RESET_EXT_STAT54 RESET_EXT_STAT55 RESET_EXT_STAT56 RESET_EXT_STAT57 RESET_EXT_STAT58 RESET_EXT_STAT59 RESET_EXT_STAT60 RESET_EXT_STAT61 RESET_EXT_STAT62 RESET_EXT_STAT63 see Table 105 see Table 105 see Table 105 see Table 105 see Table 105 see Table 105 see Table 105 see Table 105 see Table 105 see Table 105 - FT D R A FT D R A FT D 11.4.1 RGU reset control register The RGU reset control register allows software to activate and clear individual reset outputs. Each bit corresponds to an individual reset output, and writing a one activates that output. The reset output is automatically de-activated after a fixed delay period. If the reset output has a manual release, it stays activated once pulled low until a 0 is written to the appropriate bit in this register. This applies whether the reset activation came from the Reset Control Register or any other source All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 117 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 11: LPC18xx Reset Generation Unit (RGU) FT D R A D R A R A FT D R FT D Table 92. Bit 0 1 2 3 4 5 6 7 8 9 10 11 11 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Reset control register 0 (RESET_CTRL0, address 0x4005 3100) bit description Symbol CORE_RST PERIPH_RST MASTER_RST WWDT_RST CREG_RST BUS_RST SCU_RST PINMUX_RST M3_RST LCD_RST USB0_RST USB1_RST DMA_RST SDIO_RST EMC_RST ETHERNET_RST AES_RST Description Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. Writing a one activates the reset. This bit is automatically cleared to 0 after three clock cycles. Writing a one activates the reset. This bit is automatically cleared to 0 after three clock cycles. Reserved Writing a one to this bit has no effect. Writing a one to this bit has no effect. Reserved Reserved Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. Do not use during normal operation Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. Reserved Reserved Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. Reserved Reserved Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. Reserved Reserved Reserved Reserved R Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - R A FT D W W W W W W W W W W W W W W W - R A F D R A Access A FT R A R A FT D FT D FT D R A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 118 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 11: LPC18xx Reset Generation Unit (RGU) FT D R A D R A R A FT D R FT Table 92. Bit 28 29 30 31 Table 93. Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Reset control register 0 (RESET_CTRL0, address 0x4005 3100) bit description …continued Symbol GPIO_RST Description Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. Reserved Reserved Reserved Reset control register 1 (RESET_CTRL1, address 0x4005 3104) bit description Symbol TIMER0_RST TIMER1_RST TIMER2_RST TIMER3_RST OSTIMER_RST SCT_RST MOTOCONPWM_RST QEI_RST ADC0_RST ADC1_RST DAC_RST UART0_RST UART1_RST UART2_RST UART3_RST I2C0_RST I2C1_RST Description Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. Reserved Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. D R Reset value 0 - Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R A FT D W W W W W W W W W W W W W W W W W W R A F D R A Access A FT R A FT Access R A FT D FT D D R A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 119 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 11: LPC18xx Reset Generation Unit (RGU) FT D R A D R A R A FT D R FT Table 93. Bit 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Reset control register 1 (RESET_CTRL1, address 0x4005 3104) bit description …continued D R R A FT R A F A FT Symbol SSP0_RST SSP1_RST I2S_RST SPIFI_RST CAN1_RST CAN0_RST - Description Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reset value 0 0 0 0 0 0 - Access D D - R W W W W W W R A A FT D R A FT D FT D R A 11.4.2 RGU reset status register The reset status register shows which source (if any) caused the last reset activation per individual reset output of the RGU. When one (or more) inputs of the RGU caused the Reset Output to go active (indicated by value 01), the corresponding RESET_EXT_STATUS register can be read, see Section 11.4.4. The RESET_STATUS registers are cleared by writing 0 to each of the status bits. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 120 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 11: LPC18xx Reset Generation Unit (RGU) FT D R A D R A R A FT D R FT D Table 94. Bit 1:0 Reset status register 0 (RESET_STATUS0, address 0x4005 3110) bit description Description Status of the CORE_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register R R A FT R A F A FT Symbol CORE_RST Reset value 00 Access D D R/W R R A FT D R A FT D A FT D R A 3:2 PERIPH_RST Status of the PERIPH_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register 00 R/W 5:4 MASTER_RST Status of the MASTER_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register 01 R/W 7:6 9:8 WWDT_RST Reserved Status of the WWDT_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reserved 01 01 R/W 11:10 CREG_RST Status of the CREG_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reserved 01 R/W 13:12 15:14 17:16 BUS_RST Reserved Reserved Status of the BUS_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register 01 01 01 R/W 19:18 SCU_RST Status of the SCU_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register 01 R/W 21:20 23:22 25:24 - Reserved Reserved Reserved 01 01 01 - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 121 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 11: LPC18xx Reset Generation Unit (RGU) FT D R A D R A R A FT D R FT Table 94. Bit 27:26 Reset status register 0 (RESET_STATUS0, address 0x4005 3110) bit description Description Status of the M3_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register D R R A R A A Symbol M3_RST Reset value 01 Access FT D R A R A FT F FT D R/W R A FT D FT D D R A 29:28 31:30 - Reserved Reserved Reset status register 1 (RESET_STATUS1, address 0x4005 3114) bit description Symbol LCD_RST Description Status of the LCD_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register 01 01 - Table 95. Bit 1:0 Reset value 01 Access R/W 3:2 USB0_RST Status of the USB0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register 01 R/W 5:4 USB1_RST Status of the USB1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register 01 R/W 7:6 DMA_RST Status of the DMA_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register 01 R/W 9:8 SDIO_RST Status of the SDIO_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register 01 R/W 11:10 EMC_RST Status of the EMC_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register 01 R/W All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 122 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 11: LPC18xx Reset Generation Unit (RGU) FT D R A D R A R A FT D R FT Table 95. Bit 13:12 Reset status register 1 (RESET_STATUS1, address 0x4005 3114) bit description …continued D R R A FT R A F A FT Symbol ETHERNET_RST Description Status of the ETHERNET_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register Reset value 01 Access R/W D D R R A A FT D R A FT D FT D R A 15:14 AES_RST Status of the AES_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register 01 R/W 17:16 19:18 21:20 23:22 25:24 GPIO_RST Reserved Reserved Reserved Reserved Status of the GPIO_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register 01 01 01 01 01 R/W 27:26 29:28 31:30 Table 96. Bit 1:0 - Reserved Reserved Reserved Reset status register 2 (RESET_STATUS2, address 0x4005 3118) bit description Description Status of the TIMER0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register 01 01 01 - Symbol TIMER0_RST Reset value 01 Access R/W 3:2 TIMER1_RST Status of the TIMER1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register 01 R/W 5:4 TIMER2_RST Status of the TIMER2_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register 01 R/W All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 123 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 11: LPC18xx Reset Generation Unit (RGU) FT D R A D R A R A FT D R FT Table 96. Bit 7:6 Reset status register 2 (RESET_STATUS2, address 0x4005 3118) bit description …continued …continued D R R A FT R A F A FT Symbol TIMER3_RST Description Status of the TIMER3_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register Reset value 01 Access R/W D D R R A A FT D R A FT D FT D R A 9:8 RITIMER_RST Status of the OSTIMER_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register 01 R/W 11:10 SCT_RST Status of the SCT_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register 01 R/W 13:12 MOTOCONPWM_ RST Status of the MOTOCONPWM_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register 01 R/W 15:14 QEI_RST Status of the QEI_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register 01 R/W 17:16 ADC0_RST Status of the ADC0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register 01 R/W 19:18 ADC1_RST Status of the ADC1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register 01 R/W 21:20 DAC_RST Status of the DAC_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register 01 R/W 23:22 - Reserved 01 R/W All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 124 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 11: LPC18xx Reset Generation Unit (RGU) FT D R A D R A R A FT D R FT Table 96. Bit Reset status register 2 (RESET_STATUS2, address 0x4005 3118) bit description …continued …continued D R R A FT R A F A FT Symbol Description Status of the UART0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register Reset value 01 Access R/W D D R R A A FT FT 25:24 UART0_RST D D R A FT D R A 27:26 UART1_RST Status of the UART1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register 01 R/W 29:28 UART2_RST Status of the UART2_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register 01 R/W 31:30 UART3_RST Status of the UART3_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register 01 R/W Table 97. Bit 1:0 Reset status register 3 (RESET_STATUS3, address 0x4005 311C) bit description Description Status of the I2C0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register Reset value 01 Access R/W Symbol I2C0_RST 3:2 I2C1_RST Status of the I2C1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register 01 R/W 5:4 SSP0_RST Status of the SSP0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register 01 R/W All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 125 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 11: LPC18xx Reset Generation Unit (RGU) FT D R A D R A R A FT D R FT Table 97. Bit 7:6 Reset status register 3 (RESET_STATUS3, address 0x4005 311C) bit description …continued D R R A FT R A F A FT Symbol SSP1_RST Description Status of the SSP1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register Reset value 01 Access R/W D D R R A A FT D R A FT D FT D R A 9:8 I2S_RST Status of the I2S_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register 01 R/W 11:10 SPIFI_RST Status of the SPIFI_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register 01 R/W 13:12 CAN1_RST Status of the CAN1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register 01 R/W 15:14 CAN0_RST Status of the CAN0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register 01 R/W 17:16 19:18 21:20 23:22 25:24 27:26 29:28 31:30 - Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 01 01 01 01 01 01 01 01 - 11.4.3 RGU reset active status register The reset active status register shows the current value of the reset outputs of the RGU. Note that the resets are active LOW. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 126 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 11: LPC18xx Reset Generation Unit (RGU) FT D R A D R A R A FT D R FT D Table 98. Bit 0 Reset active status register 0 (RESET_ACTIVE_STATUS0, address 0x4005 3150) bit description R R R A A A FT D F FT D Symbol CORE_RST Description Current status of the CORE_RST 0 = Reset asserted 1 = No reset Reset value 0 Access R R R A A FT D R A FT D FT D R A 1 PERIPH_RST Current status of the PERIPH_RST 0 = Reset asserted 1 = No reset 0 R 2 MASTER_RST Current status of the MASTER_RST 0 = Reset asserted 1 = No reset 0 R 3 4 WWDT_RST Reserved Current status of the WWDT_RS 0 = Reset asserted 1 = No reset 0 0 R 5 CREG_RST Current status of the CREG_RST 0 = Reset asserted 1 = No reset 0 R 6 7 8 BUS_RST Reserved Reserved Current status of the BUS_RST 0 = Reset asserted 1 = No reset 0 0 0 R 9 SCU_RST Current status of the SCU_RST 0 = Reset asserted 1 = No reset 0 R 10 PINMUX_RST Current status of the PINMUX_RST 0 = Reset asserted 1 = No reset 0 R 11 12 13 M3_RST Reserved Reserved Current status of the M3_RST 0 = Reset asserted 1 = No reset 0 0 0 R 14 15 16 LCD_RST Reserved Reserved Current status of the LCD_RST 0 = Reset asserted 1 = No reset 0 0 0 R 17 USB0_RST Current status of the USB0_RST 0 = Reset asserted 1 = No reset 0 R All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 127 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 11: LPC18xx Reset Generation Unit (RGU) FT D R A D R A R A FT D R FT Table 98. Bit 18 Reset active status register 0 (RESET_ACTIVE_STATUS0, address 0x4005 3150) bit description …continued D R R R A A A FT F FT Symbol USB1_RST Description Current status of the USB1_RST 0 = Reset asserted 1 = No reset Reset value 0 Access D D R R R A A FT D R A FT D FT D R A 19 DMA_RST Current status of the DMA_RST 0 = Reset asserted 1 = No reset 0 R 20 SDIO_RST Current status of the SDIO_RST 0 = Reset asserted 1 = No reset 0 R 21 EMC_RST Current status of the EMC_RST 0 = Reset asserted 1 = No reset 0 R 22 ETHERNET_RST Current status of the ETHERNET_RST 0 = Reset asserted 1 = No reset 0 R 23 AES_RST Current status of the AES_RST 0 = Reset asserted 1 = No reset 0 R 24 25 26 27 28 GPIO_RST Reserved Reserved Reserved Reserved Current status of the GPIO_RST 0 = Reset asserted 1 = No reset 0 R 29 30 31 - Reserved Reserved Reserved - - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 128 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 11: LPC18xx Reset Generation Unit (RGU) FT D R A D R A R A FT D R FT D Table 99. Bit 0 Reset active status register 1 (RESET_ACTIVE_STATUS1, address 0x4005 3154) bit description R R R A A A FT D F FT D Symbol TIMER0_RST Description Current status of the TIMER0_RST 0 = Reset asserted 1 = No reset Reset value 0 Access R R R A A FT D R A FT D FT D R A 1 TIMER1_RST Current status of the TIMER1_RST 0 = Reset asserted 1 = No reset 0 R 2 TIMER2_RST Current status of the TIMER2_RST 0 = Reset asserted 1 = No reset 0 R 3 TIMER3_RST Current status of the TIMER3_RST 0 = Reset asserted 1 = No reset 0 R 4 RITIMER_RST Current status of the OSTIMER_RST 0 = Reset asserted 1 = No reset 0 R 5 SCT_RST Current status of the SCT_RST 0 = Reset asserted 1 = No reset 0 R 6 MOTOCONPWM_RST Current status of the MOTOCONPWM_RST 0 = Reset asserted 1 = No reset 0 R 7 QEI_RST Current status of the QEI_RST 0 = Reset asserted 1 = No reset 0 R 8 ADC0_RST Current status of the ADC0_RST 0 = Reset asserted 1 = No reset 0 R 9 ADC1_RST Current status of the ADC1_RST 0 = Reset asserted 1 = No reset 0 R 10 DAC_RST Current status of the DAC_RST 0 = Reset asserted 1 = No reset 0 R 11 12 UART0_RST Current status of the UART0_RST 0 = Reset asserted 1 = No reset 0 R 13 UART1_RST Current status of the UART1_RST 0 = Reset asserted 1 = No reset 0 R All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 129 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 11: LPC18xx Reset Generation Unit (RGU) FT D R A D R A R A FT D R FT Table 99. Bit 14 Reset active status register 1 (RESET_ACTIVE_STATUS1, address 0x4005 3154) bit description …continued D R R R A A A FT F FT Symbol UART2_RST Description Current status of the UART2_RST 0 = Reset asserted 1 = No reset Reset value 0 Access D D R R R A A FT D R A FT D FT D R A 15 UART3_RST Current status of the UART3_RST 0 = Reset asserted 1 = No reset 0 R 16 I2C0_RST Current status of the I2C0_RST 0 = Reset asserted 1 = No reset 0 R 17 I2C1_RST Current status of the I2C1_RST 0 = Reset asserted 1 = No reset 0 R 18 SSP0_RST Current status of the SSP0_RST 0 = Reset asserted 1 = No reset 0 R 19 SSP1_RST Current status of the SSP1_RST 0 = Reset asserted 1 = No reset 0 R 20 I2S_RST Current status of the I2S_RST 0 = Reset asserted 1 = No reset 0 R 21 SPIFI_RST Current status of the SPIFI_RST 0 = Reset asserted 1 = No reset 0 R 22 CAN1_RST Current status of the CAN1_RST 0 = Reset asserted 1 = No reset 0 R 23 CAN0_RST Current status of the CAN0_RST 0 = Reset asserted 1 = No reset 0 R 24 24 26 27 28 29 30 31 - Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. - - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 130 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 11: LPC18xx Reset Generation Unit (RGU) FT D R A D R A R A FT D R FT 11.4.4 Reset external status registers D R The external status registers indicate which input to the reset generator caused the reset output to go active. Any bit set to 1 in the Reset external status register should be cleared to 0 after a read operation to allow the detection of the next reset. All reset generators except the WWDT time-out reset, the BOD reset, the reset signal from the PMU, and the software reset, which have no inputs, have an associated external status register. The CORE_RST reset generator has three possible inputs (the WWDT time-out reset, the BOD reset, and the PMU), and which input caused the reset is indicated in the external status register. All other reset generators have only one input which, depending on the hierarchy, can be either the CORE_RST, the PERIPHERAL_RST, or the MASTER_RST. D R A FT D Note that the external status register does not show whether or not the reset was activated by a software reset. The software reset is indicated in the reset status registers 0 to 3 (see Table 94 to Table 97). R A FT R A F D R A FT D FT D R A R A A FT 11.4.4.1 Reset external status register 0 for CORE_RST This register shows whether or not any of the inputs to the CORE_RST reset generator has activated the CORE_RST. The CORE_RST can be activated by the external reset pin, a WWDT time-out, a BOD reset or by writing to bit 0 of the RESET_CTRL0 register. Table 100. Reset external status register 0 (RESET_EXT_STAT0, address 0x4005 3400) bit description Bit 0 Symbol EXT_RESET Description Reset activated by external reset from reset pin. Write 0 to clear. 0 = Reset not activated by reset pin 1 = Reset activated 1 2 3 4 BOD_RESET Reserved. Do not modify; read as logic 0. Reserved. Do not modify; read as logic 0. Reserved. Do not modify; read as logic 0. Reset activated by BOD reset. Write 0 to clear. 0 = Reset not activated by BOD 1 = Reset activated 5 WWDT_RESET Reset activated by WWDT time-out. Write 0 to clear. 0 0 = Reset not activated by WWDT 1 = Reset activated 31:6 Reserved. Do not modify; read as logic 0. 0 R/W 0 0 0 0 R/W Reset value 0 Access R/W 11.4.4.2 Reset external status register 1 for PERIPH_RST This register shows whether or not the CORE_RST output has activated the PERIPH_RST. A reset generated from the CORE_RST is the only possible reset source for the PERIPH_RST aside from a software reset by writing to the RESET_CTRL register. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 131 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 11: LPC18xx Reset Generation Unit (RGU) FT D R R A Table 101. Reset external status register 1 (RESET_EXT_STAT1, address 0x4005 3404) bit description D R A R A FT D R FT D R A R A A FT D F FT D Bit 0 1 Symbol - Description Reserved. Do not modify; read as logic 0. Reset value 0 Access R R A A FT R/W FT D R A D CORE_RESET Reset activated by CORE_RST output. Write 0 to 0 clear. 0 = Reset not activated 1 = Reset activated FT D R A 31:2 - Reserved. Do not modify; read as logic 0. 0 - 11.4.4.3 Reset external status register 2 for MASTER_RST Table 102. Reset external status register 2 (RESET_EXT_STAT2, address 0x4005 3408) bit description Bit 1:0 2 Symbol Description Reserved. Do not modify; read as logic 0. Reset value 0 0 Access R/W PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated 31:3 - Reserved. Do not modify; read as logic 0. 0 - 11.4.4.4 Reset external status register 4 for WWDT_RST Table 103. Reset external status register 4 (RESET_EXT_STAT4, address 0x4005 3410) bit description Bit 0 1 Symbol CORE_RESET Description Reserved. Do not modify; read as logic 0. Reset activated by CORE_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated 31:2 Reserved. Do not modify; read as logic 0. 0 Reset value 0 0 Access R/W 11.4.4.5 Reset external status register 5 for CREG_RST Table 104. Reset external status register 5 (RESET_EXT_STAT5, address 0x4005 3414) bit description Bit 0 1 Symbol CORE_RESET Description Reserved. Do not modify; read as logic 0. Reset activated by CORE_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated 31:2 Reset value 0 0 Access R/W - Reserved. Do not modify; read as logic 0. All information provided in this document is subject to legal disclaimers. 0 - © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 132 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 11: LPC18xx Reset Generation Unit (RGU) FT D R A 11.4.4.6 Reset external status registers for PERIPHERAL_RESET Refer to Table 91 for reset generators which have the PERIPH_RST output as reset source. FT D R Table 105. Reset external status registers x (RESET_EXT_STATx, address 0x4005 34xx) bit description Bit 1:0 2 Symbol Description Reserved. Do not modify; read as logic 0. Reset value 0 0 PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated D R A R A FT D R FT D R R A - R A F D R A FT A FT FT Access R/W A D R A D FT D R A 31:3 - Reserved. Do not modify; read as logic 0. 0 - 11.4.4.7 Reset external status registers for MASTER_RESET Refer to Table 91 for reset generators which have the MASTER_RST output as reset source. These are the ARM Cortex-M3 core, the LCD controller, the USB0, the GPDMA, the SDIO controller, the external memory controller, the Ethernet controller, and the AES. The reset value is dependent on the peripheral, see Table 91. Table 106. Reset external status registers y (RESET_EXT_STATy, address 0x4005 34yy) bit description Bit 2:0 3 Symbol MASTER_RESET Description Reserved. Do not modify; read as logic 0. Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated 31:4 Reserved. Do not modify; read as logic 0. 0 Reset value 0 0 Access R/W All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 133 of 1164 D R A FT D R A FT D R A FT D R A FT D R A FT UM10430 Chapter 12: LPC18xx Pin configuration Rev. 00.13 — 20 July 2011 D D D R A FT D D R A FT D R A FT D R A R A FT D R A R A FT D R A FT D R A F R A FT D R R D User manual FT D R A FT FT A FT 12.1 How to read this chapter This chapter applies to parts LPC1850_30_20_10 Rev ‘A’ only. D D R A FT D R A 12.2 Pin description On the LPC18xx, digital pins are grouped into 16 ports, named P0 to P9 and PA to PF, with up to 20 pins used per port. Each digital pin may support up to four different digital functions, including General Purpose I/O (GPIO), selectable through the SCU registers. Note that the pin name is not indicative of the GPIO port assigned to it. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 134 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 12: LPC18xx Pin configuration FT D R A D R A R A FT D R FT D Table 107. Pin description LQFP208[1] BGA180[1] BGA100[1] LBGA256 Symbol LQFP144 Reset state [2] R R A FT R A F A FT Type Description D D R A FT D R A FT D A FT R Multiplexed digital pins P0_0 L3 x x x 32 [3] D R I; PU I/O I/O I I/O GPIO0[0] — General purpose digital input/output pin. SSP1_MISO — Master In Slave Out for SSP1. ENET_RXD1 — Ethernet receive data 1 (RMII/MII interface). R — Function reserved. R — Function reserved. R — Function reserved. I2S0_TX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. I2S1_TX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. A I/O P0_1 M2 x x x 34 [3] I; PU I/O I/O I - GPIO0[1] — General purpose digital input/output pin. SSP1_MOSI — Master Out Slave in for SSP1. ENET_COL — Ethernet Collision detect (MII interface). R — Function reserved. R — Function reserved. R — Function reserved. ENET_TX_EN — Ethernet transmit enable (RMII/MII interface). I/O I2S1_TX_SDA — I2S1 transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. GPIO0[4] — General purpose digital input/output pin. CTIN_3 — SCT input 3. Capture input 1 of timer 1. EMC_A5 — External memory address line 5. R — Function reserved. R — Function reserved. SSP0_SSEL — Slave Select for SSP0. R — Function reserved. R — Function reserved. P1_0 P2 x x x 38 [3] I; PU I/O I I/O I/O - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 135 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 12: LPC18xx Pin configuration FT D R A D R A R A FT D R FT Table 107. Pin description …continued LQFP208[1] BGA180[1] BGA100[1] LBGA256 Symbol LQFP144 Reset state [2] D R R A R A A Type Description FT D R R A FT D R A A F FT D FT D P1_1 R2 x x x 42 [3] I; PU I/O O I/O I/O - GPIO0[8] — General purpose digital input/output pin. Boot pin (see Table 8). CTOUT_7 — SCT output 7. Match output 3 of timer 1. EMC_A6 — External memory address line 6. R — Function reserved. R — Function reserved. SSP0_MISO — Master In Slave Out for SSP0. R — Function reserved. R — Function reserved. GPIO0[9] — General purpose digital input/output pin. Boot pin (see Table 8). CTOUT_6 — SCT output 6. Match output 2 of timer 1. EMC_A7 — External memory address line 7. R — Function reserved. R — Function reserved. SSP0_MOSI — Master Out Slave in for SSP0. R — Function reserved. R — Function reserved. GPIO0[10] — General purpose digital input/output pin. CTOUT_8 — SCT output 8. Match output 0 of timer 2. R — Function reserved. EMC_OE — LOW active Output Enable signal. FT D R A P1_2 R3 x x x 43 [3] I; PU I/O O I/O I/O - P1_3 P5 x x x 44 [3] I; PU I/O O O O I/O O USB0_IND1 — USB0 port indicator LED control output 1. SSP1_MISO — Master In Slave Out for SSP1. R — Function reserved. SD_RST — SD/MMC reset signal for MMC4.4 card. GPIO0[11] — General purpose digital input/output pin. CTOUT_9 — SCT output 9. Match output 1 of timer 2. R — Function reserved. EMC_BLS0 — LOW active Byte Lane select signal 0. USB0_IND0 — USB0 port indicator LED control output 0. SSP1_MOSI — Master Out Slave in for SSP1. R — Function reserved. SD_VOLT1 — SD/MMC bus voltage select output 1. P1_4 T3 x x x 47 [3] I; PU I/O O O O I/O O All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 136 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 12: LPC18xx Pin configuration FT D R A D R A R A FT D R FT Table 107. Pin description …continued LQFP208[1] BGA180[1] BGA100[1] LBGA256 Symbol LQFP144 Reset state [2] D R R A R A A Type Description FT D R R A FT D R A A F FT D FT D P1_5 R5 x x x 48 [3] I; PU I/O O O O GPIO1[8] — General purpose digital input/output pin. CTOUT_10 — SCT output 10. Match output 2 of timer 2. R — Function reserved. EMC_CS0 — LOW active Chip Select 0 signal. USB0_PWR_FAULT — Port power fault signal indicating overcurrent condition; this signal monitors over-current on the USB bus (external circuitry required to detect over-current condition). SSP1_SSEL — Slave Select for SSP1. R — Function reserved. SD_POW — . GPIO1[9] — General purpose digital input/output pin. CTIN_5 — SCT input 5. Capture input 2 of timer 2. R — Function reserved. EMC_WE — LOW active Write Enable signal. R — Function reserved. R — Function reserved. R — Function reserved. SD_CMD — SD/MMC command signal. GPIO1[0] — General purpose digital input/output pin. U1_DSR — Data Set Ready input for UART1. CTOUT_13 — SCT output 13. Match output 1 of timer 3. EMC_D0 — External memory data line 0. USB0_PWR_EN — VBUS drive signal (towards external charge pump or power management unit); indicates that Vbus must be driven (active high). R — Function reserved. R — Function reserved. R — Function reserved. GPIO1[1] — General purpose digital input/output pin. U1_DTR — Data Terminal Ready output for UART1. CTOUT_12 — SCT output 12. Match output 0 of timer 3. EMC_D1 — External memory data line 1. R — Function reserved. R — Function reserved. R — Function reserved. SD_VOLT0 — SD/MMC bus voltage select output 0. FT D R A I/O O P1_6 T4 x x x 49 [3] I; PU I/O I O I/O P1_7 T5 x x x 50 [3] I; PU I/O I O I/O O P1_8 R7 x x x 51 [3] I; PU I/O O O I/O O All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 137 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 12: LPC18xx Pin configuration FT D R A D R A R A FT D R FT Table 107. Pin description …continued LQFP208[1] BGA180[1] BGA100[1] LBGA256 Symbol LQFP144 Reset state [2] D R R A R A A Type Description FT D R R A FT D R A A F FT D FT D P1_9 T7 x x x 52 [3] I; PU I/O O O I/O I/O GPIO1[2] — General purpose digital input/output pin. U1_RTS — Request to Send output for UART1. CTOUT_11 — SCT output 11. Match output 3 of timer 2. EMC_D2 — External memory data line 2. R — Function reserved. R — Function reserved. R — Function reserved. SD_DAT0 — SD/MMC data bus line 0. GPIO1[3] — General purpose digital input/output pin. U1_RI — Ring Indicator input for UART1. CTOUT_14 — SCT output 14. Match output 2 of timer 3. EMC_D3 — External memory data line 3. R — Function reserved. R — Function reserved. R — Function reserved. SD_DAT1 — SD/MMC data bus line 1. GPIO1[4] — General purpose digital input/output pin. U1_CTS — Clear to Send input for UART1. CTOUT_15 — SCT output 15. Match output 3 of timer 3. EMC_D4 — External memory data line 4. R — Function reserved. R — Function reserved. R — Function reserved. SD_DAT2 — SD/MMC data bus line 2. GPIO1[5] — General purpose digital input/output pin. U1_DCD — Data Carrier Detect input for UART1. R — Function reserved. EMC_D5 — External memory data line 5. T0_CAP1 — Capture input 1 of timer 0. R — Function reserved. R — Function reserved. SD_DAT3 — SD/MMC data bus line 3. FT D R A P1_10 R8 x x x 53 [3] I; PU I/O I O I/O I/O P1_11 T9 x x x 55 [3] I; PU I/O I O I/O I/O P1_12 R9 x x x 56 [3] I; PU I/O I I/O I I/O All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 138 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 12: LPC18xx Pin configuration FT D R A D R A R A FT D R FT Table 107. Pin description …continued LQFP208[1] BGA180[1] BGA100[1] LBGA256 Symbol LQFP144 Reset state [2] D R R A R A A Type Description FT D R R A FT D R A A F FT D FT D P1_13 R10 x x x 60 [3] I; PU I/O O I/O I I GPIO1[6] — General purpose digital input/output pin. U1_TXD — Transmitter output for UART1. R — Function reserved. EMC_D6 — External memory data line 6. T0_CAP0 — Capture input 0 of timer 0. R — Function reserved. R — Function reserved. SD_CD — SD/MMC card detect input. GPIO1[7] — General purpose digital input/output pin. U1_RXD — Receiver input for UART1. R — Function reserved. EMC_D7 — External memory data line 7. T0_MAT2 — Match output 2 of timer 0. R — Function reserved. R — Function reserved. R — Function reserved. GPIO0[2] — General purpose digital input/output pin. U2_TXD — Transmitter output for USART2. R — Function reserved. ENET_RXD0 — Ethernet receive data 0 (RMII/MII interface). T0_MAT1 — Match output 1of timer 0. R — Function reserved. R — Function reserved. R — Function reserved. GPIO0[3] — General purpose digital input/output pin. U2_RXD — Receiver input for USART2. R — Function reserved. ENET_CRS — Ethernet Carrier Sense (MII interface). T0_MAT0 — Match output 0 of timer 0. R — Function reserved. R — Function reserved. ENET_RX_DV — Ethernet Receive Data Valid (RMII/MII interface). FT D R A P1_14 R11 x x x 61 [3] I; PU I/O I I/O O - P1_15 T12 x x x 62 [3] I; PU I/O O I O - P1_16 M7 x x x 64 [3] I; PU I/O I I O I All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 139 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 12: LPC18xx Pin configuration FT D R A D R A R A FT D R FT Table 107. Pin description …continued LQFP208[1] BGA180[1] BGA100[1] LBGA256 Symbol LQFP144 Reset state [2] D R R A R A A Type Description FT D R R A FT D R A A F FT D FT D P1_17 M8 x x x 66 [4] I; PU I/O I/O I/O I O - GPIO0[12] — General purpose digital input/output pin. U2_UCLK — Serial clock input/output for USART2 in synchronous mode. R — Function reserved. ENET_MDIO — Ethernet MIIM data input and output. T0_CAP3 — Capture input 3 of timer 0. CAN1_TD — CAN1 transmitter output. R — Function reserved. R — Function reserved. GPIO0[13] — General purpose digital input/output pin. U2_DIR — RS-485/EIA-485 output enable/direction control for USART2. R — Function reserved. ENET_TXD0 — Ethernet transmit data 0 (RMII/MII interface). T0_MAT3 — Match output 3 of timer 0. CAN1_RD — CAN1 receiver input. R — Function reserved. R — Function reserved. ENET_TX_CLK (ENET_REF_CLK) — Ethernet Transmit Clock (MII interface) or Ethernet Reference Clock (RMII interface). SSP1_SCK — Serial clock for SSP1. R — Function reserved. R — Function reserved. CLKOUT — Clock output pin. R — Function reserved. I2S0_RX_MCLK — I2S receive master clock. I2S1_TX_SCK — Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. GPIO0[15] — General purpose digital input/output pin. SSP1_SSEL — Slave Select for SSP1. R — Function reserved. ENET_TXD1 — Ethernet transmit data 1 (RMII/MII interface). T0_CAP2 — Capture input 2 of timer 0. R — Function reserved. R — Function reserved. R — Function reserved. FT D R A P1_18 N12 x x x 67 [3] I; PU I/O I/O O O I - P1_19 M11 x x x 68 [3] I; PU I I/O O O I/O P1_20 M10 x x x 70 [3] I; PU I/O I/O O I - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 140 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 12: LPC18xx Pin configuration FT D R A D R A R A FT D R FT Table 107. Pin description …continued LQFP208[1] BGA180[1] BGA100[1] LBGA256 Symbol LQFP144 Reset state [2] D R R A R A A Type Description FT D R R A FT D R A A F FT D FT D P2_0 T16 x x x 75 [3] I; PU O I/O O R — Function reserved. U0_TXD — Transmitter output for USART0. EMC_A13 — External memory address line 13. USB0_PWR_EN — VBUS drive signal (towards external charge pump or power management unit); indicates that Vbus must be driven (active high). GPIO5[0] — General purpose digital input/output pin. R — Function reserved. T3_CAP0 — Capture input 0 of timer 3. ENET_MDC — Ethernet MIIM clock. R — Function reserved. U0_RXD — Receiver input for USART0. EMC_A12 — External memory address line 12. USB0_PWR_FAULT — Port power fault signal indicating overcurrent condition; this signal monitors over-current on the USB bus (external circuitry required to detect over-current condition). GPIO5[1] — General purpose digital input/output pin. R — Function reserved. T3_CAP1 — Capture input 1 of timer 3. R — Function reserved. R — Function reserved. U0_UCLK — Serial clock input/output for USART0 in synchronous mode. EMC_A11 — External memory address line 11. FT D R A I/O I O P2_1 N15 x x x 81 [3] I; PU I I/O O I/O I P2_2 M15 x x x 84 [3] I; PU I/O I/O O I/O O I - USB0_IND1 — USB0 port indicator LED control output 1. GPIO5[2] — General purpose digital input/output pin. CTOUT_6 — SCT output 6. Match output 2 of timer 1. T3_CAP2 — Capture input 2 of timer 3. R — Function reserved. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 141 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 12: LPC18xx Pin configuration FT D R A D R A R A FT D R FT Table 107. Pin description …continued LQFP208[1] BGA180[1] BGA100[1] LBGA256 Symbol LQFP144 Reset state [2] D R R A R A A Type Description FT D R R A FT D R A A F FT D FT D P2_3 J12 x x x 87 [4] I; PU I/O O I I/O O O R — Function reserved. I2C1_SDA — I2C1 data input/output (this pin does not use a specialized I2C pad). U3_TXD — Transmitter output for USART3. CTIN_1 — SCT input 1. Capture input 1 of timer 0. Capture input 1 of timer 2. GPIO5[3] — General purpose digital input/output pin. R — Function reserved. T3_MAT0 — Match output 0 of timer 3. USB0_PWR_EN — VBUS drive signal (towards external charge pump or power management unit); indicates that Vbus must be driven (active HIGH). R — Function reserved. I2C1_SCL — I2C1 clock input/output (this pin does not use a specialized I2C pad). U3_RXD — Receiver input for USART3. CTIN_0 — SCT input 0. Capture input 0 of timer 0, 1, 2, 3. GPIO5[4] — General purpose digital input/output pin. R — Function reserved. T3_MAT1 — Match output 1 of timer 3. USB0_PWR_FAULT — Port power fault signal indicating overcurrent condition; this signal monitors over-current on the USB bus (external circuitry required to detect over-current condition). R — Function reserved. CTIN_2 — SCT input 2. Capture input 2 of timer 0. USB1_VBUS — Monitors the presence of USB1 bus power. Note: This signal must be HIGH for USB reset to occur. ADCTRIG1 — ADC trigger input 1. GPIO5[5] — General purpose digital input/output pin. R — Function reserved. T3_MAT2 — Match output 2 of timer 3. FT D R A P2_4 K11 x x x 88 [4] I; PU I/O I I I/O O O P2_5 K14 x x x 91 [4] I; PU I I I I/O O O USB0_IND0 — USB0 port indicator LED control output 0. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 142 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 12: LPC18xx Pin configuration FT D R A D R A R A FT D R FT Table 107. Pin description …continued LQFP208[1] BGA180[1] BGA100[1] LBGA256 Symbol LQFP144 Reset state [2] D R R A R A A Type Description FT D R R A FT D R A A F FT D FT D P2_6 K16 x x x 95 [3] I; PU I/O I/O O I/O I I - R — Function reserved. U0_DIR — RS-485/EIA-485 output enable/direction control for USART0. EMC_A10 — External memory address line 10. FT D R A USB0_IND0 — USB0 port indicator LED control output 0. GPIO5[6] — General purpose digital input/output pin. CTIN_7 — SCT input 7. T3_CAP3 — Capture input 3 of timer 3. R — Function reserved. GPIO0[7] — General purpose digital input/output pin. ISP entry pin. If this pin is pulled LOW at reset, the part enters ISP mode using USART0. CTOUT_1 — SCT output 1. Match output 1 of timer 0. U3_UCLK — Serial clock input/output for USART3 in synchronous mode. EMC_A9 — External memory address line 9. R — Function reserved. R — Function reserved. T3_MAT3 — Match output 3 of timer 3. R — Function reserved. n.c. - Boot pin (see Table 8). CTOUT_0 — SCT output 0. Match output 0 of timer 0. U3_DIR — RS-485/EIA-485 output enable/direction control for USART3. EMC_A8 — External memory address line 8. GPIO5[7] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. GPIO1[10] — General purpose digital input/output pin. Boot pin (see Table 8). CTOUT_3 — SCT output 3. Match output 3 of timer 0. U3_BAUD — for USART3. EMC_A0 — External memory address line 0. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. P2_7 H14 x x x 96 [3] I; PU I/O O I/O I/O O P2_8 J16 x x x 98 [3] I; PU O I/O I/O I/O - P2_9 H16 x x x 102 [3] I; PU I/O O I/O I/O - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 143 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 12: LPC18xx Pin configuration FT D R A D R A R A FT D R FT Table 107. Pin description …continued LQFP208[1] BGA180[1] BGA100[1] LBGA256 Symbol LQFP144 Reset state [2] D R R A R A A Type Description FT D R R A FT D R A A F FT D FT D P2_10 G16 x x x 104 [3] I; PU I/O O O I/O - GPIO0[14] — General purpose digital input/output pin. CTOUT_2 — SCT output 2. Match output 2 of timer 0. U2_TXD — Transmitter output for USART2. EMC_A1 — External memory address line 1. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. GPIO1[11] — General purpose digital input/output pin. CTOUT_5 — SCT output 5. Match output 1 of timer 1. U2_RXD — Receiver input for USART2. EMC_A2 — External memory address line 2. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. GPIO1[12] — General purpose digital input/output pin. CTOUT_4 — SCT output 4. Match output 0 of timer 1. R — Function reserved. EMC_A3 — External memory address line 3. R — Function reserved. R — Function reserved. R — Function reserved. U2_UCLK — Serial clock input/output for USART2 in synchronous mode. GPIO1[13] — General purpose digital input/output pin. CTIN_4 — SCT input 4. Capture input 2 of timer 1. R — Function reserved. EMC_A4 — External memory address line 4. R — Function reserved. R — Function reserved. R — Function reserved. U2_DIR — RS-485/EIA-485 output enable/direction control for USART2. FT D R A P2_11 F16 x x x 105 [3] I; PU I/O O I I/O - P2_12 E15 x x x 106 [3] I; PU I/O O I/O I/O P2_13 C16 x x x 108 [3] I; PU I/O I I/O I/O All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 144 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 12: LPC18xx Pin configuration FT D R A D R A R A FT D R FT Table 107. Pin description …continued LQFP208[1] BGA180[1] BGA100[1] LBGA256 Symbol LQFP144 Reset state [2] D R R A R A A Type Description FT D R R A FT D R A A F FT D FT D P3_0 F13 x x x 112 [3] I; PU I/O I2S0_RX_SCK — I2S transmit clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. I2S0_RX_MCLK — I2S receive master clock. I2S0_TX_SCK — Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. I2S0_TX_MCLK — I2S transmit master clock. SSP0_SCK — Serial clock for SSP0. R — Function reserved. R — Function reserved. R — Function reserved. I2S0_TX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. I2S0_RX_WS — Receive Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. CAN0_RD — CAN receiver input. USB1_IND1 — USB1 Port indicator LED control output 1. GPIO5[8] — General purpose digital input/output pin. R — Function reserved. LCD_VD15 — LCD data. R — Function reserved. I2S0_TX_SDA — I2S transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. I2S0_RX_SDA — I2S Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. CAN0_TD — CAN transmitter output. USB1_IND0 — USB1 Port indicator LED control output 0. GPIO5[9] — General purpose digital input/output pin. R — Function reserved. LCD_VD14 — LCD data. R — Function reserved. FT D R A O I/O O I/O P3_1 G11 x x x 114 [3] I; PU I/O I/O I O I/O O P3_2 F11 x x x 116 [3] I; PU I/O I/O O O I/O O - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 145 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 12: LPC18xx Pin configuration FT D R A D R A R A FT D R FT Table 107. Pin description …continued LQFP208[1] BGA180[1] BGA100[1] LBGA256 Symbol LQFP144 Reset state [2] D R R A R A A Type Description FT D R R A FT D R A A F FT D FT D P3_3 B14 x x x 118 [5] I; PU I/O O O O I/O R — Function reserved. R — Function reserved. SSP0_SCK — Serial clock for SSP0. SPIFI_SCK — Serial clock for SPIFI. CGU_OUT1 — CGU spare clock output 1. R — Function reserved. I2S0_TX_MCLK — I2S transmit master clock. I2S1_TX_SCK — Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. GPIO1[14] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. SPIFI_SIO3 — I/O lane 3 for SPIFI. U1_TXD — Transmitter output for UART 1. I2S0_TX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. I2S1_RX_SDA — I2S1 Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. LCD_VD13 — LCD data. GPIO1[15] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. SPIFI_SIO2 — I/O lane 2 for SPIFI. U1_RXD — Receiver input for UART 1. I2S0_TX_SDA — I2S transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. I2S1_RX_WS — Receive Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. LCD_VD12 — LCD data. FT D R A P3_4 A15 x x x 119 [3] I; PU I/O I/O O I/O I/O O P3_5 C12 x x x 121 [3] I; PU I/O I/O I I/O I/O O All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 146 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 12: LPC18xx Pin configuration FT D R A D R A R A FT D R FT Table 107. Pin description …continued LQFP208[1] BGA180[1] BGA100[1] LBGA256 Symbol LQFP144 Reset state [2] D R R A R A A Type Description FT D R R A FT D R A A F FT D FT D P3_6 B13 x x x 122 [3] I; PU I/O I/O I/O I/O - GPIO0[6] — General purpose digital input/output pin. R — Function reserved. SSP0_SSEL — Slave Select for SSP0. SPIFI_MISO — Input 1 in SPIFI quad mode; SPIFI output IO1. R — Function reserved. SSP0_MISO — Master In Slave Out for SSP0. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. SSP0_MISO — Master In Slave Out for SSP0. SPIFI_MOSI — Input I0 in SPIFI quad mode; SPIFI output IO0. GPIO5[10] — General purpose digital input/output pin. SSP0_MOSI — Master Out Slave in for SSP0. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. SSP0_MOSI — Master Out Slave in for SSP0. SPIFI_CS — SPIFI serial flash chip select. GPIO5[11] — General purpose digital input/output pin. SSP0_SSEL — Slave Select for SSP0. R — Function reserved. R — Function reserved. GPIO2[0] — General purpose digital input/output pin. MCOA0 — Motor control PWM channel 0, output A. NMI — External interrupt input to NMI. R — Function reserved. R — Function reserved. LCD_VD13 — LCD data. U3_UCLK — Serial clock input/output for USART3 in synchronous mode. R — Function reserved. FT D R A P3_7 C11 x x x 123 [3] I; PU I/O I/O I/O I/O - P3_8 C10 x x x 124 [3] I; PU I/O I/O I/O I/O - P4_0 D5 x - x 1 [3] I; PU I/O O I O I/O - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 147 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 12: LPC18xx Pin configuration FT D R A D R A R A FT D R FT Table 107. Pin description …continued LQFP208[1] BGA180[1] BGA100[1] LBGA256 Symbol LQFP144 Reset state [2] D R R A R A A Type Description FT D R R A FT D R A A F FT D FT D P4_1 A1 x - x 3 [6] I; PU I/O O O O O I I GPIO2[1] — General purpose digital input/output pin. CTOUT_1 — SCT output 1. Match output 1 of timer 0. LCD_VD0 — LCD data. R — Function reserved. R — Function reserved. LCD_VD19 — LCD data. U3_TXD — Transmitter output for USART3. ENET_COL — Ethernet Collision detect (MII interface). ADC0_1 — ADC0, input channel 1. GPIO2[2] — General purpose digital input/output pin. CTOUT_0 — SCT output 0. Match output 0 of timer 0. LCD_VD3 — LCD data. R — Function reserved. R — Function reserved. LCD_VD12 — LCD data. U3_RXD — Receiver input for USART3. R — Function reserved. GPIO2[3] — General purpose digital input/output pin. CTOUT_3 — SCT output 0. Match output 3 of timer 0. LCD_VD2 — LCD data. R — Function reserved. R — Function reserved. LCD_VD21 — LCD data. U3_BAUD — for USART3. R — Function reserved. ADC0_0 — ADC0, input channel 0. GPIO2[4] — General purpose digital input/output pin. CTOUT_2 — SCT output 2. Match output 2 of timer 0. LCD_VD1 — LCD data. R — Function reserved. R — Function reserved. LCD_VD20 — LCD data. U3_DIR — RS-485/EIA-485 output enable/direction control for USART3. R — Function reserved. DAC — DAC output. FT D R A P4_2 D3 x - x 8 [3] I; PU I/O O O O I - P4_3 C2 x - x 7 [6] I; PU I/O O O O I/O I P4_4 B1 x - x 9 [6] I; PU I/O O O O I/O O All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 148 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 12: LPC18xx Pin configuration FT D R A D R A R A FT D R FT Table 107. Pin description …continued LQFP208[1] BGA180[1] BGA100[1] LBGA256 Symbol LQFP144 Reset state [2] D R R A R A A Type Description FT D R R A FT D R A A F FT D FT D P4_5 D2 x - x 10 [3] I; PU I/O O O - GPIO2[5] — General purpose digital input/output pin. CTOUT_5 — SCT output 5. Match output 1 of timer 1. LCD_FP — Frame pulse (STN). Vertical synchronization pulse (TFT). R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. GPIO2[6] — General purpose digital input/output pin. CTOUT_4 — SCT output 4. Match output 0 of timer 1. LCD_ENAB/LCDM — STN AC bias drive or TFT data enable input. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. LCD_DCLK — LCD panel clock. GP_CLKIN — General purpose clock input to the CGU. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. I2S1_TX_SCK — Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. I2S0_TX_SCK — Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. R — Function reserved. CTIN_5 — SCT input 5. Capture input 2 of timer 2. LCD_VD9 — LCD data. R — Function reserved. GPIO5[12] — General purpose digital input/output pin. LCD_VD22 — LCD data. CAN1_TD — CAN1 transmitter output. R — Function reserved. FT D R A P4_6 C1 x - x 11 [3] I; PU I/O O O - P4_7 H4 x - x 14 [3] O I I/O I/O P4_8 E2 x - x 15 [3] I; PU I O I/O O O - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 149 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 12: LPC18xx Pin configuration FT D R A D R A R A FT D R FT Table 107. Pin description …continued LQFP208[1] BGA180[1] BGA100[1] LBGA256 Symbol LQFP144 Reset state [2] D R R A R A A Type Description FT D R R A FT D R A A F FT D FT D P4_9 L2 x - x 33 [3] I; PU I O I/O O I - R — Function reserved. CTIN_6 — SCT input 6. Capture input 1 of timer 3. LCD_VD11 — LCD data. R — Function reserved. GPIO5[13] — General purpose digital input/output pin. LCD_VD15 — LCD data. CAN1_RD — CAN1 receiver input. R — Function reserved. R — Function reserved. CTIN_2 — SCT input 2. Capture input 2 of timer 0. LCD_VD10 — LCD data. R — Function reserved. GPIO5[14] — General purpose digital input/output pin. LCD_VD14 — LCD data. R — Function reserved. R — Function reserved. GPIO2[9] — General purpose digital input/output pin. MCOB2 — Motor control PWM channel 2, output B. EMC_D12 — External memory data line 12. R — Function reserved. U1_DSR — Data Set Ready input for UART 1. T1_CAP0 — Capture input 0 of timer 1. R — Function reserved. R — Function reserved. GPIO2[10] — General purpose digital input/output pin. MCI2 — Motor control PWM channel 2, input. EMC_D13 — External memory data line 13. R — Function reserved. U1_DTR — Data Terminal Ready output for UART 1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART 1. T1_CAP1 — Capture input 1 of timer 1. R — Function reserved. R — Function reserved. FT D R A P4_10 M3 x - x 35 [3] I; PU I O I/O O - P5_0 N3 x - x 37 [3] I; PU I/O O I/O I I - P5_1 P3 x - x 39 [3] I; PU I/O I I/O O I - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 150 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 12: LPC18xx Pin configuration FT D R A D R A R A FT D R FT Table 107. Pin description …continued LQFP208[1] BGA180[1] BGA100[1] LBGA256 Symbol LQFP144 Reset state [2] D R R A R A A Type Description FT D R R A FT D R A A F FT D FT D P5_2 R4 x - x 46 [3] I; PU I/O I I/O O GPIO2[11] — General purpose digital input/output pin. MCI1 — Motor control PWM channel 1, input. EMC_D14 — External memory data line 14. R — Function reserved. U1_RTS — Request to Send output for UART 1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART 1. T1_CAP2 — Capture input 2 of timer 1. R — Function reserved. R — Function reserved. GPIO2[12] — General purpose digital input/output pin. MCI0 — Motor control PWM channel 0, input. EMC_D15 — External memory data line 15. R — Function reserved. U1_RI — Ring Indicator input for UART 1. T1_CAP3 — Capture input 3 of timer 1. R — Function reserved. R — Function reserved. GPIO2[13] — General purpose digital input/output pin. MCOB0 — Motor control PWM channel 0, output B. EMC_D8 — External memory data line 8. R — Function reserved. U1_CTS — Clear to Send input for UART 1. T1_MAT0 — Match output 0 of timer 1. R — Function reserved. R — Function reserved. GPIO2[14] — General purpose digital input/output pin. MCOA1 — Motor control PWM channel 1, output A. EMC_D9 — External memory data line 9. R — Function reserved. U1_DCD — Data Carrier Detect input for UART 1. T1_MAT1 — Match output 1 of timer 1. R — Function reserved. R — Function reserved. FT D R A I P5_3 T8 x x 54 [3] I; PU I/O I I/O I I - P5_4 P9 x - x 57 [3] I; PU I/O O I/O I O - P5_5 P10 x - x 58 [3] I; PU I/O O I/O I O - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 151 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 12: LPC18xx Pin configuration FT D R A D R A R A FT D R FT Table 107. Pin description …continued LQFP208[1] BGA180[1] BGA100[1] LBGA256 Symbol LQFP144 Reset state [2] D R R A R A A Type Description FT D R R A FT D R A A F FT D FT D P5_6 T13 x - x 63 [3] I; PU I/O O I/O O O - GPIO2[15] — General purpose digital input/output pin. MCOB1 — Motor control PWM channel 1, output B. EMC_D10 — External memory data line 10. R — Function reserved. U1_TXD — Transmitter output for UART 1. T1_MAT2 — Match output 2 of timer 1. R — Function reserved. R — Function reserved. GPIO2[7] — General purpose digital input/output pin. MCOA2 — Motor control PWM channel 2, output A. EMC_D11 — External memory data line 11. R — Function reserved. U1_RXD — Receiver input for UART 1. T1_MAT3 — Match output 3 of timer 1. R — Function reserved. R — Function reserved. R — Function reserved. I2S0_RX_MCLK — I2S receive master clock. R — Function reserved. R — Function reserved. I2S0_RX_SCK — Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. R — Function reserved. R — Function reserved. R — Function reserved. GPIO3[0] — General purpose digital input/output pin. EMC_DYCS1 — SDRAM chip select 1. U0_UCLK — Serial clock input/output for USART0 in synchronous mode. I2S0_RX_WS — Receive Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. R — Function reserved. T2_CAP0 — Capture input 2 of timer 2. R — Function reserved. R — Function reserved. FT D R A P5_7 R12 x - x 65 [3] I; PU I/O O I/O I O - P6_0 M12 x x x 73 [3] I; PU O I/O P6_1 R15 x x x 74 [3] I; PU I/O O I/O I/O I - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 152 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 12: LPC18xx Pin configuration FT D R A D R A R A FT D R FT Table 107. Pin description …continued LQFP208[1] BGA180[1] BGA100[1] LBGA256 Symbol LQFP144 Reset state [2] D R R A R A A Type Description FT D R R A FT D R A A F FT D FT D P6_2 L13 x x x 78 [3] I; PU I/O O I/O I/O GPIO3[1] — General purpose digital input/output pin. EMC_CKEOUT1 — SDRAM clock enable 1. U0_DIR — RS-485/EIA-485 output enable/direction control for USART0. I2S0_RX_SDA — I2S Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. R — Function reserved. T2_CAP1 — Capture input 1 of timer 2. R — Function reserved. R — Function reserved. GPIO3[2] — General purpose digital input/output pin. USB0_PWR_EN — VBUS drive signal (towards external charge pump or power management unit); indicates that the VBUS signal must be driven (active HIGH). R — Function reserved. EMC_CS1 — LOW active Chip Select 1 signal. R — Function reserved. T2_CAP2 — Capture input 2 of timer 2. R — Function reserved. R — Function reserved. GPIO3[3] — General purpose digital input/output pin. CTIN_6 — SCT input 6. Capture input 1 of timer 3. U0_TXD — Transmitter output for USART0. EMC_CAS — LOW active SDRAM Column Address Strobe. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. GPIO3[4] — General purpose digital input/output pin. CTOUT_6 — SCT output 6. Match output 2 of timer 1. U0_RXD — Receiver input for USART0. EMC_RAS — LOW active SDRAM Row Address Strobe. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. FT D R A I P6_3 P15 x x 79 [3] I; PU I/O O O I P6_4 R16 x x x 80 [3] I; PU I/O I O O - P6_5 P16 x x x 82 [3] I; PU I/O O I O - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 153 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 12: LPC18xx Pin configuration FT D R A D R A R A FT D R FT Table 107. Pin description …continued LQFP208[1] BGA180[1] BGA100[1] LBGA256 Symbol LQFP144 Reset state [2] D R R A R A A Type Description FT D R R A FT D R A A F FT D FT D P6_6 L14 x - x 83 [3] I; PU I/O O O GPIO0[5] — General purpose digital input/output pin. EMC_BLS1 — LOW active Byte Lane select signal 1. R — Function reserved. USB0_PWR_FAULT — Port power fault signal indicating overcurrent condition; this signal monitors over-current on the USB bus (external circuitry required to detect over-current condition). R — Function reserved. T2_CAP3 — Capture input 3 of timer 2. R — Function reserved. R — Function reserved. R — Function reserved. EMC_A15 — External memory address line 15. R — Function reserved. FT D R A I P6_7 J13 x x 85 [3] I; PU I/O O I/O O - USB0_IND1 — USB0 port indicator LED control output 1. GPIO5[15] — General purpose digital input/output pin. T2_MAT0 — Match output 0 of timer 2. R — Function reserved. R — Function reserved. R — Function reserved. EMC_A14 — External memory address line 14. R — Function reserved. USB0_IND0 — USB0 port indicator LED control output 0. GPIO5[16] — General purpose digital input/output pin. T2_MAT1 — Match output 1 of timer 2. R — Function reserved. R — Function reserved. GPIO3[5] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. EMC_DYCS0 — SDRAM chip select 0. R — Function reserved. T2_MAT2 — Match output 2 of timer 2. R — Function reserved. R — Function reserved. P6_8 H13 x - x 86 [3] I; PU I/O O I/O O - P6_9 J15 x x x 97 [3] I; PU I/O O O - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 154 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 12: LPC18xx Pin configuration FT D R A D R A R A FT D R FT Table 107. Pin description …continued LQFP208[1] BGA180[1] BGA100[1] LBGA256 Symbol LQFP144 Reset state [2] D R R A R A A Type Description FT D R R A FT D R A A F FT D FT D P6_10 H15 x - x 100 [3] I; PU I/O O O - GPIO3[6] — General purpose digital input/output pin. MCABORT — Motor control PWM, LOW-active fast abort. R — Function reserved. EMC_DQMOUT1 — Data mask 1 used with SDRAM and static devices. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. GPIO3[7] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. EMC_CKEOUT0 — SDRAM clock enable 0. R — Function reserved. T2_MAT3 — Match output 2 of timer 3. R — Function reserved. R — Function reserved. GPIO2[8] — General purpose digital input/output pin. CTOUT_7 — SCT output 7. Match output 3 of timer 1. R — Function reserved. EMC_DQMOUT0 — Data mask 0 used with SDRAM and static devices. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. GPIO3[8] — General purpose digital input/output pin. CTOUT_14 — SCT output 14. Match output 2 of timer 3. R — Function reserved. LCD_LE — Line end signal. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. FT D R A P6_11 H12 x x x 101 [3] I; PU I/O O O - P6_12 G15 x - x 103 [3] I; PU I/O O O - P7_0 B16 x - x 110 [3] I; PU I/O O O - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 155 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 12: LPC18xx Pin configuration FT D R A D R A R A FT D R FT Table 107. Pin description …continued LQFP208[1] BGA180[1] BGA100[1] LBGA256 Symbol LQFP144 Reset state [2] D R R A R A A Type Description FT D R R A FT D R A A F FT D FT D P7_1 C14 x - x 113 [3] I; PU I/O O I/O GPIO3[9] — General purpose digital input/output pin. CTOUT_15 — SCT output 15. Match output 3 of timer 3. I2S0_TX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. LCD_VD19 — LCD data. LCD_VD7 — LCD data. R — Function reserved. U2_TXD — Transmitter output for USART2. R — Function reserved. GPIO3[10] — General purpose digital input/output pin. CTIN_4 — SCT input 4. Capture input 2 of timer 1. I2S0_TX_SDA — I2S transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. LCD_VD18 — LCD data. LCD_VD6 — LCD data. R — Function reserved. U2_RXD — Receiver input for USART2. R — Function reserved. GPIO3[11] — General purpose digital input/output pin. CTIN_3 — SCT input 3. Capture input 1 of timer 1. R — Function reserved. LCD_VD17 — LCD data. LCD_VD5 — LCD data. R — Function reserved. R — Function reserved. R — Function reserved. GPIO3[12] — General purpose digital input/output pin. CTOUT_13 — SCT output 13. Match output 1 of timer 3. R — Function reserved. LCD_VD16 — LCD data. LCD_VD4 — LCD data. TRACEDATA[0] — Trace data, bit 0. R — Function reserved. R — Function reserved. ADC0_4 — ADC0, input channel 4. FT D R A O O O P7_2 A16 x x 113 [3] I; PU I/O I I/O O O I P7_3 C13 x x 117 [3] I; PU I/O I O O - P7_4 C8 x - x 132 [6] I; PU I/O O O O O I All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 156 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 12: LPC18xx Pin configuration FT D R A D R A R A FT D R FT Table 107. Pin description …continued LQFP208[1] BGA180[1] BGA100[1] LBGA256 Symbol LQFP144 Reset state [2] D R R A R A A Type Description FT D R R A FT D R A A F FT D FT D P7_5 A7 x - x 133 [6] I; PU I/O O O O O I GPIO3[13] — General purpose digital input/output pin. CTOUT_12 — SCT output 12. Match output 0 of timer 3. R — Function reserved. LCD_VD8 — LCD data. LCD_VD23 — LCD data. TRACEDATA[1] — Trace data, bit 1. R — Function reserved. R — Function reserved. ADC0_3 — ADC0, input channel 3. GPIO3[14] — General purpose digital input/output pin. CTOUT_11 — SCT output 1. Match output 3 of timer 2. R — Function reserved. LCD_LP — Line synchronization pulse (STN). Horizontal synchronization pulse (TFT). R — Function reserved. TRACEDATA[2] — Trace data, bit 2. R — Function reserved. R — Function reserved. GPIO3[15] — General purpose digital input/output pin. CTOUT_8 — SCT output 8. Match output 0 of timer 2. R — Function reserved. LCD_PWR — LCD panel power enable. R — Function reserved. TRACEDATA[3] — Trace data, bit 3. ENET_MDC — Ethernet MIIM clock. R — Function reserved. ADC1_6 — ADC1, input channel 6. GPIO4[0] — General purpose digital input/output pin. USB0_PWR_FAULT — Port power fault signal indicating overcurrent condition; this signal monitors over-current on the USB bus (external circuitry required to detect over-current condition). R — Function reserved. MCI2 — Motor control PWM channel 2, input. R — Function reserved. R — Function reserved. R — Function reserved. T0_MAT0 — Match output 0 of timer 0. FT D R A P7_6 C7 x - x 134 [3] I; PU I/O O O O - P7_7 B6 x - x 140 [6] I; PU I/O O O O O I P8_0 E5 x - x - [4] I; PU I/O O I O All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 157 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 12: LPC18xx Pin configuration FT D R A D R A R A FT D R FT Table 107. Pin description …continued LQFP208[1] BGA180[1] BGA100[1] LBGA256 Symbol LQFP144 Reset state [2] D R R A R A A Type Description FT D R R A FT D R A A F FT D FT D P8_1 H5 x - x - [4] I; PU I/O O I O GPIO4[1] — General purpose digital input/output pin. R — Function reserved. MCI1 — Motor control PWM channel 1, input. R — Function reserved. R — Function reserved. R — Function reserved. T0_MAT1 — Match output 1 of timer 0. GPIO4[2] — General purpose digital input/output pin. FT D R A USB0_IND1 — USB0 port indicator LED control output 1. P8_2 K4 x - x - [4] I; PU I/O O I O USB0_IND0 — USB0 port indicator LED control output 0. R — Function reserved. MCI0 — Motor control PWM channel 0, input. R — Function reserved. R — Function reserved. R — Function reserved. T0_MAT2 — Match output 2 of timer 0. GPIO4[3] — General purpose digital input/output pin. USB1_ULPI_D2 — ULPI link bidirectional data line 2. R — Function reserved. LCD_VD12 — LCD data. LCD_VD19 — LCD data. R — Function reserved. R — Function reserved. T0_MAT3 — Match output 3 of timer 0. GPIO4[4] — General purpose digital input/output pin. USB1_ULPI_D1 — ULPI link bidirectional data line 1. R — Function reserved. LCD_VD7 — LCD data. LCD_VD16 — LCD data. R — Function reserved. R — Function reserved. T0_CAP0 — Capture input 0 of timer 0. P8_3 J3 x - x - [3] I; PU I/O I/O O O O P8_4 J2 x - x - [3] I; PU I/O I/O O O I All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 158 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 12: LPC18xx Pin configuration FT D R A D R A R A FT D R FT Table 107. Pin description …continued LQFP208[1] BGA180[1] BGA100[1] LBGA256 Symbol LQFP144 Reset state [2] D R R A R A A Type Description FT D R R A FT D R A A F FT D FT D P8_5 J1 x - x - [3] I; PU I/O I/O O O I GPIO4[5] — General purpose digital input/output pin. USB1_ULPI_D0 — ULPI link bidirectional data line 0. R — Function reserved. LCD_VD6 — LCD data. LCD_VD8 — LCD data. R — Function reserved. R — Function reserved. T0_CAP1 — Capture input 1 of timer 0. GPIO4[6] — General purpose digital input/output pin. USB1_ULPI_NXT — ULPI link NXT signal. Data flow control signal from the PHY. R — Function reserved. LCD_VD5 — LCD data. LCD_LP — Line synchronization pulse (STN). Horizontal synchronization pulse (TFT). R — Function reserved. R — Function reserved. T0_CAP2 — Capture input 2 of timer 0. GPIO4[7] — General purpose digital input/output pin. USB1_ULPI_STP — ULPI link STP signal. Asserted to end or interrupt transfers to the PHY. R — Function reserved. LCD_VD4 — LCD data. LCD_PWR — LCD panel power enable. R — Function reserved. R — Function reserved. T0_CAP3 — Capture input 3 of timer 0. R — Function reserved. USB1_ULPI_CLK — ULPI link CLK signal. 60 MHz clock generated by the PHY. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. CGU_OUT0 — CGU spare clock output 0. I2S1_TX_MCLK — I2S1 transmit master clock. FT D R A P8_6 K3 x - x - [3] I; PU I/O I O O I P8_7 K1 x - x - [3] I; PU I/O O O O I P8_8 L1 x - x - [3] I; PU I O O All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 159 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 12: LPC18xx Pin configuration FT D R A D R A R A FT D R FT Table 107. Pin description …continued LQFP208[1] BGA180[1] BGA100[1] LBGA256 Symbol LQFP144 Reset state [2] D R R A R A A Type Description FT D R R A FT D R A A F FT D FT D P9_0 T1 x - x - [3] I; PU I/O O I I/O GPIO4[12] — General purpose digital input/output pin. MCABORT — Motor control PWM, LOW-active fast abort. R — Function reserved. R — Function reserved. R — Function reserved. ENET_CRS — Ethernet Carrier Sense (MII interface). R — Function reserved. SSP0_SSEL — Slave Select for SSP0. GPIO4[13] — General purpose digital input/output pin. MCOA2 — Motor control PWM channel 2, output A. R — Function reserved. R — Function reserved. I2S0_TX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. ENET_RX_ER — Ethernet receive error (MII interface). R — Function reserved. SSP0_MISO — Master In Slave Out for SSP0. GPIO4[14] — General purpose digital input/output pin. MCOB2 — Motor control PWM channel 2, output B. R — Function reserved. R — Function reserved. I2S0_TX_SDA — I2S transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. ENET_RXD3 — Ethernet receive data 3 (MII interface). R — Function reserved. SSP0_MOSI — Master Out Slave in for SSP0. GPIO4[15] — General purpose digital input/output pin. MCOA0 — Motor control PWM channel 0, output A. USB1_IND1 — USB1 Port indicator LED control output 1. R — Function reserved. R — Function reserved. ENET_RXD2 — Ethernet receive data 2 (MII interface). R — Function reserved. U3_TXD — Transmitter output for USART3. FT D R A P9_1 N6 x - x - [3] I; PU I/O O I/O I I/O P9_2 N8 x x [3] I; PU I/O O I/O I I/O P9_3 M6 x x [3] I; PU I/O O O I O All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 160 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 12: LPC18xx Pin configuration FT D R A D R A R A FT D R FT Table 107. Pin description …continued LQFP208[1] BGA180[1] BGA100[1] LBGA256 Symbol LQFP144 Reset state [2] D R R A R A A Type Description FT D R R A FT D R A A F FT D FT D P9_4 N10 x - x - [3] I; PU O O I/O O I R — Function reserved. MCOB0 — Motor control PWM channel 0, output B. USB1_IND0 — USB1 Port indicator LED control output 0. R — Function reserved. GPIO5[17] — General purpose digital input/output pin. ENET_TXD2 — Ethernet transmit data 2 (MII interface). R — Function reserved. U3_RXD — Receiver input for USART3. R — Function reserved. MCOA1 — Motor control PWM channel 1, output A. USB1_VBUS_EN — USB1 VBUS power enable. R — Function reserved. GPIO5[18] — General purpose digital input/output pin. ENET_TXD3 — Ethernet transmit data 3 (MII interface). R — Function reserved. U0_TXD — Transmitter output for USART0. GPIO4[11] — General purpose digital input/output pin. MCOB1 — Motor control PWM channel 1, output B. USB1_PWR_FAULT — USB1 Port power fault signal indicating over-current condition; this signal monitors over-current on the USB1 bus (external circuitry required to detect over-current condition). R — Function reserved. R — Function reserved. ENET_COL — Ethernet Collision detect (MII interface). R — Function reserved. U0_RXD — Receiver input for USART0. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. I2S1_RX_MCLK — I2S1 receive master clock. CGU_OUT1 — CGU spare clock output 1. R — Function reserved. FT D R A P9_5 M9 x - x 69 [3] I; PU O O I/O O O P9_6 L11 x - x 72 [3] I; PU I/O O O I I PA_0 L12 x x [3] I; PU O O - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 161 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 12: LPC18xx Pin configuration FT D R A D R A R A FT D R FT Table 107. Pin description …continued LQFP208[1] BGA180[1] BGA100[1] LBGA256 Symbol LQFP144 Reset state [2] D R R A R A A Type Description FT D R R A FT D R A A F FT D FT D PA_1 J14 x - x - [4] I; PU I/O I O - GPIO4[8] — General purpose digital input/output pin. QEI_IDX — Quadrature Encoder Interface INDEX input. R — Function reserved. U2_TXD — Transmitter output for USART2. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. GPIO4[9] — General purpose digital input/output pin. QEI_PHB — Quadrature Encoder Interface PHB input. R — Function reserved. U2_RXD — Receiver input for USART2. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. GPIO4[10] — General purpose digital input/output pin. QEI_PHA — Quadrature Encoder Interface PHA input. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. CTOUT_9 — SCT output 9. Match output 1 of timer 2. R — Function reserved. EMC_A23 — External memory address line 23. GPIO5[19] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. FT D R A PA_2 K15 x - x - [4] I; PU I/O I I - PA_3 H11 x - x - [4] I; PU I/O I - PA_4 G13 x - x - [3] I; PU O I/O I/O - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 162 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 12: LPC18xx Pin configuration FT D R A D R A R A FT D R FT Table 107. Pin description …continued LQFP208[1] BGA180[1] BGA100[1] LBGA256 Symbol LQFP144 Reset state [2] D R R A R A A Type Description FT D R R A FT D R A A F FT D FT D PB_0 B15 x - x - [3] I; PU O O I/O - R — Function reserved. CTOUT_10 — SCT output 10. Match output 2 of timer 2. LCD_VD23 — LCD data. R — Function reserved. GPIO5[20] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. USB1_ULPI_DIR — ULPI link DIR signal. Controls the ULP data line direction. LCD_VD22 — LCD data. R — Function reserved. GPIO5[21] — General purpose digital input/output pin. CTOUT_6 — SCT output 6. Match output 2 of timer 1. R — Function reserved. R — Function reserved. R — Function reserved. USB1_ULPI_D7 — ULPI link bidirectional data line 7. LCD_VD21 — LCD data. R — Function reserved. GPIO5[22] — General purpose digital input/output pin. CTOUT_7 — SCT output 7. Match output 3 of timer 1. R — Function reserved. R — Function reserved. R — Function reserved. USB1_ULPI_D6 — ULPI link bidirectional data line 6. LCD_VD20 — LCD data. R — Function reserved. GPIO5[23] — General purpose digital input/output pin. CTOUT_8 — SCT output 8. Match output 0 of timer 2. R — Function reserved. R — Function reserved. FT D R A PB_1 A14 x - x - [3] I; PU I O I/O O - PB_2 B12 x - x - [3] I; PU I/O O I/O O - PB_3 A13 x - x - [3] I; PU I/O O I/O O - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 163 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 12: LPC18xx Pin configuration FT D R A D R A R A FT D R FT Table 107. Pin description …continued LQFP208[1] BGA180[1] BGA100[1] LBGA256 Symbol LQFP144 Reset state [2] D R R A R A A Type Description FT D R R A FT D R A A F FT D FT D PB_4 B11 x - x - [3] I; PU I/O O I/O I - R — Function reserved. USB1_ULPI_D5 — ULPI link bidirectional data line 5. LCD_VD15 — LCD data. R — Function reserved. GPIO5[24] — General purpose digital input/output pin. CTIN_5 — SCT input 5. Capture input 2 of timer 2. R — Function reserved. R — Function reserved. R — Function reserved. USB1_ULPI_D4 — ULPI link bidirectional data line 4. LCD_VD14 — LCD data. R — Function reserved. GPIO5[25] — General purpose digital input/output pin. CTIN_7 — SCT input 7. LCD_PWR — LCD panel power enable. R — Function reserved. R — Function reserved. USB1_ULPI_D3 — ULPI link bidirectional data line 3. LCD_VD13 — LCD data. R — Function reserved. GPIO5[26] — General purpose digital input/output pin. CTIN_6 — SCT input 6. Capture input 1 of timer 3. LCD_VD19 — LCD data. R — Function reserved. ADC0_6 — ADC0, input channel 6. R — Function reserved. USB1_ULPI_CLK — ULPI link CLK signal. 60 MHz clock generated by the PHY. R — Function reserved. ENET_RX_CLK — Ethernet Receive Clock (MII interface). LCD_DCLK — LCD panel clock. R — Function reserved. R — Function reserved. SD_CLK — SD/MMC card clock. ADC1_1 — ADC1, input channel 1. FT D R A PB_5 A12 x - x - [3] I; PU I/O O I/O I O - PB_6 A6 x - x - [6] I; PU I/O O I/O I O I PC_0 D4 x - x - [6] I; PU I I/O O I/O I All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 164 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 12: LPC18xx Pin configuration FT D R A D R A R A FT D R FT Table 107. Pin description …continued LQFP208[1] BGA180[1] BGA100[1] LBGA256 Symbol LQFP144 Reset state [2] D R R A R A A Type Description FT D R R A FT D R A A F FT D FT D PC_1 E4 - - x - [3] I; PU I/O I O I/O I O USB1_ULPI_D7 — ULPI link bidirectional data line 7. R — Function reserved. U1_RI — Ring Indicator input for UART 1. ENET_MDC — Ethernet MIIM clock. GPIO6[0] — General purpose digital input/output pin. R — Function reserved. T3_CAP0 — Capture input 0 of timer 3. SD_VOLT0 — SD/MMC bus voltage select output 0. USB1_ULPI_D6 — ULPI link bidirectional data line 6. R — Function reserved. U1_CTS — Clear to Send input for UART 1. ENET_TXD2 — Ethernet transmit data 2 (MII interface). GPIO6[1] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. SD_RST — SD/MMC reset signal for MMC4.4 card. USB1_ULPI_D5 — ULPI link bidirectional data line 5. R — Function reserved. U1_RTS — Request to Send output for UART 1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART 1. ENET_TXD3 — Ethernet transmit data 3 (MII interface). GPIO6[2] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. SD_VOLT1 — SD/MMC bus voltage select output 1. ADC1_0 — ADC1, input channel 0. R — Function reserved. USB1_ULPI_D4 — ULPI link bidirectional data line 4. R — Function reserved. ENET_TX_EN — Ethernet transmit enable (RMII/MII interface). FT D R A PC_2 F6 - - x - [3] I; PU I/O I O I/O O PC_3 F5 - - x - [6] I; PU I/O O O I/O O I PC_4 F4 x [3] I; PU I/O - I/O I I/O GPIO6[3] — General purpose digital input/output pin. R — Function reserved. T3_CAP1 — Capture input 1 of timer 3. SD_DAT0 — SD/MMC data bus line 0. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 165 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 12: LPC18xx Pin configuration FT D R A D R A R A FT D R FT Table 107. Pin description …continued LQFP208[1] BGA180[1] BGA100[1] LBGA256 Symbol LQFP144 Reset state [2] D R R A R A A Type Description FT D R R A FT D R A A F FT D FT D PC_5 G4 - - x - [3] I; PU I/O O I/O I I/O R — Function reserved. USB1_ULPI_D3 — ULPI link bidirectional data line 3. R — Function reserved. ENET_TX_ER — Ethernet Transmit Error (MII interface). GPIO6[4] — General purpose digital input/output pin. R — Function reserved. T3_CAP2 — Capture input 2 of timer 3. SD_DAT1 — SD/MMC data bus line 1. R — Function reserved. USB1_ULPI_D2 — ULPI link bidirectional data line 2. R — Function reserved. ENET_RXD2 — Ethernet receive data 2 (MII interface). GPIO6[5] — General purpose digital input/output pin. R — Function reserved. T3_CAP3 — Capture input 3 of timer 3. SD_DAT2 — SD/MMC data bus line 2. R — Function reserved. USB1_ULPI_D1 — ULPI link bidirectional data line 1. R — Function reserved. ENET_RXD3 — Ethernet receive data 3 (MII interface). GPIO6[6] — General purpose digital input/output pin. R — Function reserved. T3_MAT0 — Match output 0 of timer 3. SD_DAT3 — SD/MMC data bus line 3. R — Function reserved. USB1_ULPI_D0 — ULPI link bidirectional data line 0. R — Function reserved. ENET_RX_DV — Ethernet Receive Data Valid (RMII/MII interface). GPIO6[7] — General purpose digital input/output pin. R — Function reserved. T3_MAT1 — Match output 1 of timer 3. SD_CD — SD/MMC card detect input. FT D R A PC_6 H6 - - x - [3] I; PU I/O I I/O I I/O PC_7 G5 - - - - [3] I; PU I/O I I/O O I/O PC_8 N4 - - - - [3] I; PU I/O I I/O O I All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 166 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 12: LPC18xx Pin configuration FT D R A D R A R A FT D R FT Table 107. Pin description …continued LQFP208[1] BGA180[1] BGA100[1] LBGA256 Symbol LQFP144 Reset state [2] D R R A R A A Type Description FT D R R A FT D R A A F FT D FT D PC_9 K2 - - - - [3] I; PU I I I/O O O R — Function reserved. USB1_ULPI_NXT — ULPI link NXT signal. Data flow control signal from the PHY. R — Function reserved. ENET_RX_ER — Ethernet receive error (MII interface). GPIO6[8] — General purpose digital input/output pin. R — Function reserved. T3_MAT2 — Match output 2 of timer 3. SD_POW — . R — Function reserved. USB1_ULPI_STP — ULPI link STP signal. Asserted to end or interrupt transfers to the PHY. U1_DSR — Data Set Ready input for UART 1. R — Function reserved. GPIO6[9] — General purpose digital input/output pin. R — Function reserved. T3_MAT3 — Match output 3 of timer 3. SD_CMD — SD/MMC command signal. R — Function reserved. USB1_ULPI_DIR — ULPI link DIR signal. Controls the ULP data line direction. U1_DCD — Data Carrier Detect input for UART 1. R — Function reserved. GPIO6[10] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. SD_DAT4 — SD/MMC data bus line 4. R — Function reserved. R — Function reserved. U1_DTR — Data Terminal Ready output for UART 1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART 1. R — Function reserved. GPIO6[11] — General purpose digital input/output pin. R — Function reserved. I2S0_TX_SDA — I2S transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. SD_DAT5 — SD/MMC data bus line 5. FT D R A PC_10 M5 - - - - [3] I; PU O I I/O O I/O PC_11 L5 - - - - [3] I; PU I I I/O I/O PC_12 L6 - - - - [3] I; PU O I/O I/O I/O All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 167 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 12: LPC18xx Pin configuration FT D R A D R A R A FT D R FT Table 107. Pin description …continued LQFP208[1] BGA180[1] BGA100[1] LBGA256 Symbol LQFP144 Reset state [2] D R R A R A A Type Description FT D R R A FT D R A A F FT D FT D PC_13 M1 - - - - [3] I; PU O I/O I/O R — Function reserved. R — Function reserved. U1_TXD — Transmitter output for UART 1. R — Function reserved. GPIO6[12] — General purpose digital input/output pin. R — Function reserved. I2S0_TX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. SD_DAT6 — SD/MMC data bus line 6. R — Function reserved. R — Function reserved. U1_RXD — Receiver input for UART 1. R — Function reserved. GPIO6[13] — General purpose digital input/output pin. R — Function reserved. ENET_TX_ER — Ethernet Transmit Error (MII interface). SD_DAT7 — SD/MMC data bus line 7. R — Function reserved. CTOUT_15 — SCT output 15. Match output 3 of timer 3. EMC_DQMOUT2 — Data mask 2 used with SDRAM and static devices. R — Function reserved. GPIO6[14] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. EMC_CKEOUT2 — SDRAM clock enable 2. R — Function reserved. GPIO6[15] — General purpose digital input/output pin. SD_POW — . R — Function reserved. R — Function reserved. FT D R A I/O PC_14 N1 [3] I; PU I I/O O I/O PD_0 N2 - - - - [3] I; PU O O I/O - PD_1 P1 - - - - [3] I; PU O I/O O - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 168 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 12: LPC18xx Pin configuration FT D R A D R A R A FT D R FT Table 107. Pin description …continued LQFP208[1] BGA180[1] BGA100[1] LBGA256 Symbol LQFP144 Reset state [2] D R R A R A A Type Description FT D R R A FT D R A A F FT D FT D PD_2 R1 - - - - [3] I; PU O I/O I/O - R — Function reserved. CTOUT_7 — SCT output 7. Match output 3 of timer 1. EMC_D16 — External memory data line 16. R — Function reserved. GPIO6[16] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. CTOUT_6 — SCT output 7. Match output 2 of timer 1. EMC_D17 — External memory data line 17. R — Function reserved. GPIO6[17] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. CTOUT_8 — SCT output 8. Match output 0 of timer 2. EMC_D18 — External memory data line 18. R — Function reserved. GPIO6[18] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. CTOUT_9 — SCT output 9. Match output 1 of timer 2. EMC_D19 — External memory data line 19. R — Function reserved. GPIO6[19] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. FT D R A PD_3 P4 - - - - [3] I; PU O I/O I/O - PD_4 T2 - - - - [3] I; PU O I/O I/O - PD_5 P6 - - - - [3] I; PU O I/O I/O - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 169 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 12: LPC18xx Pin configuration FT D R A D R A R A FT D R FT Table 107. Pin description …continued LQFP208[1] BGA180[1] BGA100[1] LBGA256 Symbol LQFP144 Reset state [2] D R R A R A A Type Description FT D R R A FT D R A A F FT D FT D PD_6 R6 - - x - [3] I; PU O I/O I/O - R — Function reserved. CTOUT_10 — SCT output 10. Match output 2 of timer 2. EMC_D20 — External memory data line 20. R — Function reserved. GPIO6[20] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. CTIN_5 — SCT input 5. Capture input 2 of timer 2. EMC_D21 — External memory data line 21. R — Function reserved. GPIO6[21] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. CTIN_6 — SCT input 6. Capture input 1 of timer 3. EMC_D22 — External memory data line 22. R — Function reserved. GPIO6[22] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. CTOUT_13 — SCT output 13. Match output 1 of timer 3. EMC_D23 — External memory data line 23. R — Function reserved. GPIO6[23] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. FT D R A PD_7 T6 - - x - [3] I; PU I I/O I/O - PD_8 P8 - - x - [3] I; PU I I/O I/O - PD_9 T11 - - x - [3] I; PU O I/O I/O - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 170 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 12: LPC18xx Pin configuration FT D R A D R A R A FT D R FT Table 107. Pin description …continued LQFP208[1] BGA180[1] BGA100[1] LBGA256 Symbol LQFP144 Reset state [2] D R R A R A A Type Description FT D R R A FT D R A A F FT D FT D PD_10 P11 - - x - [3] I; PU I R — Function reserved. CTIN_1 — SCT input 1. Capture input 1 of timer 0. Capture input 1 of timer 2. EMC_BLS3 — LOW active Byte Lane select signal 3. R — Function reserved. GPIO6[24] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. EMC_CS3 — LOW active Chip Select 3 signal. R — Function reserved. GPIO6[25] — General purpose digital input/output pin. USB1_ULPI_D0 — ULPI link bidirectional data line 0. CTOUT_14 — SCT output 14. Match output 2 of timer 3. R — Function reserved. R — Function reserved. R — Function reserved. EMC_CS2 — LOW active Chip Select 2 signal. R — Function reserved. GPIO6[26] — General purpose digital input/output pin. R — Function reserved. CTOUT_10 — SCT output 10. Match output 2 of timer 2. R — Function reserved. R — Function reserved. CTIN_0 — SCT input 0. Capture input 0 of timer 0, 1, 2, 3. EMC_BLS2 — LOW active Byte Lane select signal 2. R — Function reserved. GPIO6[27] — General purpose digital input/output pin. R — Function reserved. CTOUT_13 — SCT output 13. Match output 1 of timer 3. R — Function reserved. FT D R A O I/O PD_11 N9 x x [3] I; PU O I/O I/O O - PD_12 N11 x - x - [3] I; PU O I/O O - PD_13 T14 x - - - [3] I; PU I O I/O O - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 171 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 12: LPC18xx Pin configuration FT D R A D R A R A FT D R FT Table 107. Pin description …continued LQFP208[1] BGA180[1] BGA100[1] LBGA256 Symbol LQFP144 Reset state [2] D R R A R A A Type Description FT D R R A FT D R A A F FT D FT D PD_14 R13 x - x - [3] I; PU O I/O O - R — Function reserved. R — Function reserved. EMC_DYCS2 — SDRAM chip select 2. R — Function reserved. GPIO6[28] — General purpose digital input/output pin. R — Function reserved. CTOUT_11 — SCT output 11. Match output 3 of timer 2. R — Function reserved. R — Function reserved. R — Function reserved. EMC_A17 — External memory address line 17. R — Function reserved. GPIO6[29] — General purpose digital input/output pin. SD_WP — SD/MMC card write protect input. CTOUT_8 — SCT output 8. Match output 0 of timer 2. R — Function reserved. R — Function reserved. R — Function reserved. EMC_A16 — External memory address line 16. R — Function reserved. GPIO6[30] — General purpose digital input/output pin. SD_VOLT2 — SD/MMC bus voltage select output 2. CTOUT_12 — SCT output 12. Match output 0 of timer 3. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. EMC_A18 — External memory address line 18. GPIO7[0] — General purpose digital input/output pin. CAN1_TD — CAN1 transmitter output. R — Function reserved. R — Function reserved. FT D R A PD_15 T15 x - x - [3] I; PU I/O I/O I O - PD_16 R14 x - x - [3] I; PU I/O I/O O O - PE_0 P14 x - x - [3] I; PU I/O I/O O - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 172 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 12: LPC18xx Pin configuration FT D R A D R A R A FT D R FT Table 107. Pin description …continued LQFP208[1] BGA180[1] BGA100[1] LBGA256 Symbol LQFP144 Reset state [2] D R R A R A A Type Description FT D R R A FT D R A A F FT D FT D PE_1 N14 x - x - [3] I; PU I/O I/O I - R — Function reserved. R — Function reserved. R — Function reserved. EMC_A19 — External memory address line 19. GPIO7[1] — General purpose digital input/output pin. CAN1_RD — CAN1 receiver input. R — Function reserved. R — Function reserved. ADCTRIG0 — ADC trigger input 0. CAN0_RD — CAN receiver input. R — Function reserved. EMC_A20 — External memory address line 20. GPIO7[2] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. CAN0_TD — CAN transmitter output. ADCTRIG1 — ADC trigger input 1. EMC_A21 — External memory address line 21. GPIO7[3] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. NMI — External interrupt input to NMI. R — Function reserved. EMC_A22 — External memory address line 22. GPIO7[4] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. FT D R A PE_2 M14 x - x - [3] I; PU I I I/O I/O - PE_3 K12 x - x - [3] I; PU O I I/O I/O - PE_4 K13 x - x - [3] I; PU I I/O I/O - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 173 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 12: LPC18xx Pin configuration FT D R A D R A R A FT D R FT Table 107. Pin description …continued LQFP208[1] BGA180[1] BGA100[1] LBGA256 Symbol LQFP144 Reset state [2] D R R A R A A Type Description FT D R R A FT D R A A F FT D FT D PE_5 N16 - - x - [3] I; PU O O R — Function reserved. CTOUT_3 — SCT output 3. Match output 3 of timer 0. U1_RTS — Request to Send output for UART 1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART 1. EMC_D24 — External memory data line 24. GPIO7[5] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. CTOUT_2 — SCT output 2. Match output 2 of timer 0. U1_RI — Ring Indicator input for UART 1. EMC_D25 — External memory data line 25. GPIO7[6] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. CTOUT_5 — SCT output 5. Match output 1 of timer 1. U1_CTS — Clear to Send input for UART1. EMC_D26 — External memory data line 26. GPIO7[7] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. CTOUT_4 — SCT output 4. Match output 0 of timer 0. U1_DSR — Data Set Ready input for UART 1. EMC_D27 — External memory data line 27. GPIO7[8] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. FT D R A I/O I/O PE_6 M16 x [3] I; PU O I I/O I/O - PE_7 F15 - - x - [3] I; PU O I I/O I/O - PE_8 F14 - - x - [3] I; PU O I I/O I/O - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 174 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 12: LPC18xx Pin configuration FT D R A D R A R A FT D R FT Table 107. Pin description …continued LQFP208[1] BGA180[1] BGA100[1] LBGA256 Symbol LQFP144 Reset state [2] D R R A R A A Type Description FT D R R A FT D R A A F FT D FT D PE_9 E16 - - x - [3] I; PU I I I/O I/O - R — Function reserved. CTIN_4 — SCT input 4. Capture input 2 of timer 1. U1_DCD — Data Carrier Detect input for UART 1. EMC_D28 — External memory data line 28. GPIO7[9] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. CTIN_3 — SCT input 3. Capture input 1 of timer 1. U1_DTR — Data Terminal Ready output for UART 1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART 1. EMC_D29 — External memory data line 29. GPIO7[10] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. CTOUT_12 — SCT output 12. Match output 0 of timer 3. U1_TXD — Transmitter output for UART 1. EMC_D30 — External memory data line 30. GPIO7[11] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. CTOUT_11 — SCT output 11. Match output 3 of timer 2. U1_RXD — Receiver input for UART 1. EMC_D31 — External memory data line 31. GPIO7[12] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. FT D R A PE_10 E14 - - x - [3] I; PU I O I/O I/O PE_11 D16 [3] I; PU O O I/O I/O - PE_12 D15 - - - - [3] I; PU O I I/O I/O - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 175 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 12: LPC18xx Pin configuration FT D R A D R A R A FT D R FT Table 107. Pin description …continued LQFP208[1] BGA180[1] BGA100[1] LBGA256 Symbol LQFP144 Reset state [2] D R R A R A A Type Description FT D R R A FT D R A A F FT D FT D PE_13 G14 - - - - [3] I; PU O I/O O I/O - R — Function reserved. CTOUT_14 — SCT output 14. Match output 2 of timer 3. I2C1_SDA — I2C1 data input/output (this pin does not use a specialized I2C pad). EMC_DQMOUT3 — Data mask 3 used with SDRAM and static devices. GPIO7[13] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. EMC_DYCS3 — SDRAM chip select 3. GPIO7[14] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. CTOUT_0 — SCT output 0. Match output 0 of timer 0. I2C1_SCL — I2C1 clock input/output (this pin does not use a specialized I2C pad). EMC_CKEOUT3 — SDRAM clock enable 3. GPIO7[15] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. SSP0_SCK — Serial clock for SSP0. GP_CLKIN — General purpose clock input to the CGU. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. I2S1_TX_MCLK — I2S1 transmit master clock. FT D R A PE_14 C15 - - - - [3] I; PU O I/O - PE_15 E13 - - - - [3] I; PU O I/O O I/O - PF_0 D12 - - - - [3] I;IA I/O I O All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 176 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 12: LPC18xx Pin configuration FT D R A D R A R A FT D R FT Table 107. Pin description …continued LQFP208[1] BGA180[1] BGA100[1] LBGA256 Symbol LQFP144 Reset state [2] D R R A R A A Type Description FT D R R A FT D R A A F FT D FT D PF_1 E11 - - - - [3] I; PU I/O I/O - R — Function reserved. R — Function reserved. SSP0_SSEL — Slave Select for SSP0. R — Function reserved. GPIO7[16] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. U3_TXD — Transmitter output for USART3. SSP0_MISO — Master In Slave Out for SSP0. R — Function reserved. GPIO7[17] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. U3_RXD — Receiver input for USART3. SSP0_MOSI — Master Out Slave in for SSP0. R — Function reserved. GPIO7[18] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. SSP1_SCK — Serial clock for SSP1. GP_CLKIN — General purpose clock input to the CGU. TRACECLK — Trace clock. R — Function reserved. R — Function reserved. R — Function reserved. I2S0_TX_MCLK — I2S transmit master clock. I2S0_RX_SCK — I2S transmit clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. FT D R A PF_2 D11 - - x - [3] I; PU O I/O I/O - PF_3 E10 - - x - [3] I; PU I I/O I/O - PF_4 D10 x x x 120 [3] I;IA I/O I O O I/O All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 177 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 12: LPC18xx Pin configuration FT D R A D R A R A FT D R FT Table 107. Pin description …continued LQFP208[1] BGA180[1] BGA100[1] LBGA256 Symbol LQFP144 Reset state [2] D R R A R A A Type Description FT D R R A FT D R A A F FT D FT D PF_5 E9 - - x - [6] I; PU I/O I/O O I/O I R — Function reserved. U3_UCLK — Serial clock input/output for USART3 in synchronous mode. SSP1_SSEL — Slave Select for SSP1. TRACEDATA[0] — Trace data, bit 0. GPIO7[19] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. ADC1_4 — ADC1, input channel 4. R — Function reserved. U3_DIR — RS-485/EIA-485 output enable/direction control for USART3. SSP1_MISO — Master In Slave Out for SSP1. TRACEDATA[1] — Trace data, bit 1. GPIO7[20] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. I2S1_TX_SDA — I2S1 transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. ADC1_3 — ADC1, input channel 3. R — Function reserved. U3_BAUD — for USART3. SSP1_MOSI — Master Out Slave in for SSP1. TRACEDATA[2] — Trace data, bit 2. GPIO7[21] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. I2S1_TX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. ADC1_7 — ADC1, input channel 7 or band gap output. FT D R A PF_6 E7 - - x - [6] I; PU I/O I/O O I/O I/O I PF_7 B7 x [6] I; PU I/O I/O O I/O I/O I/O All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 178 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 12: LPC18xx Pin configuration FT D R A D R A R A FT D R FT Table 107. Pin description …continued LQFP208[1] BGA180[1] BGA100[1] LBGA256 Symbol LQFP144 Reset state [2] D R R A R A A Type Description FT D R R A FT D R A A F FT D FT D PF_8 E6 - - x - [6] I; PU I/O I O I/O I R — Function reserved. U0_UCLK — Serial clock input/output for USART0 in synchronous mode. CTIN_2 — SCT input 2. Capture input 2 of timer 0. TRACEDATA[3] — Trace data, bit 3. GPIO7[22] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. ADC0_2 — ADC0, input channel 2. R — Function reserved. U0_DIR — RS-485/EIA-485 output enable/direction control for USART0. CTOUT_1 — SCT output 1. Match output 1 of timer 0. R — Function reserved. GPIO7[23] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. ADC1_2 — ADC1, input channel 2. R — Function reserved. U0_TXD — Transmitter output for USART0. R — Function reserved. R — Function reserved. GPIO7[24] — General purpose digital input/output pin. R — Function reserved. SD_WP — SD/MMC card write protect input. R — Function reserved. ADC0_5 — ADC0, input channel 5. R — Function reserved. U0_RXD — Receiver input for USART0. R — Function reserved. R — Function reserved. GPIO7[25] — General purpose digital input/output pin. R — Function reserved. SD_VOLT2 — SD/MMC bus voltage select output 2. R — Function reserved. ADC1_5 — ADC1, input channel 5. FT D R A PF_9 D6 - - x - [6] I; PU I/O O I/O I PF_10 A3 - - x - [6] I; PU O I/O I I PF_11 A2 - - x - [6] I; PU I I/O O I Clock pins All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 179 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 12: LPC18xx Pin configuration FT D R A D R A R A FT D R FT Table 107. Pin description …continued LQFP208[1] BGA180[1] BGA100[1] LBGA256 Symbol LQFP144 Reset state [2] D R R A R A A Type Description FT D R R A FT D R A A F FT D FT D CLK0 N5 x x x 45 [5] O; PU O O I/O O I/O I EMC_CLK0 — SDRAM clock 0. CLKOUT — Clock output pin. R — Function reserved. R — Function reserved. SD_CLK — SD/MMC card clock. EMC_CLK01 — SDRAM clock 0 and clock 1 combined. SSP1_SCK — Serial clock for SSP1. ENET_TX_CLK (ENET_REF_CLK) — Ethernet Transmit Clock (MII interface) or Ethernet Reference Clock (RMII interface). EMC_CLK1 — SDRAM clock 1. CLKOUT — Clock output pin. R — Function reserved. R — Function reserved. R — Function reserved. CGU_OUT0 — CGU spare clock output 0. R — Function reserved. I2S1_TX_MCLK — I2S1 transmit master clock. EMC_CLK3 — SDRAM clock 3. CLKOUT — Clock output pin. R — Function reserved. R — Function reserved. SD_CLK — SD/MMC card clock. EMC_CLK23 — SDRAM clock 2 and clock 3 combined. I2S0_TX_MCLK — I2S transmit master clock. I2S1_RX_SCK — Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. EMC_CLK2 — SDRAM clock 2. CLKOUT — Clock output pin. R — Function reserved. R — Function reserved. R — Function reserved. CGU_OUT1 — CGU spare clock output 1. R — Function reserved. I2S1_RX_SCK — Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. FT D R A CLK1 T10 x - - - [5] O; PU O O O O CLK2 D14 x x x 99 [5] O; PU O O I/O O O I/O CLK3 P12 x - - - [5] O; PU O O O I/O Debug pins All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 180 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 12: LPC18xx Pin configuration FT D R A D R A R A FT D R FT Table 107. Pin description …continued LQFP208[1] BGA180[1] BGA100[1] LBGA256 Symbol LQFP144 Reset state [2] D R R A R A A Type Description FT D R R A FT D R A A F FT D FT D DBGEN TCK/SWDCLK TRST TMS/SWDIO TDO/SWO TDI USB0 pins USB0_DP USB0_DM USB0_VBUS USB0_ID USB0_RREF USB1 pins USB1_DP USB1_DM I2C-bus pins I2C0_SCL I2C0_SDA L4 J5 M4 K6 K5 J4 F2 G2 F1 H2 H1 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 28 27 29 30 31 26 18 20 21 22 24 [3] I; PD I; F I; PU I; PU O; PU I; PU - I I I I O I I/O I/O I/O I JTAG interface control signal. Also used for boundary scan. Test Clock for JTAG interface (default) or Serial Wire (SW) clock. Test Reset for JTAG interface. Test Mode Select for JTAG interface (default) or SW debug data input/output. Test Data Out for JTAG interface (default) or SW trace output. Test Data In for JTAG interface. USB0 bidirectional D+ line. USB0 bidirectional D line. VBUS pin (power on USB cable). Indicates to the transceiver whether connected to an A-device (LOW) or a B-device (HIGH). 12.0 k (accuracy 1%) on-board resistor to ground for current reference. FT D R A [3] [3] [3] [3] [3] [7] [7] [7] [8] [8] F12 G12 L15 L16 x x x x x x x x x x x x 89 90 92 93 [9] [9] I; F I; F I/O I/O I/O I/O USB1 bidirectional D+ line. USB1 bidirectional D line. I2C clock input/output. Open-drain output (for I2C-bus compliance). I2C data input/output. Open-drain output (for I2C-bus compliance). External reset input: A LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. External wake-up input; can raise an interrupt and can cause wake-up from any of the low power modes. External wake-up input; can raise an interrupt and can cause wake-up from any of the low power modes. External wake-up input; can raise an interrupt and can cause wake-up from any of the low power modes. External wake-up input; can raise an interrupt and can cause wake-up from any of the low power modes. ADC input channel 0. Shared between 10-bit ADC0/1 and DAC. [10] [10] Reset and wake-up pins RESET D9 x x x 128 [11] I; IA I WAKEUP0 WAKEUP1 WAKEUP2 WAKEUP3 ADC pins ADC0_0/ ADC1_0/DAC A9 A10 C9 D8 x x x x x - x - 130 - [11] I; IA I; IA I; IA I; IA I I I I [11] [11] [11] E3 x x x 6 [8] I; IA I All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 181 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 12: LPC18xx Pin configuration FT D R A D R A R A FT D R FT Table 107. Pin description …continued LQFP208[1] BGA180[1] BGA100[1] LBGA256 Symbol LQFP144 Reset state [2] D R R A R A A Type Description FT D R R A FT D R A A F FT D FT D ADC0_1/ ADC1_1 ADC0_2/ ADC1_2 ADC0_3/ ADC1_3 ADC0_4/ ADC1_4 ADC0_5/ ADC1_5 ADC0_6/ ADC1_6 ADC0_7/ ADC1_7 RTC RTC_ALARM RTCX1 RTCX2 C3 A4 B5 C6 B3 A5 C5 x x x x x x x x x x - x x x x x x x 2 143 139 138 144 142 136 [8] I; IA I; IA I; IA I; IA I; IA I; IA I; IA I I I I I I I ADC input channel 1. Shared between 10-bit ADC0/1. ADC input channel 2. Shared between 10-bit ADC0/1. ADC input channel 3. Shared between 10-bit ADC0/1. ADC input channel 4. Shared between 10-bit ADC0/1. ADC input channel 5. Shared between 10-bit ADC0/1. ADC input channel 6. Shared between 10-bit ADC0/1. ADC input channel 7. Shared between 10-bit ADC0/1. FT D R A [8] [8] [8] [8] [8] [8] A11 A8 B8 x x x x x x x x x 129 125 126 [11] [8] [8] - O I O RTC controlled output. Input to the RTC 32 kHz ultra-low power oscillator circuit. Output from the RTC 32 kHz ultra-low power oscillator circuit. Input to the oscillator circuit and internal clock generator circuits. Output from the oscillator amplifier. Separate analog 3.3 V power supply for driver. USB 3.3 V separate power supply voltage. Dedicated analog ground for clean reference for termination resistors. Dedicated clean analog ground for generation of reference currents and voltages. Analog power supply and ADC reference voltage. RTC power supply: 3.3 V on this pin supplies power to the RTC. Main regulator power supply. Crystal oscillator pins XTAL1 XTAL2 USB0_VDDA 3V3_DRIVER USB0 _VDDA3V3 USB0_VSSA _TERM USB0_VSSA _REF VDDA VBAT VDDREG D1 E1 F3 G3 H3 G1 B4 B10 F10, F9, L8, L7 E8 x x x x x x x x x x x x x x x x x x x x x x x x x x x 12 13 16 17 19 23 137 127 94, 131, 59, 25 x [8] - I O - [8] Power and ground pins VPP x x x - OTP programming voltage. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 182 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 12: LPC18xx Pin configuration FT D R A D R A R A FT D R FT Table 107. Pin description …continued LQFP208[1] BGA180[1] BGA100[1] LBGA256 Symbol LQFP144 Reset state [2] D R R A R A A Type Description FT D R R A FT D R A A F FT D FT D VDDIO D7, x E12, F7, F8, G10, H10, J6, J7, K7, L9, L10, N7, N13 G9, H7, J10, J11, K8 x x x 5, 36, 41, 71, 77, 107, 111, 141 - - I/O power supply. FT D R A VSS x x - [12] - - Ground. VSSIO C4, x D13, G6, G7, G8, H8, H9, J8, J9, K9, K10, M13, P7, P13 B2 B9 x x x 4, 40, 76, 109 [12] - - Ground. VSSA Not connected [1] [2] [3] [4] [5] [6] x x 135 - - Analog ground. n.c. x = available; - = not pinned out. I = input, O = output, IA = inactive; PU = pull-up enabled (weak pull-up resistor pulls up pin to VDD(IO)); F = floating 5 V tolerant pad with 15 ns glitch filter; provides digital I/O functions with TTL levels and hysteresis; normal drive strength. 5 V tolerant pad with 15 ns glitch filter providing digital I/O functions with TTL levels, and hysteresis; high drive strength. 5 V tolerant pad with 15 ns glitch filter providing high-speed digital I/O functions with TTL levels and hysteresis. 5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input or output. When configured as a ADC input or DAC output, the pin is not 5 V tolerant and the digital section of the pad must be disabled by setting the pin to an input function and disabling the pull-up resistor through the pin’s SFSP register. 5 V tolerant transparent analog pad. Transparent analog pad. Not 5 V tolerant. Pad provides USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode only). This pad is not 5 V tolerant. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. [7] [8] [9] User manual Rev. 00.13 — 20 July 2011 183 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 12: LPC18xx Pin configuration FT D R R A [10] Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus 400 kHz specification. This pad requires an external pull-up to provide output functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines. Open-drain configuration applies to all functions on this pin. [11] 5 V tolerant pad with 20 ns glitch filter; provides digital I/O functions with open-drain output with weak pull-up resistor and hysteresis. D R A R A FT D R FT D R A R A A FT D R A F FT D R A FT FT [12] For the LQFP144 package, VSSIO and VSS are connected to a common ground plane. D D R A FT D R A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 184 of 1164 D R A FT D R A FT D R A FT D R A FT D R A FT UM10430 Rev. 00.13 — 20 July 2011 D D Chapter 13: LPC18xx System Control Unit (SCU) D R A FT D D R A FT D R A FT D R A R A FT D R A R A FT D R A FT D R A F R A FT D R R D User manual FT D R A FT FT A FT 13.1 How to read this chapter D Remark: This chapter describes parts LPC1850/30/20/10 Rev ‘A’ and parts LPC18xx (with on-chip flash). For a description of the SCU for parts LPC1850/30/20/10 Rev ‘-’, see Section 42.7. The following peripherals are not available on all parts, and the corresponding bit values that select those functions in the SFSP registers are reserved: D R A FT D R A • Ethernet: available on LPC1850/30. • USB0: available on LPC1850/30/20. • USB1: available on LPC1850/30. 13.2 Basic configuration The SCU is configured as follows: • See Table 108 for clocking and power control. • The SCU is reset by the SCU_RST (reset # 9). Table 108. SCU clocking and power control Base clock Clock to SCU register interface BASE_M3_CLK Branch clock CLK_M3_SCU Maximum frequency 150 MHz 13.3 General description The system control unit determines the function and electrical mode of the digital pins. By default function 0 is selected for all pins with pull-up enabled. Remark: Analog I/Os for the ADCs and the DAC as well as several USB functions reside on separate pins and are not controlled through the SCU. 13.3.1 Digital pin function The FUNC bits in the SFSX_Y registers control the function of each pin. If the function is GPIO, the GPIOnDIR registers determine whether the pin is configured as an input or output (see Table 280). For any peripheral function, the pin direction is controlled automatically depending on the pin’s functionality. The GPIOnDIR registers have no effect for peripheral functions. 13.3.2 Digital pin mode The MODE bits in the SFSX_Y registers allow the selection of on-chip pull-up or pull-down resistors for each pin or select the repeater mode. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 185 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 13: LPC18xx System Control Unit (SCU) FT D R R A The possible on-chip resistor configurations are pull-up enabled, pull-down enabled, or no pull-up/pull-down. The default value is pull-up enabled. R A The repeater mode enables the pull-up resistor if the pin is at a logic HIGH and enables the pull-down resistor if the pin is at a logic LOW. This causes the pin to retain its last known state if it is configured as an input and is not driven externally. Repeater mode may typically be used to prevent a pin from floating (and potentially using significant power if it floats to an indeterminate state) if it is temporarily not driven. A FT D D R A R A FT D R FT D R A A FT D R A R A FT F FT D R FT D D R A 13.3.3 I2C0-bus pins The EHS bits of the SFSI2C0 register (Table 120) configure different I2C-modes: • Standard mode/Fast-mode I2C (this includes an open-drain output according to the I2C-bus specification). • Fast-mode Plus and High-speed mode (this includes an open-drain output according to the I2C-bus specification). 13.3.4 USB1 DP1/DM1 pins The input signal to the USB1 is controlled by the SFSUSB register (Table 119). The USB_ESEA bit in this register must be set to one to enable the USB1 block. 13.3.5 EMC signal delay control The SCU contains a programmable delay control for all EMC input and output data, address, and control signals. For detail on use of the EMC delay modes, see Table 271. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 186 of 1164 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx User manual Rev. 00.13 — 20 July 2011 187 of 1164 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. NXP Semiconductors 13.3.6 Pin multiplexing Table 109. Pin multiplexing Function level LBGA256 LQFP208 LQFP144 BGA180 BGA100 0 1 2 3 4 5 6 7 8 Symbol Reference P0_0 P0_1 P1_0 P1_1 P1_2 P1_3 P1_4 P1_5 L3 M2 P2 R2 R3 P5 T3 R5 x x x x x x x x x x x x x x x x x x x x x x x x 32 34 38 42 43 44 47 48 GPIO0[0] GPIO0[1] GPIO0[4] GPIO0[8] GPIO0[9] SSP1_ MISO SSP1_ MOSI CTIN_3 CTOUT_7 CTOUT_6 ENET_ RXD1 ENET_ COL EMC_A5 EMC_A6 EMC_A7 R R R R R R R EMC_OE R R R R R USB0_ IND1 R R SSP0_ SSEL SSP0_ MISO SSP0_ MOSI SSP1_ MISO SSP1_ MOSI SSP1_ SSEL R R R R R R R R R I2S0_ TX_WS ENET_ TX_EN R R R R R R I2S1_ TX_WS I2S1_ TX_SDA R R R SD_RST SD_ VOLT1 SD_POW - Table 111 Table 111 Table 111 Table 111 Table 111 Table 111 Table 111 Table 111 GPIO0[10] CTOUT_8 GPIO0[11] CTOUT_9 GPIO1[8] EMC_BLS0 USB0_ IND0 EMC_CS0 USB0_ PWR_ FAULT R USB0_ PWR_EN R R R R T0_CAP1 T0_CAP0 T0_MAT2 D D D D D R R R R R A A A A A FT FT FT FT FT D D D D R R R R A A A A F F F T T T Chapter 13: LPC18xx System Control Unit (SCU) FT D D D D R R R R A A A CTOUT_10 R P1_6 P1_7 P1_8 P1_9 P1_10 P1_11 P1_12 P1_13 P1_14 T4 T5 R7 T7 R8 T9 R9 x x x x x x x x x x x x x x x x x x x x x x x x x 49 50 51 52 53 55 56 60 61 GPIO1[9] GPIO1[0] GPIO1[1] GPIO1[2] GPIO1[3] GPIO1[4] GPIO1[5] GPIO1[6] GPIO1[7] CTIN_5 U1_DSR U1_DTR U1_RTS U1_RI U1_CTS U1_DCD U1_TXD U1_RXD R EMC_WE R R R R R R R R R SD_CMD R SD_ VOLT0 SD_D0 SD_D1 SD_D2 SD_D3 SD_CD R - Table 111 Table 111 Table 111 Table 111 Table 111 Table 111 Table 111 CTOUT_13 EMC_D0 CTOUT_12 EMC_D1 CTOUT_11 EMC_D2 CTOUT_14 EMC_D3 CTOUT_15 EMC_D4 R R R EMC_D5 EMC_D6 EMC_ D7 UM10430 FT D R A FT R10 x R11 x Table 111 Table 111 D FT R A D FT D R A FT D R D A FT D R R FT A FT R A A D F xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 109. Pin multiplexing Function level LBGA256 LQFP208 LQFP144 BGA180 BGA100 0 1 2 3 4 5 6 7 8 Symbol Reference User manual Rev. 00.13 — 20 July 2011 188 of 1164 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. NXP Semiconductors P1_15 P1_16 P1_17 P1_18 P1_19 T12 x M7 M8 x x x x x x x x x x x x 62 64 66 67 68 GPIO0[2] GPIO0[3] U2_TXD U2_RXD R R R R ENET_ RXD0 ENET_ CRS ENET_ MDIO ENET_ TXD0 R T0_MAT1 T0_MAT0 T0_CAP3 T0_MAT3 CLKOUT R R R R R ENET_ RX_DV R R I2S1_TX_ SCK - Table 111 Table 111 Table 112 Table 111 Table 111 GPIO0[12] U2_UCLK GPIO0[13] U2_DIR ENET_ TX_CLK (ENET_R EF_CLK) CAN1_TD R CAN1_RD R R I2S0_RX_ MCLK N12 x M11 x SSP1_SCK R P1_20 P2_0 P2_1 M10 x T16 x N15 x x x x x x x 70 75 81 GPIO0[15] SSP1_ SSEL R R U0_TXD U0_RXD R EMC_A13 EMC_A12 ENET_ TXD1 USB0_ PWR_EN USB0_ PWR_ FAULT USB0_ IND1 CTIN_1 CTIN_0 T0_CAP2 GPIO5[0] GPIO5[1] R R R R T3_CAP0 T3_CAP1 R ENET_ MDC R - Table 111 Table 111 D D D D D R R R R R A A A A A FT FT FT FT FT D D D D R R R R A A A A F F F T T T Chapter 13: LPC18xx System Control Unit (SCU) FT D D D D R R R R A A A Table 111 P2_2 P2_3 P2_4 M15 x J12 x x x x x x x 84 87 88 R R R U0_UCLK I2C1_SDA I2C1_SCL EMC_A11 U3_TXD U3_RXD GPIO5[2] GPIO5[3] GPIO5[4] CTOUT_6 T3_CAP2 R R T3_MAT0 T3_MAT1 R USB0_ PWR_EN USB0_ PWR_ FAULT USB0_ IND0 R R R - Table 111 Table 112 Table 112 K11 x P2_5 P2_6 P2_7 P2_8 K14 x K16 x H14 x J16 x x x x x x x x x 91 95 96 98 R R GPIO0[7] Boot pin CTIN_2 U0_DIR CTOUT_1 CTOUT_0 USB1_ VBUS EMC_A10 U3_UCLK U3_DIR ADCTRIG1 GPIO5[5] USB0_ IND0 EMC_A9 EMC_A8 GPIO5[6] R GPIO5[7] R CTIN_7 R R T3_MAT2 T3_CAP3 T3_MAT3 R Table 112 Table 111 Table 111 UM10430 FT D R D A FT D Table 111 FT R A FT D R A FT D R D A R FT D R A FT FT R A A D F xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 109. Pin multiplexing Function level LBGA256 LQFP208 LQFP144 BGA180 BGA100 0 1 2 3 4 5 6 7 8 Symbol Reference User manual Rev. 00.13 — 20 July 2011 189 of 1164 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. NXP Semiconductors P2_9 P2_10 P2_11 P2_12 P2_13 P3_0 P3_1 P3_2 P3_3 P3_4 P3_5 P3_6 P3_7 P3_8 P4_0 P4_1 P4_2 P4_3 H16 x G16 x F16 x E15 x C16 x F13 x G11 x F11 x x x x x x x x x x x x x x x - x x x x x x x x x x x x x x x x x x 102 GPIO1[10] CTOUT_3 104 GPIO0[14] CTOUT_2 105 GPIO1[11] CTOUT_5 106 GPIO1[12] CTOUT_4 108 GPIO1[13] CTIN_4 112 I2S0_RX_ I2S0_RX_ SCK MCLK 114 I2S0_TX_ WS 116 I2S0_TX_ SDA 118 R I2S0_RX_ WS I2S0_RX_ SDA R U3_BAUD U2_TXD U2_RXD R R I2S0_TX_ SCK CAN0_RD CAN0_TD EMC_A0 EMC_A1 EMC_A2 EMC_A3 EMC_A4 I2S0_TX_ MCLK USB1_ IND1 USB1_ IND0 R R R R R SSP0_ SCK GPIO5[8] GPIO5[9] R R R R R R R R R I2S0_TX_ WS I2S0_TX_ SDA SSP0_ MISO R R R R R R R R R U2_DIR R - Table 111 Table 111 Table 111 Table 111 Table 111 Table 111 Table 111 Table 111 Table 111 Table 111 U2_UCLK - LCD_VD15 R LCD_VD14 R I2S0_TX_ MCLK I2S1_RX_ SDA I2S1_RX_ WS R R R U3_UCLK U3_TXD U3_RXD U3_BAUD I2S1_TX_ SCK B14 x A15 x C12 x B13 x C11 x C10 x D5 A1 D3 C2 x x x x SSP0_SCK SPIFI_SCK CGU_ OUT1 R R SSP0_ SSEL SSP0_ MISO SSP0_ MOSI NMI LCD_VD0 LCD_VD3 LCD_VD2 SPIFI_ SIO3 SPIFI_ SIO2 SPIFI_ MISO SPIFI_ MOSI SPIFI_CS R R R R U1_TXD U1_RXD R 119 GPIO1[14] R 121 GPIO1[15] R 122 GPIO0[6] 123 R 124 R 1 3 8 7 GPIO2[0] GPIO2[1] GPIO2[2] GPIO2[3] R R R MCOA0 CTOUT_1 CTOUT_0 CTOUT_3 LCD__VD 13 LCD_VD1 2 R R R R ENET_ COL R R - D D D D D R R R R R A A A A A FT FT FT FT FT D D D D R R R R A A A A F F F T T T Chapter 13: LPC18xx System Control Unit (SCU) FT D D D D R R R R A A A Table 111 Table 111 Table 111 Table 111 Table 111 GPIO5[10] SSP0_ MOSI GPIO5[11] SSP0_ SSEL R R R R LCD_ VD13 LCD_ VD19 LCD_ VD12 LCD_ VD21 UM10430 ADC0_1 Table 111T able 114 Table 111 FT D R D A R A ADC0_0 Table 111T able 114 FT D R A FT D FT FT R A FT D R A D A FT R D R A F FT D xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 109. Pin multiplexing Function level LBGA256 LQFP208 LQFP144 BGA180 BGA100 0 1 2 3 4 5 6 7 8 Symbol Reference User manual Rev. 00.13 — 20 July 2011 190 of 1164 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. NXP Semiconductors P4_4 P4_5 P4_6 P4_7 P4_8 P4_9 P4_10 P5_0 P5_1 P5_2 P5_3 P5_4 P5_5 P5_6 P5_7 P6_0 P6_1 P6_2 P6_3 P6_4 B1 D2 C1 H4 E2 L2 M3 N3 P3 R4 T8 P9 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 9 10 11 14 15 33 35 37 39 46 54 57 58 63 65 73 74 78 79 80 GPIO2[4] GPIO2[5] GPIO2[6] CTOUT_2 CTOUT_5 CTOUT_4 LCD_VD1 LCD_FP R R R R R R LCD_VD2 U3_DIR 0 R R R R R R R R DAC - Table 111T able 118 Table 111 Table 111 Table 111 Table 111 Table 111 Table 111 Table 111 LCD_ENAB R /LCD_M R R R LCD_DCL GP_CLKIN R K R R R GPIO2[9] CTIN_5 CTIN_6 CTIN_2 MCOB2 LCD_VD9 LCD_VD11 I2S1_TX_S I2S0_TX_ CK SCK CAN1_TD CAN1_RD R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R GPIO5[12] LCD_ VD22 GPIO5[13] LCD_ VD15 GPIO5[14] LCD_ VD14 U1_DSR U1_DTR U1_RTS U1_RI U1_CTS U1_DCD U1_TXD U1_RXD T1_CAP0 T1_CAP1 T1_CAP2 T1_CAP3 T1_MAT0 T1_MAT1 T1_MAT2 T1_MAT3 LCD_VD10 R EMCEMC_ R D12 EMC_D13 EMC_D14 EMC_D15 EMC_D8 EMC_D9 EMC_D10 EMC_D11 R U0_UCLK U0_DIR R U0_TXD R R R R R R R R I2S0_RX_ WS I2S0_RX_ SDA EMC_ CS1 EMC_CAS D D D D D R R R R R A A A A A FT FT FT FT FT D D D D R R R R A A A A F F F T T T Chapter 13: LPC18xx System Control Unit (SCU) FT D D D D R R R R A A A GPIO2[10] MCI2 GPIO2[11] MCI1 GPIO2[12] MCI0 GPIO2[13] MCOB0 GPIO2[14] MCOA1 GPIO2[15] MCOB1 GPIO2[7] R GPIO3[0] GPIO3[1] GPIO3[2] GPIO3[3] MCOA2 I2S0_RX_ MCLK EMC_ DYCS1 EMC_ CKEOUT1 USB0_ PWR_EN CTIN_6 Table 111 Table 111 Table 111 Table 111 Table 111 Table 111 Table 111 Table 111 Table 111 Table 111 P10 x T13 x R12 x M12 x R15 x L13 x I2S0_RX_ R SCK R R R R T2_CAP0 T2_CAP1 T2_CAP2 R UM10430 FT D R A FT P15 x R16 x Table 111 D FT R Table 111 A FT D R A FT D R A D A FT A F A FT D R D R D R FT xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 109. Pin multiplexing Function level LBGA256 LQFP208 LQFP144 BGA180 BGA100 0 1 2 3 4 5 6 7 8 Symbol Reference User manual Rev. 00.13 — 20 July 2011 191 of 1164 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. NXP Semiconductors P6_5 P6_6 P16 x L14 x x - x x 82 83 GPIO3[4] GPIO0[5] CTOUT_6 EMC_ BLS1 EMC_A15 EMC_A14 R U0_RXD R EMC_RAS USB0_ PWR_ FAULT USB0_ IND1 USB0_ IND0 EMC_ DYCS0 R R R T2_CAP3 R R R R - Table 111 Table 111 P6_7 P6_8 P6_9 P6_10 P6_11 P6_12 P7_0 P7_1 P7_2 P7_3 P7_4 P7_5 P7_6 P7_7 J13 x x x - x x x x x x x x x x x x x x 85 86 97 R R GPIO3[5] R R R GPIO5[15] T2_MAT0 GPIO5[16] T2_MAT1 R T2_MAT2 R T2_MAT3 R R R R R R R R R U2_TXD U2_RXD R R R R ENET_ MDC R R R R R R R R R R R R R R - Table 111 Table 111 Table 111 Table 111 Table 111 Table 111 Table 111 Table 111 Table 111 Table 111 H13 x J15 x H15 x H12 x G15 x B16 x C14 x A16 x C13 x C8 A7 C7 B6 x x x x 100 GPIO3[6] 101 GPIO3[7] 103 GPIO2[8] 110 GPIO3[8] 113 GPIO3[9] MCABORT R R CTOUT_7 R R EMC_ R DQMOUT1 EMC_ CKEOUT0 R EMC_ R DQMOUT0 LCD_LE R D D D D D R R R R R A A A A A FT FT FT FT FT D D D D R R R R A A A A F F F T T T Chapter 13: LPC18xx System Control Unit (SCU) FT D D D D R R R R A A A CTOUT_14 R CTOUT_15 I2S0_TX_ WS I2S0_TX_ SDA R LCD_VD19 LCD_VD7 R LCD_VD18 LCD_VD6 R LCD_VD17 LCD_VD5 R LCD_VD16 LCD_VD4 TRACE DATA[0] LCD_VD8 LCD_LP LCD_PWR LCD_ VD23 R R TRACE DATA[1] TRACE DATA[2] TRACE DATA[3] 113 GPIO3[10] CTIN_4 117 GPIO3[11] CTIN_3 132 GPIO3[12] CTOUT_13 R 133 GPIO3[13] CTOUT_12 R 134 GPIO3[14] CTOUT_11 R 140 GPIO3[15] CTOUT_8 R ADC0_4 Table 111T able 114 ADC0_3 Table 111T able 114 Table 111 UM10430 FT D R ADC1_6 Table 111T able 116 A FT D FT R A FT D R A FT D R A D A FT A F R D A FT D R D R FT xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 109. Pin multiplexing Function level LBGA256 LQFP208 LQFP144 BGA180 BGA100 0 1 2 3 4 5 6 7 8 Symbol Reference User manual Rev. 00.13 — 20 July 2011 192 of 1164 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. NXP Semiconductors P8_0 E5 x - x - GPIO4[0] USB0_ PWR_ FAULT USB0_ IND1 USB0_ IND0 USB1_ ULPI_D2 USB1_ ULPI_D1 USB1_ ULPI_D0 USB1_ ULPI_NXT USB1_ ULPI_STP USB1_ ULPI_CLK R MCI2 R R R T0_MAT0 - Table 112 P8_1 P8_2 P8_3 P8_4 P8_5 P8_6 P8_7 P8_8 P9_0 P9_1 P9_2 P9_3 P9_4 P9_5 H5 K4 J3 J2 J1 K3 K1 L1 T1 N6 N8 M6 x x x x x x x x x x x x - x x x x x x x x x x x x x x 69 GPIO4[1] GPIO4[2] GPIO4[3] GPIO4[4] GPIO4[5] GPIO4[6] GPIO4[7] R R R R R R R R R MCI1 MCI0 R R R R R R R R R R R R R CGU_ OUT0 R R R R R R T0_MAT1 T0_MAT2 T0_MAT3 T0_CAP0 T0_CAP1 T0_CAP2 T0_CAP3 I2S1_TX_ MCLK SSP0_ SSEL SSP0_ MISO SSP0_ MOSI U3_TXD U3_RXD U0_TXD - Table 112 Table 112 Table 111 Table 111 Table 111 Table 111 LCD_VD12 LCD_ VD19 LCD_VD7 LCD_VD6 LCD_VD5 LCD_VD4 R R R R R R R LCD_ VD16 LCD_VD8 R LCD_LP LCD_ PWR R R I2S0_TX_ WS I2S0_TX_ SDA R R R R ENET_ CRS ENET_ RX_ER ENET_ RXD3 ENET_ RXD2 D D D D D R R R R R A A A A A FT FT FT FT FT D D D D R R R R A A A A F F F T T T Chapter 13: LPC18xx System Control Unit (SCU) FT D D D D R R R R A A A Table 111 Table 111 Table 111 Table 111 Table 111 Table 111 Table 111 GPIO4[12] MCABORT R GPIO4[13] MCOA2 GPIO4[14] MCOB2 GPIO4[15] MCOA0 R R MCOB0 MCOA1 R R USB1_ IND1 USB1_ IND0 USB1_ VBUS_EN UM10430 FT N10 x M9 x GPIO5[17] ENET_ TXD2 GPIO5[18] ENET_ TXD3 D R Table 111 A FT D R A FT D R A FT D R A D A FT A F R R D A FT D R D FT FT xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 109. Pin multiplexing Function level LBGA256 LQFP208 LQFP144 BGA180 BGA100 0 1 2 3 4 5 6 7 8 Symbol Reference User manual Rev. 00.13 — 20 July 2011 193 of 1164 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. NXP Semiconductors P9_6 L11 x - x 72 GPIO4[11] MCOB1 USB1_ PWR_FAU LT R R R R R R R ENET_ COL R U0_RXD - Table 111 PA_0 PA_1 PA_2 PA_3 PA_4 PB_0 PB_1 PB_2 PB_3 PB_4 PB_5 PB_6 PC_0 PC_1 PC_2 PC_3 L12 J14 x x - x x x x x x x x x x x x x x x x - R GPIO4[8] GPIO4[9] R R R R R R R R R USB1_ ULPI_D7 USB1_ ULPI_D6 USB1_ ULPI_D5 R QEI_IDX QEI_PHB CTOUT_9 USB1_ ULPI_DIR USB1_ ULPI_D7 USB1_ ULPI_D6 USB1_ ULPI_D5 USB1_ ULPI_D4 USB1_ ULPI_D3 USB1_ ULPI_CLK R R R R U2_TXD U2_RXD R EMC_A23 R R R R I2S1_RX_ CGU_ MCLK OUT1 R R R R R R R R R R R R R R R R R R - Table 111 Table 112 Table 112 Table 112 Table 111 Table 111 Table 111 Table 111 Table 111 Table 111 Table 111 K15 x H11 x G13 x B15 x A14 x B12 x A13 x B11 x A12 x A6 D4 E4 F6 F5 x x - GPIO4[10] QEI_PHA GPIO5[19] R GPIO5[20] R CTOUT_10 LCD_VD23 R LCD_VD22 R LCD_VD21 R LCD_VD20 R LCD_VD15 R LCD_VD14 R LCD_VD13 R R U1_RI U1_CTS U1_RTS GPIO5[21] CTOUT_6 R GPIO5[22] CTOUT_7 R GPIO5[23] CTOUT_8 R GPIO5[24] CTIN_5 GPIO5[25] CTIN_7 GPIO5[26] CTIN_6 R R R R R D D D D D R R R R R A A A A A FT FT FT FT FT D D D D R R R R A A A A F F F T T T Chapter 13: LPC18xx System Control Unit (SCU) FT D D D D R R R R A A A LCD_PWR R LCD_VD19 R R T3_CAP0 R R SD_CLK SD_ VOLT0 SD_RST SD_ VOLT1 ADC0_6 Table 111T able 114 ADC1_1 Table 111T able 116 Table 111 Table 111 ENET_RX_ LCD_ CLK DCLK ENET_ MDC ENET_ TXD2 ENET_ TXD3 GPIO6[0] GPIO6[1] GPIO6[2] UM10430 FT D R ADC1_0 Table 111T able 116 A FT D R A D FT D R A FT D R A D A FT A F R R D R A FT D FT FT xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 109. Pin multiplexing Function level LBGA256 LQFP208 LQFP144 BGA180 BGA100 0 1 2 3 4 5 6 7 8 Symbol Reference User manual Rev. 00.13 — 20 July 2011 194 of 1164 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. NXP Semiconductors PC_4 PC_5 PC_6 PC_7 PC_8 PC_9 F4 G4 H6 G5 N4 K2 - - x x x x - R R R R R R R R R R R R R R R R R R USB1_ ULPI_D4 USB1_ ULPI_D3 USB1_ ULPI_D2 USB1_ ULPI_D1 USB1_ ULPI_D0 USB1_ ULPI_NXT USB1_ ULPI_STP USB1_ ULPI_DIR R R R R R R R R R U1_DSR U1_DCD U1_DTR U1_TXD U1_RXD ENET_ TX_EN ENET_ TX_ER ENET_ RXD2 ENET_ RXD3 ENET_ RX_DV ENET_ RX_ER R R R R R GPIO6[3] GPIO6[4] GPIO6[5] GPIO6[6] GPIO6[7] GPIO6[8] GPIO6[9] R R R R R R R T3_CAP1 T3_CAP2 T3_CAP3 T3_MAT0 T3_MAT1 T3_MAT2 T3_MAT3 R SD_D0 SD_D1 SD_D2 SD_D3 SD_CD SD_POW SD_CMD SD_D4 - Table 111 Table 111 Table 111 Table 111 Table 111 Table 111 Table 111 Table 111 Table 111 Table 111 Table 111 Table 111 Table 111 Table 111 Table 111 Table 111 PC_10 M5 PC_11 L5 PC_12 L6 PC_13 M1 PC_14 N1 PD_0 PD_1 PD_2 PD_3 PD_4 PD_5 PD_6 N2 P1 R1 P4 T2 P6 R6 GPIO6[10] R GPIO6[11] R GPIO6[12] R GPIO6[13] R GPIO6[14] R GPIO6[15] SD_POW GPIO6[16] R GPIO6[17] R GPIO6[18] R GPIO6[19] R GPIO6[20] R D D D D D R R R R R A A A A A FT FT FT FT FT D D D D R R R R A A A A F F F T T T Chapter 13: LPC18xx System Control Unit (SCU) FT D D D D R R R R A A A I2S0_TX_S SD_D5 DA I2S0_TX_ WS ENET_ TX_ER R R R R R R R SD_D6 SD_D7 R R R R R R R CTOUT_15 EMC_ R DQMOUT2 R CTOUT_7 CTOUT_6 CTOUT_8 CTOUT_9 EMC_ CKEOUT2 EMC_D16 EMC_D17 EMC_D18 EMC_D19 R R R R R R UM10430 FT D R D A Table 111 FT D FT R A FT CTOUT_10 EMC_D20 Table 111 R A D R A FT D FT D R A D R FT FT R A A D F xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 109. Pin multiplexing Function level LBGA256 LQFP208 LQFP144 BGA180 BGA100 0 1 2 3 4 5 6 7 8 Symbol Reference User manual Rev. 00.13 — 20 July 2011 195 of 1164 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. NXP Semiconductors PD_7 PD_8 PD_9 T6 P8 T11 x - x x x x x x x x x x x x x x x x x x x x - - R R R R R R R R R R R R ADC TRIG0 R R R R R R R R R R R CTIN_5 CTIN_6 CTIN_1 R R CTIN_0 R R R R R CAN0_RD CAN0_TD NMI CTOUT_3 CTOUT_2 CTOUT_5 CTOUT_4 CTIN_4 CTIN_3 EMC_D21 EMC_D22 R R R R R R R R EMC_A18 EMC_A19 EMC_A20 GPIO6[21] R GPIO6[22] R GPIO6[23] R GPIO6[24] R GPIO6[25] USB1_ ULPI_D0 GPIO6[26] R GPIO6[27] R GPIO6[28] R GPIO6[29] SD_WP GPIO6[30] SD_ VOLT2 GPIO7[0] GPIO7[1] GPIO7[2] GPIO7[3] GPIO7[4] GPIO7[5] GPIO7[6] GPIO7[7] GPIO7[8] GPIO7[9] R R R R R R R R - Table 111 Table 111 Table 111 Table 111 Table 111 Table 111 Table 111 Table 111 Table 111 Table 111 Table 111 Table 111 Table 111 Table 111 Table 111 Table 111 Table 111 Table 111 Table 111 Table 111 Table 111 Table 111 CTOUT_13 EMC_D23 EMC_CS3 EMC_CS2 EMC_ DYCS2 EMC_A17 EMC_A16 R R R PD_10 P11 PD_11 N9 EMC_BLS3 R CTOUT_14 R CTOUT_10 R CTOUT_13 R CTOUT_11 R CTOUT_8 R PD_12 N11 x PD_13 T14 x PD_14 R13 x PD_15 T15 x PD_16 R14 x PE_0 PE_1 PE_2 PE_3 PE_4 PE_5 PE_6 PE_7 PE_8 PE_9 P14 x N14 x M14 x K12 x K13 x N16 M16 F15 F14 E16 - EMC_BLS2 R CTOUT_12 R R R R R R R R R R R R R R R CAN1_TD R CAN1_RD R R R R R R R R R R R R R R R R R R R R R D D D D D R R R R R A A A A A FT FT FT FT FT D D D D R R R R A A A A F F F T T T Chapter 13: LPC18xx System Control Unit (SCU) FT D D D D R R R R A A A ADCTRIG1 EMC_A21 R U1_RTS U1_RI U1_CTS U1_DSR U1_DCD U1_DTR EMC_A22 EMC_D24 EMC_D25 EMC_D26 EMC_D27 EMC_D28 EMC_D29 EMC_D30 EMC_D31 UM10430 PE_10 E14 PE_11 D16 PE_12 D15 PE_13 G14 - GPIO7[10] R GPIO7[11] R GPIO7[12] R FT D CTOUT_12 U1_TXD CTOUT_11 U1_RXD CTOUT_14 I2C1_SDA R Table 111 A FT D FT R EMC_ GPIO7[13] R DQMOUT3 Table 111 A D FT D R A FT D R D A FT D R R FT A FT R A A D F xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 109. Pin multiplexing Function level LBGA256 LQFP208 LQFP144 BGA180 BGA100 0 1 2 3 4 5 6 7 8 Symbol Reference User manual Rev. 00.13 — 20 July 2011 196 of 1164 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. NXP Semiconductors PE_14 C15 PE_15 E13 PF_0 PF_1 PF_2 PF_3 PF_4 PF_5 PF_6 PF_7 PF_8 PF_9 D12 E11 D11 E10 D10 x E9 E7 B7 E6 D6 - x - x x x x x x x x x x - R R SSP0_ SCK R R R R CTOUT_0 R I2C1_SCL EMC_ DYCS3 EMC_ CKEOUT3 R R R R R TRACE DATA[0] TRACE DATA[1] TRACE DATA[2] TRACE DATA[3] R R R GPIO7[14] R GPIO7[15] R R R R R R R R R I2S0_TX_ MCLK R R R R R SD_WP SD_ VOLT2 R R I2S1_TX_ MCLK R R R - Table 111 Table 111 Table 111 Table 111 Table 111 Table 111 Table 111 GP_CLKIN R R U3_TXD U3_RXD SSP0_ SSEL SSP0_ MISO SSP0_ MOSI GPIO7[16] R GPIO7[17] R GPIO7[18] R R R 120 SSP1_ SCK R R R R R R R GP_CLKIN TRACE CLK U3_UCLK U3_DIR U3_BAUD U0_UCLK U0_DIR U0_TXD U0_RXD SSP1_ SSEL SSP1_ MISO SSP1_ MOSI CTIN_2 CTOUT_1 R R I2S0_RX_ SCK R I2S1_TX_ SDA I2S1_TX_ WS R R R R GPIO7[19] R GPIO7[20] R GPIO7[21] R GPIO7[22] R GPIO7[23] R GPIO7[24] R GPIO7[25] R ADC1_4 Table 111T able 116 ADC1_3 Table 111T able 116 ADC1_7 Table 111T able 116 ADC0_2 Table 111T able 114 ADC1_2 Table 111T able 116 ADC0_5 Table 111T able 114 ADC1_5 Table 111T able 116 Table 111 D D D D D R R R R R A A A A A FT FT FT FT FT D D D D R R R R A A A A F F F T T T Chapter 13: LPC18xx System Control Unit (SCU) FT D D D D R R R R A A A PF_10 A3 PF_11 Clock pins A2 UM10430 FT D R D A R A FT D R A FT D R A FT D R A D A FT A F R R D FT FT FT D xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 109. Pin multiplexing Function level LBGA256 LQFP208 LQFP144 BGA180 BGA100 0 1 2 3 4 5 6 7 8 Symbol Reference User manual Rev. 00.13 — 20 July 2011 197 of 1164 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. NXP Semiconductors CLK0 N5 x x x 45 EMC_CLK CLKOUT 0 R R SD_ CLK EMC_ CLK01 SSP1_SCK ENET_ TX_CLK (ENET_R EF_CLK) R I2S0_TX_ MCLK R I2S1_TX_ MCLK - Table 111 CLK1 CLK2 CLK3 T10 x D14 x P12 x x - x - 99 - EMC_ CLK1 EMC_ CLK3 EMC_ CLK2 CLKOUT CLKOUT CLKOUT R R R R R R R SD_CLK R CGU_OU T0 EMC_ CLK23 CGU_ OUT1 - Table 111 Table 111 Table 111 I2S1_RX_ SCK I2S1_RX_ SCK D D D D D R R R R R A A A A A FT FT FT FT FT D D D D R R R R A A A A F F F T T T Chapter 13: LPC18xx System Control Unit (SCU) FT D D D D R R R R A A A UM10430 FT D R A FT D R A FT D R A FT D R A D A FT A F R R D A FT D R D FT FT xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx User manual Rev. 00.13 — 20 July 2011 198 of 1164 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. NXP Semiconductors 13.4 Register description Table 110. Register overview: System Control Unit (SCU) (base address 0x4008 6000) Name Pins P0_n SFSP0_0 SFSP0_1 Pins P1_n SFSP1_0 SFSP1_1 SFSP1_2 SFSP1_3 SFSP1_4 SFSP1_5 SFSP1_6 SFSP1_7 SFSP1_8 SFSP1_9 SFSP1_10 SFSP1_11 SFSP1_12 SFSP1_13 SFSP1_14 SFSP1_15 SFSP1_16 SFSP1_17 SFSP1_18 SFSP1_19 SFSP1_20 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0x080 0x084 0x088 0x08C 0x090 0x094 0x098 0x09C 0x0A0 0x0A4 0x0A8 0x0AC 0x0B0 0x0B4 0x0B8 0x0BC 0x0C0 0x0C4 0x0C8 0x0CC 0x0D0 Pin configuration register for pin P1_0 Pin configuration register for pin P1_1 Pin configuration register for pin P1_2 Pin configuration register for pin P1_3 Pin configuration register for pin P1_4 Pin configuration register for pin P1_5 Pin configuration register for pin P1_6 Pin configuration register for pin P1_7 Pin configuration register for pin P1_8 Pin configuration register for pin P1_9 Pin configuration register for pin P1_10 Pin configuration register for pin P1_11 Pin configuration register for pin P1_12 Pin configuration register for pin P1_13 Pin configuration register for pin P1_14 Pin configuration register for pin P1_15 Pin configuration register for pin P1_16 Pin configuration register for pin P1_17 Pin configuration register for pin P1_18 Pin configuration register for pin P1_19 Pin configuration register for pin P1_20 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 R/W R/W 0x000 0x004 0x008 0x07C Pin configuration register for pin P0_0 Pin configuration register for pin P0_1 Reserved 0x00 0x00 Access Address offset Description Reset value D D D D D R R R R R A A A A A FT FT FT FT FT D D D D R R R R A A A A F F F T T T Chapter 13: LPC18xx System Control Unit (SCU) FT D D D D R R R R A A A UM10430 FT D R A FT D R A FT D R A FT D R A D A FT A F R R D A FT D R D FT FT D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 13: LPC18xx System Control Unit (SCU) FT D R R A Table 110. Register overview: System Control Unit (SCU) (base address 0x4008 6000) D R A R A FT D R FT D R A R A A …continued FT F FT Name Pins P2_n SFSP2_0 SFSP2_1 SFSP2_2 SFSP2_3 SFSP2_4 SFSP2_5 SFSP2_6 SFSP2_7 SFSP2_8 SFSP2_9 SFSP2_10 SFSP2_11 SFSP2_12 SFSP2_13 Pins P3_n SFSP3_0 SFSP3_1 SFSP3_2 SFSP3_3 SFSP3_4 SFSP3_5 SFSP3_6 SFSP3_7 SFSP3_8 Pins P4_n SFSP4_0 SFSP4_1 SFSP4_2 SFSP4_3 SFSP4_4 SFSP4_5 SFSP4_6 SFSP4_7 Access - Address offset 0x0D4 0x0FC 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x17C 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1FC 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C Description Reserved Reset value - D D R R A A FT D A FT D R A FT D R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W - Pin configuration register for pin P2_0 Pin configuration register for pin P2_1 Pin configuration register for pin P2_2 Pin configuration register for pin P2_3 Pin configuration register for pin P2_4 Pin configuration register for pin P2_5 Pin configuration register for pin P2_6 Pin configuration register for pin P2_7 Pin configuration register for pin P2_8 Pin configuration register for pin P2_9 Pin configuration register for pin P2_10 Pin configuration register for pin P2_11 Pin configuration register for pin P2_12 Pin configuration register for pin P2_13 Reserved 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 - R/W R/W R/W R/W R/W R/W R/W R/W R/W - Pin configuration register for pin P3_0 Pin configuration register for pin P3_1 Pin configuration register for pin P3_2 Pin configuration register for pin P3_3 Pin configuration register for pin P3_4 Pin configuration register for pin P3_5 Pin configuration register for pin P3_6 Pin configuration register for pin P3_7 Pin configuration register for pin P3_8 Reserved 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 - R/W R/W R/W R/W R/W R/W R/W R/W Pin configuration register for pin P4_0 Pin configuration register for pin P4_1 Pin configuration register for pin P4_2 Pin configuration register for pin P4_3 Pin configuration register for pin P4_4 Pin configuration register for pin P4_5 Pin configuration register for pin P4_6 Pin configuration register for pin P4_7 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 199 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 13: LPC18xx System Control Unit (SCU) FT D R R A Table 110. Register overview: System Control Unit (SCU) (base address 0x4008 6000) D R A R A FT D R FT D R A R A A …continued FT F FT Name SFSP4_8 SFSP4_9 SFSP4_10 Pins P5_n SFSP5_0 SFSP5_1 SFSP5_2 SFSP5_3 SFSP5_4 SFSP5_5 SFSP5_6 SFSP5_7 Pins P6_n SFSP6_0 SFSP6_1 SFSP6_2 SFSP6_3 SFSP6_4 SFSP6_5 SFSP6_6 SFSP6_7 SFSP6_8 SFSP6_9 SFSP6_10 SFSP6_11 SFSP6_12 Pins P7_n SFSP7_0 SFSP7_1 SFSP7_2 SFSP7_3 SFSP7_4 SFSP7_5 SFSP7_6 Access R/W R/W R/W - Address offset 0x220 0x224 0x228 0x22C 0x27C 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2FC 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x37C 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 Description Pin configuration register for pin P4_8 Pin configuration register for pin P4_9 Pin configuration register for pin P4_10 Reserved Reset value D D R R - A 0x00 0x00 0x00 A FT D A FT D R A FT D R R/W R/W R/W R/W R/W R/W R/W R/W - Pin configuration register for pin P5_0 Pin configuration register for pin P5_1 Pin configuration register for pin P5_2 Pin configuration register for pin P5_3 Pin configuration register for pin P5_4 Pin configuration register for pin P5_5 Pin configuration register for pin P5_6 Pin configuration register for pin P5_7 Reserved 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 - R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W - Pin configuration register for pin P6_0 Pin configuration register for pin P6_1 Pin configuration register for pin P6_2 Pin configuration register for pin P6_3 Pin configuration register for pin P6_4 Pin configuration register for pin P6_5 Pin configuration register for pin P6_6 Pin configuration register for pin P6_7 Pin configuration register for pin P6_8 Pin configuration register for pin P6_9 Pin configuration register for pin P6_10 Pin configuration register for pin P6_11 Pin configuration register for pin P6_12 Reserved 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 - R/W R/W R/W R/W R/W R/W R/W Pin configuration register for pin P7_0 Pin configuration register for pin P7_1 Pin configuration register for pin P7_2 Pin configuration register for pin P7_3 Pin configuration register for pin P7_4 Pin configuration register for pin P7_5 Pin configuration register for pin P7_6 0x00 0x00 0x00 0x00 0x00 0x00 0x00 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 200 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 13: LPC18xx System Control Unit (SCU) FT D R R A Table 110. Register overview: System Control Unit (SCU) (base address 0x4008 6000) D R A R A FT D R FT D R A R A A …continued FT F FT Name SFSP7_7 Pins P8_n SFSP8_0 SFSP8_1 SFSP8_2 SFSP8_3 SFSP8_4 SFSP8_5 SFSP8_6 SFSP8_7 SFSP8_8 Pins P9_n SFSP9_0 SFSP9_1 SFSP9_2 SFSP9_3 SFSP9_4 SFSP9_5 SFSP9_6 Pins PA_n SFSPA_1 SFSPA_2 SFSPA_3 SFSPA_4 Pins PB_n SFSPB_0 SFSPB_1 SFSPB_2 SFSPB_3 SFSPB_4 SFSPB_5 Access R/W - Address offset 0x39C 0x3A0 0x3FC 0x400 0x404 0x408 0x40C 0x410 0x414 0x418 0x41C 0x420 0x424 0x47C 0x480 0x484 0x488 0x49C 0x490 0x494 0x498 0x49C 0x4FC 0x500 0x504 0x508 0x50C 0x510 0x514 0x57C 0x580 0x584 0x588 0x58C 0x590 0x594 Description Pin configuration register for pin P7_7 Reserved Reset value - D D R R A 0x00 A FT D A FT D R A FT D R R/W R/W R/W R/W R/W R/W R/W R/W R/W - Pin configuration register for pin P8_0 Pin configuration register for pin P8_1 Pin configuration register for pin P8_2 Pin configuration register for pin P8_3 Pin configuration register for pin P8_4 Pin configuration register for pin P8_5 Pin configuration register for pin P8_6 Pin configuration register for pin P8_7 Pin configuration register for pin P8_8 Reserved 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 - R/W R/W R/W R/W R/W R/W R/W - Pin configuration register for pin P9_0 Pin configuration register for pin P9_1 Pin configuration register for pin P9_2 Pin configuration register for pin P9_3 Pin configuration register for pin P9_4 Pin configuration register for pin P9_5 Pin configuration register for pin P9_6 Reserved 0x00 0x00 0x00 0x00 0x00 0x00 0x00 - R/W R/W R/W R/W R/W - Reserved Pin configuration register for pin PA_1 Pin configuration register for pin PA_2 Pin configuration register for pin PA_3 Pin configuration register for pin PA_4 Reserved 0x00 0x00 0x00 0x00 - R/W R/W R/W R/W R/W R/W Pin configuration register for pin PB_0 Pin configuration register for pin PB_1 Pin configuration register for pin PB_2 Pin configuration register for pin PB_3 Pin configuration register for pin PB_4 Pin configuration register for pin PB_5 0x00 0x00 0x00 0x00 0x00 0x00 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 201 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 13: LPC18xx System Control Unit (SCU) FT D R R A Table 110. Register overview: System Control Unit (SCU) (base address 0x4008 6000) D R A R A FT D R FT D R A R A A …continued FT F FT Name SFSPB_6 Pins PC_n SFSPC_0 SFSPC_1 SFSPC_2 SFSPC_3 SFSPC_4 SFSPC_5 SFSPC_6 SFSPC_7 SFSPC_8 SFSPC_9 SFSPC_10 SFSPC_11 SFSPC_12 SFSPC_13 SFSPC_14 Pins PD_n SFSPD_0 SFSPD_1 SFSPD_2 SFSPD_3 SFSPD_4 SFSPD_5 SFSPD_6 SFSPD_7 SFSPD_8 SFSPD_9 SFSPD_10 SFSPD_11 SFSPD_12 SFSPD_13 SFSPD_14 SFSPD_15 SFSPD_16 Access R/W - Address offset 0x598 0x59C 0x5FC 0x600 0x604 0x608 0x60C 0x610 0x614 0x618 0x61C 0x620 0x624 0x628 0x62C 0x630 0x634 0x638 0x63C 0x67C 0x680 0x684 0x688 0x68C 0x690 0x694 0x698 0x69C 0x6A0 0x6A4 0x6A8 0x6AC 0x6B0 0x6B4 0x6B8 0x6BC 0x6C0 Description Pin configuration register for pin PB_6 Reserved Reset value 0x00 - D D R R A A FT D A FT D R A FT D R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W - Pin configuration register for pin PC_0 Pin configuration register for pin PC_1 Pin configuration register for pin PC_2 Pin configuration register for pin PC_3 Pin configuration register for pin PC_4 Pin configuration register for pin PC_5 Pin configuration register for pin PC_6 Pin configuration register for pin PC_7 Pin configuration register for pin PC_8 Pin configuration register for pin PC_9 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Pin configuration register for pin PC_10 0x00 Pin configuration register for pin PC_11 0x00 Pin configuration register for pin PC_12 0x00 Pin configuration register for pin PC_13 0x00 Pin configuration register for pin PC_14 0x00 Reserved - R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Pin configuration register for pin PD_0 Pin configuration register for pin PD_1 Pin configuration register for pin PD_2 Pin configuration register for pin PD_3 Pin configuration register for pin PD_4 Pin configuration register for pin PD_5 Pin configuration register for pin PD_6 Pin configuration register for pin PD_7 Pin configuration register for pin PD_8 Pin configuration register for pin PD_9 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Pin configuration register for pin PD_10 0x00 Pin configuration register for pin PD_11 0x00 Pin configuration register for pin PD_12 0x00 Pin configuration register for pin PD_13 0x00 Pin configuration register for pin PD_14 0x00 Pin configuration register for pin PD_15 0x00 Pin configuration register for pin PD_16 0x00 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 202 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 13: LPC18xx System Control Unit (SCU) FT D R R A Table 110. Register overview: System Control Unit (SCU) (base address 0x4008 6000) D R A R A FT D R FT D R A R A A …continued FT F FT Name Pins PE_n SFSPE_0 SFSPE_1 SFSPE_2 SFSPE_3 SFSPE_4 SFSPE_5 SFSPE_6 SFSPE_7 SFSPE_8 SFSPE_9 SFSPE_10 SFSPE_11 SFSPE_12 SFSPE_13 SFSPE_14 SFSPE_15 Pins PF_n SFSPF_0 SFSPF_1 SFSPF_2 SFSPF_3 SFSPF_4 SFSPF_5 SFSPF_6 SFSPF_7 SFSPF_8 SFSPF_9 SFSPF_10 SFSPF_11 CLKn pins SFSCLK0 SFSCLK1 SFSCLK2 Access - Address offset 0x6C4 0x6FC 0x700 0x704 0x708 0x70C 0x710 0x714 0x718 0x71C 0x720 0x724 0x728 0x72C 0x730 0x734 0x738 0x73C 0x740 0x77C 0x780 0x784 0x788 0x78C 0x790 0x794 0x798 0x79C 0x7A0 0x7A4 0x7A8 0x7AC 0x7B0 0xBFC 0xC00 0xC04 0xC08 Description Reserved Reset value - D D R R A A FT D A FT D R A FT D R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W - Pin configuration register for pin PE_0 Pin configuration register for pin PE_1 Pin configuration register for pin PE_2 Pin configuration register for pin PE_3 Pin configuration register for pin PE_4 Pin configuration register for pin PE_5 Pin configuration register for pin PE_6 Pin configuration register for pin PE_7 Pin configuration register for pin PE_8 Pin configuration register for pin PE_9 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Pin configuration register for pin PE_10 0x00 Pin configuration register for pin PE_11 0x00 Pin configuration register for pin PE_12 0x00 Pin configuration register for pin PE_13 0x00 Pin configuration register for pin PE_14 0x00 Pin configuration register for pin PE_15 0x00 Reserved - R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W - Pin configuration register for pin PF_0 Pin configuration register for pin PF_1 Pin configuration register for pin PF_2 Pin configuration register for pin PF_3 Pin configuration register for pin PF_4 Pin configuration register for pin PF_5 Pin configuration register for pin PF_6 Pin configuration register for pin PF_7 Pin configuration register for pin PF_8 Pin configuration register for pin PF_9 Pin configuration register for pin PF_11 Reserved 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 - Pin configuration register for pin PF_10 0x00 R/W R/W R/W Pin configuration register for pin CLK0 Pin configuration register for pin CLK1 Pin configuration register for pin CLK2 0x00 0x00 0x00 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 203 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 13: LPC18xx System Control Unit (SCU) FT D R R A Table 110. Register overview: System Control Unit (SCU) (base address 0x4008 6000) D R A R A FT D R FT D R A R A A …continued FT F FT Name SFSCLK3 - Access R/W - Address offset 0xC0C 0xC10 0xC84 0xC88 0xC8C 0xC90 0xC80 0xC84 Description Pin configuration register for pin CLK3 Reserved Reset value - D D R R A 0x00 A FT D A FT D R A FT D R ADC pin select registers ENAIO0 ENAIO1 ENAIO2 SFSUSB SFSI2C0 EMC delay registers EMCCLKDELAY EMCCTRLDELAY EMCCSDELAY EMCDOUTDELAY EMCFBCLKDELAY EMCADDRDELAY0 EMCADDRDELAY1 EMCADDRDELAY2 EMCDINDELAY PINTSEL0 PINTSEL1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0xD00 0xD04 0xD08 0xD0C 0xD10 0xD14 0xD18 0xD1C 0xD20 0xD24 0xE00 0xE04 EMC clock delay register EMC control delay register EMC chip select delay register EMC data out delay register EMC FBCLK delay register EMC address line delay register 0 EMC address line delay register 1 EMC address line delay register 2 Reserved EMC data delay register Pin interrupt select register for pin interrupts 0 to 3. Pin interrupt select register for pin interrupts 4 to 7. R/W R/W R/W I2C-bus R/W R/W ADC0 function select register ADC1 function select register Analog function select register Pin configuration register for Pin configuration register for I2C0-bus pins 0x00 0x00 USB DP1/DPM pins and open-drain pins Pin interrupt select registers 13.4.1 Pin configuration registers for normal drive pins Each digital pin and each clock pin on the LPC18xx have an associated pin configuration register which determines the pin’s function and electrical characteristics. The assigned functions for each pin are listed in Table 109. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 204 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 13: LPC18xx System Control Unit (SCU) FT D R R A Table 111. Pin configuration for normal drive pins P0_n to PF_n and CLK0 to CLK3 registers (SFS, address 0x4008 6000 (SPSP0_0) to 0x4008 6C0C (SFSCLK3)) bit description D R A R A FT D R FT D R A R A A FT D R A F FT D R A Bit 2:0 Symbol MODE Value Description Select pin function Reset Access value FT D A FT D R 0 R/W FT 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 3 EPD 0 1 4 EPUN 0 1 5 EHS 0 1 6 EZI Function 0 (default) Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 Enable pull-down resistor at pad Disable pull-down. Enable pull-down. Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset. Enable pull-up Disable pull-up Slew rate Slow Fast Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving. 0 R/W 0 R/W 0 R/W 0 R/W D R A 0 1 31:7 - Disable input buffer Enable input buffer Reserved - 13.4.2 Pin configuration registers for high drive pins Each digital pin and each clock pin on the LPC18xx have an associated pin configuration register which determines the pin’s function and electrical characteristics. The assigned functions for each pin are listed in Table 109. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 205 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 13: LPC18xx System Control Unit (SCU) FT D R R A Table 112. Pin configuration for high drive pins P0_n to PF_n and CLK0 to CLK3 registers (SFS, address 0x4008 6000 (SFSP0_0) to 0x4008 6C0C (SFSCLK3) bit description D R A R A FT D R FT D R A R A A FT D F FT D Bit 2:0 Symbol MODE Value Description Select pin function Reset Access value R R A A FT D FT 0 R/W D R A 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 3 EPD 0 1 4 EPUN 0 1 5 EHS 0 1 6 EZI Function 0 (default) Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 Enable pull-down resistor at pad Disable pull-down. Enable pull-down. Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset. Enable pull-up Disable pull-up Slew rate Slow Fast Input buffer enable. The input buffer is 0 disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad. R/W 0 R/W 0 R/W 0 R/W FT D R A 0 1 7 9:8 EHD 0x0 0x1 0x2 0x3 31:10 - Disable input buffer Enable input buffer Reserved Select drive strength Standard drive: 4 mA drive strength Medium drive: 8 mA drive strength High drive: 14 mA drive strength Ultra-high drive: 20 mA drive strength Reserved 0 R/W 13.4.3 ADC0 function select register For pins which have digital and analog functions, this register selects the input channel of the ADC0 over any of the possible digital functions. This option is not available for channel ADC0_7. In addition, each analog function is pinned out on a dedicated analog pin which is not affected by this register. The following pins are controlled by the ENAIO0 register: All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 206 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 13: LPC18xx System Control Unit (SCU) FT D R A D R A R A FT D R FT D Table 113. Pins controlled by the ENAIO0 register Pin P4_3 P4_1 PF_8 P7_5 P7_4 PF_10 PB_6 ADC function ADC0_0 ADC0_1 ADC0_2 ADC0_3 ADC0_4 ADC0_5 ADC0_6 0 1 2 3 4 5 6 R ENAIO0 register bit By default, all pins are connected to their digital function 0 and the corresponding ENAIO0 register bit is set to one. In this case, only the digital pad is available. Before selecting the analog pad by setting the ENAIO0 register bit to zero, the digital pad must be set as follows using the corresponding SFSP register: 1. Tri-state the output driver by selecting an input at the pinmux e.g. GPIO function in input mode. 2. Disable the receiver by setting the EZI bit to zero (see Table 111 or Table 112). This is the default setting. 3. Disable the pull-up resistor by setting the EPUN bit to one, and disable the pull-down resistor by setting the EPD bit to zero. Table 114. ADC0 function select register (ENAIO0, address 0x4008 6C88) bit description Bit 0 Symbol ADC0_0 0 1 1 ADC0_1 0 1 2 ADC0_2 0 1 3 ADC0_3 0 1 4 ADC0_4 0 1 5 ADC0_5 0 1 Value Description Select ADC0_0 Analog function ADC0_0 selected on pin P4_3. Digital function selected on pin P4_3. Select ADC0_1 Analog function ADC0_1 selected on pin P4_1. Digital function selected on pin P4_1. Select ADC0_2 Analog function ADC0_2 selected on pin PF_8. Digital function selected on pin PF_8. Select ADC0_3 Analog function ADC0_3 selected on pin P7_5. Digital function selected on pin P7_5. Select ADC0_4 Analog function ADC0_4 selected on pin P7_4. Digital function selected on pin P7_4. Select ADC0_5 Analog function ADC0_5 selected on pin PF_10. Digital function selected on pin PF_10. 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Reset Access value 0 R/W R A FT D R R A F D R A FT A FT A FT D R A D FT D R A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 207 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 13: LPC18xx System Control Unit (SCU) FT D R R A Table 114. ADC0 function select register (ENAIO0, address 0x4008 6C88) bit description D R A R A FT D R FT D R A R A A Bit 6 Symbol ADC0_6 Value Description Select ADC0_6 0 1 Analog function ADC0_6 selected on pin PB_6. Digital function selected on pin PB_6. Reserved Reset Access value FT D R A F FT D R A 0 R/W FT D R A FT D R FT D 31:7 - - A 13.4.4 ADC1 function select register For pins which have digital and analog functions, this register selects the ADC1 function over any of the possible digital functions. In addition, each analog function is pinned out on a dedicated analog pin which is not affected by this register. The following pins are controlled by the ENAIO1 register: Table 115. Pins controlled by the ENAIO1 register Pin PC_3 PC_0 PF_9 PF_6 PF_5 PF_11 P7_7 PF_7 ADC function ADC1_0 ADC1_1 ADC1_2 ADC1_3 ADC1_4 ADC1_5 ADC1_6 ADC1_7 ENAIO1 register bit 0 1 2 3 4 5 6 7 By default, all pins are connected to their digital function 0 and the corresponding ENAIO1 register bit is set to one. In this case, only the digital pad is available. Before selecting the analog pad by setting the ENAIO1 register bit to zero, the digital pad must be set as follows using the corresponding SFSP register: 1. Tri-state the output driver by selecting an input at the pinmux e.g. GPIO function in input mode. 2. Disable the receiver by setting the EZI bit to zero (see Table 111 or Table 112). This is the default setting. 3. Disable the pull-up resistor by setting the EPUN bit to one, and disable the pull-down resistor by setting the EPD bit to zero. Table 116. ADC1 function select register (ENAIO1, address 0x4008 6C8C) bit description Bit 0 Symbol ADC1_0 0 1 Value Description Select ADC1_0 Analog function ADC1_0 selected on pin PC_3. Digital function selected on pin PC_3. Reset Access value 0 R/W All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 208 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 13: LPC18xx System Control Unit (SCU) FT D R R A Table 116. ADC1 function select register (ENAIO1, address 0x4008 6C8C) bit description D R A R A FT D R FT D R A R A A Bit 1 Symbol ADC1_1 Value Description Select ADC1_1 0 1 Analog function ADC1_1 selected on pin PC_0. Digital function selected on pin PC_0. Select ADC1_2 0 1 Analog function ADC1_2 selected on pin PF_9. Digital function selected on pin PF_9. Select ADC1_3 0 1 Analog function ADC1_3 selected on pin PF_6. Digital function selected on pin PF_6. Select ADC1_4 0 1 Analog function ADC1_4 selected on pin PF_5. Digital function selected on pin PF_5. Select ADC1_5 0 1 Analog function ADC1_5 selected on pin PF_11. Digital function selected on pin PF_11. Select ADC1_6 0 1 Analog function ADC1_6 selected on pin P7_7. Digital function selected on pin P7_7. Select ADC1_7 0 1 Analog function ADC1_7 selected on pin PF_7. Digital function selected on pin PF_7. Reserved Reset Access value FT D R A F FT D R A 0 R/W FT D R A FT D R FT D 2 ADC1_2 0 R/W A 3 ADC1_3 0 R/W 4 ADC1_4 0 R/W 5 ADC1_5 0 R/W 6 ADC1_6 0 R/W 7 ADC1_7 0 R/W 31:8 - - 13.4.5 Analog function select register For pins which have digital and analog functions, this register selects the analog DAC and band gap function over any of the possible digital functions. In addition, the DAC function is pinned out on a dedicated analog pin which is not affected by this register. The following pins are controlled by the ENAIO1 register: Table 117. Pins controlled by the ENAIO2 register Pin P4_4 PF_7 ADC function DAC BG (band gap output) ENAIO2 register bit 0 4 By default, all pins are connected to their digital function 0 and the corresponding ENAIO2 register bit is set to one. In this case, only the digital pad is available. Before selecting the analog pad by setting the ENAIO2 register bit to zero, the digital pad must be set as follows using the corresponding SFSP register: All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 209 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 13: LPC18xx System Control Unit (SCU) FT D R R A 1. Tri-state the output driver by selecting an input at the pinmux e.g. GPIO function in input mode. R A FT D R A 2. Disable the receiver by setting the EZI bit to zero (see Table 111 or Table 112). This is the default setting. 3. Disable the pull-up resistor by setting the EPUN bit to one, and disable the pull-down resistor by setting the EPD bit to zero. Table 118. Analog function select register (ENAIO2, address 0x4008 6C90) bit description Bit 0 Symbol DAC 0 1 3:1 4 BG 0 1 31:5 Value Description Select DAC Analog function DAC selected on pin P4_4. Digital function selected on pin P4_4. Reserved Select band gap output Band gap output selected for pin PF_7. Digital function selected on pin PF_7. Reserved 0 R/W Reset Access value 0 R/W 13.4.6 Pin configuration register for USB1 pins DP1/DM1 Remark: The USB_ESEA bit must be set to one to use USB1. Table 119. Pin configuration for pins DP1/DM1 register (SFSUSB, address 0x4008 6C80) bit description Bit 0 Symbol USB_AIM Value Description Differential data input AIP/AIM 0 = Going LOW with full speed edge rate 1 = Going HIGH with full speed edge rate 0 1 1 USB_ESEA 0 1 31:2 Going LOW with full speed edge rate Going HIGH with full speed edge rate Control signal for differential input or single input Reserved. Do not use. Single input AIP. Enables USB1. Reserved 0 R/W Reset Access value 0 R/W 13.4.7 Pin configuration register for open-drain I2C-bus pins Table 120. Pin configuration for open-drain I2C-bus pins register (SFSI2C0, address 0x4008 6C84) bit description Bit 0 Symbol SDA_EHS 0 1 Value Description Configures I2C0-bus speed for SDA0 pin Standard/Fast mode (400 kbit/s) High-speed mode (3.4 Mbit/s) Reset Access value 0 R/W D R A R A FT D R FT D R A F D R A FT D FT D R A A FT R A D FT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 210 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 13: LPC18xx System Control Unit (SCU) FT D R R A Table 120. Pin configuration for open-drain I2C-bus pins register (SFSI2C0, address 0x4008 6C84) bit description …continued D R A R A FT D R FT D R A R A A FT F FT Bit 1 Symbol SCL_EHS Value Description Configures I2C0-bus speed for SCL0 pin Reset Access value D D R R A A FT FT 0 R/W D D R A 0 1 2 SCL_ECS 0 1 31:3 - Standard/Fast mode (400 kbit/s) High-speed mode (3.4 Mbit/s) Direction (only applies if SCL_EHS = 1) Receive Transmit Reserved 0 R/W FT D R A 13.4.8 EMC clock delay register This register provides a programmable delay for the EMC clock outputs. The delay for each clock output is approximately 0.5 ns  CLKn_DELAY or 0.5 ns  CKEn_DELAY. (CLKn_DELAY/CKEn_DELAY = 0x0: delay  0 ns, 0x1: delay  0.5 ns, ..., 0x7: delay  3.5 ns.) Table 121. EMC clock delay register (EMCCLKDELAY, address 0x4008 6D00) bit description Bit 2:0 3 6:4 7 10:8 11 14:12 15 18:16 19 22:20 23 26:24 27 30:28 31 Symbol Description Reset Access value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W - CLK0_DELAY Delay of the EMC_CLK0 clock output. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. CLK1_DELAY Delay of the EMC_CLK0 clock output. CLK2_DELAY Delay of the EMC_CLK2 clock output. CLK3_DELAY Delay of the EMC_CLK3 clock output. CKE0_DELAY Delay of the EMC_CKEOUT0 clock enable output. CKE1_DELAY Delay of the EMC_CKEOUT1 clock enable output. CKE2_DELAY Delay of the EMC_CKEOUT2 clock enable output. CKE3_DELAY Delay of the EMC_CKEOUT3 clock enable output. 13.4.9 EMC control delay register This register provides a programmable delay for the EMC control outputs. The delay for each control output is approximately 0.5 ns  XXX_DELAY. (XXX_DELAY = 0x0: delay  0 ns, 0x1: delay  0.5 ns, ..., 0x7: delay  3.5 ns.) All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 211 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 13: LPC18xx System Control Unit (SCU) FT D R R A Table 122. EMC control delay register (EMCCTRLDELAY, address 0x4008 6D04) bit description D R A R A FT D R FT D R A R A FT D D A F FT Bit 2:0 3 6:4 7 10:8 11 14:12 15 18:16 19 22:20 23 26:24 27 30:28 31 Symbol RAS_DELAY CAS_DELAY OE_DELAY WE_DELAY - Description Delay of the EMC_RAS output. Reserved. Delay of the EMC_CAS output. Reserved. Delay of the EMC_OE output. Reserved. Delay of the EMC_WE output. Reserved. Reserved. Reserved. Reserved. Reserved. Reset Access value R R A A FT D FT 0 0 0 0 0 0 0 0 - R/W R/W R/W R/W R/W R/W R/W R/W - D R A FT D R A BLS0_DELAY Delay of the EMC_BLS0 output. BLS1_DELAY Delay of the EMC_BLS1 output. BLS2_DELAY Delay of the EMC_BLS2 clock enable output. BLS3_DELAY Delay of the EMC_BLS3 clock enable output. 13.4.10 EMC chip select delay register This register provides a programmable delay for the EMC chip select outputs. The delay for each control output is approximately 0.5 ns  XXX_DELAY. (XXX_DELAY = 0x0: delay  0 ns, 0x1: delay  0.5 ns, ..., 0x7: delay  3.5 ns.) Table 123. EMC chip select delay register (EMCCSDELAY, address 0x4008 6D08) bit description Bit 2:0 3 6:4 7 10:8 11 14:12 15 18:16 19 22:20 23 26:24 Symbol DYCS0_DELAY DYCS1_DELAY DYCS2_DELAY DYCS3_DELAY CS0_DELAY CS1_DELAY CS2_DELAY Description Delay of the EMC_DYCS0 output. Reserved. Delay of the EMC_DYCS1 output. Reserved. Delay of the EMC_DYCS2 output. Reserved. Delay of the EMC_DYCS3 output. Reserved. Delay of the EMC_CS0 output. Reserved. Delay of the EMC_CS1 output. Reserved. Delay of the EMC_CS2 clock enable output. Reset Access value 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 212 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 13: LPC18xx System Control Unit (SCU) FT D R R A Table 123. EMC chip select delay register (EMCCSDELAY, address 0x4008 6D08) bit description …continued D R A R A FT D R FT D R A R A FT A F FT Bit 27 30:28 31 Symbol CS3_DELAY - Description Reserved. Delay of the EMC_CS3 clock enable output. Reserved. Reset Access value D D R R A A FT FT 0 - - D D R A FT D R/W R A 13.4.11 EMC data out delay register This register provides a programmable delay for the EMC DQM and EMC data outputs (8 data lanes per delay control). The delay for each control output is approximately 0.5 ns  XXX_DELAY. (XXX_DELAY = 0x0: delay  0 ns, 0x1: delay  0.5 ns, ..., 0x7: delay  3.5 ns.) Table 124. EMC data out delay register (EMCDOUTDELAY, address 0x4008 6D0C) bit description Bit 2:0 3 6:4 7 10:8 11 14:12 15 18:16 19 22:20 23 26:24 27 30:28 31 Symbol DQM0_DELAY DQM1_DELAY DQM2_DELAY DQM3_DELAY D0_DELAY D1_DELAY D2_DELAY D3_DELAY Description Delay of the EMC_DQM0 output. Reserved. Delay of the EMC_DQM1 output. Reserved. Delay of the EMC_DQM2 output. Reserved. Delay of the EMC_DQM3 output. Reserved. Delay of the EMC_D0 to EMC_D7 outputs. Reserved. Delay of the EMC_D8 to EMC_D15 outputs. Reserved. Delay of the EMC_D16 to EMC_D23 outputs. Reserved. Delay of the EMC_D24 to EMC_D31 outputs. Reserved. Reset Access value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W - 13.4.12 EMC feedback clock delay register This register provides a programmable delay for the EMC feedback clocks (8 data lanes per feedback clock). The delay for each control output is approximately 0.5 ns  XXX_DELAY. (XXX_DELAY = 0x0: delay  0 ns, 0x1: delay  0.5 ns, ..., 0x7: delay  3.5 ns.) All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 213 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 13: LPC18xx System Control Unit (SCU) FT D R R A Table 125. EMC DQM delay register (EMCFBCLKDELAY, address 0x4008 6D10) bit description D R A R A FT D R FT D R A R A FT D D A F FT Bit 2:0 3 6:4 7 10:8 11 14:12 15 18:16 31:19 Symbol Description Reset Access value R R A A FT D FT FBCLK0_DELAY Delay of the EMC feedback clock 0 (for byte lane 0). 0 CCLK_DELAY Reserved. Reserved. Reserved. Reserved. Delay of the EMC CCLKDELAY clock. Reserved. 0 FBCLK1_DELAY Delay of the EMC feedback clock 1 (for byte lane 1). 0 FBCLK2_DELAY Delay of the EMC feedback clock 2 (for byte lane 2). 0 FBCLK3_DELAY Delay of the EMC feedback clock 3 (for byte lane 3). 0 R/W R/W R/W R/W R/W - D R A FT D R A 13.4.13 EMC address delay register 0 This register provides a programmable delay for the EMC address outputs. The delay for each control output is approximately 0.5 ns  ADDRn_DELAY. (ADDRn_DELAY = 0x0: delay  0 ns, 0x1: delay  0.5 ns, ..., 0x7: delay  3.5 ns.) Table 126. EMC address delay register 0 (EMCADDRDELAY0, address 0x4008 6D14) bit description Bit 2:0 3 6:4 7 10:8 11 14:12 15 18:16 19 22:20 23 26:24 27 30:28 31 Symbol ADDR0_DELAY ADDR1_DELAY ADDR2_DELAY ADDR3_DELAY ADDR4_DELAY ADDR5_DELAY ADDR6_DELAY ADDR7_DELAY Description Delay of the EMC_A0 output. Reserved. Delay of the EMC_A1 output. Reserved. Delay of the EMC_A2 output. Reserved. Delay of the EMC_A3 output. Reserved. Delay of the EMC_A4 output. Reserved. Delay of the EMC_A5 output. Reserved. Delay of the EMC_A6 output. Reserved. Delay of the EMC_A7 output. Reserved. Reset Access value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W - 13.4.14 EMC address delay register 1 This register provides a programmable delay for the EMC address outputs. The delay for each control output is approximately 0.5 ns  ADDRn_DELAY. (ADDRn_DELAY = 0x0: delay  0 ns, 0x1: delay  0.5 ns, ..., 0x7: delay  3.5 ns.) All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 214 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 13: LPC18xx System Control Unit (SCU) FT D R R A Table 127. EMC address delay register 1 (EMCADDRDELAY1, address 0x4008 6D18) bit description D R A R A FT D R FT D R A R A FT D A F FT D Bit 2:0 3 6:4 7 10:8 11 14:12 15 18:16 19 22:20 23 26:24 27 30:28 31 Symbol ADDR8_DELAY ADDR9_DELAY - Description Delay of the EMC_A8 output. Reserved. Delay of the EMC_A9 output. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reset Access value R R A A FT D FT 0 0 0 0 0 0 0 0 - R/W R/W R/W R/W R/W R/W R/W R/W - D R A FT D R A ADDR10_DELAY Delay of the EMC_A10 output. ADDR11_DELAY Delay of the EMC_A11 output. ADDR12_DELAY Delay of the EMC_A12 output. ADDR13_DELAY Delay of the EMC_A13 output. ADDR14_DELAY Delay of the EMC_A14 output. ADDR15_DELAY Delay of the EMC_A15 output. 13.4.15 EMC address delay register 2 This register provides a programmable delay for the EMC address outputs. The delay for each control output is approximately 0.5 ns  ADDRn_DELAY. (ADDRn_DELAY = 0x0: delay  0 ns, 0x1: delay  0.5 ns, ..., 0x7: delay  3.5 ns.) Table 128. EMC address delay register 2 (EMCADDRDELAY2, address 0x4008 6D1C) bit description Bit 2:0 3 6:4 7 10:8 11 14:12 15 18:16 19 22:20 23 26:24 Symbol Description Reset Access value 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W ADDR16_DELAY Delay of the EMC_A16 output. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. ADDR17_DELAY Delay of the EMC_A17 output. ADDR18_DELAY Delay of the EMC_A18 output. ADDR19_DELAY Delay of the EMC_A19 output. ADDR20_DELAY Delay of the EMC_A20 output. ADDR21_DELAY Delay of the EMC_A21 output. ADDR22_DELAY Delay of the EMC_A22 output. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 215 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 13: LPC18xx System Control Unit (SCU) FT D R R A Table 128. EMC address delay register 2 (EMCADDRDELAY2, address 0x4008 6D1C) bit description …continued D R A R A FT D R FT D R A R A FT A F FT Bit 27 30:28 31 Symbol - Description Reserved. Reserved. Reset Access value D D R R A A FT FT 0 - - D D R A ADDR23_DELAY Delay of the EMC_A23 output. R/W FT D R A 13.4.16 EMC data in delay register This register provides a programmable delay for the EMC data inputs (8 data lanes per delay control). The delay for each control output is approximately 0.5 ns  ADDRn_DELAY. (ADDRn_DELAY = 0x0: delay  0 ns, 0x1: delay  0.5 ns, ..., 0x7: delay  3.5 ns.) Table 129. EMC data in delay register 3 (EMCDINDELAY, address 0x4008 6D24) bit description Bit 2:0 3 6:4 7 10:8 11 14:12 15 18:16 19 22:20 23 26:24 31:27 Symbol DIN0_DELAY DIN1_DELAY DIN2_DELAY DIN3_DELAY DEN0_DELAY DEN1_DELAY DEN2_DELAY Reserved. Delay of the data enable lines 8 to 15. Reserved. Delay of the data enable lines 16 to 23. Reserved. Description Delay of the EMC_D0 to EMC_D7 inputs. Reserved. Delay of the EMC_D8 to EMC_D15 inputs. Reserved. Delay of the EMC_D23 to EMC_D16 inputs. Reserved. Delay of the EMC_D31 to EMC_D24 inputs. Reserved. Reset Access value 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W - 13.4.17 Pin interrupt select register 0 This register selects one GPIO pin from all GPIO pins on all ports as the source for pin interrupts 0 to 3. As an example, for pin interrupt 1, INTPIN1 = 0xA selects GPIO pin GPIO0[10] if PORTSEL1 = 0 or pin GPIO1[10] if PORTSEL = 1. Each pin interrupt must be enabled in the NVIC using interrupt slot # . To enable each pin interrupt and configure its edge or level sensitivity, use the GPIO pin interrupt registers (see ). All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 216 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 13: LPC18xx System Control Unit (SCU) FT D R R A Table 130. Pin interrupt select register 0 (PINTSEL0, address 0x4008 6E00) bit description D R A R A FT D R FT D R A R A A FT FT F Bit 4:0 7:5 Symbol INTPIN0 PORTSEL0 Value Description Reset value D Pint interrupt 0: Select the pin number within the GPIO port 0 selected by the PORTSEL0 bit in this register. Pin interrupt 0: Select the port for the pin number to be selected in the INTPIN0 bits of this register. 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 GPIO Port 0 GPIO Port 1 GPIO Port 2 GPIO Port 3 GPIO Port 4 GPIO Port 5 GPIO Port 6 GPIO Port 7 Pint interrupt 1: Select the pin number within the GPIO port 0 selected by the PORTSEL1 bit in this register. Pin interrupt 1: Select the port for the pin number to be selected in the INTPIN1 bits of this register. 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 GPIO Port 0 GPIO Port 1 GPIO Port 2 GPIO Port 3 GPIO Port 4 GPIO Port 5 GPIO Port 6 GPIO Port 7 Pint interrupt 2: Select the pin number within the GPIO port 0 selected by the PORTSEL2 bit in this register. Pin interrupt 2: Select the port for the pin number to be selected in the INTPIN2 bits of this register. 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 GPIO Port 0 GPIO Port 1 GPIO Port 2 GPIO Port 3 GPIO Port 4 GPIO Port 5 GPIO Port 6 GPIO Port 7 Pint interrupt 3: Select the pin number within the GPIO port 0 selected by the PORTSEL3 bit in this register. 0 0 0 D R R A A FT D R A FT D FT D R A 12:8 15:13 INTPIN1 PORTSEL1 20:16 23:21 INTPIN2 PORTSEL2 28:24 INTPIN3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 217 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 13: LPC18xx System Control Unit (SCU) FT D R R A Table 130. Pin interrupt select register 0 (PINTSEL0, address 0x4008 6E00) bit description D R A R A FT D R FT D R A R A A Bit 31:29 Symbol PORTSEL3 Value Description Reset value FT D R A F FT D Pin interrupt 3: Select the port for the pin number to be selected in the INTPIN3 bits of this register. 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 GPIO Port 0 GPIO Port 1 GPIO Port 2 GPIO Port 3 GPIO Port 4 GPIO Port 5 GPIO Port 6 GPIO Port 7 R 0 A FT D R A FT D FT D R A 13.4.18 Pin interrupt select register 1 This register selects one GPIO pin from all GPIO pins on all ports as the source for pin interrupts 4 to 7. As an example, for pin interrupt 4, INTPIN4 = 0xA selects GPIO pin GPIO0[10] if PORTSEL1 = 0 or pin GPIO1[10] if PORTSEL = 1. Each pin interrupt must be enabled in the NVIC using interrupt slots 32 to 39. To enable each pin interrupt and configure its edge or level sensitivity, use the GPIO pin interrupt registers (see Section 15.4.1). Table 131. Pin interrupt select register 1 (PINTSEL1, address 0x4008 6E04) bit description Bit 4:0 7:5 Symbol INTPIN4 PORTSEL4 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 12:8 INTPIN5 Value Description Reset value Pint interrupt 4: Select the pin number within the GPIO port 0 selected by the PORTSEL4 bit in this register. Pin interrupt 4: Select the port for the pin number to be selected in the INTPIN4 bits of this register. GPIO Port 0 GPIO Port 1 GPIO Port 2 GPIO Port 3 GPIO Port 4 GPIO Port 5 GPIO Port 6 GPIO Port 7 Pint interrupt 5: Select the pin number within the GPIO port 0 selected by the PORTSEL5 bit in this register. 0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 218 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 13: LPC18xx System Control Unit (SCU) FT D R R A Table 131. Pin interrupt select register 1 (PINTSEL1, address 0x4008 6E04) bit description D R A R A FT D R FT D R A R A A Bit 15:13 Symbol PORTSEL5 Value Description Reset value FT D R A F FT D Pin interrupt 5: Select the port for the pin number to be selected in the INTPIN5 bits of this register. 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 20:16 23:21 INTPIN6 PORTSEL6 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 28:24 31:29 INTPIN7 PORTSEL7 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 GPIO Port 0 GPIO Port 1 GPIO Port 2 GPIO Port 3 GPIO Port 4 GPIO Port 5 GPIO Port 6 GPIO Port 7 Pin interrupt 6: Select the port for the pin number to be selected in the INTPIN6 bits of this register. GPIO Port 0 GPIO Port 1 GPIO Port 2 GPIO Port 3 GPIO Port 4 GPIO Port 5 GPIO Port 6 GPIO Port 7 Pin interrupt 7: Select the port for the pin number to be selected in the INTPIN7 bits of this register. GPIO Port 0 GPIO Port 1 GPIO Port 2 GPIO Port 3 GPIO Port 4 GPIO Port 5 GPIO Port 6 GPIO Port 7 Pint interrupt 6: Select the pin number within the GPIO port 0 selected by the PORTSEL6 bit in this register. 0 Pint interrupt 7: Select the pin number within the GPIO port 0 selected by the PORTSEL7 bit in this register. 0 R 0 A FT D R A FT D FT D R A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 219 of 1164 D R A FT D R A FT D R A FT D R A FT D R A FT UM10430 Rev. 00.13 — 20 July 2011 D D Chapter 14: LPC18xx Global Input Multiplexer Array (GIMA) D R R A A FT FT D D R A FT D R A FT D R A FT D FT D R A D R A FT R A R A FT D R A FT D R A F R A FT D FT R User manual 14.1 How to read this chapter Remark: This chapter describes parts LPC1850/30/20/10 Rev ‘A’. Remark: The VADC block is not available on the LPC1850/30/20/10 Rev ‘A’. D D R A FT D R A 14.2 Basic configuration The GIMA is configured as follows: • See Table 132 for clocking and power control. • The GIMA is reset by the GIMA_RST (reset # ). • The GIMA outputs are connected to the timer, SCT, ADC, and event router peripherals (see Figure 24 and Figure 25). Table 132. GIMA clocking and power control Base clock Clock to GIMA register interface BASE_M3_CLK Branch clock CLK_M3_BUS Maximum frequency 150 MHz 14.3 General description The Global Input Multiplexer Array (GIMA) provides an internal crosslink multiplexer array to connect and synchronize inputs from the pads or internal inputs to event driven peripherals such as the timers, the ADC, or the event router. The GIMA has 30 outputs, each of which is connected to a peripheral function like a timer capture input or the ADC conversion start input. One register for each output configures the input and controls the synchronizer. Table 133. GIMA inputs Input 0 1 4:2 5 6 7 8 9 10 11 12 13 Source GPIO6[28] GPIO5[3] reserved MCOB2 pin CTIN_0 pin CTIN_1 pin CTIN_2 pin CTIN_3 pin CTIN_4 pin CTIN_5 pin CTIN_6 pin CTIN_7 Possible connections to peripheral blocks VADC VADC VADC T0 CAP0 T0 CAP1 T0 CAP2 T1 CAP1 T1 CAP2 T2 CAP2 T3 CAP1 T3 CAP2 T1 CAP0 T2 CAP1 SCT CAP2 SCT CAP3 SCT CAP4 SCT CAP5 SCT CAP6 SCT CAP7 © NXP B.V. 2011. All rights reserved. T3 CAP0 SCT CAP1 SCT CAP0 All information provided in this document is subject to legal disclaimers. User manual Rev. 00.13 — 20 July 2011 220 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 14: LPC18xx Global Input Multiplexer Array (GIMA) FT D R A D R A R A FT D R FT Table 133. GIMA inputs Input 14 15 16 17 18 19 Source T0 MAT0 or CTOUT 0 T0 MAT2 or CTOUT_2 T0 MAT3 or CTOUT 3 T1 MAT2 or CTOUT 6 T1 MAT3 or CTOUT 7 T2 MAT0 or CTOUT 8 Possible connections to peripheral blocks VADC Event router channel 13 T1 CAP3 Event router channel 14 T2 CAP3 VADC ADC start conversion (START = 0x3) D R R A FT D R R A F D R A FT A FT A FT D R A D FT D R A 20 21 22 T2 MAT3 or CTOUT 11 T3 MAT2 or CTOUT 14 T3 MAT3 or CTOUT 15 T3 CAP3 Event router channel 16 T0 CAP3 ADC start conversion (START = 0x2) SCT CAP3 SCT CAP4 T2 CAP1 SCT CAP5 SCT CAP6 SCT CAP7 SCT CAP6 SCT CAP6 SCT CAP7 SCT CAP7 SCT CAP3 SCT CAP3 SCT CAP4 SCT CAP4 SCT CAP1 23 24 25 26 27 28 29 30 31 32 36:33 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 U0 TXD U0 RXD U2 TXD U2 RXD U3 TXD U3 RXD I2S0_RX_MWS I2S0_TX_MWS SOF0 SOF1 Reserved I2S1_RX_MWS I2S1_TX_MWS pin T0_CAP0 pin T0_CAP1 pin T0_CAP2 pin T0_CAP3 pin T1_CAP0 pin T1_CAP1 pin T1_CAP2 pin T1_CAP3 pin T2_CAP0 pin T2_CAP1 pin T2_CAP2 pin T2_CAP3 pin T3_CAP0 pin T3_CAP1 T1 CAP1 T1 CAP2 T0 CAP1 T2 CAP2 T3 CAP1 T3 CAP2 T3 CAP0 T3 CAP1 T3 CAP2 T3 CAP3 T2 CAP1 T2 CAP2 T0 CAP0 T0 CAP1 T0 CAP2 T0 CAP3 T1 CAP0 T1 CAP1 T1 CAP2 T1 CAP3 T2 CAP0 T2 CAP1 T2 CAP2 T2 CAP3 T3 CAP0 T3 CAP1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 221 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 14: LPC18xx Global Input Multiplexer Array (GIMA) FT D R A D R A R A FT D R FT Table 133. GIMA inputs Input 53 54 55 Source pin T3_CAP2 pin T3_CAP3 T0 MAT0 Possible connections to peripheral blocks T3 CAP2 T3 CAP3 VADC ADC start0 conversion (ADC CR register bit START = 0x2) D R R A FT D R R A F D R A FT A FT A FT D R A D FT D R A 56 57 58 59 60 T0 MAT2 T0 MAT3 T1 MAT2 T1 MAT3 T2 MAT0 Event router channel 13 T1 CAP3 Event router channel 14 T2 CAP3 VADC ADC start1 conversion (ADC CR register bit START = 0x3) 61 62 63 T2 MAT3 T3 MAT2 T3 MAT3 T3 CAP3 Event router channel 16 T0 CAP3 Each GIMA output control consists of five stages: 1. Input selection 2. Input inversion: inverts the path between source and destination. 3. Asynchronous capture 4. Synchronization to peripheral clock 5. Pulse generation If the source generates shorter pulses than the output clock, the source pulses can be missed. In this case, the asynchronous capture stage can be used to capture the rising edge, the synchronizer stage synchronizes the edge to the peripheral clock and pulse generator stage can optionally generate a singe cycle pulse. (By default the generated pulse is two clock cycles.) Remark: Use the capture and the synchronizer stage together to avoid the creation of very short, spurious pulses. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 222 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 14: LPC18xx Global Input Multiplexer Array (GIMA) FT D R R A D R A R A FT D R FT D R A R A FT FT A F input input inv cap SET sync Q Q pulse Q Q D D R A FT R A FT D SET Q Q D SET D SET Q Q D D 4 input R A FT output 0 D CLR 1 CLR CLR 2 CLR 3 D (peripheral) R A output_clk (peripheral clock) Fig 23. GIMA input stages All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 223 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 14: LPC18xx Global Input Multiplexer Array (GIMA) FT D R A D R A R A FT D R FT 14.3.1 GIMA cross connections D R R A FT D R R A F D R A FT A FT A FT pinmux CTIN_0..7 T0_CAP0..3 T1_CAP0..3 T2_CAP0..3 T3_CAP0..3 outp16 outp17 outp18 outp19 outp20 outp21 outp22 outp23 inp6..13 inp39..42 inp43..46 inp47..50 inp51..54 inp55 outp0 outp1 outp2 outp3 inp56 inp57 outp4 outp5 outp6 outp7 inp58 inp59 inp60 outp8 outp9 outp10 outp11 inp61 outp12 outp13 outp14 outp15 inp62 inp63 inp14 inp15 inp16 inp17 inp18 inp19 inp20 inp21 inp21 GIMA SCT inp0 inp1 inp2 inp3 inp4 inp5 inp6 inp7 outp0 outp1 outp2 outp3 outp4 outp5 outp6 outp7 outp8 outp9 outp10 outp11 outp12 outp13 outp14 outp15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 D D R A FT D creg R A pinmux CTOUT_x timer0 inp0 outp0 inp1 outp1 inp2 outp2 inp3 outp3 0 1 2 3 timer1 inp0 outp0 inp1 outp1 inp2 outp2 inp3 outp3 4 5 6 7 timer2 inp0 outp0 inp1 outp1 inp2 outp2 inp3 outp3 timer3 inp0 outp0 inp1 outp1 inp2 outp2 inp3 outp3 8 9 10 11 12 13 14 15 0 2 3 6 7 8 11 14 15 Fig 24. Cross connections between GIMA, SCT, and timer0/1/2/3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 224 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 14: LPC18xx Global Input Multiplexer Array (GIMA) FT D R R A D R A _ GIMA inp33 inp34 inp2 inp3 inp35 inp36 inp4 inp31 inp32 inp0 inp1 inp23 inp24 inp25 inp26 inp27 inp28 inp29 inp30 inp37 inp38 outp24 outp25 outp26 outp27 inp5 inp30 outp28 outp29 tbd adctrig0 R A FT D R FT D R A R A FT FT D R A FT D R A D A F R A FT D FT usb0 SOF_VF_INDICATOR usb1 SOF_VF_INDICATOR i2s0 rx_mws tx_mws i2s1 rx_mws tx_mws GPIO6[28] GPIO5[3] U0_TXD U0_RXD U2_TXD U2_RXD U3_TXD U3_RXD D R A div128 div128 div128 div128 vadc event router ADC start0 ADC start1 ADC start3 ADC start4 ADC start5 motocon MCO2B adc0/1 adctrig1 MCO2A Fig 25. Cross connections between GIMA, ADC, and event router 14.4 Register description Table 134. Register overview: GIMA (base address: 0x400C 7000) Name CAP0_0_IN CAP0_1_IN CAP0_2_IN CAP0_3_IN CAP1_0_IN CAP1_1_IN CAP1_2_IN CAP1_3_IN CAP2_0_IN Access Address offset R/W R/W R/W R/W R/W R/W R/W R/W R/W 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 Description Timer 0 CAP0_0 capture input multiplexer (GIMA output 0) Timer 0 CAP0_1 capture input multiplexer (GIMA output 1) Timer 0 CAP0_2 capture input multiplexer (GIMA output 2) Timer 0 CAP0_3 capture input multiplexer (GIMA output 3) Timer 1 CAP1_0 capture input multiplexer (GIMA output 4) Timer 1 CAP1_1 capture input multiplexer (GIMA output 5) Timer 1 CAP1_2 capture input multiplexer (GIMA output 6) Timer 1 CAP1_3 capture input multiplexer (GIMA output 7) Timer 2 CAP2_0 capture input multiplexer (GIMA output 8) Reset value 0 0 0 0 0 0 0 0 0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 225 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 14: LPC18xx Global Input Multiplexer Array (GIMA) FT D R Table 134. Register overview: GIMA (base address: 0x400C 7000) Name CAP2_1_IN CAP2_2_IN CAP2_3_IN CAP3_0_IN CAP3_1_IN CAP3_2_IN CAP3_3_IN CTIN_0_IN CTIN_1_IN CTIN_2_IN CTIN_3_IN CTIN_4_IN CTIN_5_IN CTIN_6_IN CTIN_7_IN VADC_TRIGGER_IN EVENTROUTER_13_IN EVENTROUTER_14_IN EVENTROUTER_16_IN ADCSTART0_IN ADCSTART1_IN Access Address offset R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0x024 0x028 0x02C 0x030 0x034 0x038 0x03C 0x040 0x044 0x048 0x04C 0x050 0x054 0x058 0x05C 0x060 0x064 0x068 0x06C 0x070 0x074 Description Timer 2 CAP2_1 capture input multiplexer (GIMA output 9) Timer 2 CAP2_2 capture input multiplexer (GIMA output 10) Timer 2 CAP2_3 capture input multiplexer (GIMA output 11) Timer 3 CAP3_0 capture input multiplexer (GIMA output 12) Timer 3 CAP3_1 capture input multiplexer (GIMA output 13) Timer 3 CAP3_2 capture input multiplexer (GIMA output 14) Timer 3 CAP3_3 capture input multiplexer (GIMA output 15) SCT CTIN_0 capture input multiplexer (GIMA output 16) SCT CTIN_1 capture input multiplexer (GIMA output 17) SCT CTIN_2 capture input multiplexer (GIMA output 18) SCT CTIN_3 capture input multiplexer (GIMA output 19) SCT CTIN_4 capture input multiplexer (GIMA output 20) SCT CTIN_5 capture input multiplexer (GIMA output 21) SCT CTIN_6 capture input multiplexer (GIMA output 22) SCT CTIN_7 capture input multiplexer (GIMA output 23) VADC trigger input multiplexer (GIMA output 24) Event router input 13 multiplexer (GIMA output 25) Event router input 14 multiplexer (GIMA output 26) Event router input 16 multiplexer (GIMA output 27) ADC start0 input multiplexer (GIMA output 28) ADC start1 input multiplexer (GIMA output 29) D R A R A FT D R FT D A R R A FT D R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R A F D R A FT D A FT D R A Reset value A FT R A FT D All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 226 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 14: LPC18xx Global Input Multiplexer Array (GIMA) FT D R A 14.4.1 Timer 0 CAP0_0 capture input multiplexer (CAP0_0_IN) Table 135. Timer 0 CAP0_0 capture input multiplexer (CAP0_0_IN, address 0x400C 7000) bit description D R A R A FT D R FT D R R A FT D R R A F D R A FT A FT A FT Bit 0 Symbol INV Value Description Invert input Reset value D D R A FT D R 0 1 1 EDGE 0 1 2 SYNCH 0 1 3 PULSE 0 1 7:4 SELECT 0x0 0x1 0x2 31:8 - Not inverted. Input inverted. Enable rising edge detection No edge detection. Rising edge detection enabled. Enable synchronization Disable synchronization. Enable synchronization. Enable single pulse generation. Disable single pulse generation. Enable single pulse generation. Select input. Values 0x3 to 0xF are reserved. CTIN_0 Reserved T0_CAP0 Reserved A 14.4.2 Timer 0 CAP0_1 capture input multiplexer (CAP0_1_IN) Table 136. Timer 0 CAP0_1 capture input multiplexer (CAP0_1_IN, address 0x400C 7004) bit description Bit 0 Symbol INV 0 1 1 EDGE 0 1 2 SYNCH 0 1 3 PULSE 0 1 7:4 SELECT 0x0 Value Description Invert input Not inverted. Input inverted. Enable rising edge detection No edge detection. Rising edge detection enabled. Enable synchronization Disable synchronization. Enable synchronization. Enable single pulse generation. Disable single pulse generation. Enable single pulse generation. Select input. Values 0x3 to 0xF are reserved. CTIN_1 Reset value All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 227 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 14: LPC18xx Global Input Multiplexer Array (GIMA) FT D R R A Table 136. Timer 0 CAP0_1 capture input multiplexer (CAP0_1_IN, address 0x400C 7004) bit description D R A R A FT D R FT D R A R A A FT F FT Bit Symbol Value 0x1 0x2 Description U2_TXD T0_CAP1 Reserved Reset value D D R R A A FT D R A FT D FT D 31:8 - R A 14.4.3 Timer 0 CAP0_2 capture input multiplexer (CAP0_2_IN) Table 137. Timer 0 CAP0_2 capture input multiplexer (CAP0_2_IN, address 0x400C 7008) bit description Bit 0 Symbol INV 0 1 1 EDGE 0 1 2 SYNCH 0 1 3 PULSE 0 1 7:4 SELECT 0x0 0x1 0x2 31:8 Value Description Invert input Not inverted. Input inverted. Enable rising edge detection No edge detection. Rising edge detection enabled. Enable synchronization Disable synchronization. Enable synchronization. Enable single pulse generation. Disable single pulse generation. Enable single pulse generation. Select input. Values 0x3 to 0xF are reserved. CTIN_2 Reserved T0_CAP2 Reserved Reset value 14.4.4 Timer 0 CAP0_3 capture input multiplexer (CAP0_3_IN) Table 138. Timer 0 CAP0_3 capture input multiplexer (CAP0_3_IN, address 0x400C 700C) bit description Bit 0 Symbol INV 0 1 1 EDGE 0 1 2 SYNCH 0 Value Description Invert input Not inverted. Input inverted. Enable rising edge detection No edge detection. Rising edge detection enabled. Enable synchronization Disable synchronization. Reset value All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 228 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 14: LPC18xx Global Input Multiplexer Array (GIMA) FT D R R A Table 138. Timer 0 CAP0_3 capture input multiplexer (CAP0_3_IN, address 0x400C 700C) bit description D R A R A FT D R FT D R A R A A FT F FT Bit Symbol Value 1 Description Enable synchronization. Enable single pulse generation. Disable single pulse generation. Enable single pulse generation. Select input. Values 0x3 to 0xF are reserved. CTOUT_15 or T3_MAT3 T0_CAP3 T3_MAT3 Reserved Reset value D D R R A A FT D R A FT D 3 PULSE 0 1 FT D R A 7:4 SELECT 0x0 0x1 0x2 31:8 - 14.4.5 Timer 1 CAP1_0 capture input multiplexer (CAP1_0_IN) Table 139. Timer 1 CAP1_0 capture input multiplexer (CAP1_0_IN, address 0x400C 7010) bit description Bit 0 Symbol INV 0 1 1 EDGE 0 1 2 SYNCH 0 1 3 PULSE 0 1 7:4 SELECT 0x0 0x1 0x2 31:8 Value Description Invert input Not inverted. Input inverted. Enable rising edge detection No edge detection. Rising edge detection enabled. Enable synchronization Disable synchronization. Enable synchronization. Enable single pulse generation. Disable single pulse generation. Enable single pulse generation. Select input. Values 0x3 to 0xF are reserved. CTIN_0 Reserved T1_CAP0 Reserved Reset value All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 229 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 14: LPC18xx Global Input Multiplexer Array (GIMA) FT D R A 14.4.6 Timer 1 CAP1_1 capture input multiplexer (CAP1_1_IN) Table 140. Timer 1 CAP1_1 capture input multiplexer (CAP1_1_IN, address 0x400C 7014) bit description D R A R A FT D R FT D R R A FT D R R A F D R A FT A FT A FT Bit 0 Symbol INV Value Description Invert input Reset value D D R A FT D R 0 1 1 EDGE 0 1 2 SYNCH 0 1 3 PULSE 0 1 7:4 SELECT 0x0 0x1 0x2 31:8 - Not inverted. Input inverted. Enable rising edge detection No edge detection. Rising edge detection enabled. Enable synchronization Disable synchronization. Enable synchronization. Enable single pulse generation. Disable single pulse generation. Enable single pulse generation. Select input. Values 0x3 to 0xF are reserved. CTIN_3 U0_TXD T1_CAP1 Reserved A 14.4.7 Timer 1 CAP1_2 capture input multiplexer (CAP1_2_IN) Table 141. Timer 1 CAP1_2 capture input multiplexer (CAP1_2_IN, address 0x400C 7018) bit description Bit 0 Symbol INV 0 1 1 EDGE 0 1 2 SYNCH 0 1 3 PULSE 0 1 7:4 SELECT 0x0 Value Description Invert input Not inverted. Input inverted. Enable rising edge detection No edge detection. Rising edge detection enabled. Enable synchronization Disable synchronization. Enable synchronization. Enable single pulse generation. Disable single pulse generation. Enable single pulse generation. Select input. Values 0x3 to 0xF are reserved. CTIN_4 Reset value All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 230 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 14: LPC18xx Global Input Multiplexer Array (GIMA) FT D R R A Table 141. Timer 1 CAP1_2 capture input multiplexer (CAP1_2_IN, address 0x400C 7018) bit description D R A R A FT D R FT D R A R A A FT F FT Bit Symbol Value 0x1 0x2 Description U0_RXD T1_CAP2 Reserved Reset value D D R R A FT D R A FT D A FT D 31:8 - R A 14.4.8 Timer 1 CAP1_3 capture input multiplexer (CAP1_3_IN) Table 142. Timer 1 CAP1_3 capture input multiplexer (CAP1_3_IN, address 0x400C 701C) bit description Bit 0 Symbol INV 0 1 1 EDGE 0 1 2 SYNCH 0 1 3 PULSE 0 1 7:4 SELECT 0x0 0x1 0x2 31:8 Value Description Invert input Not inverted. Input inverted. Enable rising edge detection No edge detection. Rising edge detection enabled. Enable synchronization Disable synchronization. Enable synchronization. Enable single pulse generation. Disable single pulse generation. Enable single pulse generation. Select input. Values 0x3 to 0xF are reserved. CTOUT_3 or T0_MAT3 T1_CAP3 T0_MAT3 Reserved Reset value 14.4.9 Timer 2 CAP2_0 capture input multiplexer (CAP2_0_IN) Table 143. Timer 2 CAP2_0 capture input multiplexer (CAP2_0_IN, address 0x400C 7020) bit description Bit 0 Symbol INV 0 1 1 EDGE 0 1 2 SYNCH 0 Value Description Invert input Not inverted. Input inverted. Enable rising edge detection No edge detection. Rising edge detection enabled. Enable synchronization Disable synchronization. Reset value All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 231 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 14: LPC18xx Global Input Multiplexer Array (GIMA) FT D R R A Table 143. Timer 2 CAP2_0 capture input multiplexer (CAP2_0_IN, address 0x400C 7020) bit description D R A R A FT D R FT D R A R A A FT F FT Bit Symbol Value 1 Description Enable synchronization. Enable single pulse generation. Disable single pulse generation. Enable single pulse generation. Select input. Values 0x4 to 0xF are reserved. CTIN_0 Reserved T2_CAP0 Reserved Reset value D D R R A A FT D R A FT D 3 PULSE 0 1 FT D R A 7:4 SELECT 0x0 0x1 0x2 31:8 - 14.4.10 Timer 2 CAP2_1 capture input multiplexer (CAP2_1_IN) Table 144. Timer 2 CAP2_1 capture input multiplexer (CAP2_1_IN, address 0x400C 7024) bit description Bit 0 Symbol INV 0 1 1 EDGE 0 1 2 SYNCH 0 1 3 PULSE 0 1 7:4 SELECT 0x0 0x1 0x2 0x3 31:8 Value Description Invert input Not inverted. Input inverted. Enable rising edge detection No edge detection. Rising edge detection enabled. Enable synchronization Disable synchronization. Enable synchronization. Enable single pulse generation. Disable single pulse generation. Enable single pulse generation. Select input. Values 0x4 to 0xF are reserved. CTIN_1 U2_TXD - I2S1_RX_MWS T2_CAP1 Reserved Reset value All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 232 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 14: LPC18xx Global Input Multiplexer Array (GIMA) FT D R A 14.4.11 Timer 2 CAP2_2 capture input multiplexer (CAP2_2_IN) Table 145. Timer 2 CAP2_2 capture input multiplexer (CAP2_2_IN, address 0x400C 7028) bit description D R A R A FT D R FT D R R A FT D R R A F D R A FT A FT A FT Bit 0 Symbol INV Value Description Invert input Reset value D D R A FT D R 0 1 1 EDGE 0 1 2 SYNCH 0 1 3 PULSE 0 1 7:4 SELECT 0x0 0x1 0x2 0x3 31:8 - Not inverted. Input inverted. Enable rising edge detection No edge detection. Rising edge detection enabled. Enable synchronization Disable synchronization. Enable synchronization. Enable single pulse generation. Disable single pulse generation. Enable single pulse generation. Select input. Values 0x4 to 0xF are reserved. CTIN_5 U2_RXD - I2S1_TX_MWS T2_CAP2 Reserved A 14.4.12 Timer 2 CAP2_3 capture input multiplexer (CAP2_3_IN) Table 146. Timer 2 CAP2_3 capture input multiplexer (CAP2_3_IN, address 0x400C 702C) bit description Bit 0 Symbol INV 0 1 1 EDGE 0 1 2 SYNCH 0 1 3 PULSE 0 1 7:4 SELECT Value Description Invert input Not inverted. Input inverted. Enable rising edge detection No edge detection. Rising edge detection enabled. Enable synchronization Disable synchronization. Enable synchronization. Enable single pulse generation. Disable single pulse generation. Enable single pulse generation. Select input. Values 0x3 to 0xF are reserved. © NXP B.V. 2011. All rights reserved. Reset value All information provided in this document is subject to legal disclaimers. User manual Rev. 00.13 — 20 July 2011 233 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 14: LPC18xx Global Input Multiplexer Array (GIMA) FT D R R A Table 146. Timer 2 CAP2_3 capture input multiplexer (CAP2_3_IN, address 0x400C 702C) bit description D R A R A FT D R FT D R A R A A FT F FT Bit Symbol Value 0x0 0x1 0x2 Description CTOUT_7 or T1_MAT3 T2_CAP3 T1_MAT3 Reserved Reset value D D R R A FT D R A FT D A FT D R A 31:8 - 14.4.13 Timer 3 CAP3_0 capture input multiplexer (CAP3_0_IN) Table 147. Timer 3 CAP3_0 capture input multiplexer (CAP3_0_IN, address 0x400C 7030) bit description Bit 0 Symbol INV 0 1 1 EDGE 0 1 2 SYNCH 0 1 3 PULSE 0 1 7:4 SELECT 0x0 0x1 0x2 31:8 Value Description Invert input Not inverted. Input inverted. Enable rising edge detection No edge detection. Rising edge detection enabled. Enable synchronization Disable synchronization. Enable synchronization. Enable single pulse generation. Disable single pulse generation. Enable single pulse generation. Select input. Values 0x3 to 0xF are reserved. CTIN_0 I2S0_RX_MWS T3_CAP0 Reserved Reset value 14.4.14 Timer 3 CAP3_1 capture input multiplexer (CAP3_1_IN) Table 148. Timer 3 CAP3_1 capture input multiplexer (CAP3_1_IN, address 0x400C 7034) bit description Bit 0 Symbol INV 0 1 1 EDGE 0 1 2 Value Description Invert input Not inverted. Input inverted. Enable rising edge detection No edge detection. Rising edge detection enabled. Enable synchronization Reset value SYNCH All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 234 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 14: LPC18xx Global Input Multiplexer Array (GIMA) FT D R R A Table 148. Timer 3 CAP3_1 capture input multiplexer (CAP3_1_IN, address 0x400C 7034) bit description D R A R A FT D R FT D R A R A A FT F FT Bit Symbol Value 0 1 Description Disable synchronization. Enable synchronization. Enable single pulse generation. Disable single pulse generation. Enable single pulse generation. Select input. Values 0x4 to 0xF are reserved. CTIN_6 U3_TXD TBD - I2S0_TX_MWS T3_CAP1 Reserved Reset value D D R R A FT D R A FT D A FT D 3 PULSE 0 1 R A 7:4 SELECT 0x0 0x1 0x2 0x3 31:8 - 14.4.15 Timer 3 CAP3_2 capture input multiplexer (CAP3_2_IN) Table 149. Timer 3 CAP3_2 capture input multiplexer (CAP3_2_IN, address 0x400C 7038) bit description Bit 0 Symbol INV 0 1 1 EDGE 0 1 2 SYNCH 0 1 3 PULSE 0 1 7:4 SELECT 0x0 0x1 0x2 0x3 31:8 Value Description Invert input Not inverted. Input inverted. Enable rising edge detection No edge detection. Rising edge detection enabled. Enable synchronization Disable synchronization. Enable synchronization. Enable single pulse generation. Disable single pulse generation. Enable single pulse generation. Select input. Values 0x4 to 0xF are reserved. CTIN_7 U3_RXD SOF0 (Start-Of-Frame USB0) T3_CAP2 Reserved Reset value All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 235 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 14: LPC18xx Global Input Multiplexer Array (GIMA) FT D R A 14.4.16 Timer 3 CAP3_3 capture input multiplexer (CAP3_3_IN) Table 150. Timer 3 CAP3_3 capture input multiplexer (CAP3_3_IN, address 0x400C 703C) bit description D R A R A FT D R FT D R R A FT D R R A F D R A FT A FT A FT Bit 0 Symbol INV Value Description Invert input Reset value D D R A FT D R 0 1 1 EDGE 0 1 2 SYNCH 0 1 3 PULSE 0 1 7:4 SELECT 0x0 0x1 0x2 0x3 31:8 - Not inverted. Input inverted. Enable rising edge detection No edge detection. Rising edge detection enabled. Enable synchronization Disable synchronization. Enable synchronization. Enable single pulse generation. Disable single pulse generation. Enable single pulse generation. Select input. Values 0x4 to 0xF are reserved. CTOUT11 or T2_MAT3 SOF1 T3_CAP3 T2_MAT3 Reserved A 14.4.17 SCT CTIN_0 capture input multiplexer (CTIN_0_IN) Table 151. SCT CTIN_0 capture input multiplexer (CTIN_0_IN, address 0x400C 7040) bit description Bit 0 Symbol INV 0 1 1 EDGE 0 1 2 SYNCH 0 1 3 PULSE 0 1 7:4 SELECT 0x0 Value Description Invert input Not inverted. Input inverted. Enable rising edge detection No edge detection. Rising edge detection enabled. Enable synchronization Disable synchronization. Enable synchronization. Enable single pulse generation. Disable single pulse generation. Enable single pulse generation. Select input. Values 0x3 to 0xF are reserved. CTIN_0 Reset value All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 236 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 14: LPC18xx Global Input Multiplexer Array (GIMA) FT D R R A Table 151. SCT CTIN_0 capture input multiplexer (CTIN_0_IN, address 0x400C 7040) bit description D R A R A FT D R FT D R A R A FT A F FT Bit Symbol Value 0x1 0x2 Description Reserved Reserved Reserved Reset value D D R R A FT D R A FT D A FT 31:8 - D R A 14.4.18 SCT CTIN_1 capture input multiplexer (CTIN_1_IN) Table 152. SCT CTIN_1 capture input multiplexer (CTIN_1_IN, address 0x400C 7044) bit description Bit 0 Symbol INV 0 1 1 EDGE 0 1 2 SYNCH 0 1 3 PULSE 0 1 7:4 SELECT 0x0 0x1 0x2 31:8 Value Description Invert input Not inverted. Input inverted. Enable rising edge detection No edge detection. Rising edge detection enabled. Enable synchronization Disable synchronization. Enable synchronization. Enable single pulse generation. Disable single pulse generation. Enable single pulse generation. Select input. Values 0x3 to 0xF are reserved. CTIN_1 U2_TXD Reserved Reserved Reset value 14.4.19 SCT CTIN_2 capture input multiplexer (CTIN_2_IN) Table 153. SCT CTIN_2 capture input multiplexer (CTIN_2_IN, address 0x400C 7048) bit description Bit 0 Symbol INV 0 1 1 EDGE 0 1 2 SYNCH 0 1 3 Value Description Invert input Not inverted. Input inverted. Enable rising edge detection No edge detection. Rising edge detection enabled. Enable synchronization Disable synchronization. Enable synchronization. Enable single pulse generation. Reset value PULSE All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 237 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 14: LPC18xx Global Input Multiplexer Array (GIMA) FT D R R A Table 153. SCT CTIN_2 capture input multiplexer (CTIN_2_IN, address 0x400C 7048) bit description D R A R A FT D R FT D R A R A FT A F FT Bit Symbol Value Description 0 1 Disable single pulse generation. Enable single pulse generation. Select input. Values 0x3 to 0xF are reserved. 0x0 0x1 0x2 CTIN_2 Reserved Reserved Reserved Reset value D D R R A FT D R A FT D A FT 7:4 SELECT D R A 31:8 - 14.4.20 SCT CTIN_3 capture input multiplexer (CTIN_3_IN) Table 154. SCT CTIN_3 capture input multiplexer (CTIN_3_IN, address 0x400C 704C) bit description Bit 0 Symbol INV 0 1 1 EDGE 0 1 2 SYNCH 0 1 3 PULSE 0 1 7:4 SELECT 0x0 0x1 0x2 0x3 31:8 Value Description Invert input Not inverted. Input inverted. Enable rising edge detection No edge detection. Rising edge detection enabled. Enable synchronization Disable synchronization. Enable synchronization. Enable single pulse generation. Disable single pulse generation. Enable single pulse generation. Select input. Values 0x4 to 0xF are reserved. CTIN_3 U0_TXD Reserved Reserved Reserved Reset value 14.4.21 SCT CTIN_4 capture input multiplexer (CTIN_4_IN) Table 155. SCT CTIN_4 capture input multiplexer (CTIN_4_IN, address 0x400C 7050) bit description Bit 0 Symbol INV 0 1 1 EDGE 0 Value Description Invert input Not inverted. Input inverted. Enable rising edge detection No edge detection. Reset value All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 238 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 14: LPC18xx Global Input Multiplexer Array (GIMA) FT D R R A Table 155. SCT CTIN_4 capture input multiplexer (CTIN_4_IN, address 0x400C 7050) bit description D R A R A FT D R FT D R A R A FT A F FT Bit 2 Symbol SYNCH Value 1 0 1 Description Rising edge detection enabled. Enable synchronization Disable synchronization. Enable synchronization. Enable single pulse generation. Disable single pulse generation. Enable single pulse generation. Select input. Values 0x4 to 0xF are reserved. CTIN_4 U0_RXD TBD - I2S1_RX_MWS1 TBD - I2S1_TX_MWS1 Reserved Reset value D D R R A FT D R A FT D A FT D R A 3 PULSE 0 1 7:4 SELECT 0x0 0x1 0x2 0x3 31:8 - 14.4.22 SCT CTIN_5 capture input multiplexer (CTIN_5_IN) Table 156. SCT CTIN_5 capture input multiplexer (CTIN_5_IN, address 0x400C 7054) bit description Bit 0 Symbol INV 0 1 1 EDGE 0 1 2 SYNCH 0 1 3 PULSE 0 1 7:4 SELECT 0x0 0x1 0x2 31:8 Value Description Invert input Not inverted. Input inverted. Enable rising edge detection No edge detection. Rising edge detection enabled. Enable synchronization Disable synchronization. Enable synchronization. Enable single pulse generation. Disable single pulse generation. Enable single pulse generation. Select input. Values 0x3 to 0xF are reserved. CTIN_5 U2_RXD Reserved Reserved Reset value All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 239 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 14: LPC18xx Global Input Multiplexer Array (GIMA) FT D R A 14.4.23 SCT CTIN_6 capture input multiplexer (CTIN_6_IN) Table 157. SCT CTIN_6 capture input multiplexer (CTIN_6_IN, address 0x400C 7058) bit description D R A R A FT D R FT D R R A FT D R R A F D R A FT A FT A FT Bit 0 Symbol INV Value 0 1 Description Invert input Not inverted. Input inverted. Enable rising edge detection No edge detection. Rising edge detection enabled. Enable synchronization Disable synchronization. Enable synchronization. Enable single pulse generation. Disable single pulse generation. Enable single pulse generation. Select input. Values 0x4 to 0xF are reserved. Reset value D D R A FT D R A 1 EDGE 0 1 2 SYNCH 0 1 3 PULSE 0 1 7:4 SELECT 0x0 0x1 0x2 0x3 CTIN_6 U3_TXD TBD - I2S0_RX_MWS TBD - I2S0_TX_MWS Reserved 31:8 - 14.4.24 SCT CTIN_7 capture input multiplexer (CTIN_7_IN) Table 158. SCT CTIN_7 capture input multiplexer (CTIN_7_IN, address 0x400C 705C) bit description Bit 0 Symbol INV 0 1 1 EDGE 0 1 2 SYNCH 0 1 3 PULSE 0 1 7:4 SELECT 0x0 0x1 Value Description Invert input Not inverted. Input inverted. Enable rising edge detection No edge detection. Rising edge detection enabled. Enable synchronization Disable synchronization. Enable synchronization. Enable single pulse generation. Disable single pulse generation. Enable single pulse generation. Select input. Values 0x4 to 0xF are reserved. CTIN_7 U3_RXD Reset value All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 240 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 14: LPC18xx Global Input Multiplexer Array (GIMA) FT D R R A Table 158. SCT CTIN_7 capture input multiplexer (CTIN_7_IN, address 0x400C 705C) bit description D R A R A FT D R FT D R A R A FT A F FT Bit Symbol Value 0x2 0x3 Description SOF0 (Start-Of-Frame USB0) SOF1 (Start-Of-Frame USB1) Reserved Reset value D D R R A FT D R A FT D A FT 31:8 - D R A 14.4.25 VADC trigger input multiplexer (VADC_TRIGGER_IN) Table 159. ADC trigger input multiplexer (VADC_TRIGGER_IN, address 0x400C 7060) bit description Bit 0 Symbol INV 0 1 1 EDGE 0 1 2 SYNCH 0 1 3 PULSE 0 1 7:4 SELECT 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 31:8 Value Description Invert input Not inverted. Input inverted. Enable rising edge detection No edge detection. Rising edge detection enabled. Enable synchronization Disable synchronization. Enable synchronization. Enable single pulse generation. Disable single pulse generation. Enable single pulse generation. Select input. Values 0xA to 0xF are reserved. GPIO6[28] GPIO5[3] Reserved Reserved Reserved MCOB2 CTOUT_0 or T0_MAT0 CTOUT_8 or T2_MAT0 T0_MAT0 T2_MAT0 Reserved Reset value 14.4.26 Event router input 13 multiplexer (EVENTROUTER_13_IN) Table 160. Event router input 13 multiplexer (EVENTROUTER_13_IN, address 0x400C 7064) bit description Bit 0 Symbol INV 0 1 Value Description Invert input Not inverted. Input inverted. Reset value All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 241 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 14: LPC18xx Global Input Multiplexer Array (GIMA) FT D R R A Table 160. Event router input 13 multiplexer (EVENTROUTER_13_IN, address 0x400C 7064) bit description D R A R A FT D R FT D R A R A A FT F FT Bit 1 Symbol EDGE Value Description Enable rising edge detection 0 1 No edge detection. Rising edge detection enabled. Enable synchronization 0 1 Disable synchronization. Enable synchronization. Enable single pulse generation. 0 1 Disable single pulse generation. Enable single pulse generation. Select input. Values 0x3 to 0xF are reserved. 0x0 0x1 0x2 CTOUT_2 or T0_MAT2 Reserved T0_MAT2 Reserved Reset value D D R R A FT D R A FT D A FT D R 2 SYNCH A 3 PULSE 7:4 SELECT 31:8 - 14.4.27 Event router input 14 multiplexer (EVENTROUTER_14_IN) Table 161. Event router input 14 multiplexer (EVENTROUTER_14_IN, address 0x400C 7068) bit description Bit 0 Symbol INV 0 1 1 EDGE 0 1 2 SYNCH 0 1 3 PULSE 0 1 7:4 SELECT 0x0 0x1 0x2 31:8 Value Description Invert input Not inverted. Input inverted. Enable rising edge detection No edge detection. Rising edge detection enabled. Enable synchronization Disable synchronization. Enable synchronization. Enable single pulse generation. Disable single pulse generation. Enable single pulse generation. Select input. Values 0x3 to 0xF are reserved. CTOUT_6 or T1_MAT2 Reserved T1_MAT2 Reserved Reset value All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 242 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 14: LPC18xx Global Input Multiplexer Array (GIMA) FT D R A 14.4.28 Event router input 16 multiplexer (EVENTROUTER_16_IN) Table 162. Event router input 16multiplexer (EVENTROUTER_16_IN, address 0x400C 706C) bit description D R A R A FT D R FT D R R A FT D R R A F D R A FT A FT A FT Bit 0 Symbol INV Value 0 1 Description Invert input Not inverted. Input inverted. Enable rising edge detection No edge detection. Rising edge detection enabled. Enable synchronization Disable synchronization. Enable synchronization. Enable single pulse generation. Disable single pulse generation. Enable single pulse generation. Select input. Values 0x2 to 0xF are reserved. CTOUT_14 or T3_MAT2 T3_MAT2 Reserved Reset value D D R A FT D R A 1 EDGE 0 1 2 SYNCH 0 1 3 PULSE 0 1 7:4 SELECT 0x0 0x1 31:8 - 14.4.29 ADC start0 input multiplexer (ADCSTART0_IN) Table 163. ADC start0 input multiplexer (ADCSTART0_IN, address 0x400C 7070) bit description Bit 0 Symbol INV 0 1 1 EDGE 0 1 2 SYNCH 0 1 3 PULSE 0 1 7:4 SELECT 0x0 0x1 31:8 Value Description Invert input Not inverted. Input inverted. Enable rising edge detection No edge detection. Rising edge detection enabled. Enable synchronization Disable synchronization. Enable synchronization. Enable single pulse generation. Disable single pulse generation. Enable single pulse generation. Select input. Values 0x2 to 0xF are reserved. CTOUT_15 or T3_MAT3 T0_MAT0 Reserved Reset value All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 243 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 14: LPC18xx Global Input Multiplexer Array (GIMA) FT D R A D R A R A FT D R FT 14.4.30 ADC start1 input multiplexer (ADCSTART1_IN) D R Table 164. ADC start1 input multiplexer (ADCSTART1_IN, address 0x400C 7074) bit description Bit 0 Symbol INV 0 1 1 EDGE 0 1 2 SYNCH 0 1 3 PULSE 0 1 7:4 SELECT 0x0 0x1 31:8 Value Description Invert input Not inverted. Input inverted. Enable rising edge detection No edge detection. Rising edge detection enabled. Enable synchronization Disable synchronization. Enable synchronization. Enable single pulse generation. Disable single pulse generation. Enable single pulse generation. Select input. Values 0x2 to 0xF are reserved. CTOUT_8 or T2_MAT0 T2_MAT0 Reserved Reset value R A FT D R R A F D R A FT A FT A FT D R A D FT D R A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 244 of 1164 D R A FT D R A FT D R A FT D R A FT D R A FT UM10430 Chapter 15: LPC18xx GPIO Rev. 00.13 — 20 July 2011 D D D R A FT D D R A FT D R A FT D R A R A FT D R A R A FT D R A FT D R A F R A FT D R R D User manual FT D R A FT FT A FT 15.1 How to read this chapter D Remark: This chapter describes the GPIO of the LPC18xx Rev ‘A’ parts. For the GPIO block of the LPC18xx Rev ‘-’ parts, see Section 42.8. All GPIO register bit descriptions refer to up to 31 pins on each GPIO port. Depending on the package type, not all pins are available, and the corresponding bits in the GPIO registers are reserved (see Table 165). Table 165. GPIO pins available LBGA256 GPIO Port 0 GPIO Port 1 GPIO Port 2 GPIO Port 3 GPIO0[15:0] GPIO1[15:0] GPIO2[15:0] GPIO3[15:0] TFBGA180 GPIO0[15:0] GPIO1[15:0] GPIO2[15:0] GPIO3[15:0] TFBGA100 GPIO0[4:0]; GPIO0[15:6] GPIO1[15:0] GPIO3[1:0]; GPIO3[5:3]; GPIO3[7] GPIO5[11:0] LQFP208 GPIO0[15:0] GPIO1[15:0] GPIO2[15:0] GPIO3[15:0] LQFP144 GPIO0[15:0] GPIO1[15:0] GPIO2[15:0] GPIO3[15:0] LQFP100 GPIO0[4:0]; GPIO0[15:6] GPIO1[15:0] GPIO3[1:0]; GPIO3[5:3]; GPIO3[7] GPIO5[11:0] - D R A FT D R A GPIO Port 4 GPIO Port 5 GPIO Port 6 GPIO Port 7 GPIO4[15:0] GPIO5[26:0] GPIO6[30:0] GPIO7[25:0] GPIO4[15:0] GPIO5[26:0] GPIO6[30:25] GPIO7[4:0] GPIO4[15:0] GPIO5[26:0] GPIO6[30:0] GPIO7[25:0] GPIO4[11] GPIO5[16:0]; GPIO5[18] - 15.2 Basic configuration The GPIO blocks share a common clock and reset connection and are configured as follows: • • • • See Table 166 for clocking and power control. The GPIO is reset by a GPIO_RST (reset #28). All GPIO pins are set to input by default. For the pin interrupts, select up to 8 external interrupt pins from all GPIO port pins in the SCU (see Table 130 and Table 131). The pin interrupts must be enabled in the NVIC (see Table 13). • The GPIO group interrupts must be enabled in the NVIC (see Table 13). Table 166. GPIO clocking and power control Base clock GPIO, GPIO pin interrupt, GPIO group0 interrupt, GPIO group1 interrupt BASE_M3_CLK Branch clock CLK_M3_GPIO Maximum frequency 150 MHz All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 245 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 15: LPC18xx GPIO FT D R A D R A R A FT D R FT 15.3 Features 15.3.1 GPIO pin interrupt features requests. Each request creates a separate interrupt in the NVIC. D R • Up to 8 pins can be selected from all GPIO pins as edge- or level-sensitive interrupt • Edge-sensitive interrupt pins can interrupt on rising or falling edges or both. • Level-sensitive interrupt pins can be HIGH- or LOW-active. 15.3.2 GPIO group interrupt features • The inputs from any number of GPIO pins can be enabled to contribute to a combined group interrupt. • The polarity of each input enabled for the group interrupt can be configured HIGH or LOW. • Enabled interrupts can be logically combined through an OR or AND operation. • Two group interrupts are supported to reflect two distinct interrupt patterns. • The GPIO group interrupts can wake up the part from sleep, deep-sleep or power-down modes. R A FT D R R A F D R A FT A FT A FT D R A D FT D R A 15.3.3 GPIO port features • GPIO pins can be configured as input or output by software. • All GPIO pins default to inputs with interrupt disabled at reset. • Pin registers allow pins to be sensed and set individually. 15.4 Introduction The GPIO pins can be used in several ways to set pins as inputs or outputs and use the inputs as combinations of level and edge sensitive interrupts. 15.4.1 GPIO pin interrupts From all available GPIO pins, up to eight pins can be selected in the system control block to serve as external interrupt pins (see ). The external interrupt pins are connected to eight individual interrupts in the NVIC and are created based on rising or falling edges or on the input level on the pin. 15.4.2 GPIO group interrupt For each port/pin connected to one of the two the GPIO Grouped Interrupt blocks (GROUP0 and GROUP1), the GPIO grouped interrupt registers determine which pins are enabled to generate interrupts and what the active polarities of each of those inputs are. The GPIO grouped interrupt registers also select whether the interrupt output will be level or edge triggered and whether it will be based on the OR or the AND of all of the enabled inputs. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 246 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 15: LPC18xx GPIO FT D R R A When the designated pattern is detected on the selected input pins, the GPIO grouped interrupt block will generate an interrupt. If the part is in a power-savings mode it will first asynchronously wake the part up prior to asserting the interrupt request. The interrupt request line can be cleared by writing a one to the interrupt status bit in the control register. R A A FT D R A FT D R A R A FT D R FT D R A F R A FT D FT D FT R A D 15.4.3 GPIO port The GPIO port registers can be used to configure each GPIO pin as input or output and read the state of each pin if the pin is configured as input or set the state of each pin if the pin is configured as output. D R A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 247 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 15: LPC18xx GPIO FT D R A D R A R A FT D R FT 15.5 Register description The GPIO consists of the following blocks: D R • The GPIO pin interrupts block at address 0x4008 7000. Registers in this block enable D the up to 8 pin interrupts selected in (see ) and configure the level and edge sensitivity for each selected pin interrupt. The GPIO interrupt registers are listed in and • The GPIO GROUP0 interrupt block at address 0x4008 8000. Registers in this block allow to configure any pin on port 0 and 1 to contribute to a combined interrupt. The GPIO GROUP0 registers are listed in Table 168 and Section 15.5.2. • The GPIO GROUP1 interrupt block at address 0x4008 9000. Registers in this block allow to configure any pin on port 0 and 1 to contribute to a combined interrupt. The GPIO GROUP1 registers are listed in Table 169 and Section 15.5.2. • The GPIO port block at address 0x400F 4000. Registers in this block allow to read and write to port pins and configure port pins as inputs or outputs.The GPIO port registers are listed in Table 170 and Section 15.5.3. Note: In all GPIO registers, bits that are not shown are reserved. Table 167. Register overview: GPIO pin interrupts (base address: 0x4008 7000) Name ISEL IENR SIENR CIENR IENF SIENF CIENF RISE FALL IST Access Address offset R/W R/W WO WO R/W WO WO R/W R/W R/W 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 0x024 Description Pin Interrupt Mode register Pin Interrupt Enable (Rising) register Set Pin Interrupt Enable (Rising) register Clear Pin Interrupt Enable (Rising) register Pin Interrupt Enable Falling Edge / Active Level register Set Pin Interrupt Enable Falling Edge / Active Level register Clear Pin Interrupt Enable Falling Edge / Active Level address Pin Interrupt Rising Edge register Pin Interrupt Falling Edge register Pin Interrupt Status register Reset value 0 0 NA NA 0 NA NA 0 0 0 Table 168. Register overview: GPIO GROUP0 interrupt (base address 0x4008 8000) Name CTRL PORT_POL0 PORT_POL1 PORT_POL2 Access Address offset R/W R/W R/W R/W 0x000 0x020 0x024 0x028 Description GPIO grouped interrupt control register GPIO grouped interrupt port 0 polarity register GPIO grouped interrupt port 1 polarity register GPIO grouped interrupt port 2 polarity register Reset value 0 0xFFFF FFFF 0xFFFF FFFF 0xFFFF FFFF R A FT D R R A F D R A FT A FT A FT R A D FT D R A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 248 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 15: LPC18xx GPIO FT D R R A Table 168. Register overview: GPIO GROUP0 interrupt (base address 0x4008 8000) D R A R A FT D R FT D R A R A A Name PORT_POL3 PORT_POL4 PORT_POL5 PORT_POL6 PORT_POL7 PORT_ENA0 PORT_ENA1 PORT_ENA2 PORT_ENA3 PORT_ENA4 PORT_ENA5 PORT_ENA6 PORT_ENA7 Access Address offset R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0x02C 0x030 0x034 0x038 0x03C 0x040 0x044 0x048 0x04C 0x050 0x054 0x058 0x05C Description Reset value FT D R A F FT 0 0 0 0 0 0 0 0 D R A GPIO grouped interrupt port 3 polarity register GPIO grouped interrupt port 4 polarity register GPIO grouped interrupt port 5 polarity register GPIO grouped interrupt port 6 polarity register GPIO grouped interrupt port 7 polarity register GPIO grouped interrupt port 0 enable register GPIO grouped interrupt port 1 enable register GPIO grouped interrupt port 2 enable register GPIO grouped interrupt port 3 enable register GPIO grouped interrupt port 4 enable register GPIO grouped interrupt port 5 enable register GPIO grouped interrupt port 5 enable register GPIO grouped interrupt port 5 enable register 0xFFFF FFFF 0xFFFF FFFF 0xFFFF FFFF 0xFFFF FFFF 0xFFFF FFFF FT D R A FT D R A FT D Table 169. Register overview: GPIO GROUP1 interrupt (base address 0x4008 9000) Name CTRL PORT_POL0 PORT_POL1 PORT_POL2 PORT_POL3 PORT_POL4 PORT_POL5 PORT_POL6 PORT_POL7 PORT_ENA0 PORT_ENA1 PORT_ENA2 PORT_ENA3 PORT_ENA4 Access Address offset R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0x000 0x020 0x024 0x028 0x02C 0x030 0x034 0x038 0x03C 0x040 0x044 0x048 0x04C 0x050 Description GPIO grouped interrupt control register GPIO grouped interrupt port 0 polarity register GPIO grouped interrupt port 1 polarity register GPIO grouped interrupt port 2 polarity register GPIO grouped interrupt port 3 polarity register GPIO grouped interrupt port 4 polarity register GPIO grouped interrupt port 5 polarity register GPIO grouped interrupt port 6 polarity register GPIO grouped interrupt port 7 polarity register GPIO grouped interrupt port 0 enable register GPIO grouped interrupt port 1 enable register GPIO grouped interrupt port 2 enable register GPIO grouped interrupt port 3 enable register GPIO grouped interrupt port 4 enable register Reset value 0 0xFFFF FFFF 0xFFFF FFFF 0xFFFF FFFF 0xFFFF FFFF 0xFFFF FFFF 0xFFFF FFFF 0xFFFF FFFF 0xFFFF FFFF 0 0 0 0 0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 249 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 15: LPC18xx GPIO FT D R R A Table 169. Register overview: GPIO GROUP1 interrupt (base address 0x4008 9000) D R A R A FT D R FT D R A R A A Name PORT_ENA5 PORT_ENA6 PORT_ENA7 Access Address offset R/W R/W R/W 0x054 0x058 0x05C Description GPIO grouped interrupt port 5 enable register GPIO grouped interrupt port 5 enable register GPIO grouped interrupt port 5 enable register Reset value FT D R A F FT 0 0 0 D R A FT D R A FT D FT D R A GPIO port addresses can be read and written as bytes, halfwords, or words. Table 170. Register overview: GPIO port (base address 0x400F 4000) Name B0 to B31 B32 to Bx B64 to Bx B96 to Bx B128 to Bx B160 to Bx B192 to Bx B224 to Bx W0 to Wx W32 to Wx W64 to Wx W96 to Wx W128 to Wx W160 to Wx W192 to Wx W224 to Wx DIR0 DIR1 DIR2 DIR3 DIR4 DIR5 DIR6 DIR7 MASK0 MASK1 MASK2 MASK3 MASK4 MASK5 MASK6 MASK7 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Address offset 0x0000 to x001F 0x0020 to 0x003F 0x0040 to 0x005F 0x0060 to 0x007F 0x0080 to 0x009F 0x00A0 to 0x00BF 0x00C0 to0x00DF 0x00E0 to 0x00FC 0x1000 to 0x107C 0x1080 to 0x10FC 0x1100 to 0x11FC 0x1180 to 0x11FC 0x1200 to 0x12FC 0x1280 to 0x12FC 0x1300 to 0x137C 0x1380 to 0x13FC 0x2000 0x2004 0x2008 0x200C 0x2010 0x2014 0x2018 0x201C 0x2080 0x2084 0x2088 0x208C 0x2090 0x2094 0x2098 0x209C Description Reset value Width byte (8 bit) byte (8 bit) byte (8 bit) byte (8 bit) byte (8 bit) byte (8 bit) byte (8 bit) byte (8 bit) word (32 bit) word (32 bit) word (32 bit) word (32 bit) word (32 bit) word (32 bit) word (32 bit) word (32 bit) word (32 bit) word (32 bit) word (32 bit) word (32 bit) word (32 bit) word (32 bit) word (32 bit) word (32 bit) word (32 bit) word (32 bit) word (32 bit) word (32 bit) word (32 bit) word (32 bit) word (32 bit) word (32 bit) © NXP B.V. 2011. All rights reserved. Byte pin registers port 0; pins PIO0_0 ext[1] to PIO0_31 Byte pin registers port 1 Byte pin registers port 2 Byte pin registers port 3 Byte pin registers port 4 Byte pin registers port 5 Byte pin registers port 6 Byte pin registers port 7 Word pin registers port 0 Word pin registers port 1 Word pin registers port 2 Word pin registers port 3 Word pin registers port 4 Word pin registers port 5 Word pin registers port 6 Word pin registers port 7 Direction registers port 0 Direction registers port 1 Direction registers port 2 Direction registers port 3 Direction registers port 4 Direction registers port 5 Direction registers port 6 Direction registers port 7 Mask register port 0 Mask register port 1 Mask register port 2 Mask register port 3 Mask register port 4 Mask register port 5 Mask register port 6 Mask register port 7 ext[1] ext[1] ext[1] ext[1] ext[1] ext[1] ext[1] ext[1] ext[1] ext[1] ext[1] ext[1] ext[1] ext[1] ext[1] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 All information provided in this document is subject to legal disclaimers. User manual Rev. 00.13 — 20 July 2011 250 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 15: LPC18xx GPIO FT D R A D R A R A FT D R FT Table 170. Register overview: GPIO port (base address 0x400F 4000) Name PIN0 PIN1 PIN2 PIN3 PIN4 PIN5 PIN6 PIN7 MPIN0 MPIN1 MPIN2 MPIN3 MPIN4 MPIN5 MPIN6 MPIN7 SET0 SET1 SET2 SET3 SET4 SET5 SET6 SET7 CLR0 CLR1 CLR2 CLR3 CLR4 CLR5 CLR6 CLR7 NOT0 NOT1 D R R A R A A Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W WO WO WO WO WO WO WO WO WO WO Address offset 0x2100 0x2104 0x2108 0x210C 0x2110 0x2114 0x2118 0x211C 0x2180 0x2184 0x2188 0x218C 0x2190 0x2194 0x2198 0x219C 0x2200 0x2204 0x2208 0x220C 0x2210 0x2214 0x2218 0x221C 0x2280 0x2284 0x2288 0x228C 0x2290 0x2294 0x2298 0x229C 0x2300 0x2304 Description Port pin register port 0 Port pin register port 1 Port pin register port 2 Port pin register port 3 Port pin register port 4 Port pin register port 5 Port pin register port 6 Port pin register port 7 Masked port register port 0 Masked port register port 1 Masked port register port 2 Masked port register port 3 Masked port register port 4 Masked port register port 5 Masked port register port 6 Masked port register port 7 Write: Set register for port 0 Read: output bits for port 0 Write: Set register for port 1 Read: output bits for port 1 Write: Set register for port 2 Read: output bits for port 2 Write: Set register for port 3 Read: output bits for port 3 Write: Set register for port 4 Read: output bits for port 4 Write: Set register for port 5 Read: output bits for port 5 Write: Set register for port 6 Read: output bits for port 6 Write: Set register for port 7 Read: output bits for port 7 Clear port 0 Clear port 1 Clear port 2 Clear port 3 Clear port 4 Clear port 5 Clear port 6 Clear port 7 Toggle port 0 Toggle port 1 All information provided in this document is subject to legal disclaimers. Reset value ext[1] ext[1] ext[1] ext[1] ext[1] ext[1] ext[1] ext[1] ext[1] ext[1] ext[1] ext[1] ext[1] ext[1] ext[1] ext[1] 0 0 0 0 0 0 0 0 NA NA NA NA NA NA NA NA NA NA Width FT D R R A FT D R A FT A F word (32 bit) word (32 bit) word (32 bit) word (32 bit) word (32 bit) word (32 bit) word (32 bit) word (32 bit) word (32 bit) word (32 bit) word (32 bit) word (32 bit) word (32 bit) word (32 bit) word (32 bit) word (32 bit) word (32 bit) word (32 bit) word (32 bit) word (32 bit) word (32 bit) word (32 bit) word (32 bit) word (32 bit) word (32 bit) word (32 bit) word (32 bit) word (32 bit) word (32 bit) word (32 bit) word (32 bit) word (32 bit) word (32 bit) word (32 bit) © NXP B.V. 2011. All rights reserved. FT D FT D D R A User manual Rev. 00.13 — 20 July 2011 251 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 15: LPC18xx GPIO FT D R A D R A R A FT D R FT Table 170. Register overview: GPIO port (base address 0x400F 4000) Name NOT2 NOT3 NOT4 NOT5 NOT6 NOT7 [1] D R R A R A A Access WO WO WO WO WO WO Address offset 0x2308 0x230C 0x2310 0x2314 0x2318 0x231C Description Toggle port 2 Toggle port 3 Toggle port 4 Toggle port 5 Toggle port 6 Toggle port 7 Reset value NA NA NA NA NA NA Width FT D R R A FT D R A FT A F word (32 bit) word (32 bit) word (32 bit) word (32 bit) word (32 bit) word (32 bit) “ext” in this table and subsequent tables indicates that the data read after reset depends on the state of the pin, which in turn may depend on an external source. FT D FT D D R A 15.5.1 GPIO pin interrupts register description 15.5.1.1 Pin interrupt mode register For each of the 8 pin interrupts selected in Table 130 and Table 131, one bit in the ISEL register determines whether the interrupt is edge or level sensitive. Table 171. Pin interrupt mode register (ISEL, address 0x4008 7000) bit description Bit 7:0 Symbol Description PMODE Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive Reserved. Reset Access value 0 R/W 31:8 - - 15.5.1.2 Pin interrupt level (rising edge interrupt) enable register For each of the 8 pin interrupts selected in the PINTSEL registers (see Table 130 and Table 131), one bit in the IENR register enables the interrupt depending on the pin interrupt mode configured in the ISEL register: • If the pin interrupt mode is edge sensitive (PMODE = 0), the rising edge interrupt is enabled. • If the pin interrupt mode is level sensitive (PMODE = 1), the level interrupt is enabled. The PINTEN_F register configures the active level (HIGH or LOW) for this interrupt. Table 172. Pin interrupt level (rising edge interrupt enable) register (IENR, address 0x4008 7004) bit description Bit 7:0 Symbol ENRL Description Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt. Reserved. Reset Access value 0 R/W 31:8 - - - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 252 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 15: LPC18xx GPIO FT D R A D R A R A FT D R FT 15.5.1.3 Pin interrupt level (rising edge interrupt) set register D R For each of the 8 pin interrupts selected in the PINTSEL registers (see Table 130 and Table 131), one bit in the SIENR register sets the corresponding bit in the IENR register depending on the pin interrupt mode configured in the PINTMODE register: • If the pin interrupt mode is edge sensitive (PMODE = 0), the rising edge interrupt is set. • If the pin interrupt mode is level sensitive (PMODE = 1), the level interrupt is set. Table 173. Pin interrupt level (rising edge interrupt) set register (SIENR, address 0x4008 7008) bit description Bit 7:0 Symbol SETENRL Description Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt. Reserved. Reset Access value NA WO R A FT D R R A F D R A FT D R A FT D R A A FT A FT D 31:8 - - - 15.5.1.4 Pin interrupt level (rising edge interrupt) clear register For each of the 8 pin interrupts selected in the PINTSEL registers (see Table 130 and Table 131), one bit in the CIENR register clears the corresponding bit in the IENR register depending on the pin interrupt mode configured in the ISEL register: • If the pin interrupt mode is edge sensitive (PMODE = 0), the rising edge interrupt is cleared. • If the pin interrupt mode is level sensitive (PMODE = 1), the level interrupt is cleared. Table 174. Pin interrupt level (rising edge interrupt) clear register (PCIENR, address 0x4008 700C) bit description Bit 7:0 Symbol CENRL Description Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt. Reserved. Reset Access value NA WO 31:8 - - - 15.5.1.5 Pin interrupt active level (falling edge interrupt enable) register For each of the 8 pin interrupts selected in the PINTSEL registers (see Table 130 and Table 131), one bit in the PINTSEN_F register enables the falling edge interrupt or the configures the level sensitivity depending on the pin interrupt mode configured in the ISEL register: • If the pin interrupt mode is edge sensitive (PMODE = 0), the falling edge interrupt is enabled. • If the pin interrupt mode is level sensitive (PMODE = 1), the active level of the level interrupt (HIGH or LOW) is configured. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 253 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 15: LPC18xx GPIO FT D R R A Table 175. Pin interrupt active level (falling edge interrupt enable) register (IENF, address 0x4008 7010) bit description D R A R A FT D R FT D R A R A A FT D F FT D Bit 7:0 Symbol Description ENAF Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH. Reserved. Reset Access value R R A A FT D FT 0 R/W D R A FT D R A 31:8 - - - 15.5.1.6 Pin interrupt active level (falling edge interrupt) set register For each of the 8 pin interrupts selected in the PINTSEL registers (see Table 130 and Table 131), one bit in the SIENF register sets the corresponding bit in the IENF register depending on the pin interrupt mode configured in the ISEL register: • If the pin interrupt mode is edge sensitive (PMODE = 0), the falling edge interrupt is set. • If the pin interrupt mode is level sensitive (PMODE = 1), the HIGH-active interrupt is selected. Table 176. Pin interrupt active level (falling edge interrupt) set register (SIENF, address 0x4008 7014) bit description Bit 7:0 Symbol Description Reset Access value NA WO SETENAF Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt. Reserved. 31:8 - - 15.5.1.7 Pin interrupt active level (falling edge interrupt) clear register For each of the 8 pin interrupts selected in the PINTSEL registers (see Table 130 and Table 131), one bit in the CIENF register sets the corresponding bit in the IENF register depending on the pin interrupt mode configured in the ISEL register: • If the pin interrupt mode is edge sensitive (PMODE = 0), the falling edge interrupt is cleared. • If the pin interrupt mode is level sensitive (PMODE = 1), the LOW-active interrupt is selected. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 254 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 15: LPC18xx GPIO FT D R R A Table 177. Pin interrupt active level (falling edge interrupt) clear register (CIENF, address 0x4008 7018) bit description D R A R A FT D R FT D R A R A FT D A F FT D Bit 7:0 Symbol Description CENAF Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled. Reserved. Reset Access value R R A A FT D FT NA WO D R A FT D R A 31:8 - - - 15.5.1.8 Pin interrupt rising edge register This register contains ones for pin interrupts selected in the PINTSEL registers (see Table 130 and Table 131) on which a rising edge has been detected. Writing ones to this register clears rising edge detection. Ones in this register assert an interrupt request for pins that are enabled for rising-edge interrupts. All edges are detected for all pins selected by the PINTSEL registers, regardless of whether they are interrupt-enabled. Table 178. Pin interrupt rising edge register (RISE, address 0x4008 701C) bit description Bit 7:0 Symbol RDET Description Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin. Reserved. Reset Access value 0 R/W 31:8 - - - 15.5.1.9 Pin interrupt falling edge register This register contains ones for pin interrupts selected in the PINTSEL registers (see Table 130 and Table 131) on which a falling edge has been detected. Writing ones to this register clears falling edge detection. Ones in this register assert an interrupt request for pins that are enabled for falling-edge interrupts. All edges are detected for all pins selected by the PINTSEL registers, regardless of whether they are interrupt-enabled. Table 179. Pin interrupt falling edge register (FALL, address 0x4008 7020) bit description Bit 7:0 Symbol Description FDET Reset Access value R/W Falling edge detect. Bit n detects the falling edge of the pin 0 selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin. Reserved. - 31:8 - - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 255 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 15: LPC18xx GPIO FT D R A D R A R A FT D R FT 15.5.1.10 Pin interrupt status register D R Reading this register returns ones for pin interrupts that are currently requesting an interrupt. For pins identified as edge-sensitive in the Interrupt Select register, writing ones to this register clears both rising- and falling-edge detection for the pin. For level-sensitive pins, writing ones inverts the corresponding bit in the Active level register, thus switching the active level on the pin. Table 180. Pin interrupt status register (IST address 0x4008 7024) bit description Bit 7:0 Symbol Description PSTAT Reset Access value R/W R A FT D R R A F D R A FT D FT D R A A FT R A A FT D Pin interrupt status. Bit n returns the status, clears the edge 0 interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register). Reserved. - 31:8 - - 15.5.2 GPIO GROUP0/GROUP1 interrupt register description 15.5.2.1 Grouped interrupt control register Table 181. GPIO grouped interrupt control register (CTRL, addresses 0x4008 8000 (GROUP0 INT) and 0x4008 9000 (GROUP1 INT)) bit description Bit 0 Symbol INT 0 1 1 COMB 0 Value Description Reset value Group interrupt status. This bit is cleared by writing a 0 one to it. Writing zero has no effect. No interrupt request is pending. Interrupt request is active. Combine enabled inputs for group interrupt OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity). AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity). Group interrupt trigger 0 1 31:3 Edge-triggered Level-triggered Reserved 0 0 0 1 2 TRIG 15.5.2.2 GPIO grouped interrupt port polarity registers The grouped interrupt port polarity registers determine how the polarity of each enabled pin contributes to the grouped interrupt. Each port n (n = 0 to 7) is associated with its own port polarity register, and the values of all registers together determine the grouped interrupt. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 256 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 15: LPC18xx GPIO FT D R R A Table 182. GPIO grouped interrupt port polarity registers (PORT_POL, addresses 0x4008 8020 (PORT_POL0) to 0x4008 803C (PORT_POL7) (GROUP0 INT) and 0x4008 9020 (PORT_POL0) to 0x4008 903C (PORT_POL7) (GROUP1 INT)) bit description D R A R A FT D R FT D R A R A A FT D R A F FT D R A Bit 31:0 Symbol Description POL Reset Access value FT D R A FT D Configure pin polarity of port n pins for group interrupt. Bit m 1 corresponds to pin GPIOn[m] of port n. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. - FT D R A 15.5.2.3 GPIO grouped interrupt port enable registers The grouped interrupt port enable registers enable the pins which contribute to the grouped interrupt. Each port n (n = 0 to 7) is associated with its own port enable register, and the values of all registers together determine which pins contribute to the grouped interrupt. Table 183. GPIO grouped interrupt port n enable registers (PORT_ENA, addresses 0x4008 8040 (PORT_ENA0) to 0x4008 805C (PORT_ENA7) (GROUP0 INT) and 0x4008 9040 (PORT_ENA0) to 0x4008 905C (PORT_ENA7) (GROUP1 INT)) bit description Bit 31:0 Symbol Description ENA Reset Access value - Enable port n pin for group interrupt. Bit m corresponds to pin 0 GPIOPn[m] of port n. 0 = the port n pin is disabled and does not contribute to the grouped interrupt. 1 = the port n pin is enabled and contributes to the grouped interrupt. 15.5.3 GPIO port register description 15.5.3.1 GPIO port byte pin registers Each GPIO pin GPIOn[m] has a byte register in this address range. The byte pin registers of GPIO port 0 correspond to registers B0 to B31, the byte pin registers of GPIO port 1 correspond to registers B32 to B63, etc.. Byte addresses are reserved for unused GPIO port pins (see Table 165). Software typically reads and writes bytes to access individual pins but also can read or write halfwords to sense or set the state of two pins, and read or write words to sense or set the state of four pins. Table 184. GPIO port byte pin registers (B, addresses 0x400F 4000 (B0) to 0x400F 00FC (B255)) bit description Bit 0 Symbol Description PBYTE Reset Access value R/W Read: state of the pin GPIOn[m], regardless of direction, ext masking, or alternate function. Pins configured as analog I/O always read as 0. Write: loads the pin’s output bit. Reserved (0 on read, ignored on write) 0 7:1 - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 257 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 15: LPC18xx GPIO FT D R A D R A R A FT D R FT 15.5.3.2 GPIO port word pin registers D R Each GPIO pin GPIOn[m] has a word register in this address range. The word pin registers of GPIO port 0 correspond to registers W0 to W31, the word pin registers of GPIO port 1 correspond to registers W32 to W63, etc.. Word addresses are reserved for unused GPIO port pins (see Table 165). FT D R A FT Any byte, halfword, or word read in this range will be all zeros if the pin is low or all ones if the pin is high, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as zeros. Any write will clear the pin’s output bit if the value written is all zeros, else it will set the pin’s output bit. Table 185. GPIO port word pin registers (W, addresses 0x400F 5000 (W0) to 0x400F 13FC (W255)) bit description Bit 31:0 Symbol PWORD Description Read 0: pin GPIOn[m] is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Remark: Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. Reset Access value ext R/W R A R A F D R A FT D A FT D R A R A FT D 15.5.3.3 GPIO port direction registers Each GPIO port n (n = 0 to 7) has one direction register for configuring the port pins as inputs or outputs. Table 186. GPIO port direction register (DIR, addresses 0x400F 6000 (DIR0) to 0x400F 601C (DIR7)) bit description Bit 31:0 Symbol DIR Description Selects pin direction for pin GPIOn[m] (bit 0 = GPIOn[0], bit 1 = GPIOn[1], ..., bit 31 = GPIOn[31]). 0 = input. 1 = output. Reset Access value 0 R/W 15.5.3.4 GPIO port mask registers Each GPIO port has one mask register. The mask registers affect writing and reading the MPORT registers. Zeroes in these registers enable reading and writing; ones disable writing and result in zeros in corresponding positions when reading. Table 187. GPIO port mask register (MASK, addresses 0x400F 6080 (MASK0) to 0x400F 609C (MASK7)) bit description Bit 31:0 Symbol MASK Description Reset Access value R/W Controls which bits corresponding to GPIOn[m] are active in 0 the MPORT register (bit 0 = GPIOn[0], bit 1 = GPIOn[1], ..., bit 31 = GPIOn[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 258 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 15: LPC18xx GPIO FT D R A D R A R A FT D R FT 15.5.3.5 GPIO port pin registers D R Each GPIO port has one port pin register. Reading these registers returns the current state of the pins read, regardless of direction, masking, or alternate functions, except that pins configured as analog I/O always read as 0s. Writing these registers loads the output bits of the pins written to, regardless of the Mask register. FT D R A FT D Table 188. GPIO port pin register (PIN, addresses 0x400F 6100 (PIN0) to 0x400F 611C (PIN7)) bit description Bit 31:0 Symbol Description PORT Reset Access value R/W Reads pin states or loads output bits (bit 0 = GPIOn[0], bit 1 = ext GPIOn[1], ..., bit 31 = GPIOn[31]). 0 = Read: pin is LOW; write: clear output bit. 1 = Read: pin is HIGH; write: set output bit. R A R A F D R A FT D FT D R A R A A FT 15.5.3.6 GPIO masked port pin registers Each GPIO port has one masked port pin register. These registers are similar to the PORT registers, except that the value read is masked by ANDing with the inverted contents of the corresponding MASK register, and writing to one of these registers only affects output register bits that are enabled by zeros in the corresponding MASK register. Table 189. GPIO masked port pin register (MPIN, addresses 0x400F 6180 (MPIN0) to 0x400F 619C (MPIN7)) bit description Bit 31:0 Symbol MPORT Description Masked port register (bit 0 = GPIOn[0], bit 1 = GPIOn[1], ..., bit 31 = GPIOn[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. Reset Access value ext R/W 15.5.3.7 GPIO port set registers Each GPIO port has one port set register. Output bits can be set by writing ones to these registers, regardless of MASK registers. Reading from these register returns the port’s output bits, regardless of pin directions. Table 190. GPIO port set register (SET, addresses 0x400F 6200 (SET0) to 0x400F 621C (SET7)) bit description Bit 31:0 Symbol SET Description Read or set output bits (bit 0 = GPIOn[0], bit 1 = GPIOn[1], ..., bit 31 = GPIOn[31]). 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. Reset value 0 Access R/W All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 259 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 15: LPC18xx GPIO FT D R A D R A R A FT D R FT 15.5.3.8 GPIO port clear registers D R Each GPIO port has one output clear register. Output bits can be cleared by writing ones to these write-only registers, regardless of MASK registers. Table 191. GPIO port clear register (CLR, addresses 0x400F 6280 (CLR0) to 0x400F 629C (CLR7)) bit description Bit 31:0 Symbol CLR Description Clear output bits (bit 0 = GPIOn[0], bit 1 = GPIOn[1], ..., bit 31 = GPIOn[31]): 0 = No operation. 1 = Clear output bit. Reset Access value NA WO R A FT D R R A F D R A FT D A FT D R A A FT R A FT D 15.5.3.9 GPIO port toggle registers Each GPIO port has one output toggle register. Output bits can be toggled/inverted/complemented by writing ones to these write-only registers, regardless of MASK registers. Table 192. GPIO port toggle register (NOT, addresses 0x400F 6300 (NOT0) to 0x400F 632C (NOT7)) bit description Bit 31:0 Symbol Description NOTP0 Reset Access value WO Toggle output bits (bit 0 = GPIOn[0], bit 1 = GPIOn[1], ..., bit NA 31 = GPIOn[31]): 0 = no operation. 1 = Toggle output bit. 15.6 Functional description 15.6.1 Reading pin state Software can read the state of all GPIO pins except those selected for analog input or output in the “I/O Configuration” logic. A pin does not have to be selected for GPIO in “I/O Configuration” in order to read its state. There are four ways to read pin state: • The state of a single pin can be read with 7 high-order zeros from a Byte Pin register. • The state of a single pin can be read in all bits of a byte, halfword, or word from a Word Pin register. • The state of multiple pins in a port can be read as a byte, halfword, or word from a PORT register. • The state of a selected subset of the pins in a port can be read from a Masked Port (MPORT) register. Pins having a 1 in the port’s Mask register will read as 0 from its MPORT register. 15.6.2 GPIO output Each GPIO pin has an output bit in the GPIO block. These output bits are the targets of write operations “to the pins”. Two conditions must be met in order for a pin’s output bit to be driven onto the pin: 1. The pin must be selected for GPIO operation in the “I/O Configuration” block, and All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 260 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 15: LPC18xx GPIO FT D R A 2. the pin must be selected for output by a 1 in its port’s DIR register. If either or both of these conditions is (are) not met, “writing to the pin” has no effect. D R A D R A R A FT D R FT D R R A FT R A F D R A A FT There are seven ways to change GPIO output bits: FT D R A FT D R A • Writing to a Byte Pin register loads the output bit from the least significant bit. • Writing to a Word Pin register loads the output bit with the OR of all of the bits written. (This feature follows the definition of “truth” of a multi-bit value in programming languages.) • Writing to a port’s PORT register loads the output bits of all the pins written to. • Writing to a port’s MPORT register loads the output bits of pins identified by zeros in corresponding positions of the port’s MASK register. FT D • Writing ones to a port’s SET register sets output bits. • Writing ones to a port’s CLR register clears output bits. • Writing ones to a port’s NOT register toggles/complements/inverts output bits. The state of a port’s output bits can be read from its SET register. Reading any of the registers described in 15.6.1 returns the state of pins, regardless of their direction or alternate functions. 15.6.3 Masked I/O A port’s MASK register defines which of its pins should be accessible in its MPORT register. Zeroes in MASK enable the corresponding pins to be read from and written to MPORT. Ones in MASK force a pin to read as 0 and its output bit to be unaffected by writes to MPORT. When a port’s MASK register contains all zeros, its PORT and MPORT registers operate identically for reading and writing. Users of previous NXP devices with similar GPIO blocks should be aware of an incompatibility: on the LPC11A1x, writing to the SET, CLR, and NOT registers is not affected by the MASK register. On previous devices these registers were masked. Applications in which interrupts can result in Masked GPIO operation, or in task switching among tasks that do Masked GPIO operation, must treat code that uses the Mask register as a protected/restricted region. This can be done by interrupt disabling or by using a semaphore. The simpler way to protect a block of code that uses a MASK register is to disable interrupts before setting the MASK register, and re-enable them after the last operation that uses the MPORT or MASK register. More efficiently, software can dedicate a semaphore to the MASK registers, and set/capture the semaphore controlling exclusive use of the MASK registers before setting the MASK registers, and release the semaphore after the last operation that uses the MPORT or MASK registers. 15.6.4 GPIO Interrupts Two separate GPIO interrupt facilities are provided. With pin interrupts, up to eight GPIO pins can each have separately-vectored, edge- or level-sensitive interrupts. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 261 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 15: LPC18xx GPIO FT D R R A With group interrupts, any subset of the pins in each port can be selected to contribute to a common interrupt. Any of the pin and port interrupts can be enabled to wake the part from Deep-sleep mode or Power-down mode. R A A FT D R A FT D R A R A FT D R FT D R A F R A FT D FT 15.6.4.1 Pin interrupts D In this interrupt facility, up to 8 pins are identified as interrupt sources by the Pin Interrupt Select registers (PINTSEL0-7). All of the other Pin Interrupt registers contain 8 bits, corresponding to the pins called out by the PINTSEL0-7 registers. The PINTMODE register defines whether each interrupt pin is edge- or level-sensitive. The PINTRISE and PINTFALL registers detect edges on each interrupt pin, and can be written to clear (and set) edge detection. The PINTST register indicates whether each interrupt pin is currently requesting an interrupt, and PINTST can be written to clear interrupts. The other pin interrupt registers play different roles for edge-sensitive and level-sensitive pins, as described in Table 193. Table 193. Pin interrupt registers for edge- and level-sensitive pins Name PINTEN_R PINTSEN_R PINTCEN_R PINTEN_F PINTSEN_F PINTCEN_F Edge-sensitive function Enables rising-edge interrupts. Write to enable rising-edge interrupts. Enables falling-edge interrupts. Level-sensitive function Enables interrupts. Write to enable interrupts. Selects active level. D R A FT D Write to disable rising-edge interrupts. Write to disable interrupts. Write to enable falling-edge interrupts. Write to select high-active. Write to disable falling-edge interrupts. Write to select low-active. R A 15.6.4.2 Group interrupts In this interrupt facility, an interrupt can be requested for each port, based on any selected subset of pins within each port. The pins that contribute to each port interrupt are selected by 1s in the port’s Enable register, and an interrupt polarity can be selected for each pin in the port’s Polarity register. The level on each pin is exclusive-ORed with its polarity bit and the result is ANDed with its enable bit, and these results are then inclusive-ORed among all the pins in the port, to create the port’s raw interrupt request. The raw interrupt request from each of the two group interrupts is sent to the NVIC, which can be programmed to treat it as level- or edge-sensitive (see Section 6.8). 15.6.5 Recommended practices The following lists some recommended uses for using the GPIO port registers: • • • • For initial setup after Reset or re-initialization, write the PORT registers. To change the state of one pin, write a Byte Pin or Word Pin register. To change the state of multiple pins at a time, write the SET and/or CLR registers. To change the state of multiple pins in a tightly controlled environment like a software state machine, consider using the NOT register. This can require less write operations than SET and CLR. • To read the state of one pin, read a Byte Pin or Word Pin register. • To make a decision based on multiple pins, read and mask a PORT register. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 262 of 1164 D R A FT D R A FT D R A FT D R A FT D R A FT UM10430 Rev. 00.13 — 20 July 2011 D D Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller D R A FT D R D R A FT D R A FT D R A FT D R D R A FT A FT D A FT R A R A FT D R A FT D R A F R A FT D R D FT D R User manual 16.1 How to read this chapter The GPDMA is available on all LPC18xx parts. See Table 921 for the DMA-to-peripheral connections for parts LPC1850/30/20/10 Rev ‘-’. A FT D R A 16.2 Basic configuration The GPDMA is configured as follows: • See Table 194 for clocking and power control. • The GPDMA is reset by the DMA_RST (reset # 19). • The DMAMUX register in the CREG block (see Table 35) selects between up to three peripherals for each GPDMA-to-peripheral line. Table 194. GPDMA clocking and power control Base clock GPDMA BASE_M3_CLK Branch clock CLK_M3_DMA Maximum frequency 150 MHz 16.3 Features • Eight DMA channels. Each channel can support an unidirectional transfer. • 16 DMA request lines. • Single DMA and burst DMA request signals. Each peripheral connected to the DMA Controller can assert either a burst DMA request or a single DMA request. The DMA burst size is set by programming the DMA Controller. • Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral transfers are supported. • Scatter or gather DMA is supported through the use of linked lists. This means that the source and destination areas do not have to occupy contiguous areas of memory. • Hardware DMA channel priority. • AHB slave DMA programming interface. The DMA Controller is programmed by writing to the DMA control registers over the AHB slave interface. • Two AHB bus masters for transferring data. These interfaces transfer data when a DMA request goes active. Master 1 can access memories and peripherals, master 0 can access memories only. • 32-bit AHB master bus width. • Incrementing or non-incrementing addressing for source and destination. • Programmable DMA burst size. The DMA burst size can be programmed to more efficiently transfer data. • Internal four-word FIFO per channel. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 263 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller FT D R R A • Supports 8, 16, and 32-bit wide transactions. • Big-endian and little-endian support. The DMA Controller defaults to little-endian A FT D D R A R A FT D R FT D R A F D R A FT mode on reset. error has occurred. prior to masking. R • An interrupt to the processor can be generated on a DMA completion or when a DMA • Raw interrupt status. The DMA error and DMA count raw interrupt status can be read D R A R A FT A FT D FT D R A 16.4 General description The DMA controller allows peripheral-to memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream provides unidirectional serial DMA transfers for a single source and destination. For example, a bi-directional port requires one stream for transmit and one for receives. The source and destination areas can each be either a memory region or a peripheral for master 1, but only memory for master 0. 16.5 DMA system connections The connection of the DMA Controller to supported peripheral devices is shown in Table 195. The LPC18xx supports up to three different muxing options for each channel to connect peripherals to the DMA. The DMAMUX register in the CREG block controls which option is used (see Table 35). Table 195. Peripheral connections to the DMA controller and matching flow control signals Peripheral DMA Number muxing option (see Table 35) 0 0x0 0x1 0x2 0x3 1 0x0 0x1 0x2 0x3 2 0x0 0x1 0x2 0x3 3 0x0 0x1 0x2 0x3 SREQ BREQ SPIFI SCT match 2 Reserved Timer 3 match 1 n.c. n.c. Reserved n.c. n.c. n.c. Reserved n.c. n.c. n.c. n.c. SSP1 transmit SPIFI Reserved Timer 0 match 0 USART0 transmit Reserved AES input Timer 0 match 1 USART0 receive Reserved AES output Timer 1 match 0 UART1 transmit I2S1 channel 0 SSP1 transmit © NXP B.V. 2011. All rights reserved. All information provided in this document is subject to legal disclaimers. User manual Rev. 00.13 — 20 July 2011 264 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller FT D R R A Table 195. Peripheral connections to the DMA controller and matching flow control signals D R A R A FT D R FT D R A R A A Peripheral DMA Number muxing option (see Table 35) 4 0x0 0x1 0x2 0x3 5 0x0 0x1 0x2 0x3 6 0x0 0x1 0x2 0x3 7 0x0 0x1 0x2 0x3 8 0x0 0x1 0x2 0x3 9 0x0 0x1 0x2 0x3 10 0x0 0x1 0x2 0x3 11 0x0 0x1 0x2 0x3 12 0x0 0x1 0x2 0x3 SREQ BREQ FT D R R A FT D R A FT A F FT D FT D n.c. n.c. n.c. SSP1 receive n.c. n.c. SSP1 transmit Reserved n.c. n.c. SSP1 receive Reserved n.c. n.c. n.c. Reserved n.c. n.c. n.c. Reserved SSP0 receive n.c. n.c. n.c. SSP0 transmit n.c. n.c. n.c. SSP1 receive Reserved n.c. n.c. SSP1 transmit Reserved n.c. n.c. Timer 1 match 1 UART 1 receive I2S1 channel 1 SSP1 receive Timer 2 match 0 USART 2 transmit SSP1 transmit Reserved Timer 2 match 1 USART 2 receive SSP1 receive Reserved Timer 3 match 0 USART3 transmit SCT DMA request 0 Reserved Timer 3 match 1 USART3 receive SCT DMA request 1 Reserved SSP0 receive I2S channel 0 SCT DMA request 1 n.c. SSP0 transmit I2S channel 1 SCT DMA request 0 n.c. SSP1 receive Reserved USART0 transmit n.c. SSP1 transmit Reserved USART0 receive n.c. D R A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 265 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller FT D R R A Table 195. Peripheral connections to the DMA controller and matching flow control signals D R A R A FT D R FT D R A R A A Peripheral DMA Number muxing option (see Table 35) 13 0x0 0x1 0x2 0x3 14 0x0 0x1 0x2 0x3 15 0x0 0x1 0x2 0x3 SREQ BREQ FT D R R A FT D R A FT A F FT D FT D n.c. n.c. SSP1 receive n.c. n.c. n.c. SSP1 transmit n.c. n.c. SCT match 3 Reserved n.c. ADC0 AES input SSP1 receive USART3 receive ADC1 AES output SSP1 transmit USART3 transmit DAC Reserved Timer3 match 0 D R A In addition to the peripherals listed in Table 195, the GPIOs, the WWDT, and the timers can be accessed by the GPDMA as a memory-to-memory transaction with no flow control. 16.5.1 DMA request signals The DMA request signals are used by peripherals to request a data transfer. The DMA request signals indicate whether a single or burst transfer of data is required and whether the transfer is the last in the data packet. The DMA available request signals are: BREQ[15:0] — Burst request signals. These cause a programmed burst number of data to be transferred. SREQ[15:0] — Single transfer request signals. These cause a single data to be transferred. The DMA controller transfers a single transfer to or from the peripheral. LBREQ[15:0] — Last burst request signals. LSREQ[15:0] — Last single transfer request signals. Note that most peripherals do not support all request types. 16.5.2 DMA response signals The DMA response signals indicate whether the transfer initiated by the DMA request signal has completed. The response signals can also be used to indicate whether a complete packet has been transferred. The DMA response signals from the DMA controller are: CLR[15:0] — DMA clear or acknowledge signals. The CLR signal is used by the DMA controller to acknowledge a DMA request from the peripheral. TC[15:0] — DMA terminal count signals. The TC signal can be used by the DMA controller to indicate to the peripheral that the DMA transfer is complete. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 266 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller FT D R A D R A R A FT D R FT 16.6 Register description D R The DMA Controller supports 8 channels. Each channel has registers specific to the operation of that channel. Other registers controls aspects of how source peripherals relate to the DMA Controller. There are also global DMA control and status registers. R Table 196. Register overview: GPDMA (base address 0x4000 2000) Name General registers INTSTAT INTTCSTAT INTTCCLEAR INTERRSTAT INTERRCLR RAWINTTCSTAT RAWINTERRSTAT ENBLDCHNS SOFTBREQ SOFTSREQ SOFTLBREQ SOFTLSREQ CONFIG SYNC Channel 0 registers C0SRCADDR C0DESTADDR C0LLI C0CONTROL C0CONFIG Channel 1 registers C1SRCADDR C1DESTADDR C1LLI C1CONTROL C1CONFIG Channel 2 registers C2SRCADDR C2DESTADDR C2LLI C2CONTROL C2CONFIG R A FT D R A F D R A FT D A FT A FT D R A FT D R A Access Address offset RO RO WO RO WO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 0x024 0x028 0x02C 0x030 0x034 0x100 0x104 0x108 0x10C 0x110 0x120 0x124 0x128 0x12C 0x130 0x140 0x144 0x148 0x14C 0x150 Description Reset value DMA Interrupt Status Register DMA Interrupt Terminal Count Request Status Register DMA Interrupt Terminal Count Request Clear Register DMA Interrupt Error Status Register DMA Interrupt Error Clear Register DMA Raw Interrupt Terminal Count Status Register DMA Raw Error Interrupt Status Register DMA Enabled Channel Register DMA Software Burst Request Register DMA Software Single Request Register DMA Software Last Burst Request Register DMA Software Last Single Request Register DMA Configuration Register DMA Synchronization Register DMA Channel 0 Source Address Register DMA Channel 0 Destination Address Register DMA Channel 0 Linked List Item Register DMA Channel 0 Control Register DMA Channel 0 Configuration Register DMA Channel 1 Source Address Register DMA Channel 1 Destination Address Register DMA Channel 1 Linked List Item Register DMA Channel 1 Control Register DMA Channel 1 Configuration Register DMA Channel 2 Source Address Register DMA Channel 2 Destination Address Register DMA Channel 2 Linked List Item Register DMA Channel 2 Control Register DMA Channel 2 Configuration Register 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000[1] 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000[1] 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000[1] © NXP B.V. 2011. All rights reserved. All information provided in this document is subject to legal disclaimers. User manual Rev. 00.13 — 20 July 2011 267 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller FT D R A D R A R A FT D R FT Table 196. Register overview: GPDMA (base address 0x4000 2000) …continued Name Channel 3 registers C3SRCADDR C3DESTADDR C3LLI C3CONTROL C3CONFIG Channel 4 registers C4SRCADDR C4DESTADDR C4LLI C4CONTROL C4CONFIG Channel 5 registers C5SRCADDR C5DESTADDR C5LLI C5CONTROL C5CONFIG Channel 6 registers C6SRCADDR C6DESTADDR C6LLI C6CONTROL C6CONFIG Channel 7 registers C7SRCADDR C7DESTADDR C7LLI C7CONTROL C7CONFIG [1] D R R A R A A Access Address offset R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0x160 0x164 0x168 0x16C 0x170 0x180 0x184 0x188 0x18C 0x190 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1C0 0x1C4 0x1C8 01CC 0x1D0 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 Description Reset value FT D R A D F FT D R A FT FT D DMA Channel 3 Source Address Register DMA Channel 3 Destination Address Register DMA Channel 3 Linked List Item Register DMA Channel 3 Control Register DMA Channel 3 Configuration Register DMA Channel 4 Source Address Register DMA Channel 4 Destination Address Register DMA Channel 4 Linked List Item Register DMA Channel 4 Control Register DMA Channel 4 Configuration Register DMA Channel 5 Source Address Register DMA Channel 5 Destination Address Register DMA Channel 5 Linked List Item Register DMA Channel 5 Control Register DMA Channel 5 Configuration Register DMA Channel 6 Source Address Register DMA Channel 6 Destination Address Register DMA Channel 6 Linked List Item Register DMA Channel 6 Control Register DMA Channel 6 Configuration Register DMA Channel 7 Source Address Register DMA Channel 7 Destination Address Register DMA Channel 7 Linked List Item Register DMA Channel 7 Control Register DMA Channel 7 Configuration Register 0x0000 0000 R A FT D R A 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000[1] 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000[1] 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000[1] 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000[1] 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000[1] Bit 17 of this register is a read-only status flag. 16.6.1 DMA Interrupt Status Register The IntStat Register is read-only and shows the status of the interrupts after masking. A HIGH bit indicates that a specific DMA channel interrupt request is active. The request can be generated from either the error or terminal count interrupt requests. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 268 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller FT D R R A Table 197. DMA Interrupt Status register (INTSTAT, address 0x4000 2000) bit description D R A R A FT D R FT D R A R A FT A FT F Bit 7:0 Symbol INTSTAT Description Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. Reset value 0x00 Access RO D D R A FT D R A FT D A FT D R A R 31:8 - Reserved. Read undefined. - - 16.6.2 DMA Interrupt Terminal Count Request Status Register The INTTCSTAT Register is read-only and indicates the status of the terminal count after masking. Table 198. DMA Interrupt Terminal Count Request Status Register (INTTCSTAT, address 0x4000 2004) bit description Bit 7:0 Symbol INTTCSTAT Description Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. 31:8 Reserved. Read undefined. Reset value 0x00 Access RO 16.6.3 DMA Interrupt Terminal Count Request Clear Register The INTTCCLEAR Register is write-only and clears one or more terminal count interrupt requests. When writing to this register, each data bit that is set HIGH causes the corresponding bit in the status register (IntTCStat) to be cleared. Data bits that are LOW have no effect. Table 199. DMA Interrupt Terminal Count Request Clear Register (INTTCCLEAR, address 0x4000 2008) bit description Bit 7:0 Symbol Description Reset value Access WO INTTCCLEAR Allows clearing the Terminal count interrupt request 0x00 (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. 31:8 - Reserved. Read undefined. Write reserved bits as zero. - - 16.6.4 DMA Interrupt Error Status Register The INTERRSTAT Register is read-only and indicates the status of the error request after masking. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 269 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller FT D R R A Table 200. DMA Interrupt Error Status Register (INTERRSTAT, address 0x4000 200C) bit description D R A R A FT D R FT D R A R A FT D A F FT D Bit 7:0 Symbol Description Reset value 0x00 Access R INTERRSTAT Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. RO R A A FT D R A FT D FT D R A 31:8 - Reserved. Read undefined. - - 16.6.5 DMA Interrupt Error Clear Register The INTERRCLR Register is write-only and clears the error interrupt requests. When writing to this register, each data bit that is HIGH causes the corresponding bit in the status register to be cleared. Data bits that are LOW have no effect on the corresponding bit in the register. Table 201. DMA Interrupt Error Clear Register (INTERRCLR, address 0x4000 2010) bit description Bit 7:0 Symbol INTERRCLR Description Reset value Access WO Writing a 1 clears the error interrupt request (IntErrStat) 0x00 for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. 31:8 - Reserved. Read undefined. Write reserved bits as zero. - - 16.6.6 DMA Raw Interrupt Terminal Count Status Register The RAWINTTCSTAT Register is read-only and indicates which DMA channel is requesting a transfer complete (terminal count interrupt) prior to masking. (Note: the IntTCStat Register contains the same information after masking.) A HIGH bit indicates that the terminal count interrupt request is active prior to masking. Table 202. DMA Raw Interrupt Terminal Count Status Register (RAWINTTCSTAT, address 0x4000 2014) bit description Bit 7:0 Symbol Description Reset value Access RO RAWINTTCSTAT Status of the terminal count interrupt for DMA 0x00 channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. 31:8 - Reserved. Read undefined. - - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 270 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller FT D R A D R A R A FT D R FT 16.6.7 DMA Raw Error Interrupt Status Register D R The RAWINTERRSTAT Register is read-only and indicates which DMA channel is requesting an error interrupt prior to masking. (Note: the IntErrStat Register contains the same information after masking.) A HIGH bit indicates that the error interrupt request is active prior to masking. Table 203. DMA Raw Error Interrupt Status Register (RAWINTERRSTAT, address 0x4000 2018) bit description Bit 7:0 Symbol Description Reset value Access RO RAWINTERRSTAT Status of the error interrupt for DMA channels prior 0x00 to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. R A FT D R R A F D R A FT D A FT D R A A FT R A FT D 31:8 - Reserved. Read undefined. - - 16.6.8 DMA Enabled Channel Register The ENBLDCHNS Register is read-only and indicates which DMA channels are enabled, as indicated by the Enable bit in the CCONFIG Register. A HIGH bit indicates that a DMA channel is enabled. A bit is cleared on completion of the DMA transfer. Table 204. DMA Enabled Channel Register (ENBLDCHNS, address 0x4000 201C) bit description Bit 7:0 Symbol Description Reset value 0x00 Access RO ENABLEDCHANNELS Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. 31:8 - Reserved. Read undefined. - - 16.6.9 DMA Software Burst Request Register The SOFTBREQ Register is read/write and enables DMA burst requests to be generated by software. A DMA request can be generated for each source by writing a 1 to the corresponding register bit. A register bit is cleared when the transaction has completed. Reading the register indicates which sources are requesting DMA burst transfers. A request can be generated from either a peripheral or the software request register. Each bit is cleared when the related transaction has completed. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 271 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller FT D R R A Table 205. DMA Software Burst Request Register (SOFTBREQ, address 0x4000 2020) bit description D R A R A FT D R FT D R A R A FT D A F FT D Bit 15:0 Symbol Description Reset Access value R R A A FT D FT SOFTBREQ Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 195 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. 0x00 R/W D R A FT D R A 31:16 - Reserved. Read undefined. Write reserved bits as zero. - - Note: It is recommended that software and hardware peripheral requests are not used at the same time. 16.6.10 DMA Software Single Request Register The SOFTSREQ Register is read/write and enables DMA single transfer requests to be generated by software. A DMA request can be generated for each source by writing a 1 to the corresponding register bit. A register bit is cleared when the transaction has completed. Reading the register indicates which sources are requesting single DMA transfers. A request can be generated from either a peripheral or the software request register. Table 206. DMA Software Single Request Register (SOFTSREQ, address 0x4000 2024) bit description Bit 15:0 Symbol Description Reset Access value 0x00 R/W SOFTSREQ Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. 31:16 - Reserved. Read undefined. Write reserved bits as zero. - - 16.6.11 DMA Software Last Burst Request Register The SOFTLBREQ Register is read/write and enables DMA last burst requests to be generated by software. A DMA request can be generated for each source by writing a 1 to the corresponding register bit. A register bit is cleared when the transaction has completed. Reading the register indicates which sources are requesting last burst DMA transfers. A request can be generated from either a peripheral or the software request register. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 272 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller FT D R R A Table 207. DMA Software Last Burst Request Register (SOFTLBREQ, address 0x4000 2028) bit description D R A R A FT D R FT D R A R A A FT D F FT D Bit 15:0 Symbol SOFTLBREQ Description Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. Reset Access value R R A A FT D FT 0x00 R/W D R A FT D R A 31:16 - Reserved. Read undefined. Write reserved bits as zero. - - 16.6.12 DMA Software Last Single Request Register The SOFTLSREQ Register is read/write and enables DMA last single requests to be generated by software. A DMA request can be generated for each source by writing a 1 to the corresponding register bit. A register bit is cleared when the transaction has completed. Reading the register indicates which sources are requesting last single DMA transfers. A request can be generated from either a peripheral or the software request register. Table 208. DMA Software Last Single Request Register (SOFTLSREQ, address 0x4000 202C) bit description Bit 15:0 Symbol SOFTLSREQ Description Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. 31:16 Reserved. Read undefined. Write reserved bits as zero. Reset Access value 0x00 R/W 16.6.13 DMA Configuration Register The CONFIG Register is read/write and configures the operation of the DMA Controller. The endianness of the AHB master interface can be altered by writing to the M bit of this register. The AHB master interface is set to little-endian mode on reset. Table 209. DMA Configuration Register (CONFIG, address 0x4000 2030) bit description Bit 0 Symbol Value E 0 1 1 M0 0 1 Description DMA Controller enable: Disabled (default). Disabling the DMA Controller reduces power consumption. Enabled AHB Master 0 endianness configuration: Little-endian mode (default). Big-endian mode. Reset Access value 0x00 R/W 0x00 R/W All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 273 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller FT D R R A Table 209. DMA Configuration Register (CONFIG, address 0x4000 2030) bit description D R A R A FT D R FT D R A R A A Bit 2 Symbol Value M1 0 1 Description AHB Master 1 endianness configuration: Little-endian mode (default). Big-endian mode. Reserved. Read undefined. Write reserved bits as zero. Reset Access value FT D R A F FT D R A FT D R A 0x00 R/W FT D FT D R 31:3 - A 16.6.14 DMA Synchronization Register The Sync Register is read/write and enables or disables synchronization logic for the DMA request signals. The DMA request signals consist of the BREQ[15:0], SREQ[15:0], LBREQ[15:0], and LSREQ[15:0]. A bit set to 0 enables the synchronization logic for a particular group of DMA requests. A bit set to 1 disables the synchronization logic for a particular group of DMA requests. This register is reset to 0, synchronization logic enabled. Table 210. DMA Synchronization Register (SYNC, address 0x4000 2034) bit description Bit 15:0 Symbol Description Reset Access value 0x00 R/W DMACSYNC Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are disabled. 1 - synchronization logic for the corresponding request line signals are enabled. 31:16 - Reserved. Read undefined. Write reserved bits as zero. - - 16.6.15 DMA Channel registers The channel registers are used to program the eight DMA channels. These registers consist of: • • • • • Eight CSRCADDR Registers. Eight CDESTADDR Registers. Eight CLLI Registers. Eight CCONTROL Registers. Eight CCONFIG Registers. When performing scatter/gather DMA, the first four of these are automatically updated. 16.6.16 DMA Channel Source Address Registers The eight read/write CSRCADDR Registers (C0SRCADDR to C7SRCADDR) contain the current source address (byte-aligned) of the data to be transferred. Each register is programmed directly by software before the appropriate channel is enabled. When the DMA channel is enabled this register is updated: All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 274 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller FT D Table 211. DMA Channel Source Address Registers (CSRCADDR, 0x4000 2100 (C0SRCADDR) to 0x4000 21E0 (C7SRCADDR)) bit description Bit 31:0 Symbol SRCADDR Description DMA source address. Reading this register will return the current source address. Reset value Access 0x0000 0000 R/W • As the source address is incremented. • By following the linked list when a complete packet of data has been transferred. R A FT D R Reading the register when the channel is active does not provide useful information. This is because by the time software has processed the value read, the address may have progressed. It is intended to be read only when the channel has stopped, in which case it shows the source address of the last item read. A FT D Note: The source and destination addresses must be aligned to the source and destination widths. D R A R A FT D R R A FT D R A FT D R A FT D FT D R A R A F A R 16.6.17 DMA Channel Destination Address registers The eight read/write CDESTADDR Registers (C0DESTADDR to C7DESTADDR) contain the current destination address (byte-aligned) of the data to be transferred. Each register is programmed directly by software before the channel is enabled. When the DMA channel is enabled the register is updated as the destination address is incremented and by following the linked list when a complete packet of data has been transferred. Reading the register when the channel is active does not provide useful information. This is because by the time that software has processed the value read, the address may have progressed. It is intended to be read only when a channel has stopped, in which case it shows the destination address of the last item read. Table 212. DMA Channel Destination Address registers (CDESTADDR, 0x4000 2104 (C0DESTADDR) to 0x4000 21E4 (C7DESTADDR)) bit description Bit 31:0 Symbol DESTADDR Description DMA Destination address. Reading this register will return the current destination address. Reset value Access 0x0000 0000 R/W 16.6.18 DMA Channel Linked List Item registers The eight read/write CLLI Registers (C0LLI to C7LLI) contain a word-aligned address of the next Linked List Item (LLI). If the LLI is 0, then the current LLI is the last in the chain, and the DMA channel is disabled when all DMA transfers associated with it are completed. Programming this register when the DMA channel is enabled may have unpredictable side effects. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 275 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller FT D R R A Table 213. DMA Channel Linked List Item registers (CLLI, 0x4000 2108 (C0LLI) to 0x4000 21E8 (C7LLI)) bit description D R A R A FT D R FT D R A R A FT D A F FT D Bit 0 Symbol LM Value Description AHB master select for loading the next LLI: Reset value 0 Access R/W R R A A FT D R A FT D 0 1 1 31:2 R LLI AHB Master 0. AHB Master 1. Reserved, and must be written as 0, masked on read. Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0. 0 R/W FT D R A 0x0000 R/W 0000 16.6.19 DMA channel control registers The eight read/write CCONTROL Registers (C0CONTROL to C7CONTROL) contain DMA channel control information such as the transfer size, burst size, and transfer width. Each register is programmed directly by software before the DMA channel is enabled. When the channel is enabled the register is updated by following the linked list when a complete packet of data has been transferred. Reading the register while the channel is active does not give useful information. This is because by the time software has processed the value read, the channel may have advanced. It is intended to be read only when a channel has stopped. Table 214. DMA Channel Control registers (CCONTROL, 0x4000 210C (C0CONTROL) to 0x4000 21EC (C7CONTROL)) bit description Bit 11:0 Symbol TRANSFERSIZE Value Description Reset value Access R/W Transfer size in number of transfers. A write to this field sets the 0x0 size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 276 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller FT D R R A Table 214. DMA Channel Control registers (CCONTROL, 0x4000 210C (C0CONTROL) to 0x4000 21EC (C7CONTROL)) bit description …continued D R A R A FT D R FT D R A R A A FT F FT Bit 14:12 Symbol SBSIZE Value Description Reset value Access D D R R A A FT FT Source burst size. Indicates the number of transfers that make 0x0 up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 5). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral. 0x0 0x1 0x2 0x3 0x4 0x4 0x6 0x7 Source burst size = 1 Source burst size = 4 Source burst size = 8 Source burst size = 16 Source burst size = 32 Source burst size = 64 Source burst size = 128 Source burst size = 256 Destination burst size. Indicates the number of transfers that 0x0 make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral. 0x0 0x1 0x2 0x3 0x4 0x4 0x6 0x7 Destination burst size = 1 Destination burst size = 4 Destination burst size = 8 Destination burst size = 16 Destination burst size = 32 Destination burst size = 64 Destination burst size = 128 Destination burst size = 256 Source transfer width. Transfers wider than the AHB master bus 0x0 width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved. 0x0 0x1 0x2 Byte (8-bit) Halfword (16-bit) Word (32-bit) Destination transfer width. Transfers wider than the AHB master 0x0 bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved. 0x0 0x1 0x2 Byte (8-bit) Halfword (16-bit) Word (32-bit) R/W D D R A FT D R A 17:15 DBSIZE R/W 20:18 SWIDTH R/W 23:21 DWIDTH R/W All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 277 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller FT D R R A Table 214. DMA Channel Control registers (CCONTROL, 0x4000 210C (C0CONTROL) to 0x4000 21EC (C7CONTROL)) bit description …continued D R A R A FT D R FT D R A R A A FT F FT Bit 24 Symbol S Value Description Source AHB master select: 0 1 AHB Master 0 selected for source transfer. AHB Master 1 selected for source transfer. Destination AHB master select: Remark: Only Master1 can access a peripheral. Master0 can only access memory. 0 1 AHB Master 0 selected for destination transfer. AHB Master 1 selected for destination transfer. Source increment: 0 1 The source address is not incremented after each transfer. The source address is incremented after each transfer. Destination increment: 0 1 The destination address is not incremented after each transfer. The destination address is incremented after each transfer. Indicates that the access is in user mode or privileged mode: 0 1 Access is in user mode Access is in privileged mode. Indicates that the access is bufferable or not bufferable: 0 1 Access is not bufferable. Access is bufferable. Indicates that the access is cacheable or not cacheable: 0 1 Access is not cacheable. Access is cacheable. Terminal count interrupt enable bit. 0 1 The terminal count interrupt is disabled. The terminal count interrupt is enabled. Reset value 0 Access R/W D D R R A A FT D R A FT D FT D R A 25 D 0 R/W 26 SI 0 R/W 27 DI 0 R/W 28 PROT1 0 R/W 29 PROT2 0 R/W 30 PROT3 0 R/W 31 I 0 R/W 16.6.19.1 Protection and access information AHB access information is provided to the source and destination peripherals when a transfer occurs. The transfer information is provided by programming the DMA channel (the Prot bits of the CCONTROL Register, and the Lock bit of the CCONFIG Register). These bits are programmed by software. Peripherals can use this information if necessary. 16.6.20 Channel Configuration registers The eight CCONFIG Registers (C0CONFIG to C7CONFIG) are read/write with the exception of bit[17] which is read-only. Used these to configure the DMA channel. The registers are not updated when a new LLI is requested. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 278 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller FT D R R A Table 215. DMA Channel Configuration registers (CCONFIG, 0x4000 2110 (C0CONFIG) to 0x4000 21F0 (C7CONFIG)) bit description D R A R A FT D R FT D R A R A A FT D F FT D Bit 0 Symbol E Value Description Reset value Access R R A A FT FT D Channel enable. Reading this bit indicates whether a channel is 0 currently enabled or disabled: The Channel Enable bit status can also be found by reading the ENBLDCHNS Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared. 0 1 Channel disabled. Channel enabled. Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 195 for details. 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF Source = SPIFI Source = Timer 0 match 0/UART0 transmit Source = Timer 0 match 1/UART0 receive Source = Timer 1 match 0/UART1 transmit Source = Timer 1 match 1/UART 1 receive Source = Timer 2 match 0/UART 2 transmit Source = Timer 2 match 1/UART 2 receive Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0 Source = Timer 3 match 1/UART3 receive/SCT DMA request 1 Source = SSP0 receive/I2S channel 0 Source = SSP0 transmit/I2S channel 1 Source = SSP1 receive Source = SSP1 transmit Source = ADC0 Source = ADC1 Source = DAC R/W D R A FT D R A 5:1 SRCPERIPHERAL R/W All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 279 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller FT D R R A Table 215. DMA Channel Configuration registers (CCONFIG, 0x4000 2110 (C0CONFIG) to 0x4000 21F0 (C7CONFIG)) bit description …continued D R A R A FT D R FT D R A R A A FT F FT Bit 10:6 Symbol DESTPERIPHERAL Value Description Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 195 for details. Reset value Access R/W D D R R A A FT D R A FT D FT D R 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF 13:11 FLOWCNTRL Destination = SPIFI Destination = Timer 0 match 0/UART0 transmit Destination = Timer 0 match 1/UART0 receive Destination = Timer 1 match 0/UART1 transmit Destination = Timer 1 match 1/UART 1 receive Destination = Timer 2 match 0/UART 2 transmit Destination = Timer 2 match 1/UART 2 receive Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0 Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1 Destination = SSP0 receive/I2S channel 0 Destination = SSP0 transmit/I2S channel 1 Destination = SSP1 receive Destination = SSP1 transmit Destination = ADC0 Destination = ADC1 Destination = DAC Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 216 for the encoding of this field. R/W A 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 14 15 16 IE ITC L Memory to memory (DMA control) Memory to peripheral (DMA control) Peripheral to memory (DMA control) Source peripheral to destination peripheral (DMA control) Source peripheral to destination peripheral (destination control) Memory to peripheral (peripheral control) Peripheral to memory (peripheral control) Source peripheral to destination peripheral (source control) Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel. Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel. Lock. When set, this bit enables locked transfers. R/W R/W R/W All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 280 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller FT D R R A Table 215. DMA Channel Configuration registers (CCONFIG, 0x4000 2110 (C0CONFIG) to 0x4000 21F0 (C7CONFIG)) bit description …continued D R A R A FT D R FT D R A R A A FT F FT Bit 17 Symbol A Value Description Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit. Reset value Access RO D D R 18 H Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel. 0 1 Enable DMA requests. Ignore further source DMA requests. Reserved, do not modify, masked on read. R/W R A A FT D R A FT D FT D R A 31:19 - - 16.6.20.1 Lock control The lock control may set the lock bit by writing a 1 to bit 16 of the CCONFIG Register. When a burst occurs, the AHB arbiter will not de-grant the master during the burst until the lock is deasserted. The DMA Controller can be locked for a a single burst such as a long source fetch burst or a long destination drain burst. The DMA Controller does not usually assert the lock continuously for a source fetch burst followed by a destination drain burst. There are situations when the DMA Controller asserts the lock for source transfers followed by destination transfers. This is possible when internal conditions in the DMA Controller permit it to perform a source fetch followed by a destination drain back-to-back. 16.6.20.2 Flow control and transfer type Table 216 lists the bit values of the three flow control and transfer type bits identified in Table Table 215. Table 216. Flow control and transfer type bits Bit value 000 001 010 011 100 101 110 111 Transfer type Memory to memory Memory to peripheral Peripheral to memory Source peripheral to destination peripheral Source peripheral to destination peripheral Memory to peripheral Peripheral to memory Source peripheral to destination peripheral Controller DMA DMA DMA DMA Destination peripheral Peripheral Peripheral Source peripheral All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 281 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller FT D R A D R A R A FT D R FT 16.7 Functional description 16.7.1 DMA controller functional description D R The DMA Controller enables peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream provides unidirectional serial DMA transfers for a single source and destination. For example, a bidirectional port requires one stream for transmit and one for receive. The source and destination areas can each be either a memory region or a peripheral, and can be accessed through the AHB master. Figure 26 shows a block diagram of the DMA Controller. R A FT D R R A F D R A FT A FT A FT D R A D FT D R A AHB Matrix AHB Slave Interface Control Logic and Registers AHB Master Interface M0 AHB Matrix DMA requests DMA responses DMA Interrupt DMA request and response interface Interrupt request Channel logic and registers AHB Master Interface M1 AHB Matrix Fig 26. DMA controller block diagram The functions of the DMA Controller are described in the following sections. 16.7.1.1 AHB slave interface All transactions to DMA Controller registers on the AHB slave interface are 32 bits wide. Eight bit and 16-bit accesses are not supported and will result in an exception. 16.7.1.2 Control logic and register bank The register block stores data written or to be read across the AHB interface. 16.7.1.3 DMA request and response interface See DMA Interface description for information on the DMA request and response interface. 16.7.1.4 Channel logic and channel register bank The channel logic and channel register bank contains registers and logic required for each DMA channel. 16.7.1.5 Interrupt request The interrupt request generates the interrupt to the ARM processor. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 282 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller FT D R A D R A R A FT D R FT 16.7.1.6 AHB master interface D R The DMA Controller contains two AHB master interfaces. Each AHB master is capable of dealing with all types of AHB transactions, including: • Split, retry, and error responses from slaves. If a peripheral performs a split or retry, the DMA Controller stalls and waits until the transaction can complete. R A FT D R R A F D R A FT D FT D A FT R A A FT D • Locked transfers for source and destination of each stream. • Setting of protection bits for transfers on each stream. 16.7.1.6.1 Bus and transfer widths The physical width of the AHB bus is 32 bits. Source and destination transfers can be of differing widths and can be the same width or narrower than the physical bus width. The DMA Controller packs or unpacks data as appropriate. 16.7.1.6.2 Endian behavior The DMA Controller can cope with both little-endian and big-endian addressing. Software can set the endianness of each AHB master individually. Internally the DMA Controller treats all data as a stream of bytes instead of 16-bit or 32-bit quantities. This means that when performing mixed-endian activity, where the endianness of the source and destination are different, byte swapping of the data within the 32-bit data bus is observed. Note: If byte swapping is not required, then use of different endianness between the source and destination addresses must be avoided. Table 217 shows endian behavior for different source and destination combinations. Table 217. Endian behavior Source endian Little Destination endian Little Source width 8 Destination width 8 Source Source data Destination Destination data transfer transfer no/byte lane no/byte lane 1/[7:0] 2/[15:8] 3/[23:16] 4/[31:24] Little Little 8 16 1/[7:0] 2/[15:8] 3/[23:16] 4/[31:24] Little Little 8 32 1/[7:0] 2/[15:8] 3/[23:16] 4/[31:24] Little Little 16 8 1/[7:0] 1/[15:8] 2/[23:16] 2/[31:24] 21 43 65 87 21 43 65 87 21 43 65 87 21 43 65 87 1/[7:0] 2/[15:8] 3/[23:16] 4/[31:24] 21212121 43434343 65656565 87878787 1/[31:0] 87654321 1/[7:0] 2/[15:8] 3/[23:16] 4/[31:24] 1/[15:0] 2/[31:16] 21212121 43434343 65656565 87878787 43214321 87658765 R A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 283 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller FT D R A D R A R A FT D R FT Table 217. Endian behavior …continued Source endian Little Destination endian Little Source width 16 Destination width 16 D R Source Source data Destination Destination data transfer transfer no/byte lane no/byte lane R A FT D R R A F D R A FT A FT A FT 1/[7:0] 1/[15:8] 2/[23:16] 2/[31:24] 21 43 65 87 21 43 65 87 21 43 65 87 21 43 65 87 21 43 65 87 12 34 56 78 12 34 56 78 12 34 56 78 12 34 56 78 12 34 56 78 1/[15:0] 2/[31:16] 43214321 87658765 D D R A FT D R A Little Little 16 32 1/[7:0] 1/[15:8] 2/[23:16] 2/[31:24] 1/[31:0] 87654321 Little Little 32 8 1/[7:0] 1/[15:8] 1/[23:16] 1/[31:24] 1/[7:0] 2/[15:8] 3/[23:16] 4/[31:24] 1/[15:0] 2/[31:16] 21212121 43434343 65656565 87878787 43214321 87658765 Little Little 32 16 1/[7:0] 1/[15:8] 1/[23:16] 1/[31:24] Little Little 32 32 1/[7:0] 1/[15:8] 1/[23:16] 1/[31:24] 1/[31:0] 87654321 Big Big 8 8 1/[31:24] 2/[23:16] 3/[15:8] 4/[7:0] 1/[31:24] 2/[23:16] 3/[15:8] 4/[7:0] 1/[15:0] 2/[31:16] 12121212 34343434 56565656 78787878 12341234 56785678 Big Big 8 16 1/[31:24] 2/[23:16] 3/[15:8] 4/[7:0] Big Big 8 32 1/[31:24] 2/[23:16] 3/[15:8] 4/[7:0] 1/[31:0] 12345678 Big Big 16 8 1/[31:24] 1/[23:16] 2/[15:8] 2/[7:0] 1/[31:24] 2/[23:16] 3/[15:8] 4/[7:0] 1/[15:0] 2/[31:16] 12121212 34343434 56565656 78787878 12341234 56785678 Big Big 16 16 1/[31:24] 1/[23:16] 2/[15:8] 2/[7:0] All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 284 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller FT D R A D R A R A FT D R FT Table 217. Endian behavior …continued Source endian Big Destination endian Big Source width 16 Destination width 32 D R Source Source data Destination Destination data transfer transfer no/byte lane no/byte lane R A FT D R R A F D R A FT A FT A FT 1/[31:24] 1/[23:16] 2/[15:8] 2/[7:0] 12 34 56 78 12 34 56 78 12 34 56 78 12 34 56 78 1/[31:0] 12345678 D D R A FT D R A Big Big 32 8 1/[31:24] 1/[23:16] 1/[15:8] 1/[7:0] 1/[31:24] 2/[23:16] 3/[15:8] 4/[7:0] 1/[15:0] 2/[31:16] 12121212 34343434 56565656 78787878 12341234 56785678 Big Big 32 16 1/[31:24] 1/[23:16] 1/[15:8] 1/[7:0] Big Big 32 32 1/[31:24] 1/[23:16] 1/[15:8] 1/[7:0] 1/[31:0] 12345678 16.7.1.6.3 Error conditions An error during a DMA transfer is flagged directly by the peripheral by asserting an Error response on the AHB bus during the transfer. The DMA Controller automatically disables the DMA stream after the current transfer has completed, and can optionally generate an error interrupt to the CPU. This error interrupt can be masked. 16.7.1.7 Channel hardware Each stream is supported by a dedicated hardware channel, including source and destination controllers, as well as a FIFO. This enables better latency than a DMA controller with only a single hardware channel shared between several DMA streams and simplifies the control logic. 16.7.1.8 DMA request priority DMA channel priority is fixed. DMA channel 0 has the highest priority and DMA channel 7 has the lowest priority. If the DMA Controller is transferring data for the lower priority channel and then the higher priority channel goes active, it completes the number of transfers delegated to the master interface by the lower priority channel before switching over to transfer data for the higher priority channel. In the worst case this is as large as a one quadword. It is recommended that memory-to-memory transactions use the lowest priority channel. Otherwise other AHB bus masters are prevented from accessing the bus during DMA Controller memory-to-memory transfer. 16.7.1.9 Interrupt generation A combined interrupt output is generated as an OR function of the individual interrupt requests of the DMA Controller and is connected to the interrupt controller. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 285 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller FT D R A D R A R A FT D R FT 16.8 Using the DMA controller 16.8.1 Programming the DMA controller D R All accesses to the DMA Controller internal register must be word (32-bit) reads and writes. R A FT D R R A F D R A FT A FT A FT D R A D FT D R A 16.8.1.1 Enabling the DMA controller To enable the DMA controller set the Enable bit in the CONFIG register. 16.8.1.2 Disabling the DMA controller To disable the DMA controller: • Read the ENBLDCHNS register and ensure that all the DMA channels have been disabled. If any channels are active, see Disabling a DMA channel. • Disable the DMA controller by writing 0 to the DMA Enable bit in the CONFIG register. 16.8.1.3 Enabling a DMA channel To enable the DMA channel set the channel enable bit in the relevant DMA channel configuration register. Note that the channel must be fully initialized before it is enabled. 16.8.1.4 Disabling a DMA channel A DMA channel can be disabled in three ways: • By writing directly to the channel enable bit. Any outstanding data in the FIFO’s is lost if this method is used. • By using the active and halt bits in conjunction with the channel enable bit. • By waiting until the transfer completes. This automatically clears the channel. Disabling a DMA channel and losing data in the FIFO Clear the relevant channel enable bit in the relevant channel configuration register. The current AHB transfer (if one is in progress) completes and the channel is disabled. Any data in the FIFO is lost. Disabling the DMA channel without losing data in the FIFO • Set the halt bit in the relevant channel configuration register. This causes any future DMA request to be ignored. • Poll the active bit in the relevant channel configuration register until it reaches 0. This bit indicates whether there is any data in the channel that has to be transferred. • Clear the channel enable bit in the relevant channel configuration register 16.8.1.5 Setting up a new DMA transfer To set up a new DMA transfer: If the channel is not set aside for the DMA transaction: 1. Read the ENBLDCHNS controller register and find out which channels are inactive. 2. Choose an inactive channel that has the required priority. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 286 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller FT D R A D R A R A FT D R FT 3. Program the DMA controller D R R A FT R A F A FT 16.8.1.6 Halting a DMA channel D Set the halt bit in the relevant DMA channel configuration register. The current source request is serviced. Any further source DMA request is ignored until the halt bit is cleared. FT D D R A R A FT D FT R A 16.8.1.7 Programming a DMA channel 1. Choose a free DMA channel with the priority needed. DMA channel 0 has the highest priority and DMA channel 7 the lowest priority. 2. Clear any pending interrupts on the channel to be used by writing to the IntTCClear and INTERRCLEAR register. The previous channel operation might have left interrupt active. 3. Write the source address into the CSRCADDR register. 4. Write the destination address into the CDESTADDR register. 5. Write the address of the next LLI into the CLLI register. If the transfer comprises of a single packet of data then 0 must be written into this register. 6. Write the control information into the CCONTROL register. 7. Write the channel configuration information into the CCONFIG register. If the enable bit is set then the DMA channel is automatically enabled. D R A 16.8.2 Flow control The peripheral that controls the length of the packet is known as the flow controller. The flow controller is usually the DMA Controller where the packet length is programmed by software before the DMA channel is enabled. If the packet length is unknown when the DMA channel is enabled, either the source or destination peripherals can be used as the flow controller. For simple or low-performance peripherals that know the packet length (that is, when the peripheral is the flow controller), a simple way to indicate that a transaction has completed is for the peripheral to generate an interrupt and enable the processor to reprogram the DMA channel. The transfer size value (in the CCONTROL register) is ignored if a peripheral is configured as the flow controller. When the DMA transfer is completed: 1. The DMA Controller issues an acknowledge to the peripheral in order to indicate that the transfer has finished. 2. A TC interrupt is generated, if enabled. 3. The DMA Controller moves on to the next LLI. The following sections describe the DMA Controller data flow sequences for the four allowed transfer types: • Memory-to-peripheral (master 1 only). • Peripheral-to-memory (master 1 only). • Memory-to-memory. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 287 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller FT D R A D R A R A FT D R FT • Peripheral-to-peripheral (master 1 only). D R Each transfer type can have either the peripheral or the DMA Controller as the flow controller so there are eight possible control scenarios. D R A FT R R A F D R A FT A FT FT D A D Table 218 indicates the request signals used for each type of transfer. Table 218. DMA request signal usage Transfer direction Memory-to-peripheral Memory-to-peripheral Peripheral-to-memory Peripheral-to-memory Memory-to-memory Source peripheral to destination peripheral Source peripheral to destination peripheral Source peripheral to destination peripheral Request generator Peripheral Peripheral Peripheral Peripheral DMA Controller Source peripheral and destination peripheral Source peripheral and destination peripheral Source peripheral and destination peripheral Flow controller DMA Controller Peripheral DMA Controller Peripheral DMA Controller Source peripheral R A FT D R A Destination peripheral DMA Controller 16.8.2.1 Peripheral-to-memory or memory-to-peripheral DMA flow For a peripheral-to-memory or memory-to-peripheral DMA flow, the following sequence occurs: 1. Program and enable the DMA channel. 2. Wait for a DMA request. 3. The DMA Controller starts transferring data when: – The DMA request goes active. – The DMA stream has the highest pending priority. – The DMA Controller is the bus master of the AHB bus. 4. If an error occurs while transferring the data, an error interrupt is generated and disables the DMA stream, and the flow sequence ends. 5. Decrement the transfer count if the DMA Controller is performing the flow control. 6. If the transfer has completed (indicated by the transfer count reaching 0, if the DMA Controller is performing flow control, or by the peripheral sending a DMA request, if the peripheral is performing flow control): – The DMA Controller responds with a DMA acknowledge. – The terminal count interrupt is generated (this interrupt can be masked). – If the CLLI Register is not 0, then reload the CSRCADDR, CDESTADDR, CLLI, and CCONTROL registers and go to back to step 2. However, if CLLI is 0, the DMA stream is disabled and the flow sequence ends. 16.8.2.2 Peripheral-to-peripheral DMA flow For a peripheral-to-peripheral DMA flow, the following sequence occurs: 1. Program and enable the DMA channel. 2. Wait for a source DMA request. 3. The DMA Controller starts transferring data when: All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 288 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller FT D R A D R A R A FT D R FT – The DMA request goes active. – The DMA stream has the highest pending priority. – The DMA Controller is the bus master of the AHB bus. D R 4. If an error occurs while transferring the data an error interrupt is generated, the DMA stream is disabled, and the flow sequence ends. D 5. Decrement the transfer count if the DMA Controller is performing the flow control. 6. If the transfer has completed (indicated by the transfer count reaching 0 if the DMA Controller is performing flow control, or by the peripheral sending a DMA request if the peripheral is performing flow control): – The DMA Controller responds with a DMA acknowledge to the source peripheral. – Further source DMA requests are ignored. 7. When the destination DMA request goes active and there is data in the DMA Controller FIFO, transfer data into the destination peripheral. 8. If an error occurs while transferring the data, an error interrupt is generated, the DMA stream is disabled, and the flow sequence ends. 9. If the transfer has completed it is indicated by the transfer count reaching 0 if the DMA Controller is performing flow control, or by the sending a DMA request if the peripheral is performing flow control. The following happens: – The DMA Controller responds with a DMA acknowledge to the destination peripheral. – The terminal count interrupt is generated (this interrupt can be masked). – If the CLLI Register is not 0, then reload the CSRCADDR, CDESTADDR, CLLI, and CCONTROL Registers and go to back to step 2. However, if CLLI is 0, the DMA stream is disabled and the flow sequence ends. R A FT D R R A F D R A FT A FT A FT R A D FT D R A 16.8.2.3 Memory-to-memory DMA flow For a memory-to-memory DMA flow the following sequence occurs: 1. Program and enable the DMA channel. 2. Transfer data whenever the DMA channel has the highest pending priority and the DMA Controller gains mastership of the AHB bus. 3. If an error occurs while transferring the data, generate an error interrupt and disable the DMA stream. 4. Decrement the transfer count. 5. If the count has reached zero: – Generate a terminal count interrupt (the interrupt can be masked). – If the CLLI Register is not 0, then reload the CSRCADDR, CDESTADDR, CLLI, and CCONTROL Registers and go to back to step 2. However, if CLLI is 0, the DMA stream is disabled and the flow sequence ends. Note: Memory-to-memory transfers should be programmed with a low channel priority, otherwise other DMA channels cannot access the bus until the memory-to-memory transfer has finished, or other AHB masters cannot perform any transaction. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 289 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller FT D R A D R A R A FT D R FT 16.8.3 Interrupt requests D R Interrupt requests can be generated when an AHB error is encountered or at the end of a transfer (terminal count), after all the data corresponding to the current LLI has been transferred to the destination. The interrupts can be masked by programming bits in the relevant CCONTROL and CCONFIG Channel Registers. Interrupt status registers are provided which group the interrupt requests from all the DMA channels prior to interrupt masking (RAWINTTCSTAT and RAWINTERRSTAT), and after interrupt masking (INTTCSTAT and INTERRSTAT). The INTSTAT Register combines both the INTTCSTAT and INTERRSTAT requests into a single register to enable the source of an interrupt to be quickly found. Writing to the INTTCCLEAR or the INTERRCLR Registers with a bit set HIGH enables selective clearing of interrupts. D R A FT D R A FT R A F D R A FT D FT D R A R A A FT 16.8.3.1 Hardware interrupt sequence flow When a DMA interrupt request occurs, the Interrupt Service Routine needs to: 1. Read the INTTCSTAT Register to determine whether the interrupt was generated due to the end of the transfer (terminal count). A HIGH bit indicates that the transfer completed. If more than one request is active, it is recommended that the highest priority channels be checked first. 2. Read the INTERRSTAT Register to determine whether the interrupt was generated due to an error occurring. A HIGH bit indicates that an error occurred. 3. Service the interrupt request. 4. For a terminal count interrupt, write a 1 to the relevant bit of the INTTCCLR Register. For an error interrupt write a 1 to the relevant bit of the INTERRCLR Register to clear the interrupt request. 16.8.4 Address generation Address generation can be either incrementing or non-incrementing (address wrapping is not supported). Some devices, especially memories, disallow burst accesses across certain address boundaries. The DMA controller assumes that this is the case with any source or destination area, which is configured for incrementing addressing. This boundary is assumed to be aligned with the specified burst size. For example, if the channel is set for 16-transfer burst to a 32-bit wide device then the boundary is 64-bytes aligned (that is address bits [5:0] equal 0). If a DMA burst is to cross one of these boundaries, then, instead of a burst, that transfer is split into separate AHB transactions. Note: When transferring data to or from the SDRAM, the SDRAM access must always be programmed to 32 bit accesses. The SDRAM memory controller does not support AHB-INCR4 or INCR8 bursts using halfword or byte transfer-size. Start address in SDRAM should always be aligned to a burst boundary address. 16.8.4.1 Word-aligned transfers across a boundary The channel is configured for 16-transfer bursts, each transfer 32-bits wide, to a destination for which address incrementing is enabled. The start address for the current burst is 0x0C000024, the next boundary (calculated from the burst size and transfer width) is 0x0C000040. The transfer will be split into two AHB transactions: All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 290 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller FT D R A D R A R A FT D R FT • a 7-transfer burst starting at address 0x0C000024 • a 9-transfer burst starting at address 0x0C000040. 16.8.5 Scatter/gather D R Scatter/gather is supported through the use of linked lists. This means that the source and destination areas do not have to occupy contiguous areas in memory. Where scatter/gather is not required, the CLLI Register must be set to 0. The source and destination data areas are defined by a series of linked lists. Each Linked List Item (LLI) controls the transfer of one block of data, and then optionally loads another LLI to continue the DMA operation, or stops the DMA stream. The first LLI is programmed into the DMA Controller. The data to be transferred described by a LLI (referred to as the packet of data) usually requires one or more DMA bursts (to each of the source and destination). R A FT D R R A F D R A FT A FT A FT D R A D FT D R A 16.8.5.1 Linked list items A Linked List Item (LLI) consists of four words. These words are organized in the following order: 1. CSRCADDR 2. CDESTADDR 3. CLLI 4. CCONTROL Note: The CCONFIG DMA channel Configuration Register is not part of the linked list item. 16.8.5.1.1 Programming the DMA controller for scatter/gather DMA To program the DMA Controller for scatter/gather DMA: 1. Write the LLIs for the complete DMA transfer to memory. Each linked list item contains four words: – Source address. – Destination address. – Pointer to next LLI. – Control word. The last LLI has its linked list word pointer set to 0. 2. Choose a free DMA channel with the priority required. DMA channel 0 has the highest priority and DMA channel 7 the lowest priority. 3. Write the first linked list item, previously written to memory, to the relevant channel in the DMA Controller. 4. Write the channel configuration information to the channel Configuration Register and set the Channel Enable bit. The DMA Controller then transfers the first and then subsequent packets of data as each linked list item is loaded. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 291 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller FT D R R A 5. An interrupt can be generated at the end of each LLI depending on the Terminal Count bit in the CCONTROL Register. If this bit is set an interrupt is generated at the end of the relevant LLI. The interrupt request must then be serviced and the relevant bit in the INTTCCLEAR Register must be set to clear the interrupt. R A A FT D R A FT D D R A R A FT D R FT D R A F R A FT D D FT R 16.8.5.1.2 Example of scatter/gather DMA See Figure 27 for an example of an LLI. A section of memory is to be transferred to a peripheral. The addresses of each LLI entry are given, in hexadecimal, at the left-hand side of the figure. The right side of the figure shows the memory containing the data to be transferred. Linked List Array LLI1 Source address 0x2002 0000 Destination address Next LLI address Control information LLI2 Source address 0x2002 0010 Destination address Next LLI address Control information LLI3 Source address 0x2002 0020 Destination address Next LLI address Control information = 0x 2002 A200 = peripheral = 0x2002 0010 = length 3072 = 0x 2002 B200 = peripheral = 0x2002 0020 = length 3072 = 0x 2002 C200 = peripheral = 0x2002 0030 = length 3072 A FT D R A 0x2002 A200 3072 bytes of data 0x2002 ADFF 0x2002 B200 3072 bytes of data 0x2002 BDFF 0x2002 C200 3072 bytes of data 0x2002 CDFF LLI8 Source address 0x2002 0070 Destination address Next LLI address Control information = 0x 2003 1200 = peripheral = 0 (end of list) = length 3072 0x2003 1200 3072 bytes of data 0x2003 1DFF Fig 27. LLI example The first LLI, stored at 0x2002 0000, defines the first block of data to be transferred, which is the data stored from address 0x2002 A200 to 0x2002 ADFF: • • • • • • Source start address 0x2002 A200. Destination address set to the destination peripheral address. Transfer width, word (32-bit). Transfer size, 3072 bytes (0xC00). Source and destination burst sizes, 16 transfers. Next LLI address, 0x2002 0010. The second LLI, stored at 0x2002 0010, describes the next block of data to be transferred: • Source start address 0x2002 B200. • Destination address set to the destination peripheral address. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 292 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller FT D R A D R A R A FT D R FT • • • • Transfer width, word (32-bit). Transfer size, 3072 bytes (0xC00). Source and destination burst sizes, 16 transfers. Next LLI address, 0x2002 0020. D R A chain of descriptors is built up, each one pointing to the next in the series. To initialize the DMA stream, the first LLI, 0x2002 0000, is programmed into the DMA Controller. When the first packet of data has been transferred the next LLI is automatically loaded. The final LLI is stored at 0x2002 0070 and contains: R A FT D R R A F D R A FT A FT A FT D R A D FT D R A • • • • • • Source start address 0x2003 1200. Destination address set to the destination peripheral address. Transfer width, word (32-bit). Transfer size, 3072 bytes (0xC00). Source and destination burst sizes, 16 transfers. Next LLI address, 0x0. Because the next LLI address is set to zero, this is the last descriptor, and the DMA channel is disabled after transferring the last item of data. The channel is probably set to generate an interrupt at this point to indicate to the ARM processor that the channel can be reprogrammed. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 293 of 1164 D R A FT D R A FT D R A FT D R A FT D R A FT UM10430 Rev. 00.13 — 20 July 2011 D D Chapter 17: LPC18xx SPI Flash Interface (SPIFI) D R A FT D D R A FT D R A FT D R A R A FT D R A R A FT D R A FT D R A F R A FT D R R D User manual FT D R A FT FT A FT 17.1 How to read this chapter The SPIFI is available on all LPC18xx parts. D D R A FT D R A 17.2 Basic configuration The SPIFI is configured as follows: • See Table 219 for clocking and power control. • The SPIFI is reset by the SPIFI_RST (reset # 53). Table 219. SPIFI clocking and power control Base clock Branch clock Maximum frequency SPIFI AHB register clock (HCLK) SPIFI serial clock input (SCKI) BASE_M3_CLK BASE_SPIFI_CLK CLK_M3_SPIFI SPIFI_CLK 150 MHz 132 MHz 17.3 Features • • • • Interfaces to serial flash memory in the main memory map. Supports 1-, 2-, and 4-bit bidirectional serial protocols. Half-duplex protocol compatible with various vendors and devices. Data rates of up to 66 MB per second. 17.4 General description The SPI Flash Interface (SPIFI) allows low-cost serial flash memories to be connected to the Cortex-M3 processor with little performance penalty compared to parallel flash devices with higher pin count. A driver API included in on-chip ROM handles setup, programming and erasure. After an initialize call to the SPIFI driver, the flash content is accessible as normal memory using byte, halfword, and word accesses by the processor and/or DMA channels. Many serial flash devices use a half-duplex command-driven SPI protocol for device setup and initialization. Quad devices then use a half-duplex, command-driven 4-bit protocol for normal operation. Different serial flash vendors and devices accept or require different commands and command formats. SPIFI provides sufficient flexibility to be compatible with common flash devices, and includes extensions to help insure compatibility with future devices. Serial flash devices respond to commands sent by software or automatically sent by the SPIFI when software reads either of the two read-only serial flash regions in the memory map (see Table 220). All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 294 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 17: LPC18xx SPI Flash Interface (SPIFI) FT D R A D R A R A FT D R FT D Table 220. SPIFI flash memory map Memory Address R R A FT D R A F D A FT SPIFI data 0x1400 0000 to 0x17FF FFFF 0x8000 0000 to 0x87FF FFFF R Remark: These are the spaces allocated to the SPIFI in the LPC18xx. The same data appears in the first area and the first half of the second area. These areas allow maxima of 64 and 128 MB of SPI flash (respectively) to be mapped into the Cortex-M3 memory space. In practice, the usable space is limited to the size of the connected device Commands are divided into fields called opcode, address, intermediate, and data. The address, intermediate, and data fields are optional depending on the opcode. Some devices include a mode in which the opcode can be implied in read commands for higher performance. Data fields are further divided into input and output data fields depending on the opcode. Remark: Flashless parts (LPC1850/30/20/10) can use the SPIFI for booting. See Section 3.3.4.3. R A FT D R A FT D A FT D R A 17.5 Pin description Table 221. SPIFI Pin description Pin Direction Description SPIFI_SCK SPIFI_CS O O Serial clock for the flash memory, switched only during active bits on the MOSI/IO0, MISO/IO1, and IO3:2 lines. Chip select for the flash memory, driven low while a command is in progress, and high between commands. In the typical case of one serial slave, this signal can be connected directly to the device. If more than one serial slave is connected, software and off-chip hardware should use general-purpose I/O signals in combination with this signal to generate the chip selects for the various slaves. This is an output except in quad/dual input data fields. After a quad/dual input data field, it becomes an output again one serial clock period after CS goes high. This is an output in quad/dual opcode, address, intermediate, and output data fields, and an input in SPI mode and in quad/dual input data fields. After an input data field in quad/dual mode, it becomes an output again one serial clock period after CS goes high. These are outputs in quad opcode, address, intermediate, and output data fields, and inputs in quad input data fields. If the flash memory does not have quad capability, these pins can be assigned to GPIO or other functions. SPIFI_MOSI or IO0 SPIFI_MISO or IO1 I/O I/O SPIFI_SIO[3:2] I/O 17.6 SPIFI API calls The SPIFI interface is controlled through a set of simple API calls located in the LPC18xx ROM. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 295 of 1164 D R A FT D R A FT D R A FT D R A FT D R A FT UM10430 Chapter 18: LPC18xx SD/MMC interface Rev. 00.13 — 20 July 2011 D D D R A FT D D R A FT D R A FT D R A R A FT D R A R A FT D R A FT D R A F R A FT D R R D User manual FT D R A FT FT A FT 18.1 How to read this chapter The SD/MMC card interface is available on LPC18xx Rev ‘A’. D D R A FT D R A 18.2 Basic configuration Table 222. SDIO clocking and power control Base clock Branch clock Maximum frequency SDIO register interface SDIO bit rate clock BASE_M3_CLK BASE_SDIO_CLK CLK_M3_SDIO CLK_SDIO 150 MHz The SDIO is reset by the SD_RST (reset # 20). 18.3 Features The SD/MMC card interface supports the following modes: • • • • Secure Digital memory (SD version 3.0) Secure Digital I/O (SDIO version 2.0) Consumer Electronics Advanced Transport Architecture (CE-ATA version 1.1) Multimedia Cards (MMC version 4.4) 18.4 General description All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 296 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 18: LPC18xx SD/MMC interface FT D R R A D R A R A FT D R FT D R A R A FT FT A F clk Interrupts , status BIU Interrupt Control Power, Pullup, Card Detect, & Debounce Control CIU SDIO Interrupt Control Synchronizer Regulators Power Switches D D R R A FT D R A FT D A FT D R APB/AHB Slave Interface Socket A Input Sample Register Output Hold Register Host Interface Unit MUX/ De-Mux Unit Write Protect Card Detect Registers DMA Interface Control AHB Master Interface Command Control Path FIFO Control Data Path Control Cards cclk ccmd cdata Internal DMA Controller cclk_in_drv cclk_in_sample cclk_in RAM Interface *** FIFO RAM**** Clock Control *** Optional RAM Interface **** FIFO RAM can be chosen as either internal or external RAM Note: The card_detect and write-protect signals are from the SD/MMC card socket and not from the SD/MMC card. Fig 28. SD/MMC block diagram 18.5 Pin description Table 223. SDIO pin description Pin name Direction Description SD_CLK SD_CD SD_WP SD_LED SD_CMD SD_D[7:0] SD_POW SD_VOLT[2:0] O O O O I/O I/O SD/SDIO/MMC clock SDIO card detect for single slot SDIO card write protect LED On signal. This signal cautions the user not to remove the SD card while it is accessed. Command input/output Data input/output for data lines DAT[7:0] All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 297 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 18: LPC18xx SD/MMC interface FT D R A D R A R A FT D R FT D R R A FT D R A F D A FT 18.6 Register description Table 224. Register overview: SDMMC (base address: 0x4000 4000) Name Access Address offset Description R Reset value R A FT D R A FT D A FT D R A CTRL PWREN CLKDIV CLKSRC CLKENA TMOUT CTYPE BLKSIZ BYTCNT INTMASK CMDARG CMD RESP0 RESP1 RESP2 RESP3 MINTSTS RINTSTS STATUS FIFOTH CDETECT WRTPRT GPIO TCBCNT TBBCNT DEBNCE USRID VERID UHS_REG RST_N BMOD PLDMND DBADDR IDSTS R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R r R/W R R/W R R R/W R R R/W R/W R R/W R/W R/W W R/W R/W 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 0x024 0x028 0x02C 0x030 0x034 0x038 0x03C 0x040 0x044 0x048 0x04C 0x050 0x054 0x058 0x05C 0x060 0x064 0x068 0x06C 0x074 0x078 0x080 0x084 0x088 0x08C Control Register Power Enable Register Clock Divider Register SD Clock Source Register Clock Enable Register Time-out Register Card Type Register Block Size Register Byte Count Register Interrupt Mask Register Command Argument Register Command Register Response Register 0 Response Register 1 Response Register 2 Response Register 3 Masked Interrupt Status Register Raw Interrupt Status Register Status Register FIFO Threshold Watermark Register Card Detect Register Write Protect Register General Purpose Input/Output Register Transferred CIU Card Byte Count Register Transferred Host to BIU-FIFO Byte Count Register Debounce Count Register User ID Register Version ID Register UHS-1 Register Hardware Reset Bus Mode Register Poll Demand Register Descriptor List Base Address Register Internal DMAC Status Register 0x00000000 0x00000000 0x00000000 0x00000000 0x5342230a 0x00000000 0x00000000 0 0x00000000 0x00000000 0x00000000 0x00000000 0 0 Reset value 0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 298 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 18: LPC18xx SD/MMC interface FT D R Table 224. Register overview: SDMMC (base address: 0x4000 4000) Name Access Address offset Description D R A R A FT D R FT D A R Reset value R A FT D R R A F D R A A FT A IDINTEN DSCADDR BUFADDR R/W R R 0x090 0x094 0x098 Internal DMAC Interrupt Enable Register Current Host Descriptor Address Register Current Buffer Descriptor Address Register 0x00000000 0x00000000 0x00000000 FT D R A FT D R A FT D 18.6.1 Control Register (CTRL) Table 225. Control Register (CTRL, address 0x4000 4000) bit description Bit Symbol Value Description Reset value 0 CONTROLLER_RESET Controller reset. To reset controller, firmware should set bit to 1. This bit is auto-cleared after two AHB and two cclk_in clock cycles. This resets: - BIU/CIU interface - CIU and state machines - abort_read_data, send_irq_response, and read_wait bits of Control register - start_cmd bit of Command register Does not affect any registers or DMA interface, or FIFO or host interrupts 0 1 No change Reset DWC_mobile_storage controller Fifo reset. To reset FIFO, firmware should set bit to 1. This bit is auto-cleared after completion of reset operation. auto-cleared after two AHB clocks. 0 1 No change Reset to data FIFO To reset FIFO pointers 0 1 FIFO_RESET 0 2 DMA_RESET 0 1 dma_reset. To reset DMA interface, firmware should set bit to 1. This 0 bit is auto-cleared after two AHB clocks. No change Reset internal DMA interface control logic Reserved Global interrupt enable/disable bit. The int port is 1 only when this bit is 1 and one or more unmasked interrupts are set. 0 1 Disable interrupts Enable interrupts DMA enable. Valid only if DWC_mobile_storage configured for External DMA interface. Even when DMA mode is enabled, host can still push/pop data into or from FIFO; this should not happen during the normal operation. If there is simultaneous FIFO access from host/DMA, the data coherency is lost. Also, there is no arbitration inside DWC_mobile_storage to prioritize simultaneous host/DMA access. 0 1 Disable DMA transfer mode Enable DMA transfer mode 0 0 3 4 INT_ENABLE 5 DMA_ENABLE All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 299 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 18: LPC18xx SD/MMC interface FT D R A D R A R A FT D R FT Table 225. Control Register (CTRL, address 0x4000 4000) bit description Bit Symbol Value Description D R R A FT D R R A Reset value A FT D R F A A 6 READ_WAIT 0 1 read_wait. For sending read-wait to SDIO cards. Clear read wait Assert read wait 0 FT D R A FT D R FT D 7 SEND_IRQ_RESPONS E Send irq response. Bit automatically clears once response is sent. To 0 wait for MMC card interrupts, host issues CMD40, and DWC_mobile_storage waits for interrupt response from MMC card(s). In meantime, if host wants DWC_mobile_storage to exit waiting for interrupt state, it can set this bit, at which time DWC_mobile_storage command state-machine sends CMD40 response on bus and returns to idle state. 0 1 No change Send auto IRQ response Abort read data. Used in SDIO card suspend sequence. 0 1 No change After suspend command is issued during read-transfer, software polls card to find when suspend happened. Once suspend occurs, software sets bit to reset data state-machine, which is waiting for next block of data. Bit automatically clears once data state machine resets to idle. Send ccsd. When set, DWC_mobile_storage sends CCSD to CE-ATA 0 device. Software sets this bit only if current command is expecting CCS (that is, RW_BLK) and interrupts are enabled in CE-ATA device. Once the CCSD pattern is sent to device, DWC_mobile_storage automatically clears send_ccsd bit. It also sets Command Done (CD) bit in RINTSTS register and generates interrupt to host if Command Done interrupt is not masked. NOTE: Once send_ccsd bit is set, it takes two card clock cycles to drive the CCSD on the CMD line. Due to this, during the boundary conditions it may happen that CCSD is sent to the CE-ATA device, even if the device signalled CCS. 0 1 Clear bit if DWC_mobile_storage does not reset the bit. Send Command Completion Signal Disable (CCSD) to CE-ATA device Send auto stop ccsd. NOTE: Always set send_auto_stop_ccsd and 0 send_ccsd bits together; send_auto_stop_ccsd should not be set independent of send_ccsd. When set, DWC_Mobile_Storage automatically sends internallygenerated STOP command (CMD12) to CE-ATA device. After sending internally-generated STOP command, Auto Command Done (ACD) bit in RINTSTS is set and generates interrupt to host if Auto Command Done interrupt is not masked. After sending the CCSD, DWC_mobile_storage automatically clears send_auto_stop_ccsd bit. 0 1 Clear bit if DWC_mobile_storage does not reset the bit. Send internally generated STOP after sending CCSD to CE-ATA device. 0 A 8 ABORT_READ_DATA 9 SEND_CCSD 10 SEND_AUTO_STOP_C CSD All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 300 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 18: LPC18xx SD/MMC interface FT D R A D R A R A FT D R FT Table 225. Control Register (CTRL, address 0x4000 4000) bit description Bit Symbol Value Description D R R A FT D R R A Reset value A FT D R F A A 11 CEATA_DEVICE_INTE RRUPT _STATUS CEATA device interrupt status. Software should appropriately write to 0 this bit after power-on reset or any other reset to CE-ATA device. After reset, usually CE-ATA device interrupt is disabled (nIEN = 1). If the host enables CE-ATA device interrupt, then software should set this bit. 0 1 Interrupts not enabled in CE-ATA device (nIEN = 1 in ATA control register) Interrupts are enabled in CE-ATA device (nIEN = 0 in ATA control register) Reserved Card regulator-A voltage setting; output to card_volt_a port. Optional feature; ports can be used as general-purpose outputs. Card regulator-B voltage setting; output to card_volt_b port. Optional feature; ports can be used as general-purpose outputs. 0 0 FT D R A FT D R A FT D 15:12 19:16 23:20 24 CARD_VOLTAGE_A CARD_VOLTAGE_B ENABLE_OD_PULLUP External open-drain pull up. Inverted value of this bit is output to 1 ccmd_od_pullup_en_n port. When bit is set, command output always driven in open-drive mode; that is, DWC_mobile_storage drives either 0 or high impedance, and does not drive hard 1. 0 1 Disable Enable Present only for the Internal DMAC configuration; else, it is reserved. 0 0 1 The host performs data transfers through the slave interface Internal DMAC used for data transfer Reserved 25 USE_INTERNAL_DMA C 31:26 - 18.6.2 Power Enable Register (PWREN) Table 226. Power Enable Register (PWREN, address 0x4000 4004) bit description Bit Symbol Description Reset value 29:0 POWER_ENABLE Power on/off switch for up to 16 cards; for example, bit[0] controls card 0. Once power is turned on, firmware should wait for regulator/switch ramp-up time before trying to initialize card. 0 - power off 1 - power on Only NUM_CARDS number of bits are implemented. Bit values output to card_power_en port. Optional feature; ports can be used as general-purpose outputs. Reserved 0 31:30 - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 301 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 18: LPC18xx SD/MMC interface FT D R A D R A R A FT D R FT 18.6.3 Clock Divider Register (CLKDIV) Bit Symbol Description D R Table 227. Clock Divider Register (CLKDIV, address 0x4000 4008) bit description R A FT D R R A F D R A FT A FT A FT D R Reset value D 7:0 CLK_DIVIDER0 Clock divider-0 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of ff means divide by 2*255 = 510, and so on. 0 A FT D R A 15:8 CLK_DIVIDER1 Clock divider-1 value. Clock division is 2*n. For example, 0 value of 0 means divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of ff means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported. Clock divider-2 value. Clock division is 2*n. For example, 0 value of 0 means divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of ff means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported. Clock divider-3 value. Clock division is 2*n. For example, 0 value of 0 means divide by 2*0 = 0 (no division, bypass), a value of 1 means divide by 2*1 = 2, a value of ff means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported. divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of ff means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported. 23:16 CLK_DIVIDER2 31:24 CLK_DIVIDER3 18.6.4 SD Clock Source Register (CLKSRC) Table 228. SD Clock Source Register (CLKSRC, address 0x4000 400C) bit description Bit Symbol Description Reset value 31:0 CLK_SOURCE Clock divider source for up to 16 SD cards supported. Each card 0 has two bits assigned to it. For example, bits[1:0] assigned for card-0, which maps and internally routes clock divider[3:0] outputs to cclk_out[15:0] pins, depending on bit value. 00 - Clock divider 0 01 - Clock divider 1 10 - Clock divider 2 11 - Clock divider 3 In MMC-Ver3.3-only controller, only one clock divider supported. The cclk_out is always from clock divider 0, and this register is not implemented. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 302 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 18: LPC18xx SD/MMC interface FT D R A D R A R A FT D R FT 18.6.5 Clock Enable Register (CLKENA) Bit Symbol Description D R Table 229. Clock Enable Register (CLKENA, address 0x4000 4010) bit description R A FT D R R A F D R A FT A FT A FT D R Reset value D 15:0 CCLK_ENABLE Low-power control for up to 16 SD card clocks and one 0 MMC card clock supported. 0 - Non-low-power mode 1 Low-power mode; stop clock when card in IDLE (should be normally set to only MMC and SD memory cards; for SDIO cards, if interrupts must be detected, clock should not be stopped). In MMC-Ver3.3-only mode, since there is only one cclk_out, only cclk_low_power[0] is used. supported. 0 - Clock disabled 1 - Clock enabled In MMC-Ver3.3-only mode, since there is only one cclk_out, only cclk_enable[0] is used. Clock-enable control for up to 16 SD card clocks and one 0 MMC card clock supported. 0 - Clock disabled 1 - Clock enabled In MMC-Ver3.3-only mode, since there is only one cclk_out, only cclk_enable[0] is used. supported. 0 - Non-low-power mode 1 - Low-power mode; stop clock when card in IDLE (should be normally set to only MMC and SD memory cards; for SDIO cards, if interrupts must be detected, clock should not be stopped). In MMC-Ver3.3-only mode, since there is only one cclk_out, only cclk_low_power[0] is used. A FT D R A 31:16 CCLK_LOW_PO WER 18.6.6 Time-out Register (TMOUT) Table 230. Time-out Register (TMOUT, address 0x4000 4014) bit description Bit Symbol Description Reset value 7:0 31:8 RESPONSE_TIM Response time-out value. Value is in number of card EOUT output clocks - cclk_out. DATA_TIMEOUT 0x40 Value for card Data Read time-out; same value also 0xFFFFFF used for Data Starvation by Host time-out. Value is in number of card output clocks - cclk_out of selected card. Starvation by Host time-out. Value is in number of card output clocks - cclk_out of selected card. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 303 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 18: LPC18xx SD/MMC interface FT D R A D R A R A FT D R FT 18.6.7 Card Type Register (CTYPE) Table 231. Card Type Register (CTYPE, address 0x4000 4018) bit description Bit Symbol Description D R R A FT D R R A F D R A FT A FT Reset value A FT D D R 15:0 CARD_WIDTH One bit per card indicates if card is 1-bit or 4-bit: 0 - 1-bit mode 1 - 4-bit mode Bit[15] corresponds to card[15], bit[0] corresponds to card[0]. Only NUM_CARDS*2 number of bits are implemented. One bit per card indicates if card is 8-bit: 0 - Non 8-bit mode 1 - 8-bit mode Bit[31] corresponds to card[15]; bit[16] corresponds to card[0]. 0 A FT D R A 31:16 CARD_WIDTH 0 18.6.8 Block Size Register (BLKSIZ) Table 232. Block Size Register (BLKSIZ, address 0x4000 401C) bit description Bit Symbol Description Reset value 15:0 31:16 BLOCK_SIZE - Block size Reserved 0x200 18.6.9 Byte Count Register (BYTCNT) Table 233. Byte Count Register (BYTCNT, address 0x4000 4020) bit description Bit Symbol Description Reset value 31:0 BYTE_COUNT Number of bytes to be transferred; should be integer multiple 0x200 of Block Size for block transfers. For undefined number of byte transfers, byte count should be set to 0. When byte count is set to 0, it is responsibility of host to explicitly send stop/abort command to terminate data transfer. 18.6.10 Interrupt Mask Register (INTMASK) Table 234. Interrupt Mask Register (INTMASK, address 0x4000 4024) bit description Bit Symbol Description Reset value 0 1 2 3 4 CD RE CD DTO TXDR Card detect. Bits used to mask unwanted interrupts. Value 0 of 0 masks interrupt; value of 1 enables interrupt. Response error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt. Command done. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt. 0 0 Data transfer over. Bits used to mask unwanted interrupts. 0 Value of 0 masks interrupt; value of 1 enables interrupt. Transmit FIFO data request. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt. 0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 304 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 18: LPC18xx SD/MMC interface FT D R R A Table 234. Interrupt Mask Register (INTMASK, address 0x4000 4024) bit description D R A R A FT D R FT D R A R A A Bit Symbol Description Reset value FT D R A F FT D R A 5 RXDR Receive FIFO data request. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt. Response CRC error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt. Data CRC error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt. Response time-out. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt. 0 FT D R A FT FT D 6 RCRC 0 D R A 7 8 DCRC RTO 0 0 9 10 DRTO HTO Data read time-out. Bits used to mask unwanted interrupts. 0 Value of 0 masks interrupt; value of 1 enables interrupt. Data starvation-by-host time-out (HTO) /Volt_switch_int. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt. 0 11 FRUN FIFO underrun/overrun error. Bits used to mask unwanted 0 interrupts. Value of 0 masks interrupt; value of 1 enables interrupt. Hardware locked write error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt. Start-bit error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt. Auto command done. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt. 0 12 HLE 13 14 SBE ACD 0 0 15 EBE End-bit error (read)/Write no CRC. Bits used to mask 0 unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt. 31:16 SDIO_INT_MASK Mask SDIO interrupts One bit for each card. Bit[31] 0 corresponds to card[15], and bit[16] corresponds to card[0]. When masked, SDIO interrupt detection for that card is disabled. A 0 masks an interrupt, and 1 enables an interrupt. In MMC-Ver3.3-only mode, these bits are always 0. 18.6.11 Command Argument Register (CMDARG) Table 235. Command Argument Register (CMDARG, address 0x4000 4028) bit description Bit Symbol Description Reset value 31:0 CMD_ARG Value indicates command argument to be passed to card. 0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 305 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 18: LPC18xx SD/MMC interface FT D R A D R A R A FT D R FT 18.6.12 Command Register (CMD) Table 236. Command Register (CMD, address 0x4000 402C) bit description Bit Symbol Value Description D R R A FT D R R A F D R A FT A FT Reset value A FT D D R 5:0 6 CMD_INDEX RESPONSE_EXPECT 0 1 Command index response expect No response expected from card Response expected from card response length 0 1 Short response expected from card Long response expected from card 0 0 A FT D R A 7 RESPONSE_ LENGTH 0 8 CHECK_RESPONSE_C RC 0 1 check response crc Some of command responses do not return valid 0 CRC bits. Software should disable CRC checks for those commands in order to disable CRC checking by controller. Do not check response CRC Check response CRC data expected 0 1 No data transfer expected (read/write) Data transfer expected (read/write) read/write. Don't care if no data expected from card. 0 1 Read from card Data transfer expected (read/write) transfer mode. Don't care if no data expected. 0 1 Block data transfer command Stream data transfer command send auto stop. When set, DWC_mobile_storage sends stop 0 command to SD_MMC_CEATA cards at end of data transfer. Refer to to determine: - when send_auto_stop bit should be set, since some data transfers do not need explicit stop commands - open-ended transfers that software should explicitly send to stop command Additionally, when resume is sent to resume - suspended memory access of SD-Combo card - bit should be set correctly if suspended data transfer needs send_auto_stop. Don't care if no data expected from card. 0 1 No stop command sent at end of data transfer Send stop command at end of data transfer wait prvdata complete. The wait_prvdata_complete = 0 option typically used to query status of card during data transfer or to stop current data transfer; card_number should be same as in previous command. 0 1 Send command at once, even if previous data transfer has not completed. Wait for previous data transfer completion before sending command. 0 0 0 0 9 DATA_EXPECTED 10 READ_WRITE 11 TRANSFER_MODE 12 SEND_AUTO_STOP 13 WAIT_PRVDATA_COM PLETE All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 306 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 18: LPC18xx SD/MMC interface FT D R A D R A R A FT D R FT Table 236. Command Register (CMD, address 0x4000 402C) bit description Bit Symbol Value Description D R R A FT D R R A F D R A Reset value A FT A 14 STOP_ABORT_CMD stop abort cmd. When open-ended or predefined data transfer is in progress, and host issues stop or abort command to stop data transfer, bit should be set so that command/data state-machines of CIU can return correctly to idle state. This is also applicable for Boot mode transfers. To Abort boot mode, this bit should be set along with CMD[26] = disable_boot. 0 Neither stop nor abort command to stop current data transfer in progress. If abort is sent to function-number currently selected or not in data-transfer mode, then bit should be set to 0. Stop or abort command intended to stop current data transfer in progress. 0 FT D R A FT D R A FT D 1 15 SEND_INITIALIZATION send initialization. After power on, 80 clocks must be sent to card for 0 initialization before sending any commands to card. Bit should be set while sending first command to card so that controller will initialize clocks before sending command to card. This bit should not be set for either of the boot modes (alternate or mandatory). 0 1 Do not send initialization sequence (80 clocks of 1) before sending this command. Send initialization sequence before sending this command. card number. Card number in use. Represents physical slot number 0 of card being accessed. In MMC-Ver3.3-only mode, up to 30 cards are supported; in SD-only mode, up to 16 cards are supported. Registered version of this is reflected on dw_dma_card_num and ge_dma_card_num ports, which can be used to create separate DMA requests, if needed. In addition, in SD mode this is used to mux or demux signals from selected card because each card is interfaced to DWC_mobile_storage by separate bus. update clock registers only. Following register values transferred into card clock domain: CLKDIV, CLRSRC, CLKENA. Changes card clocks (change frequency, truncate off or on, and set low-frequency mode); provided in order to change clock frequency or stop clock without having to send command to cards. During normal command sequence, when update_clock_registers_only = 0, following control registers are transferred from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, BYTCNT. CIU uses new register values for new command sequence to card(s). When bit is set, there are no Command Done interrupts because no command is sent to SD_MMC_CEATA cards. registers_only. 0 1 Normal command sequence Do not send commands, just update clock register value into card clock domain 0 20:16 CARD_NUMBER 21 UPDATE_CLOC_REGI STERS_ONLY All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 307 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 18: LPC18xx SD/MMC interface FT D R A D R A R A FT D R FT Table 236. Command Register (CMD, address 0x4000 402C) bit description Bit Symbol Value Description D R R A FT D R R A F D R A Reset value A FT A 22 READ_CEATA_DEVICE read ceata device. Software should set this bit to indicate that CE-ATA 0 device is being accessed for read transfer. This bit is used to disable read data time-out indication while performing CE-ATA read transfers. Maximum value of I/O transmission delay can be no less than 10 seconds. DWC_mobile_storage should not indicate read data time-out while waiting for data from CE-ATA device. 0 1 Host is not performing read access (RW_REG or RW_BLK) towards CE-ATA device. Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device. ccs expected. If the command expects Command Completion Signal (CCS) from the CE-ATA device, the software should set this control bit. DWC_mobile_storage sets Data Transfer Over (DTO) bit in RINTSTS register and generates interrupt to host if Data Transfer Over interrupt is not masked. 0 1 Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register), or command does not expect CCS from device. Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects command completion signal from CE-ATA device. Enable Boot - this bit should be set only for mandatory boot mode. When Software sets this bit along with start_cmd, CIU starts the boot sequence for the corresponding card by asserting the CMD line low. Do NOT set disable_boot and enable_boot together. Expect Boot Acknowledge. When Software sets this bit along with enable_boot, CIU expects a boot acknowledge start pattern of 0-1-0 from the selected card. Disable Boot. When software sets this bit along with start_cmd, CIU terminates the boot operation. Do NOT set disable_boot and enable_boot together. Boot Mode 0 1 Mandatory Boot operation Alternate Boot operation Voltage switch bit 0 1 No voltage switching Voltage switching enabled; must be set for CMD11 only Reserved Start command. Once command is taken by CIU, bit is cleared. When bit is set, host should not attempt to write to any command registers. If write is attempted, hardware lock error is set in raw interrupt register. Once command is sent and response is received from SD_MMC_CEATA cards, Command Done bit is set in raw interrupt register. 0 FT D R A FT D R A FT D 23 CCS_EXPECTED 0 24 ENABLE_BOOT 0 25 EXPECT_BOOT_ACK 0 26 DISABLE_BOOT 0 27 BOOT_MODE 0 28 VOLT_SWITCH 30:29 31 START_CMD All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 308 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 18: LPC18xx SD/MMC interface FT D R A D R A R A FT D R FT 18.6.13 Response Register 0 (RESP0) Bit Symbol Description D R R A FT Reset value R A F A FT Table 237. Response Register 0 (RESP0, address 0x4000 4030) bit description D D R A FT D R A FT D R 31:0 RESPONSE0 Bit[31:0] of response 0 A FT D R A 18.6.14 Response Register 1 (RESP1) Table 238. Response Register 1 (RESP1, address 0x4000 4034) bit description Bit Symbol Description Reset value 31:0 RESPONSE1 Register represents bit[63:32] of long response. When CIU 0 sends auto-stop command, then response is saved in register. Response for previous command sent by host is still preserved in Response 0 register. Additional auto-stop issued only for data transfer commands, and response type is always short for them. For information on when CIU sends auto-stop commands, refer to Auto-Stop . 18.6.15 Response Register 2 (RESP2) Table 239. Response Register 2 (RESP2, address 0x4000 4038) bit description Bit Symbol Description Reset value 31:0 RESPONSE2 Bit[95:64] of long response 0 18.6.16 Response Register 3 (RESP3) Table 240. Response Register 3 (RESP3, address 0x4000 403C) bit description Bit Symbol Description Reset value 31:0 RESPONSE3 Bit[127:96] of long response 0 18.6.17 Masked Interrupt Status Register (MINTSTS) Table 241. Masked Interrupt Status Register (MINTSTS, address 0x4000 4040) bit description Bit Symbol Description Reset value 0 1 2 3 4 CD RE CD DTO TXDR Card detect. Interrupt enabled only if corresponding bit in interrupt mask register is set. Response error. Interrupt enabled only if corresponding bit in interrupt mask register is set. Command done. Interrupt enabled only if corresponding bit in interrupt mask register is set. Data transfer over. Interrupt enabled only if corresponding bit in interrupt mask register is set. Transmit FIFO data request. Interrupt enabled only if corresponding bit in interrupt mask register is set. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 309 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 18: LPC18xx SD/MMC interface FT D R R A Table 241. Masked Interrupt Status Register (MINTSTS, address 0x4000 4040) bit description D R A R A FT D R FT D R A R A A Bit Symbol Description Reset value FT D R A F FT D R A 5 6 7 8 9 10 11 12 13 14 15 31:16 RXDR RCRC DCRC RTO DRTO HTO FRUN HLE SBE ACD EBE Receive FIFO data request. Interrupt enabled only if corresponding bit in interrupt mask register is set. Response CRC error. Interrupt enabled only if corresponding bit in interrupt mask register is set. Data CRC error. Interrupt enabled only if corresponding bit in interrupt mask register is set. Response time-out. Interrupt enabled only if corresponding bit in interrupt mask register is set. Data read time-out. Interrupt enabled only if corresponding bit in interrupt mask register is set. Data starvation-by-host time-out (HTO). Interrupt enabled only if corresponding bit in interrupt mask register is set. FIFO underrun/overrun error. Interrupt enabled only if corresponding bit in interrupt mask register is set. Hardware locked write error. Interrupt enabled only if corresponding bit in interrupt mask register is set. Start-bit error. Interrupt enabled only if corresponding bit in interrupt mask register is set. Auto command done. Interrupt enabled only if corresponding bit in interrupt mask register is set. End-bit error (read)/write no CRC. Interrupt enabled only if corresponding bit in interrupt mask register is set. FT D R A FT D R A FT D SDIO_INTERR Interrupt from SDIO card; one bit for each card. Bit[31] UPT corresponds to Card[15], and bit[16] is for Card[0]. SDIO interrupt for card enabled only if corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1 enables interrupt; 0 masks interrupt). 0 - No SDIO interrupt from card 1 - SDIO interrupt from card In MMC-Ver3.3-only mode, bits always 0. 18.6.18 Raw Interrupt Status Register (RINTSTS) Table 242. Raw Interrupt Status Register (RINTSTS, address 0x4000 4044) bit description Bit Symbol Description Reset value 0 CD Card detect. Writes to bits clear status bit. Value of 1 clears 0 status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status. Response error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status. Command done. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status. 0 1 RE 2 CD 0 3 DTO Data transfer over. Writes to bits clear status bit. Value of 1 0 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 310 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 18: LPC18xx SD/MMC interface FT D R R A Table 242. Raw Interrupt Status Register (RINTSTS, address 0x4000 4044) bit description D R A R A FT D R FT D R A R A A Bit Symbol Description Reset value FT D R A F FT D R A 4 TXDR Transmit FIFO data request. Writes to bits clear status bit. 0 Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status. Receive FIFO data request. Writes to bits clear status bit. 0 Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status. Response CRC error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status. Data CRC error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status. Response time-out (RTO)/Boot Ack Received (BAR). Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status. Data read time-out (DRTO)/Boot Data Start (BDS). Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status. 0 FT D R A FT FT D 5 RXDR D R A 6 RCRC 7 DCRC 0 8 RTO_BAR 0 9 DRTO_BDS 0 10 HTO Data starvation-by-host time-out (HTO). Writes to bits clear 0 status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status./Volt_switch_int FIFO underrun/overrun error. Writes to bits clear status bit. 0 Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status. Hardware locked write error. Writes to bits clear status bit. 0 Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status. Start-bit error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status. Auto command done. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status. 0 11 FRUN 12 HLE 13 SBE 14 ACD 0 15 EBE End-bit error (read)/write no CRC. Writes to bits clear 0 status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status. Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15], and bit[16] is for Card[0]. Writes to these bits clear them. Value of 1 clears bit and 0 leaves bit intact. 0 - No SDIO interrupt from card 1 - SDIO interrupt from card In MMC-Ver3.3-only mode, bits always 0. Bits are logged regardless of interrupt-mask status. 0 31:16 SDIO_INTERRUPT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 311 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 18: LPC18xx SD/MMC interface FT D R A D R A R A FT D R FT 18.6.19 Status Register (STATUS) Table 243. Status Register (STATUS, address 0x4000 4048) bit description Bit Symbol Description D R R A FT D R R A F D R A FT A FT A FT D R Reset value D 0 1 2 3 7:4 FIFO_RX_WATERM FIFO reached Receive watermark level; not qualified with data ARK FIFO_TX_WATERM FIFO reached Transmit watermark level; not qualified with data transfer. ARK FIFO_EMPTY FIFO_FULL CMDFSMSTATES FIFO is empty status FIFO is full status Command FSM states: 0 - Idle 1 - Send init sequence 2 - Tx cmd start bit 3 - Tx cmd tx bit 4 - Tx cmd index + arg 5 - Tx cmd crc7 6 - Tx cmd end bit 7 - Rx resp start bit 8 - Rx resp IRQ response 9 - Rx resp tx bit 10 - Rx resp cmd idx 11 - Rx resp data 12 - Rx resp crc7 13 - Rx resp end bit 14 - Cmd path wait NCC 15 - Wait; CMD-to-response turnaround NOTE: The command FSM state is represented using 19 bits. The STATUS Register(7:4) has 4 bits to represent the command FSM states. Using these 4 bits, only 16 states can be represented. Thus three states cannot be represented in the STATUS(7:4) register. The three states that are not represented in the STATUS Register(7:4) are: - Bit 16 - Wait for CCS - Bit 17 - Send CCSD - Bit 18 - Boot Mode Due to this, while command FSM is in Wait for CCS state or Send CCSD or Boot Mode?, the Status register indicates status as 0 for the bit field 7:4. Raw selected card_data[3]; checks whether card is present 0 - card not present 1 - card present Inverted version of raw selected card_data[0] 0 - card data not busy 1 - card data busy Data transmit or receive state-machine is busy 0 1 1 0 0 A FT D R A 8 DATA_3_STATUS 9 DATA_BUSY 10 16:11 29:17 30 31 DATA_STATE_MC_ BUSY FIFO_COUNT DMA_ACK DMA_REQ 1 0 0 0 0 RESPONSE_INDEX Index of previous response, including any auto-stop sent by core. FIFO count - Number of filled locations in FIFO DMA acknowledge signal state; either dw_dma_ack or ge_dma_ack, depending on DW-DMA or Generic-DMA selection. DMA request signal state; either dw_dma_req or ge_dma_req, depending on DW-DMA or Generic-DMA selection. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 312 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 18: LPC18xx SD/MMC interface FT D R A D R A R A FT D R FT 18.6.20 FIFO Threshold Watermark Register (FIFOTH) Table 244. FIFO Threshold Watermark Register (FIFOTH, address 0x4000 404C) bit description Bit Symbol Value Description D R R A FT D R R A F D R A FT A FT A FT D R Reset value D 11:0 TX_WMARK FIFO threshold watermark level when transmitting data to card. When FIFO data count is less than or equal to this number, DMA/FIFO request is raised. If Interrupt is enabled, then interrupt occurs. During end of packet, request or interrupt is generated, regardless of threshold programming. In non-DMA mode, when transmit FIFO threshold (TXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, on last interrupt, host is responsible for filling FIFO with only required remaining bytes (not before FIFO is full or after CIU completes data transfers, because FIFO may not be empty). In DMA mode, at end of packet, if last transfer is less than burst size, DMA controller does single cycles until required bytes are transferred. 12 bits - 1 bit less than FIFO-count of status register, which is 13 bits. Limitation: TX_WMark >= 1; Recommended: FIFO_DEPTH/2; (means less than or equal to FIFO_DEPTH/2). Reserved. FIFO threshold watermark level when receiving data to card. When FIFO data count reaches greater than this number, DMA/FIFO request is raised. During end of packet, request is generated regardless of threshold programming in order to complete any remaining data. In non-DMA mode, when receiver FIFO threshold (RXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, interrupt is not generated if threshold programming is larger than any remaining data. It is responsibility of host to read remaining bytes on seeing Data Transfer Done interrupt. In DMA mode, at end of packet, even if remaining bytes are less than threshold, DMA request does single transfers to flush out any remaining bytes before Data Transfer Done interrupt is set. 12 bits - 1 bit less than FIFO-count of status register, which is 13 bits. Limitation: RX_WMark less than FIFO_DEPTH-2 Recommended: (FIFO_DEPTH/2) - 1; (means greater than (FIFO_DEPTH/2) - 1) NOTE: In DMA mode during CCS time-out, the DMA does not generate the request at the end of packet, even if remaining bytes are less than threshold. In this case, there will be some data left in the FIFO. It is the responsibility of the application to reset the FIFO after the CCS time-out. A FT D R A 15:12 27:16 RX_WMARK All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 313 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 18: LPC18xx SD/MMC interface FT D R Table 244. FIFO Threshold Watermark Register (FIFOTH, address 0x4000 404C) bit description Bit Symbol Value Description D R A R A FT D R FT D A R R A FT D R R A Reset value A FT D R F A A 30:28 DW_DMA_MUTIP LE_ TRANSACTION_ SIZE Burst size of multiple transaction; should be programmed same as 0 DW-DMA controller multiple-transaction-size SRC/DEST_MSIZE.The units for transfers is the H_DATA_WIDTH parameter. A single transfer (dw_dma_single assertion in case of Non DW DMA interface) would be signalled based on this value. Value should be sub-multiple of (RX_WMark + 1)* (F_DATA_WIDTH/H_DATA_WIDTH) and (FIFO_DEPTH - TX_WMark)* (F_DATA_WIDTH/ H_DATA_WIDTH) For example, if FIFO_DEPTH = 16, FDATA_WIDTH == H_DATA_WIDTH Allowed combinations for MSize and TX_WMark are: MSize = 1, TX_WMARK = 1-15 MSize = 4, TX_WMark = 8 MSize = 4, TX_WMark = 4 MSize = 4, TX_WMark = 12 MSize = 8, TX_WMark = 8 MSize = 8, TX_WMark = 4. Allowed combinations for MSize and RX_WMark are: MSize = 1, RX_WMARK = 0-14 MSize = 4, RX_WMark = 3 MSize = 4, RX_WMark = 7 MSize = 4, RX_WMark = 11 MSize = 8, RX_WMark = 7 MSize = 8, RX_WMark = 11 Recommended: MSize = 8, TX_WMark = 8, RX_WMark = 7 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 1 transfer 4 transfers 8 transfers 16 transfers 32 transfers 64 transfers 128 transfers 256 transfers Reserved FT D R A FT D R A FT D 31 - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 314 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 18: LPC18xx SD/MMC interface FT D R A D R A R A FT D R FT 18.6.21 Card Detect Register (CDETECT) Bit Symbol Description D R Table 245. Card Detect Register (CDETECT, address 0x4000 4050) bit description R A FT D R R A F D R A FT A FT Reset value A FT D D R 29:0 CARD_DETECT_N Value on card_detect_n input ports (1 bit per card); read-only bits. 0 represents presence of card. Only NUM_CARDS number of bits are implemented. Reserved A FT D R A 31:30 - 18.6.22 Write Protect Register (WRTPRT) Table 246. Write Protect Register (WRTPRT, address 0x4000 4054) bit description Bit Symbol Description Reset value 29:0 WRITE_PROTECT Value on card_write_prt input ports (1 bit per card). 1 represents write protection. Only NUM_CARDS number of bits are implemented. Reserved 31:30 - 18.6.23 General Purpose Input/Output Register (GPIO) Table 247. General Purpose Input/Output Register (GPIO, address 0x4000 4058) bit description Bit Symbol Description Reset value 7:0 23:8 31:24 GPI GPO - Value on gpi input ports; this portion of register is read-only. Valid only when AREA_OPTIMIZED parameter is 0. Value needed to be driven to gpo pins; this portion of register is read/write. Valid only when AREA_OPTIMIZED parameter is 0. Reserved 0 18.6.24 Transferred CIU Card Byte Count Register (TCBCNT) Table 248. Transferred CIU Card Byte Count Register (TCBCNT, address 0x4000 405C) bit description Bit Symbol Description Reset value 31:0 TRANS_CARD_BYTE Number of bytes transferred by CIU unit to card. In 32-bit or 64-bit AMBA 0 _COUNT data-bus-width modes, register should be accessed in full to avoid read-coherency problems. In 16-bit AMBA data-bus-width mode, internal 16-bit coherency register is implemented. User should first read lower 16 bits and then higher 16 bits. When reading lower 16 bits, higher 16 bits of counter are stored in temporary register. When higher 16 bits are read, data from temporary register is supplied. Both TCBCNT and TBBCNT share same coherency register. When AREA_OPTIMIZED parameter is 1, register should be read only after data transfer completes; during data transfer, register returns 0. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 315 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 18: LPC18xx SD/MMC interface FT D R R A 18.6.25 Transferred Host to BIU-FIFO Byte Count Register (TBBCNT) Table 249. Transferred Host to BIU-FIFO Byte Count Register (TBBCNT, address 0x4000 4060) bit description D R A R A FT D R FT D R A R A FT D D R A A FT F R A Bit Symbol Description Reset value FT D R FT D 31:0 TRANS_FIFO_BYTE_ Number of bytes transferred between Host/DMA memory and BIU FIFO. In 32-bit 0 COUNT or 64-bit AMBA data-bus-width modes, register should be accessed in full to avoid read-coherency problems. In 16-bit AMBA data-bus-width mode, internal 16-bit coherency register is implemented. User should first read lower 16 bits and then higher 16 bits. When reading lower 16 bits, higher 16 bits of counter are stored in temporary register. When higher 16 bits are read, data from temporary register is supplied. Both TCBCNT and TBBCNT share same coherency register. A FT D R A 18.6.26 Debounce Count Register (DEBNCE) Table 250. Debounce Count Register (DEBNCE, address 0x4000 4064) bit description Bit Symbol Description Reset value 23:0 31:24 DEBOUNCE_CO UNT - Number of host clocks (clk) used by debounce filter logic; typical debounce time is 5-25 ms. Reserved 0xFFFFFF 18.6.27 User ID Register (USRID) Table 251. User ID Register (USRID, address 0x4000 4068) bit description Bit Symbol Description Reset value 31:0 USRID User identification register; value set by user. Default reset value NA can be picked by user while configuring core before synthesis. Can also be used as scratch pad register by user. 18.6.28 Version ID Register (VERID) Table 252. Version ID Register (VERID, address 0x4000 406C) bit description Bit Symbol Description Reset value 31:0 VERID Version identification register; register value is 0x5342230a hard-wired. Can be read by firmware to support different versions of core. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 316 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 18: LPC18xx SD/MMC interface FT D R A D R A R A FT D R FT 18.6.29 UHS-1 Register (UHS_REG) Table 253. UHS-1 Register (UHS_REG, address 0x4000 4074) bit description Bit Symbol Description D R R A FT D R R A F D R A FT A FT Reset value A FT D D R 15:0 VOLT_REG High Voltage mode. Determines the voltage fed to the buffers by an 0 external voltage regulator. 0 - Buffers supplied with 3.3V Vdd 1 - Buffers supplied with 1.8V Vdd These bits function as the output of the host controller and are fed to an external voltage regulator. The voltage regulator must switch the voltage of the buffers of a particular card to either 3.3V or 1.8V, depending on the value programmed in the register. VOLT_REG[0] should be set to 1 for card number 0 in order to make it operate for 1.8V. DDR mode. Determines the voltage fed to the buffers by an 0 external voltage regulator. 0 - Non-DDR mode 1 - DDR mode UHS_REG [16] should be set for card number 0, UHS_REG [17] for card number 1 and so on. A FT D R A 31:16 DDR_REG 18.6.30 Hardware Reset (RST_N) Table 254. Hardware Reset (RST_N, address 0x4000 4078) bit description Bit Symbol Description Reset value 15:0 CARD_RESET Hardware reset. 1 1 - Active mode 0 - Reset These bits cause the cards to enter pre-idle state, which requires them to be re-initialized. CARD_RESET[0] should be set to 1 to reset card number 0, and CARD_RESET[15] should be set to reset card number 15. The number of bits implemented is restricted to NUM_CARDS. Reserved 31:16 - 18.6.31 Bus Mode Register (BMOD) Table 255. Bus Mode Register (BMOD, address 0x4000 4080) bit description Bit Symbol Value Description Reset value 0 1 SWR FB Software Reset. When set, the DMA Controller resets all its internal registers. SWR 0 is read/write. It is automatically cleared after 1 clock cycle. Fixed Burst. Controls whether the AHB Master interface performs fixed burst transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations. FB is read/write. 0 6:2 DSL Descriptor Skip Length. Specifies the number of HWord/Word/Dword (depending 0 on 16/32/64-bit bus) to skip between two unchained descriptors. This is applicable only for dual buffer structure. DSL is read/write. IDMAC Enable. When set, the IDMAC is enabled. DE is read/write. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. 7 DE User manual Rev. 00.13 — 20 July 2011 317 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 18: LPC18xx SD/MMC interface FT D R A D R A R A FT D R FT Table 255. Bus Mode Register (BMOD, address 0x4000 4080) bit description Bit Symbol Value Description D R R A FT D R R A F D R A Reset value A FT A 10:8 PBL Programmable Burst Length. These bits indicate the maximum number of beats to 0 be performed in one IDMAC transaction. The IDMAC will always attempt to burst as specified in PBL each time it starts a Burst transfer on the host bus. The permissible values are 1, 4, 8, 16, 32, 64, 128 and 256. This value is the mirror of MSIZE of FIFOTH register. In order to change this value, write the required value to FIFOTH register. This is an encode value as follows.Transfer unit is either 16, 32, or 64 bits, based on HDATA_WIDTH. PBL is a read-only value. 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 1 transfer 4 transfers 8 transfers 16 transfers 32 transfers 64 transfers 128 transfers 256 transfers Reserved FT D R A FT D R A FT D 31:11 - 18.6.32 Poll Demand Register (PLDMND) Table 256. Poll Demand Register (PLDMND, address 0x4000 4084) bit description Bit Symbol Description Reset value 31:0 PD Poll Demand. If the OWN bit of a descriptor is not set, the FSM goes to the Suspend state. The host needs to write any value into this register for the IDMAC FSM to resume normal descriptor fetch operation. This is a write only register. PD bit is write-only. 18.6.33 Descriptor List Base Address Register (DBADDR) Table 257. Descriptor List Base Address Register (DBADDR, address 0x4000 4088) bit description Bit Symbol Description Reset value 31:0 SDL Start of Descriptor List. Contains the base address of the First Descriptor. The LSB bits [0/1/2:0] for 16/32/64-bit bus-width) are ignored and taken as all-zero by the IDMAC internally. Hence these LSB bits are read-only. 0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 318 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 18: LPC18xx SD/MMC interface FT D R A D R A R A FT D R FT 18.6.34 Internal DMAC Status Register (IDSTS) Bit Symbol Description D R Table 258. Internal DMAC Status Register (IDSTS, address 0x4000 408C) bit description Reset value R A FT D R R A F D R A FT D A FT D R A FT 0 1 2 TI RI FBE Transmit Interrupt. Indicates that data transmission is finished for a descriptor. Writing a 1 clears this bit. Receive Interrupt. Indicates the completion of data reception for a descriptor. Writing a 1 clears this bit. Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS[12:10]). When this bit is set, the DMA disables all its bus accesses. Writing a 1 clears this bit. Reserved 0 0 0 A FT D R A 3 4 DU Descriptor Unavailable Interrupt. This bit is set when the descriptor 0 is unavailable due to OWN bit = 0 (DES0[31] =0). Writing a 1 clears this bit. Card Error Summary. Indicates the status of the transaction to/from 0 the card; also present in RINTSTS. Indicates the logical OR of the following bits: EBE - End Bit Error RTO - Response Time-out/Boot Ack Time-out RCRC - Response CRC SBE - Start Bit Error DRTO Data Read Time-out/BDS time-out DCRC - Data CRC for Receive RE - Response Error Writing a 1 clears this bit. Reserved Normal Interrupt Summary. Logical OR of the following: IDSTS[0] - 0 Transmit Interrupt IDSTS[1] - Receive Interrupt Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes NIS to be set is cleared. Writing a 1 clears this bit. Abnormal Interrupt Summary. Logical OR of the following: IDSTS[2] 0 - Fatal Bus Interrupt IDSTS[4] - DU bit Interrupt IDSTS[5] - Card Error Summary Interrupt Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared. Writing a 1 clears this bit. Error Bits. Indicates the type of error that caused a Bus Error. Valid 0 only with Fatal Bus Error bit (IDSTS[2]) set. This field does not generate an interrupt. 001 - Host Abort received during transmission 010 - Host Abort received during reception Others: Reserved EB is read-only. DMAC FSM present state. 0 - DMA_IDLE 1 - DMA_SUSPEND 2 - DESC_RD 3 - DESC_CHK 4 - DMA_RD_REQ_WAIT 5 - DMA_WR_REQ_WAIT 6 - DMA_RD 7 - DMA_WR 8 - DESC_CLOSE This bit is read-only. Reserved 0 5 CES 7:6 8 NIS 9 AIS 12:10 EB 16:13 FSM 31:16 - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 319 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 18: LPC18xx SD/MMC interface FT D R A 18.6.35 Internal DMAC Interrupt Enable Register (IDINTEN) Table 259. Internal DMAC Interrupt Enable Register (IDINTEN, address 0x4000 4090) bit description D R A R A FT D R FT D R R A FT D R R A F D R A FT A FT A FT Bit Symbol Description Reset value D D R A FT 0 TI Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit Interrupt is enabled. When reset, Transmit Interrupt is disabled. Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive Interrupt is enabled. When reset, Receive Interrupt is disabled. Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the Fatal Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is disabled. Reserved Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary Enable, the DU interrupt is enabled. 0 D R A 1 RI 0 2 FBE 0 3 4 DU 0 5 7:6 8 CES NIS Card Error summary Interrupt Enable. When set, it enables 0 the Card Interrupt summary. Reserved Normal Interrupt Summary Enable. When set, a normal interrupt is enabled. When reset, a normal interrupt is disabled. This bit enables the following bits: IDINTEN[0] Transmit Interrupt IDINTEN[1] - Receive Interrupt Abnormal Interrupt Summary Enable. When set, an abnormal interrupt is enabled. This bit enables the following bits: IDINTEN[2] - Fatal Bus Error Interrupt IDINTEN[4] - DU Interrupt IDINTEN[5] - Card Error Summary Interrupt Reserved 0 9 AIS 0 31:10 - 18.6.36 Current Host Descriptor Address Register (DSCADDR) Table 260. Current Host Descriptor Address Register (DSCADDR, address 0x4000 4094) bit description Bit Symbol Description Reset value 31:0 HDA Host Descriptor Address Pointer. Cleared on reset. Pointer 0 updated by IDMAC during operation. This register points to the start address of the current descriptor read by the IDMAC. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 320 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 18: LPC18xx SD/MMC interface FT D R A 18.6.37 Current Buffer Descriptor Address Register (BUFADDR) Table 261. Current Buffer Descriptor Address Register (BUFADDR, address 0x4000 4098) bit description D R A R A FT D R FT D R R A FT D R R A F D R A FT A FT A FT Bit Symbol Description Reset value D D R A FT 31:0 HBA Host Buffer Address Pointer. Cleared on Reset. Pointer updated 0 by IDMAC during operation. This register points to the current Data Buffer Address being accessed by the IDMAC. D R A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 321 of 1164 D R A FT D R A FT D R A FT D R A FT D R A FT UM10430 Rev. 00.13 — 20 July 2011 D D Chapter 19: LPC18xx External Memory Controller (EMC) D R R A FT D R A FT D R A FT D R A FT D A FT D R D R A FT D A FT R A R A FT D R A FT D R A F R A FT D FT R User manual 19.1 How to read this chapter The EMC is available on all LPC18xx parts. The reset value of the EMCSTATICWAITRD0 register varies with the part revision: D D R A FT D R A • LPC1850/30/20/10 Rev ‘A’: Reset value of the EMCSTATICWAITRD0 register is 0x0000 000E. • LPC1850/30/20/10 Rev ‘-’: Reset value of the EMCSTATICWAITRD0 register is 0x0000 0007. For LPC1850/30/20/10 Rev ‘A’ only: The EMC supports a CCLK clock which is half of the frequency of the BASE_M3_CLK. The EMC divided clock must be configured for half-frequency clock operation in both the CREG6 register (Table 37) and the CCU1 CLK_EMCDIV_CFG register (Table 84). 19.2 Basic configuration The External Memory Controller is configured as follows: • See Table 262 for clocking and power control. • If the EMC CCLK is using the divided clock, the CLK_M3_EMC_DIV branch clock must be configured for half-frequency clock operation in both the CREG6 register (Table 37) and the CCU1 CLK_EMCDIV_CFG register (Table 84). • The EMC is reset by the EMC_RST (reset # 21). • Delay value for address, data, and command lines can be programmed through registers in the SCU block. (See Section 19.4.4 to Section 19.4.12.) Table 262. EMC clocking and power control Base clock Branch clock Maximum frequency Notes EMC registers EMC CCLK BASE_M3_CLK BASE_M3_CLK CLK_M3_EMC CLK_M3_EMC_DIV 120 MHz 120 MHz This is the CCLK clock for the EMC timing. 19.3 Features • Dynamic chip selects each support up to 256 MB of data. • Dynamic memory interface support including Single Data Rate SDRAM. • Asynchronous static memory device support including RAM, ROM, and NOR Flash, with or without asynchronous page mode. • Low transaction latency. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 322 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 19: LPC18xx External Memory Controller (EMC) FT D R A • • • • Read and write buffers to reduce latency and to improve performance. 8-bit, 16-bit, and 32-bit wide static memory support. 16-bit and 32-bit wide chip select SDRAM memory support. Static memory features include: – Asynchronous page mode read – Programmable wait states – Bus turnaround delay – Output enable and write enable delays – Extended wait • Four chip selects for synchronous memory and four chip selects for static memory devices. • Power-saving modes dynamically control EMC_CKE and EMC_CLK to SDRAMs. • Dynamic memory self-refresh mode controlled by software. • Controller supports 2 kbit, 4 kbit, and 8 kbit row address synchronous memory parts. That is typical 512 MB, 256 MB, and 128 MB parts, with 4, 8, 16, or 32 data bits per device. • Separate reset domains allow the for auto-refresh through a chip reset if desired. • Programmable delay elements allow fine-tuning EMC timing. Remark: Synchronous static memory devices (synchronous burst mode) are not supported. D R A R A FT D R FT D R R A FT D R R A F D R A FT A FT A FT D R A D FT D R A 19.4 General description The LPC18xx External Memory Controller (EMC) is an ARM PrimeCell MultiPort Memory Controller peripheral offering support for asynchronous static memory devices such as RAM, ROM and Flash, as well as dynamic memories such as Single Data Rate SDRAM. The EMC is an Advanced Microcontroller Bus Architecture (AMBA) compliant peripheral. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 323 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 19: LPC18xx External Memory Controller (EMC) FT D R R A D R A R A FT D R FT D R A R A FT FT D D A F EMC R EXTBUS_A[23:0] EXTBUS_D[31:0] EXTBUS_WE shared signals R A FT D R A FT D A FT D R A EXTBUS_OE PAD INTERFACE AHB SLAVE REGISTER INTERFACE AHB Bus DATA BUFFERS EXTBUS_BLS[3:0] EXTBUS_CS[3:0] static memory signals AHB SLAVE MEMORY INTERFACE MEMORY CONTROLLER STATE MACHINE EXTBUS_DYCS[3:0] EXTBUS_CAS EXTBUS_RAS EXTBUS_CLK[3:0] EXTBUS_CKEOUT[3:0] EXTBUS_DQMOUT[3:0] dynamic memory signals Fig 29. EMC block diagram 19.5 Memory bank select Eight independently-configurable memory chip selects are supported: • Pins EMC_CS3 to EMC_CS0 are used to select static memory devices. • Pins EMC_DYCS3 to EMC_DYCS0 are used to select dynamic memory devices. Static memory chip select ranges are each 16 Megabytes in size, while dynamic memory chip selects cover a range of 256 megabytes each. Table 263 shows the address ranges of the chip selects. Table 263. Memory bank selection Chip select pin Address range Memory type Size of range EMC_CS0 EMC_CS1 EMC_CS2 EMC_CS3 EMC_DYCS0 EMC_DYCS1 EMC_DYCS2 EMC_DYCS3 0x1C00 0000 - 0x1CFF FFFF 0x1D00 0000 - 01DFF FFFF 0x1E00 0000 - 0x1EFF FFFF 0x1F00 0000 - 0x1FFF FFFF 0x2800 0000 - 0x2FFF FFFF 0x3000 0000 - 0x3FFF FFFF 0x6000 0000 - 0x6FFF FFFF 0x7000 0000 - 0x7FFF FFFF Static Static Static Static Dynamic Dynamic Dynamic Dynamic 16 MB 16 MB 16 MB 16 MB 128 MB 256 MB 256 MB 256 MB All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 324 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 19: LPC18xx External Memory Controller (EMC) FT D R A D R A R A FT D R FT 19.6 Pin description Table 264. EMC pin description Function pinned out Direction Description D R R A FT D R R A F D R A FT A FT A FT D R D EMC_A[22:0] EMC_D[31:0] EMC_BLS[3:0] EMC_CS[3:0] EMC_OE EMC_WE EMC_CKEOUT[3:0] EMC_CLK[3:0] EMC_DQMOUT[3:0] EMC_DYCS[3:0] EMC_CAS EMC_RAS O I/O O O O O O O O O O O Address bus Data bus Byte lane select Static RAM memory bank select Output enable Write enable SDRAM clock enable signals SDRAM clock signals Data mask output to SDRAM memory banks SDRAM memory bank select Column address strobe Row address strobe A FT D R A 19.7 Register description This chapter describes the EMC registers and provides details required when programming the microcontroller. The EMC registers are shown in Table 265. Reset value reflects the data stored in used bits only. It does not include the content of reserved bits. Table 265. Register overview: External memory controller (base address 0x4000 5000) Name Access Address Description offset Reset value CONTROL STATUS CONFIG DYNAMICCONTROL DYNAMICREFRESH DYNAMICREADCONFIG DYNAMICRP DYNAMICRAS DYNAMICSREX DYNAMICAPR DYNAMICDAL DYNAMICWR DYNAMICRC DYNAMICRFC R/W RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0x000 0x004 0x008 0x00C 0x01C 0x020 0x024 0x028 0x02C 0x030 0x034 0x038 0x03C 0x040 0x044 0x048 0x04C Controls operation of the memory controller. Provides EMC status information. Configures operation of the memory controller. Reserved. Controls dynamic memory operation. Configures dynamic memory refresh operation. Configures the dynamic memory read strategy. Reserved. Selects the precharge command period. Selects the active to precharge command period. Selects the self-refresh exit time. Selects the last-data-out to active command time. Selects the data-in to active command time. Selects the write recovery time. Selects the active to active command period. Selects the auto-refresh period. 0x0000 0003[1] 0x0000 0005 0x0 0x0000 0006 0x0 0x0 0x0000 000F 0x0000 000F 0x0000 000F 0x0000 000F 0x0000 000F 0x0000 000F 0x0000 001F 0x0000 001F © NXP B.V. 2011. All rights reserved. All information provided in this document is subject to legal disclaimers. User manual Rev. 00.13 — 20 July 2011 325 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 19: LPC18xx External Memory Controller (EMC) FT D Table 265. Register overview: External memory controller (base address 0x4000 5000) …continued Name Access Address Description offset D R A R A FT D R R R A FT D R A R A FT Reset value A F FT D D R A R A DYNAMICXSR DYNAMICRRD DYNAMICMRD STATICEXTENDEDWAIT DYNAMICCONFIG0 DYNAMICRASCAS0 DYNAMICCONFIG1 DYNAMICRASCAS1 DYNAMICCONFIG2 DYNAMICRASCAS2 DYNAMICCONFIG3 DYNAMICRASCAS3 STATICCONFIG0 STATICWAITWEN0 STATICWAITOEN0 STATICWAITRD0 STATICWAITPAGE0 STATICWAITWR0 STATICWAITTURN0 STATICCONFIG1 STATICWAITWEN1 R/W R/W R/W R/W R/W R/W R/W R/W 0x050 0x054 0x058 0x05C 0x07C 0x080 0x100 0x104 0x108 0x11C Selects the exit self-refresh to active command time. Selects the active bank A to active bank B latency. Selects the load mode register to active command time. Reserved. Selects time for long static memory read and write transfers. Reserved. Selects the configuration information for dynamic memory chip select 0. Selects the RAS and CAS latencies for dynamic memory chip select 0. Reserved. Selects the configuration information for dynamic memory chip select 1. Selects the RAS and CAS latencies for dynamic memory chip select 1. Reserved. Selects the configuration information for dynamic memory chip select 2. Selects the RAS and CAS latencies for dynamic memory chip select 2. Reserved. Selects the configuration information for dynamic memory chip select 3. Selects the RAS and CAS latencies for dynamic memory chip select 3. Reserved. Selects the memory configuration for static chip select 0. Selects the delay from chip select 0 to write enable. Selects the delay from chip select 0 or address change, whichever is later, to output enable. Selects the delay from chip select 0 to a read access. Selects the delay for asynchronous page mode sequential accesses for chip select 0. Selects the delay from chip select 0 to a write access. 0x0000 001F 0x0000 000F 0x0000 000F 0x0 0x0 0x0000 0303 0x0 0x0000 0303 0x0 0x0000 0303 0x0 0x0000 0303 0x0 0x0 0x0 0x0000 0007 0x0000 001F 0x0000 001F FT D A FT D R A FT D R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0x120 0x124 0x128 0x13C 0x140 0x144 0x148 0x15C 0x160 0x164 0x168 0x1FC 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x220 0x224 Selects the number of bus turnaround cycles for chip select 0x0000 000F 0. Selects the memory configuration for static chip select 1. Selects the delay from chip select 1 to write enable. 0x0 0x0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 326 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 19: LPC18xx External Memory Controller (EMC) FT D Table 265. Register overview: External memory controller (base address 0x4000 5000) …continued Name Access Address Description offset D R A R A FT D R R R A FT D R A R A FT Reset value A F FT D D R A R A STATICWAITOEN1 STATICWAITRD1 STATICWAITPAGE1 STATICWAITWR1 STATICWAITTURN1 STATICCONFIG2 STATICWAITWEN2 STATICWAITOEN2 STATICWAITRD2 STATICWAITPAGE2 STATICWAITWR2 STATICWAITTURN2 STATICCONFIG3 STATICWAITWEN3 STATICWAITOEN3 STATICWAITRD3 STATICWAITPAGE3 STATICWAITWR3 STATICWAITTURN3 [1] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0x228 0x22C 0x230 0x234 0x238 0x23C 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 Selects the delay from chip select 1 or address change, whichever is later, to output enable. Selects the delay from chip select 1 to a read access. Selects the delay for asynchronous page mode sequential accesses for chip select 1. Selects the delay from chip select 1 to a write access. 0x0 FT D R A FT D R A 0x0000 001F 0x0000 001F 0x0000 001F Selects the number of bus turnaround cycles for chip select 0x0000 000F 1. Reserved. Selects the memory configuration for static chip select 2. Selects the delay from chip select 2 to write enable. Selects the delay from chip select 2 or address change, whichever is later, to output enable. Selects the delay from chip select 2 to a read access. Selects the delay for asynchronous page mode sequential accesses for chip select 2. Selects the delay from chip select 2 to a write access. 0x0 0x0 0x0 0x0000 001F 0x0000 001F 0x0000 001F Selects the number of bus turnaround cycles for chip select 0x0000 000F 2. Reserved. Selects the memory configuration for static chip select 3. Selects the delay from chip select 3 to write enable. Selects the delay from chip select 3 or address change, whichever is later, to output enable. Selects the delay from chip select 3 to a read access. Selects the delay for asynchronous page mode sequential accesses for chip select 3. Selects the delay from chip select 3 to a write access. 0x0 0x0 0x0 0x0000 001F 0x0000 001F 0x0000 001F Selects the number of bus turnaround cycles for chip select 0x0000 000F 3. FT D The reset value after warm reset for the CONTROL register is 0x0000 0001. 19.7.1 EMC Control register The Control register is a read/write register that controls operation of the memory controller. The control bits can be altered during normal operation. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 327 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 19: LPC18xx External Memory Controller (EMC) FT D R R A Table 266. EMC Control register (CONTROL - address 0x4000 5000) bit description D R A R A FT D R FT D R A R A FT A FT F Bit Symbol Value Description Reset value D D R R A A 0 E EMC Enable. Indicates if the EMC is enabled or 1 disabled.Disabling the EMC reduces power consumption. When the memory controller is disabled the memory is not refreshed. The memory controller is enabled by setting the enable bit, or by reset. This bit must only be modified when the EMC is in idle state.[1] 0 1 Disabled Enabled (POR and warm reset value). Address mirror. Indicates normal or reset memory map. On POR, 1 CS1 is mirrored to both CS0 and DYCS0 memory areas. Clearing the M bit enables CS0 and DYCS0 memory to be accessed. 0 1 Normal memory map. Reset memory map. Static memory CS1 is mirrored onto CS0 and DYCS0 (POR reset value). Low-power mode. Indicates normal, or low-power mode. 0 Entering low-power mode reduces memory controller power consumption. Dynamic memory is refreshed as necessary. The memory controller returns to normal functional mode by clearing the low-power mode bit (L), or by POR. This bit must only be modified when the EMC is in idle state.[1] 0 1 Normal mode (warm reset value). Low-power mode. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - FT D R A FT D R A FT D 1 M 2 L 31:3 [1] - - The external memory cannot be accessed in low-power or disabled state. If a memory access is performed an AHB error response is generated. The EMC registers can be programmed in low-power and/or disabled state. 19.7.2 EMC Status register The read-only Status register provides EMC status information. Table 267. EMC Status register (STATUS - address 0x4000 5008) bit description Bit Symbol Value Description Reset value 0 B Busy. 1 This bit is used to ensure that the memory controller enters the low-power or disabled mode cleanly by determining if the memory controller is busy or not: 0 1 EMC is idle (warm reset value). EMC is busy performing memory transactions, commands, auto-refresh cycles, or is in self-refresh mode (POR reset value). Write buffer status. This bit enables the EMC to enter low-power mode or disabled mode cleanly: 0 1 Write buffers empty (POR reset value) Write buffers contain data. © NXP B.V. 2011. All rights reserved. 1 S 0 All information provided in this document is subject to legal disclaimers. User manual Rev. 00.13 — 20 July 2011 328 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 19: LPC18xx External Memory Controller (EMC) FT D Table 267. EMC Status register (STATUS - address 0x4000 5008) bit description Bit Symbol Value Description D R A R A FT D R R R A FT D R A R A A FT Reset value FT D R A F D R A 2 SA 0 1 Self-refresh acknowledge. This bit indicates the operating mode of the EMC: Normal mode Self-refresh mode (POR reset value). Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 1 FT D R A FT D R A FT D 31:3 - - - 19.7.3 EMC Configuration register The Config register configures the operation of the memory controller. It is recommended that this register is modified during system initialization, or when there are no current or outstanding transactions. This can be ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode. This register is accessed with one wait state. Table 268. EMC Configuration register (CONFIG - address 0x4000 5008) bit description Bit Symbol Value Description Reset value 0 EM 0 1 Endian mode. Little-endian mode (POR reset value). Big-endian mode. On power-on reset, the value of the endian bit is 0. All data must be flushed in the EMC before switching between little-endian and big-endian modes. 0 7:1 8 CR - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Clock Ratio. CCLK: CLKOUT[1:0] ratio: 1:1 (POR reset value) 1:2 This bit must contain 0 for proper operation of the EMC. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0 0 1 31:9 - - 19.7.4 Dynamic Memory Control register The DynamicControl register controls dynamic memory operation. The control bits can be altered during normal operation. Table 269. Dynamic Control register (DYNAMICCONTROL - address 0x4000 5020) bit description Bit Symbol Value Description Reset value 0 CE 0 1 Dynamic memory clock enable. Clock enable of idle devices are deasserted to save power (POR reset value). All clock enables are driven HIGH continuously.[1] 0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 329 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 19: LPC18xx External Memory Controller (EMC) FT D R R A Table 269. Dynamic Control register (DYNAMICCONTROL - address 0x4000 5020) bit description D R A R A FT D R FT D R A R A FT A F FT Bit Symbol Value Description Reset value D D R R A A FT FT 1 CS Dynamic memory clock control. When clock control is LOW the 1 output clock CLKOUT is stopped when there are no SDRAM transactions. The clock is also stopped during self-refresh mode. 0 1 CLKOUT stops when all SDRAMs are idle and during self-refresh mode. CLKOUT runs continuously (POR reset value). Self-refresh request, EMCSREFREQ. By writing 1 to this bit self-refresh can be entered under software control. Writing 0 to this bit returns the EMC to normal mode. The self-refresh acknowledge bit in the Status register must be polled to discover the current operating mode of the EMC.[2] 0 1 Normal mode. Enter self-refresh mode (POR reset value). Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Memory clock control. 0 1 CLKOUT enabled (POR reset value). CLKOUT disabled.[3] Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. SDRAM initialization. 0x0 0x1 0x2 0x3 Issue SDRAM NORMAL operation command (POR reset value). Issue SDRAM MODE command. Issue SDRAM PALL (precharge all) command. Issue SDRAM NOP (no operation) command) Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Low-power SDRAM deep-sleep mode. 0 1 Normal operation (POR reset value). Enter Deep-sleep mode. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0 - D D R A FT D R A 2 SR 1 4:3 5 MMC - 0 6 8:7 I - 00 12:9 13 DP - 31:14 [1] [2] [3] - Clock enable must be HIGH during SDRAM initialization. The memory controller exits from power-on reset with the self-refresh bit HIGH. To enter normal functional mode set this bit LOW. Disabling CLKOUT can be performed if there are no SDRAM memory transactions. When enabled this bit can be used in conjunction with the dynamic memory clock control (CS) field. Remark: Deep-sleep mode can be entered by setting the deep-sleep mode (DP) bit, the dynamic memory clock enable bit (CE), and the dynamic clock control bit (CS) to one. The device is then put into a low-power mode where the device is powered down and no longer refreshed. All data in the memory is lost. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 330 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 19: LPC18xx External Memory Controller (EMC) FT D R A D R A R A FT D R FT 19.7.5 Dynamic Memory Refresh Timer register D R The DynamicRefresh register configures dynamic memory operation. It is recommended that this register is modified during system initialization, or when there are no current or outstanding transactions. This can be ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode. However, these control bits can, if necessary, be altered during normal operation. This register is accessed with one wait state. Note: This register is used for all four dynamic memory chip selects. Therefore the worst case value for all of the chip selects must be programmed. Table 270. Dynamic Memory Refresh Timer register (DYNAMICREFRESH - address 0x4000 5024) bit description Bit Symbol Description R A FT D R R A F D R A FT D A FT D R A A FT R A Reset value FT D 10:0 REFRESH Refresh timer. 0 Indicates the multiple of 16 CCLKs between SDRAM refresh cycles. 0x0 = Refresh disabled (POR reset value). 0x1 - 0x7FF = n x16 = 16n CCLKs between SDRAM refresh cycles. For example: 0x1 = 1 x 16 = 16 CCLKs between SDRAM refresh cycles. 0x8 = 8 x 16 = 128 CCLKs between SDRAM refresh cycles 31:11 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - For example, for the refresh period of 16 µs, and a CCLK frequency of 50 MHz, the following value must be programmed into this register: (16 x 10-6 x 50 x 106) / 16 = 50 or 0x32 If auto-refresh through warm reset is requested (by setting the EMC_Reset_Disable bit), the timing of auto-refresh must be adjusted to allow a sufficient refresh rate when the clock rate is reduced during the wake-up period of a reset cycle. During this period, the EMC (and all other portions of the chip that are being clocked) run from the IRC oscillator at 12 MHz. The IRC oscillator frequency must be used as the CCLK rate for refresh calculations if auto-refresh through warm reset is requested. Note: The refresh cycles are evenly distributed. However, there might be slight variations when the auto-refresh command is issued depending on the status of the memory controller. 19.7.6 Dynamic Memory Read Configuration register The DynamicReadConfig register configures the dynamic memory read strategy. This register must only be modified during system initialization. This register is accessed with one wait state. Note: This register is used for all four dynamic memory chip selects. Therefore the worst case value for all of the chip selects must be programmed. Important: It should be highlighted that the default clock delay methodology requires the output clock to be delayed externally to the chip to avoid hold time issue for the SDRAM. In most application boards, there will be no such external delay circuit and the application should write correct value to the DynamicReadConfig register to use Command Delay Strategy. The Clock Delay Strategy is the default setting on reset! All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 331 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 19: LPC18xx External Memory Controller (EMC) FT D R R A See Section 19.4.4 to Section 19.4.12 for programming delay value for address, data, and command lines. R A A FT D R A FT Table 271. Dynamic Memory Read Configuration register (DYNAMICREADCONFIG - address 0x4000 5028) bit description D R A R A FT D R FT D R A F R A FT D D FT R D Bit Symbol Value Description Reset value A FT D R 1:0 RD 0x0 0x1 0x2 0x3 Read data strategy. Clock out delayed strategy, using CLKOUT (command not delayed, clock out delayed). POR reset value. Command delayed strategy, using CCLKDELAY (command delayed, clock out not delayed). Command delayed strategy plus one clock cycle, using CCLKDELAY (command delayed, clock out not delayed). Command delayed strategy plus two clock cycles, using CCLKDELAY (command delayed, clock out not delayed). 0x0 A 31:2 - - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 19.7.7 Dynamic Memory Precharge Command Period register The DynamicTRP register enables you to program the precharge command period, tRP. This register must only be modified during system initialization. This value is normally found in SDRAM data sheets as tRP. This register is accessed with one wait state. Note: This register is used for all four dynamic memory chip selects. Therefore the worst case value for all of the chip selects must be programmed. Table 272. Dynamic Memory Precharge Command Period register (DYNAMICRP - address 0x4000 5030) bit description Bit Symbol Description Reset value 3:0 tRP Precharge command period. 0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles. 0xF = 16 clock cycles (POR reset value). Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0xF 31:4 - - 19.7.8 Dynamic Memory Active to Precharge Command Period register The DynamicTRAS register enables you to program the active to precharge command period, tRAS. It is recommended that this register is modified during system initialization, or when there are no current or outstanding transactions. This can be ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode. This value is normally found in SDRAM data sheets as tRAS. This register is accessed with one wait state. Note: This register is used for all four dynamic memory chip selects. Therefore the worst case value for all of the chip selects must be programmed. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 332 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 19: LPC18xx External Memory Controller (EMC) FT D R R A Table 273. Dynamic Memory Active to Precharge Command Period register (DYNAMICRAS address 0x4000 5034) bit description D R A R A FT D R FT D R A R A A FT D F FT D Bit Symbol Description Reset value R R A A FT D FT 3:0 tRAS Active to precharge command period. 0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles. 0xF = 16 clock cycles (POR reset value). Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0xF D R A FT D R A 31:4 - - 19.7.9 Dynamic Memory Self Refresh Exit Time register The DynamicTSREX register enables you to program the self-refresh exit time, tSREX. It is recommended that this register is modified during system initialization, or when there are no current or outstanding transactions. This can be ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode. This value is normally found in SDRAM data sheets as tSREX, for devices without this parameter you use the same value as tXSR. This register is accessed with one wait state. Note: This register is used for all four dynamic memory chip selects. Therefore the worst case value for all of the chip selects must be programmed. Table 274. Dynamic Memory Self Refresh Exit Time register (DYNAMICSREX - address 0x4000 5038) bit description Bit Symbol Description Reset value 3:0 tSREX Self-refresh exit time. 0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles. 0xF = 16 clock cycles (POR reset value). Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0xF 31:4 - - 19.7.10 Dynamic Memory Last Data Out to Active Time register The DynamicTAPR register enables you to program the last-data-out to active command time, tAPR. It is recommended that this register is modified during system initialization, or when there are no current or outstanding transactions. This can be ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode. This value is normally found in SDRAM data sheets as tAPR. This register is accessed with one wait state. Note: This register is used for all four dynamic memory chip selects. Therefore the worst case value for all of the chip selects must be programmed. Table 275. Dynamic Memory Last Data Out to Active Time register (DYNAMICAPR - address 0x4000 503C) bit description Bit Symbol Description Reset value 3:0 tAPR Last-data-out to active command time. 0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles. 0xF = 16 clock cycles (POR reset value). Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. All information provided in this document is subject to legal disclaimers. 0xF 31:4 - - © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 333 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 19: LPC18xx External Memory Controller (EMC) FT D R A 19.7.11 Dynamic Memory Data In to Active Command Time register The DynamicTDAL register enables you to program the data-in to active command time, tDAL. It is recommended that this register is modified during system initialization, or when there are no current or outstanding transactions. This can be ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode. This value is normally found in SDRAM data sheets as tDAL, or tAPW. This register is accessed with one wait state. Note: This register is used for all four dynamic memory chip selects. Therefore the worst case value for all of the chip selects must be programmed. Table 276. Dynamic Memory Data In to Active Command Time register (DYNAMICDAL address 0x4000 5040) bit description Bit Symbol Description Reset value D R A R A FT D R FT D R R A FT D R R A F D R A FT D FT D R A A FT R A A FT D 3:0 tDAL Data-in to active command. 0x0 - 0xE = n clock cycles. The delay is in CCLK cycles. 0xF = 15 clock cycles (POR reset value). Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0xF 31:4 - - 19.7.12 Dynamic Memory Write Recovery Time register The DynamicTWR register enables you to program the write recovery time, tWR. It is recommended that this register is modified during system initialization, or when there are no current or outstanding transactions. This can be ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode. This value is normally found in SDRAM data sheets as tWR, tDPL, tRWL, or tRDL. This register is accessed with one wait state. Note: This register is used for all four dynamic memory chip selects. Therefore the worst case value for all of the chip selects must be programmed. Table 277. Dynamic Memory Write Recovery Time register (DYNAMICWR - address 0x4000 5044) bit description Bit Symbol Description Reset value 3:0 tWR Write recovery time. 0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles. 0xF = 16 clock cycles (POR reset value). Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0xF 31:4 - - 19.7.13 Dynamic Memory Active to Active Command Period register The DynamicTRC register enables you to program the active to active command period, tRC. It is recommended that this register is modified during system initialization, or when there are no current or outstanding transactions. This can be ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode. This value is normally found in SDRAM data sheets as tRC. This register is accessed with one wait state. Note: This register is used for all four dynamic memory chip selects. Therefore the worst case value for all of the chip selects must be programmed. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 334 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 19: LPC18xx External Memory Controller (EMC) FT D R R A Table 278. Dynamic Memory Active to Active Command Period register (DYNAMICRC address 0x4000 5048) bit description D R A R A FT D R FT D R A R A FT D A F FT D Bit Symbol Description Reset value R R A A FT D FT 4:0 tRC Active to active command period. 0x0 - 0x1E = n + 1 clock cycles. The delay is in CCLK cycles. 0x1F = 32 clock cycles (POR reset value). Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0x1F D R A FT D R A 31:5 - - 19.7.14 Dynamic Memory Auto-refresh Period register The DynamicTRFC register enables you to program the auto-refresh period, and auto-refresh to active command period, tRFC. It is recommended that this register is modified during system initialization, or when there are no current or outstanding transactions. This can be ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode. This value is normally found in SDRAM data sheets as tRFC, or sometimes as tRC. This register is accessed with one wait state. Note: This register is used for all four dynamic memory chip selects. Therefore the worst case value for all of the chip selects must be programmed. Table 279. Dynamic Memory Auto Refresh Period register (DYNAMICRFC - address 0x4000 504C) bit description Bit Symbol Description Reset value 4:0 tRFC Auto-refresh period and auto-refresh to active command period. 0x0 - 0x1E = n + 1 clock cycles. The delay is in CCLK cycles. 0x1F = 32 clock cycles (POR reset value). Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0x1F 31:5 - - 19.7.15 Dynamic Memory Exit Self Refresh register The DynamicTXSR register enables you to program the exit self-refresh to active command time, tXSR. It is recommended that this register is modified during system initialization, or when there are no current or outstanding transactions. This can be ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode. This value is normally found in SDRAM data sheets as tXSR. This register is accessed with one wait state. Note: This register is used for all four dynamic memory chip selects. Therefore the worst case value for all of the chip selects must be programmed. Table 280. Dynamic Memory Exit Self Refresh register (DYNAMICXSR - address 0x4000 5050) bit description Bit Symbol Description Reset value 4:0 tXSR Exit self-refresh to active command time. 0x0 - 0x1E = n + 1 clock cycles. The delay is in CCLK cycles. 0x1F = 32 clock cycles (POR reset value). Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. All information provided in this document is subject to legal disclaimers. 0x1F 31:5 - - © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 335 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 19: LPC18xx External Memory Controller (EMC) FT D R R A 19.7.16 Dynamic Memory Active Bank A to Active Bank B Time register A FT D The DynamicTRRD register enables you to program the active bank A to active bank B latency, tRRD. It is recommended that this register is modified during system initialization, or when there are no current or outstanding transactions. This can be ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode. This value is normally found in SDRAM data sheets as tRRD. This register is accessed with one wait state. Note: This register is used for all four dynamic memory chip selects. Therefore the worst case value for all of the chip selects must be programmed. Table 281. Dynamic Memory Active Bank A to Active Bank B Time register (DYNAMICRRD address 0x4000 5054) bit description Bit Symbol Description Reset value D R A R A FT D R FT D R A F R D A FT D FT D R A R A FT R A A FT D R 3:0 tRRD Active bank A to active bank B latency 0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles. 0xF = 16 clock cycles (POR reset value). Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0xF 31:4 - - 19.7.17 Dynamic Memory Load Mode register to Active Command Time The DynamicTMRD register enables you to program the load mode register to active command time, tMRD. It is recommended that this register is modified during system initialization, or when there are no current or outstanding transactions. This can be ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode. This value is normally found in SDRAM data sheets as tMRD, or tRSA. This register is accessed with one wait state. Note: This register is used for all four dynamic memory chip selects. Therefore the worst case value for all of the chip selects must be programmed. Table 282. Dynamic Memory Load Mode register to Active Command Time (DYNAMICMRD address 0x4000 5058) bit description Bit Symbol Description Reset value 3:0 tMRD Load mode register to active command time. 0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles. 0xF = 16 clock cycles (POR reset value). Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0xF 31:4 - - 19.7.18 Static Memory Extended Wait register ExtendedWait (EW) bit in the StaticConfig register is set. It is recommended that this register is modified during system initialization, or when there are no current or outstanding transactions. However, if necessary, these control bits can be altered during normal operation. This register is accessed with one wait state. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 336 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 19: LPC18xx External Memory Controller (EMC) FT D R R A Table 283. Static Memory Extended Wait register (STATICEXTENDEDWAIT - address 0x4000 5080) bit description D R A R A FT D R FT D R A R A FT D A F FT D Bit Symbol Description Reset value R R A A FT D FT 9:0 EXTENDEDWAIT Extended wait time out. 16 clock cycles (POR reset value). The delay is in CCLK cycles. 0x0 = 16 clock cycles. 0x1 - 0x3FF = (n+1) x16 clock cycles. 0x0 D R A FT D R A 31:10 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. For example, for a static memory read/write transfer time of 16 µs, and a CCLK frequency of 50 MHz, the following value must be programmed into this register: (16 x 10-6 x 50 x 106) / 16 - 1 = 49 19.7.19 Dynamic Memory Configuration registers The DynamicConfig registers enable you to program the configuration information for the relevant dynamic memory chip select. These registers are normally only modified during system initialization. These registers are accessed with one wait state. Table 284. Dynamic Memory Configuration registers (DYNAMICCONFIG, address 0x4000 5100 (DYNAMICCONFIG0), 0x4000 5120 (DYNAMICCONFIG1), 0x4000 5140 (DYNAMICCONFIG2), 0x4000 5160 (DYNAMICCONFIG3)) bit description Bit Symbol Value Description Reset value 2:0 4:3 MD - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Memory device. 00 SDRAM (POR reset value). Low-power SDRAM. Reserved. Reserved. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Address mapping. See Table 285. 000000 = reset value.[1] 0 0x0 0x1 0x2 0x3 6:5 12:7 13 14 AM0 AM1 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Address mapping See Table 285. 0 = reset value. 0 18:15 19 B Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Buffer enable. Buffer disabled for accesses to this chip select (POR reset value). Buffer enabled for accesses to this chip select. After configuration of the dynamic memory, the buffer must be enabled for normal operation. [2] © NXP B.V. 2011. All rights reserved. 0 1 All information provided in this document is subject to legal disclaimers. User manual Rev. 00.13 — 20 July 2011 337 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 19: LPC18xx External Memory Controller (EMC) FT D R R A Table 284. Dynamic Memory Configuration registers (DYNAMICCONFIG, address 0x4000 5100 (DYNAMICCONFIG0), 0x4000 5120 (DYNAMICCONFIG1), 0x4000 5140 (DYNAMICCONFIG2), 0x4000 5160 (DYNAMICCONFIG3)) bit description D R A R A FT D R FT D R A R A FT D R A FT A F FT D R A FT Bit Symbol Value Description Reset value D D R A FT 20 P 0 1 Write protect. Writes not protected (POR reset value). Writes protected. 0 D R A 31:21 [1] [2] - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. The SDRAM column and row width and number of banks are computed automatically from the address mapping. The buffers must be disabled during SDRAM and SyncFlash initialization. They must also be disabled when performing SyncFlash commands. The buffers must be enabled during normal operation. Address mappings that are not shown in Table 285 are reserved. Table 285. Address mapping 14 12 11:9 8:7 Description 16 bit external bus high-performance address mapping (Row, Bank, Column) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 000 000 001 001 010 010 011 011 100 100 000 000 001 001 010 010 011 011 100 100 000 000 001 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 16 Mb (2Mx8), 2 banks, row length = 11, column length = 9 16 Mb (1Mx16), 2 banks, row length = 11, column length = 8 64 Mb (8Mx8), 4 banks, row length = 12, column length = 9 64 Mb (4Mx16), 4 banks, row length = 12, column length = 8 128 Mb (16Mx8), 4 banks, row length = 12, column length = 10 128 Mb (8Mx16), 4 banks, row length = 12, column length = 9 256 Mb (32Mx8), 4 banks, row length = 13, column length = 10 256 Mb (16Mx16), 4 banks, row length = 13, column length = 9 512 Mb (64Mx8), 4 banks, row length = 13, column length = 11 512 Mb (32Mx16), 4 banks, row length = 13, column length = 10 16 Mb (2Mx8), 2 banks, row length = 11, column length = 9 16 Mb (1Mx16), 2 banks, row length = 11, column length = 8 64 Mb (8Mx8), 4 banks, row length = 12, column length = 9 64 Mb (4Mx16), 4 banks, row length = 12, column length = 8 128 Mb (16Mx8), 4 banks, row length = 12, column length = 10 128 Mb (8Mx16), 4 banks, row length = 12, column length = 9 256 Mb (32Mx8), 4 banks, row length = 13, column length = 10 256 Mb (16Mx16), 4 banks, row length = 13, column length = 9 512 Mb (64Mx8), 4 banks, row length = 13, column length = 11 512 Mb (32Mx16), 4 banks, row length = 13, column length = 10 16 Mb (2Mx8), 2 banks, row length = 11, column length = 9 16 Mb (1Mx16), 2 banks, row length = 11, column length = 8 64 Mb (8Mx8), 4 banks, row length = 12, column length = 9 © NXP B.V. 2011. All rights reserved. 16 bit external bus low-power SDRAM address mapping (Bank, Row, Column) 32 bit external bus high-performance address mapping (Row, Bank, Column) All information provided in this document is subject to legal disclaimers. User manual Rev. 00.13 — 20 July 2011 338 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 19: LPC18xx External Memory Controller (EMC) FT D R A D R A R A FT D R FT Table 285. Address mapping 14 12 11:9 8:7 Description D R R A FT D R A F D A FT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 001 001 010 010 010 011 011 011 100 100 000 000 001 001 001 010 010 010 011 011 011 100 100 01 10 00 01 10 00 01 10 00 01 00 01 00 01 10 00 01 10 00 01 10 00 01 64 Mb (4Mx16), 4 banks, row length = 12, column length = 8 64 Mb (2Mx32), 4 banks, row length = 11, column length = 8 128 Mb (16Mx8), 4 banks, row length = 12, column length = 10 128 Mb (8Mx16), 4 banks, row length = 12, column length = 9 128 Mb (4Mx32), 4 banks, row length = 12, column length = 8 256 Mb (32Mx8), 4 banks, row length = 13, column length = 10 256 Mb (16Mx16), 4 banks, row length = 13, column length = 9 256 Mb (8Mx32), 4 banks, row length = 13, column length = 8 512 Mb (64Mx8), 4 banks, row length = 13, column length = 11 512 Mb (32Mx16), 4 banks, row length = 13, column length = 10 16 Mb (2Mx8), 2 banks, row length = 11, column length = 9 16 Mb (1Mx16), 2 banks, row length = 11, column length = 8 64 Mb (8Mx8), 4 banks, row length = 12, column length = 9 64 Mb (4Mx16), 4 banks, row length = 12, column length = 8 64 Mb (2Mx32), 4 banks, row length = 11, column length = 8 128 Mb (16Mx8), 4 banks, row length = 12, column length = 10 128 Mb (8Mx16), 4 banks, row length = 12, column length = 9 128 Mb (4Mx32), 4 banks, row length = 12, column length = 8 256 Mb (32Mx8), 4 banks, row length = 13, column length = 10 256 Mb (16Mx16), 4 banks, row length = 13, column length = 9 256 Mb (8Mx32), 4 banks, row length = 13, column length = 8 512 Mb (64Mx8), 4 banks, row length = 13, column length = 11 512 Mb (32Mx16), 4 banks, row length = 13, column length = 10 R R A FT D R A FT D A FT D R A 32 bit external bus low-power SDRAM address mapping (Bank, Row, Column) A chip select can be connected to a single memory device, in this case the chip select data bus width is the same as the device width. Alternatively the chip select can be connected to a number of external devices. In this case the chip select data bus width is the sum of the memory device data bus widths. For example, for a chip select connected to: • • • • a 32-bit wide memory device, choose a 32-bit wide address mapping. a 16-bit wide memory device, choose a 16-bit wide address mapping. four x 8-bit wide memory devices, choose a 32-bit wide address mapping. two x 8-bit wide memory devices, choose a 16-bit wide address mapping. The SDRAM bank select pins BA1 and BA0 are connected to address lines A14 and A13, respectively. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 339 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 19: LPC18xx External Memory Controller (EMC) FT D R A D R A R A FT D R FT 19.7.20 Dynamic Memory RAS & CAS Delay registers D R The DynamicRasCas0:3 registers enable you to program the RAS and CAS latencies for the relevant dynamic memory. It is recommended that these registers are modified during system initialization, or when there are no current or outstanding transactions. This can be ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode. These registers are accessed with one wait state. Note: The values programmed into these registers must be consistent with the values used to initialize the SDRAM memory device. Table 286. Dynamic Memory RASCAS Delay registers (DYNAMICRASCAS, address 0x4000 5104 (DYNAMICRASCAS0), 0x4000 5124 (DYNAMICRASCAS1), 0x4000 5144 (DYNAMICRASCAS2), 0x4000 5164 (DYNAMICRASCAS3)) bit description Bit Symbol Value Description Reset value R A FT D R R A F D R A FT D FT D R A A FT R A A FT D 1:0 RAS 0x0 0x1 0x2 0x3 RAS latency (active to read/write delay). Reserved. One CCLK cycle. Two CCLK cycles. Three CCLK cycles (POR reset value). 11 7:2 9:8 CAS - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. CAS latency. 11 0x0 0x1 0x2 0x3 31:10 - Reserved. One CCLK cycle. Two CCLK cycles. Three CCLK cycles (POR reset value). Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 19.7.21 Static Memory Configuration registers The StaticConfig registers configure the static memory configuration. It is recommended that these registers are modified during system initialization, or when there are no current or outstanding transactions. This can be ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode. These registers are accessed with one wait state. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 340 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 19: LPC18xx External Memory Controller (EMC) FT D R R A Table 287. Static Memory Configuration registers (STATICCONFIG, address 0x4000 5200 (STATICCONFIG0), 0x4000 5220 (STATICCONFIG1), 0x4000 5240 (STATICCONFIG2), 0x4000 5260 (STATICCONFIG3)) bit description D R A R A FT D R FT D R A R A FT D A F FT D R R A A Bit Symbol Value Description Reset value FT D A FT D R 1:0 MW 0x0 0x1 0x2 0x3 Memory width. 8 bit (POR reset value). 16 bit. 32 bit. Reserved. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Page mode. In page mode the EMC can burst up to four external accesses. Therefore devices with asynchronous page mode burst four or higher devices are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally. 0 1 Disabled (POR reset value). Async page mode enabled (page length four). Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Chip select polarity. The value of the chip select polarity on power-on reset is 0. 0 1 Active LOW chip select. Active HIGH chip select. 0 FT D R A 2 3 PM - 0 5:4 6 PC - 0 7 PB Byte lane state. 0 The byte lane state bit, PB, enables different types of memory to be connected. For byte-wide static memories the BLSn[3:0] signal from the EMC is usually connected to WE (write enable). In this case for reads all the BLSn[3:0] bits must be HIGH. This means that the byte lane state (PB) bit must be LOW. 16 bit wide static memory devices usually have the BLSn[3:0] signals connected to the UBn and LBn (upper byte and lower byte) signals in the static memory. In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW. For reads, all the UB and LB signals must be asserted LOW so that the bus is driven. In this case the byte lane state (PB) bit must be HIGH. Remark: When PB is set to 0, the WE signal is undefined or 0. You must set PB to 1, to use the WE signal. 0 1 For reads all the bits in BLSn[3:0] are HIGH. For writes the respective active bits in BLSn[3:0] are LOW (POR reset value). For reads the respective active bits in BLSn[3:0] are LOW. For writes the respective active bits in BLSn[3:0] are LOW. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 341 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 19: LPC18xx External Memory Controller (EMC) FT D R R A Table 287. Static Memory Configuration registers (STATICCONFIG, address 0x4000 5200 (STATICCONFIG0), 0x4000 5220 (STATICCONFIG1), 0x4000 5240 (STATICCONFIG2), 0x4000 5260 (STATICCONFIG3)) bit description D R A R A FT D R FT D R A R A FT D A F FT D R R A Bit Symbol Value Description Reset value A FT D FT D R 8 EW Extended wait. Extended wait (EW) uses the StaticExtendedWait register to time both the read and write transfers rather than the StaticWaitRd and StaticWaitWr registers. This enables much longer transactions.[1] 0 1 Extended wait disabled (POR reset value). Extended wait enabled. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Buffer enable[2]. 0 1 Buffer disabled (POR reset value). Buffer enabled. Write protect. 0 1 Writes not protected (POR reset value). Write protected. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0 A FT D R A 18:9 19 B - 0 20 P 0 31:21 [1] [2] - - Extended wait and page mode cannot be selected simultaneously. EMC may perform burst read access even when the buffer enable bit is cleared. 19.7.22 Static Memory Write Enable Delay registers The StaticWaitWen registers enable you to program the delay from the chip select to the write enable. It is recommended that these registers are modified during system initialization, or when there are no current or outstanding transactions. This can be ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode. These registers are accessed with one wait state. Table 288. Static Memory Write Enable Delay registers (STATICWAITWEN, address 0x4000 5204 (STATICWAITWEN0), 0x4000 5224 (STATICWAITWEN1), 0x4000 5244 (STATICWAITWEN2), 0x4000 5264 (STATICWAITWEN3)) bit description Bit Symbol Description Reset value 3:0 WAITWEN Wait write enable. 0x0 Delay from chip select assertion to write enable. 0x0 = One CCLK cycle delay between assertion of chip select and write enable (POR reset value). 0x1 - 0xF = (n + 1) CCLK cycle delay. The delay is (WAITWEN +1) x tCCLK. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - 31:4 - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 342 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 19: LPC18xx External Memory Controller (EMC) FT D R A D R A R A FT D R FT 19.7.23 Static Memory Output Enable Delay registers D R The StaticWaitOen registers enable you to program the delay from the chip select or address change, whichever is later, to the output enable. It is recommended that these registers are modified during system initialization, or when there are no current or outstanding transactions. This can be ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode. These registers are accessed with one wait state. Table 289. Static Memory Output Enable delay registers (STATICWAITOEN, address 0x4000 5208 (STATICWAITOEN0), 0x4000 5228 (STATICWAITOEN1), 0x4000 5248 (STATICWAITOEN2), 0x4000 5268 (STATICWAITOEN3)) bit description Bit Symbol Description Reset value R A FT D R R A F D R A FT D A FT D R A A FT R A FT D 3:0 WAITOEN Wait output enable. Delay from chip select assertion to output enable. 0x0 = No delay (POR reset value). 0x1 - 0xF = n cycle delay. The delay is WAITOEN x tCCLK. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0x0 31:4 - - 19.7.24 Static Memory Read Delay registers The StaticWaitRd registers enable you to program the delay from the chip select to the read access. It is recommended that these registers are modified during system initialization, or when there are no current or outstanding transactions. This can be ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode. It is not used if the extended wait bit is enabled in the StaticConfig registers. These registers are accessed with one wait state. Table 290. Static Memory Read Delay registers (STATICWAITRD, address 0x4000 520C (STATICWAITRD0), 0x4000 522C (STATICWAITRD1), 0x4000 524C (STATICWAITRD2), 0x4000 526C (STATICWAITRD3)) bit description Bit Symbol Description Reset value 4:0 WAITRD Non-page mode read wait states or asynchronous page mode read first 0xB [1] access wait state. Non-page mode read or asynchronous page mode read, first read only: 0x0 - 0x1E = (n + 1) CCLK cycles for read accesses. For non-sequential reads, the wait state time is (WAITRD + 1) x tCCLK. 0x1F = 32 CCLK cycles for read accesses (POR reset value). Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - 31:5 [1] - The reset value is 0x0B for the STATICWAITRD0 register only. 19.7.25 Static Memory Page Mode Read Delay registers The StaticWaitPage registers enable you to program the delay for asynchronous page mode sequential accesses. It is recommended that these registers are modified during system initialization, or when there are no current or outstanding transactions. This can be ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode. This register is accessed with one wait state. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 343 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 19: LPC18xx External Memory Controller (EMC) FT D R R A Table 291. Static Memory Page Mode Read Delay registers (STATICWAITPAGE, address 0x4000 5210 (STATICWAITPAGE0), 0x4000 5230 (STATICWAITPAGE1), 0x4000 5250 (STATICWAITPAGE2), 0x4000 5270 (STATICWAITPAGE3)) bit description D R A R A FT D R FT D R A R A FT D A F FT D R R A A FT FT Bit Symbol Description Reset value D D R A FT 4:0 WAITPAGE Asynchronous page mode read after the first read wait states. 0x1F Number of wait states for asynchronous page mode read accesses after the first read: 0x0 - 0x1E = (n+ 1) CCLK cycle read access time. For asynchronous page mode read for sequential reads, the wait state time for page mode accesses after the first read is (WAITPAGE + 1) x tCCLK. 0x1F = 32 CCLK cycle read access time (POR reset value). Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. D R A 31:5 19.7.26 Static Memory Write Delay registers The StaticWaitWr registers enable you to program the delay from the chip select to the write access. It is recommended that these registers are modified during system initialization, or when there are no current or outstanding transactions. This can be ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode.These registers are not used if the extended wait (EW) bit is enabled in the StaticConfig register. These registers are accessed with one wait state. Table 292. Static Memory Write Delay registers (STATICWAITWR, address 0x4000 5214 (STATICWAITWR0), 0x4000 5234 (STATICWAITWR1), 0x4000 5254 (STATICWAITWR2), 0x4000 5274 (STATICWAITWR3)) bit description Bit Symbol Description Reset value 4:0 WAITWR Write wait states. 0x1F SRAM wait state time for write accesses after the first read: 0x0 - 0x1E = (n + 2) CCLK cycle write access time. The wait state time for write accesses after the first read is WAITWR (n + 2) x tCCLK. 0x1F = 33 CCLK cycle write access time (POR reset value). Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - 31:5 - 19.7.27 Static Memory Turn Round Delay registers The StaticWaitTurn registers enable you to program the number of bus turnaround cycles. It is recommended that these registers are modified during system initialization, or when there are no current or outstanding transactions. This can be ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode. These registers are accessed with one wait state. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 344 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 19: LPC18xx External Memory Controller (EMC) FT D R R A Table 293. Static Memory Turn Round Delay registers (STATICWAITTURN, address 0x4000 5218 (STATICWAITTURN0), 0x4000 5238 (STATICWAITTURN1), 0x4000 5258 (STATICWAITTURN2), 0x4000 5278 (STATICWAITTURN3)) bit description D R A R A FT D R FT D R A R A FT D R A FT A F FT D R A FT Bit Symbol Description Reset value D D R A FT 3:0 WAITTURN Bus turnaround cycles. 0x0 - 0xE = (n + 1) CCLK turnaround cycles. Bus turnaround time is (WAITTURN + 1) x tCCLK. 0xF = 16 CCLK turnaround cycles (POR reset value). Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0xF D R A 31:4 - To prevent bus contention on the external memory data bus, the WAITTURN field controls the number of bus turnaround cycles added between static memory read and write accesses. The WAITTURN field also controls the number of turnaround cycles between static memory and dynamic memory accesses. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 345 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 19: LPC18xx External Memory Controller (EMC) FT D R A D R A R A FT D R FT 19.8 Functional description Figure 30 shows a block diagram of the EMC. D R R A FT D R R A F D R A FT A FT A FT D R A D FT EMC D EXTBUS_A[23:0] EXTBUS_D[31:0] EXTBUS_WE shared signals R A EXTBUS_OE PAD INTERFACE AHB SLAVE REGISTER INTERFACE AHB Bus DATA BUFFERS EXTBUS_BLS[3:0] EXTBUS_CS[3:0] static memory signals AHB SLAVE MEMORY INTERFACE MEMORY CONTROLLER STATE MACHINE EXTBUS_DYCS[3:0] EXTBUS_CAS EXTBUS_RAS EXTBUS_CLK[3:0] EXTBUS_CKEOUT[3:0] EXTBUS_DQMOUT[3:0] dynamic memory signals Fig 30. EMC block diagram The functions of the EMC blocks are described in the following sections: • • • • • AHB slave register interface. AHB slave memory interfaces. Data buffers. Memory controller state machine. Pad interface. Note: For 32 bit wide chip selects data is transferred to and from dynamic memory in SDRAM bursts of four. For 16 bit wide chip selects SDRAM bursts of eight are used. 19.8.1 AHB slave register interface The AHB slave register interface block enables the registers of the EMC to be programmed. This module also contains most of the registers and performs the majority of the register address decoding. To eliminate the possibility of endianness problems, all data transfers to and from the registers of the EMC must be 32 bits wide. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 346 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 19: LPC18xx External Memory Controller (EMC) FT D R R A Note: If an access is attempted with a size other than a word (32 bits), it causes an ERROR response to the AHB bus and the transfer is terminated. A FT D D R A R A FT D R FT D R A F R D A R A FT R A 19.8.2 AHB slave memory interface The AHB slave memory interface allows access to external memories. FT D R A FT D FT D 19.8.2.1 Memory transaction endianness The endianness of the data transfers to and from the external memories is determined by the Endian mode (N) bit in the Config register. Note: The memory controller must be idle (see the busy field of the Status Register) before endianness is changed, so that the data is transferred correctly. R A 19.8.2.2 Memory transaction size Memory transactions can be 8, 16, or 32 bits wide. Any access attempted with a size greater than a word (32 bits) causes an ERROR response to the AHB bus and the transfer is terminated. 19.8.2.3 Write protected memory areas Write transactions to write-protected memory areas generate an ERROR response to the AHB bus and the transfer is terminated. 19.8.3 Pad interface The pad interface block provides the interface to the pads. The pad interface uses one feedback clock per lane, FBCLKIN[3:0], from the CLKOUT[3:0] outputs of the EMC to resynchronize SDRAM read data from the off-chip to on-chip domains. The EMC dynamic memory requires 2 CLKOUT signals for 16-bit memory and 4 CLKOUT signals for 32-bit memory. 19.8.4 Data buffers The AHB interface reads and writes via buffers to improve memory bandwidth and reduce transaction latency. The EMC contains four 16-word buffers. The buffers can be used as read buffers, write buffers, or a combination of both. The buffers are allocated automatically. The buffers must be disabled during SDRAM and SyncFlash initialization. They must also be disabled when performing SyncFlash commands. The buffers must be enabled during normal operation. The buffers can be enabled or disabled for static memory using the StaticConfig Registers. 19.8.4.1 Write buffers Write buffers are used to: • Merge write transactions so that the number of external transactions are minimized. Buffer data until the EMC can complete the write transaction, improving AHB write latency. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 347 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 19: LPC18xx External Memory Controller (EMC) FT D R R A Convert all dynamic memory write transactions into quadword bursts on the external memory interface. This enhances transfer efficiency for dynamic memory. R A • Reduce external memory traffic. This improves memory bandwidth and reduces power consumption. Write buffer operation: (LRU) buffer, if empty. • If the buffers are enabled, an AHB write operation writes into the Least Recently Used If the LRU buffer is not empty, the contents of the buffer are flushed to memory to make space for the AHB write data. • If a buffer contains write data it is marked as dirty, and its contents are written to memory before the buffer can be reallocated. The write buffers are flushed whenever: • The memory controller state machine is not busy performing accesses to external memory. The memory controller state machine is not busy performing accesses to external memory, and an AHB interface is writing to a different buffer. Note: For dynamic memory, the smallest buffer flush is a quadword of data. For static memory, the smallest buffer flush is a byte of data. D R A R A FT D R FT D R A A FT D R A R A FT F FT D R A FT D FT D D R A 19.8.4.2 Read buffers Read buffers are used to: • Buffer read requests from memory. Future read requests that hit the buffer read the data from the buffer rather than memory, reducing transaction latency. Convert all read transactions into quadword bursts on the external memory interface. This enhances transfer efficiency for dynamic memory. • Reduce external memory traffic. This improves memory bandwidth and reduces power consumption. Read buffer operation: • If the buffers are enabled and the read data is contained in one of the buffers, the read data is provided directly from the buffer. • If the read data is not contained in a buffer, the LRU buffer is selected. If the buffer is dirty (contains write data), the write data is flushed to memory. When an empty buffer is available the read command is posted to the memory. A buffer filled by performing a read from memory is marked as not-dirty (not containing write data) and its contents are not flushed back to the memory controller unless a subsequent AHB transfer performs a write that hits the buffer. 19.9 Low-power operation In many systems, the contents of the memory system have to be maintained during low-power sleep modes. The EMC provides a mechanism to place the dynamic memories into self-refresh mode. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 348 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 19: LPC18xx External Memory Controller (EMC) FT D R R A Self-refresh mode can be entered by software by setting the SREFREQ bit in the DynamicControl Register and polling the SREFACK bit in the Status Register. A Any transactions to memory that are generated while the memory controller is in self-refresh mode are rejected and an error response is generated to the AHB bus. Clearing the SREFREQ bit in the DynamicControl Register returns the memory to normal operation. See the memory data sheet for refresh requirements. Note: The static memory can be accessed as normal when the SDRAM memory is in self-refresh mode. A FT D D R A R A FT D R FT D R A F R A FT D R R A FT D R A FT D FT D R A 19.9.1 Low-power SDRAM Deep-sleep Mode The EMC supports JEDEC low-power SDRAM deep-sleep mode. Deep-sleep mode can be entered by setting the deep-sleep mode (DP) bit, the dynamic memory clock enable bit (CE), and the dynamic clock control bit (CS) in the DynamicControl register. The device is then put into a low-power mode where the device is powered down and no longer refreshed. All data in the memory is lost. 19.9.2 Low-power SDRAM partial array refresh The EMC supports JEDEC low-power SDRAM partial array refresh. Partial array refresh can be programmed by initializing the SDRAM memory device appropriately. When the memory device is put into self-refresh mode only the memory banks specified are refreshed. The memory banks that are not refreshed lose their data contents. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 349 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 19: LPC18xx External Memory Controller (EMC) FT D R A D R A R A FT D R FT 19.10 External static memory interface D R External memory interfacing depends on the bank width (32, 16 or 8 bit selected via MW bits in corresponding StaticConfig register). R A FT D If a memory bank is configured to be 32 bits wide, address lines A0 and A1 can be used as non-address lines. If a memory bank is configured to 16 bits wide, A0 is not required. However, 8 bit wide memory banks do require all address lines down to A0. Configuring A1 and/or A0 line(s) to provide address or non-address function is accomplished using the SYSCON registers. Symbol "a_b" in the following figures refers to the highest order address line in the data bus. Symbol "a_m" refers to the highest order address line of the memory chip used in the external memory interface. If the external memory is used as external boot memory for flashless devices, refer to Section 3.2 on how to connect the EMC. The memory bank width for memory banks 1 and 2 is determined by the setting of the BOOT pins. R A FT D R A F D R A FT D A FT D R A R A FT 19.10.1 32-bit wide memory bank connection CS OE CE OE WE IO[7:0] A[a_m:0] CE OE WE IO[7:0] A[a_m:0] CE OE WE IO[7:0] A[a_m:0] CE OE WE IO[7:0] A[a_m:0] BLS[3] D[31:24] A[a_b:2] BLS[2] D[23:16] BLS[1] D[15:8] BLS[0] D[7:0] a. 32 bit wide memory bank interfaced to four 8 bit memory chips CS OE WE CE OE WE UB LB IO[15:0] A[a_m:0] CE OE WE UB LB IO[15:0] A[a_m:0] BLS[3] BLS[2] D[31:16] BLS[1] BLS[0] D[15:0] A[a_b:2] b. 32 bit wide memory bank interfaced to two 16 bit memory chips All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 350 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 19: LPC18xx External Memory Controller (EMC) FT D R R A D R A R A FT D R FT D R A R A FT FT A F CS OE WE CE OE WE B3 B2 B1 B0 IO[31:0] A[a_m:0] D D R A FT D R A FT D A FT D R A R BLS[3] BLS[2] BLS[1] BLS[0] D[31:0] A[a_b:2] c. 32 bit wide memory bank interfaced to one 8 bit memory chip Fig 31. 32 bit bank external memory interfaces ( bits MW = 10) 19.10.2 16-bit wide memory bank connection CS OE CE OE WE IO[7:0] A[a_m:0] CE OE WE IO[7:0] A[a_m:0] BLS[1] D[15:8] A[a_b:1] BLS[0] D[7:0] a. 16 bit wide memory bank interfaced to two 8 bit memory chips CS OE WE CE OE WE UB LB IO[15:0] A[a_m:0] BLS[1] BLS[0] D[15:0] A[a_b:1] b. 16 bit wide memory bank interfaced to a 16 bit memory chip Fig 32. 16 bit bank external memory interfaces (bits MW = 01) All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 351 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 19: LPC18xx External Memory Controller (EMC) FT D R A D R A R A FT D R FT 19.10.3 8-bit wide memory bank connection CS OE CE OE WE D[7:0] A[a_b:0] WE IO[7:0] A[a_m:0] D R R A FT D R R A F D R A FT A FT A FT D R A D FT D R A Fig 33. 8 bit bank external memory interface (bits MW = 00) All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 352 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 19: LPC18xx External Memory Controller (EMC) FT D R A D R A R A FT D R FT 19.10.4 Memory configuration example A[20:0] D[31:0] D R R A FT D R R A F D R A FT A FT A FT A[20:0] CS0 OE A[20:0] nCE nOE Q[31:0] D[31:0] D D R A FT D 2Mx32 Burst Mask ROM A[15:0] D[31:16] R A A[15:0] CS1 IO[15:0] nCE nOE WE nWE nUB nLB A[15:0] D[15:0] A[15:0] nCE nOE nWE nUB nLB IO[15:0] 64Kx16 SRAM, two off A[16:0] D[31:24] A[16:0] CS2 IO[7:0] nCE nOE BLS3 A[16:0] nWE D[23:16] A[16:0] nCE nOE BLS2 A[16:0] IO[7:0] nWE D[15:8] A[16:0] nCE nOE BLS1 A[16:0] IO[7:0] nWE D[7:0] A[16:0] nCE nOE BLS0 IO[7:0] nWE 128Kx8 SRAM, four off Fig 34. Typical memory configuration diagram All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 353 of 1164 D R A FT D R A FT D R A FT D R A FT D R A FT UM10430 Rev. 00.13 — 20 July 2011 D D Chapter 20: LPC18xx USB0 Host/Device/OTG controller D R R A FT D R A D R A FT D R A FT D A FT D R D R A FT FT D A FT R A R A FT D R A FT D R A F R A FT D FT R User manual 20.1 How to read this chapter D D R A FT D The USB0 Host/Device/OTG controller is available on parts LPC1850, LPC1830, and LPC1820. R A 20.2 Basic configuration The USB0 Host/Device/OTG controller is configured as follows: • See Table 294 for clocking and power control. • The USB0 is reset by the USB0_RST (reset # 17). • The USB0 is connected to interrupt slot # 8 in the NVIC, and the is connected to slot # 9 in the Event router. Table 294. USB0 clocking and power control Base clock Branch clock Maximum frequency Notes USB0 clock BASE_USB0_CLK CLK_USB0 480 MHz Uses PLL0 dedicated to USB0. CLK_USB0 must be 480 MHz clock for the USB0 to operate in all three modes (low-speed, full-speed, and high-speed modes). Uses PLL1. USB0 register interface clock BASE_M3_CLK CLK_M3_USB0 150 MHz 20.3 Features • • • • • • • • • • • • Complies with Universal Serial Bus specification 2.0. Complies with USB On-The-Go supplement. Complies with Enhanced Host Controller Interface Specification. Complies with AMBA specification. Supports auto USB 2.0 mode discovery. Supports all high-speed USB-compliant peripherals. Supports all full-speed USB-compliant peripherals. Supports all low-speed USB-compliant peripherals. Supports software HNP and SRP for OTG peripherals. Contains UTMI+ compliant transceiver (PHY). Supports power management. Supports six endpoints, control endpoint included. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 354 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R A D R A R A FT D R FT 20.4 Introduction D R Universal Serial Bus (USB) is a standard protocol developed to connect several types of devices to each other in order to exchange data or for other purposes. Many portable devices can benefit from the ability to communicate to each other over the USB interface without intervention of a host PC. The addition of the On-The-Go functionality to USB makes this possible without losing the benefits of the standard USB protocol. Examples of USB devices are: PC, mouse, keyboard, MP3 player, digital camera, USB storage device (USB stick). R A FT D R A FT D R A F D R A FT D FT D R A R A A FT 20.4.1 Block diagram ARM Cortex-M3 SYSTEM MEMORY AHB master TX-BUFFER (DUAL-PORT RAM) slave USB 2.0 HIGH-SPEED OTG RX-BUFFER (DUAL-PORT RAM) USB bus Fig 35. High-speed USB OTG block diagram 20.4.2 About USB On-The-Go The USB On-The-Go block enables usage in both device mode and in host mode. This means that you can connect to a PC to exchange data, but also to another USB device such as a digital camera or MP3 player. 20.4.3 USB acronyms and abbreviations Table 295. USB related acronyms Acronym Description ATX DCD dQH dTD EOP EP FS HCD Analog Transceiver Device Controller Driver device Endpoint Queue Head device Transfer Descriptor End Of Packet End Point Full Speed Host Controller Driver All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 355 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R A D R A R A FT D R FT Table 295. USB related acronyms Acronym Description D R R A FT D R A F D A FT HS LS MPS NAK OTG PID QH SE0 SOF TT USB High Speed Low Speed Maximum Packet Size Negative Acknowledge On-The-Go Packet Identifier Queue Head Single Ended 0 Start Of Frame Transaction Translator Universal Serial Bus R R A FT D R A FT D A FT D R A 20.4.4 Transmit and receive buffers The USB OTG controller contains a Tx buffer to store data to be transmitted on the USB and an Rx buffer to store data received from the USB. The Rx buffer contains 256 words, and the Tx buffer contains 128 words for each endpoint in device mode and 512 words in host mode. 20.4.5 Fixed endpoint configuration Table 296 shows the supported endpoint configurations. The Maximum Packet Size (MPS) (see Table 297) is dependent on the type of endpoint and the device configuration (low-speed, full-speed, or high-speed). Table 296. Fixed endpoint configuration Logical endpoint Physical endpoint Endpoint type Direction 0 0 1 1 2 2 3 3 4 4 5 5 0 1 2 3 4 5 6 7 8 9 10 11 Control Control Interrupt/Bulk/Isochronous Interrupt/Bulk/Isochronous Interrupt/Bulk/Isochronous Interrupt/Bulk/Isochronous Interrupt/Bulk/Isochronous Interrupt/Bulk/Isochronous Interrupt/Bulk/Isochronous Interrupt/Bulk/Isochronous Interrupt/Bulk/Isochronous Interrupt/Bulk/Isochronous Out In Out In Out In Out In Out In Out In All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 356 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R A D R A R A FT D R FT D Table 297. USB Packet size Endpoint type Speed R Packet size (byte) R A FT D R A F D A FT Control Low-speed Full-speed High-speed 8 8, 16, 32, or 64 64 n/a up to 1023 up to 1024 up to 8 up to 64 up to 1024 n/a 8, 16, 32, or 64 8, 16, 32, 64 or 512 R R A FT D R A FT D A FT Isochronous Low-speed Full-speed High-speed D R A Interrupt Low-speed Full-speed High-speed Bulk Low-speed Full-speed High-speed 20.5 Pin description Table 298. USB0 pin description Function pinned out Direction Description USB0_IND0 USB0_IND1 USB0_PWR_FAULT O O O Port indicator LED control output. Port indicator LED control output. Port power fault signal indicating overcurrent condition; this signal monitors over-current on the USB bus (external circuitry required to detect over-current condition). VBUS drive signal (towards external charge pump or power management unit); indicates that Vbus must be driven (active high). USB0 bidirectional D+ line. USB0 bidirectional D line. VBUS pin (power on USB cable). Indicates to the transceiver whether connected a A-device (ID LOW) or B-device (ID HIGH). 12.0 kOhm (accuracy 1%) on-board resistor to ground for current reference; Separate analog power supply for driver, 3.3V. USB 3.3 V separate power supply voltage Dedicated analog ground for clean reference for termination resistors. Dedicated clean analog ground for generation of reference currents and voltages. USB0_PWR_EN O USB0_DP USB0_DM USB0_VBUS USB0_ID USB0_RREF USB0_VDDA3V3_ DRIVER USB0_VDDA3V3 USB0_VSSA_TERM USB0_VSSA_REF I/O I/O I I All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 357 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R A D R A R A FT D R FT 20.6 Register description Table 299. Register access abbreviations Abbreviation Description D R R A FT D R R A F D R A FT A FT A FT D R D R/W R/WC R/WO RO WO Read/Write Read/Write one to Clear Read/Write Once Read Only Write Only A FT D R A Table 300. Register overview: USB0 OTG controller (register base address 0x4000 6000) Name Access Address Description offset Reset value - - 0x000 0x0FF 0x100 0x104 0x108 0x120 0x124 0x128 0x13C 0x140 0x140 0x144 0x144 0x148 0x148 0x14C 0x14C 0x150 0x154 0x154 0x158 0x158 0x15C 0x160 0x164 0x168 0x170 Reserved Device/host capability registers CAPLENGTH HCSPARAMS HCCPARAMS DCIVERSION DCCPARAMS - RO RO RO RO RO - Capability register length 0x0100 0040 Host controller structural parameters 0x0001 0011 Host controller capability parameters 0x0000 0006 Device interface version number Device controller capability parameters Reserved 0x0000 0001 0x0000 0186 Device/host operational registers USBCMD_D USBCMD_H USBSTS_D USBSTS_H USBINTR_D USBINTR_H FRINDEX_D FRINDEX_H DEVICEADDR PERIODICLISTBASE ASYNCLISTADDR TTCTRL BURSTSIZE TXFILLTUNING - R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W - USB command (device mode) USB command (host mode) USB status (device mode) USB status (host mode) USB interrupt enable (device mode) USB interrupt enable (host mode) USB frame index (device mode) USB frame index (host mode) Reserved USB device address (device mode) Address of endpoint list in memory Address of endpoint list in memory Asynchronous buffer status for embedded TT (host mode) Programmable burst size Host transmit pre-buffer packet tuning (host mode) Reserved 0x0008 0000 0x0008 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 - Frame list base address (host mode) 0x0000 0000 ENDPOINTLISTADDR R/W All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 358 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R R A Table 300. Register overview: USB0 OTG controller (register base address 0x4000 6000) D R A R A FT D R FT D R A R A A Name Access Address Description offset Reset value FT D R A F FT D R A BINTERVAL ENDPTNAK ENDPTNAKEN PORTSC1_D PORTSC1_H OTGSC USBMODE_D USBMODE_H ENDPTSETUPSTAT ENDPTPRIME ENDPTFLUSH ENDPTSTAT ENDPTCOMPLETE ENDPTCTRL0 ENDPTCTRL1 ENDPTCTRL2 ENDPTCTRL3 ENDPTCTRL4 ENDPTCTRL5 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RO R/W R/W R/W R/W R/W R/W R/W 0x174 0x178 0x17C 0x180 0x184 0x184 0x188 0x1A0 0x1A4 0x1A8 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 Length of virtual frame Endpoint NAK (device mode) Reserved Port 1 status/control (device mode) Port 1 status/control (host mode) 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 FT D A FT D R A Endpoint NAK Enable (device mode) 0x0000 0000 FT D R OTG status and control USB device mode (device mode) USB device mode (host mode) Endpoint setup status Endpoint initialization Endpoint de-initialization Endpoint status Endpoint complete Endpoint control 0 Endpoint control 1 Endpoint control 2 Endpoint control 3 Endpoint control 4 Endpoint control 5 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 Device endpoint registers 20.6.1 Use of registers The register interface has bit functions described for device mode and bit functions described for host mode. However, during OTG operations it is necessary to perform tasks independent of the controller mode. The only way to transition the controller mode out of host or device mode is by setting the controller reset bit. Therefore, it is also necessary for the OTG tasks to be performed independently of a controller reset as well as independently of the controller mode. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 359 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R R A D R A R A FT D R FT D R A R A FT FT A F Hardware reset or USBCMD RST bit = 1 D D R IDLE MODE = 00 R A FT D R A FT D A write 10 to USBMODE write 11 to USBMODE FT D R A DEVICE MODE = 10 HOST MODE = 11 Fig 36. USB controller modes The following registers and register bits are used for OTG operations. The values of these register bits are independent of the controller mode and are not affected by a write to the RESET bit in the USBCMD register. • • • • All identification registers All device/host capabilities registers All bits of the OTGSC register (Section 20.6.16) The following bits of the PORTSC register (Section 20.6.15): – PTS (parallel interface select) – STS (serial transceiver select) – PTW (parallel transceiver width) – PHCD (PHY low power suspend) – WKOC, WKDC, WKCN (wake signals) – PIC[1:0] (port indicators) – PP (port power) 20.6.2 Device/host capability registers Table 301. CAPLENGTH register (CAPLENGTH - address 0x4000 6100) bit description Bit Symbol Description Reset value Access 7:0 CAPLENGTH Indicates offset to add to the register base address at the beginning of the Operational Register BCD encoding of the EHCI revision number supported by this host controller. These bits are reserved and should be set to zero. 0x40 RO 23:8 31:24 HCIVERSION - 0x100 - RO - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 360 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R R A Table 302. HCSPARAMS register (HCSPARAMS - address 0x4000 6104) bit description D R A R A FT D R FT D R A R A FT A FT F Bit Symbol Description Reset value Access D D R A R A 3:0 N_PORTS Number of downstream ports. This field specifies the number of physical downstream ports implemented on this host controller. Port Power Control. This field indicates whether the host controller implementation includes port power control. Number of Ports per Companion Controller. This field indicates the number of ports supported per internal Companion Controller. Number of Companion Controller. This field indicates the number of companion controllers associated with this USB2.0 host controller. Port indicators. This bit indicates whether the ports support port indicator control. 0x1 RO FT D R A FT FT D 4 PPC 0x1 RO D R A 7:5 11:8 N_PCC These bits are reserved and should be set to zero. 0x0 RO 15:12 N_CC 0x0 RO 16 19:17 23:20 PI N_PTT 0x1 RO RO These bits are reserved and should be set to zero. Number of Ports per Transaction Translator. This 0x0 field indicates the number of ports assigned to each transaction translator within the USB2.0 host controller. Number of Transaction Translators. This field indicates the number of embedded transaction translators associated with the USB2.0 host controller. 0x0 27:24 N_TT RO 31:28 - These bits are reserved and should be set to zero. - - Table 303. HCCPARAMS register (HCCPARAMS - address 0x4000 6108) bit description Bit Symbol Description Reset value Access 0 1 ADC PFL 64-bit Addressing Capability. If zero, no 64-bit addressing capability is supported. 0 RO RO Programmable Frame List Flag. If set to one, then the 1 system software can specify and use a smaller frame list and configure the host controller via the USBCMD register Frame List Size field. The frame list must always be aligned on a 4K-boundary. This requirement ensures that the frame list is always physically contiguous. Asynchronous Schedule Park Capability. If this bit is set to 1 a one, then the host controller supports the park feature for high-speed queue heads in the Asynchronous Schedule.The feature can be disabled or enabled and set to a specific level by using the Asynchronous Schedule Park Mode Enable and Asynchronous Schedule Park Mode Count fields in the USBCMD register. 2 ASP RO All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 361 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R R A Table 303. HCCPARAMS register (HCCPARAMS - address 0x4000 6108) bit description D R A R A FT D R FT D R A R A A Bit Symbol Description Reset value Access FT D R A F FT D R A 7:4 IST Isochronous Scheduling Threshold. This field indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule. EHCI Extended Capabilities Pointer. This optional field indicates the existence of a capabilities list. These bits are reserved and should be set to zero. 0 RO FT D R A FT D R FT D 15:8 31:9 EECP - 0 - RO - A Table 304. DCIVERSION register (DCIVERSION - address 0x4000 6120) bit description Bit Symbol Description Reset value Access 15:0 DCIVERSION The device controller interface conforms to the two-byte BCD encoding of the interface version number contained in this register. 0x1 RO Table 305. DCCPARAMS (address 0x4000 6124) Bit Symbol Description Reset value Access 4:0 6:5 7 8 31:9 DEN DC HC - Device Endpoint Number. These bits are reserved and should be set to zero. Device Capable. Host Capable. These bits are reserved and should be set to zero. 0x4 0x1 0x1 - RO RO RO - 20.6.3 USB Command register (USBCMD) The host/device controller executes the command indicated in this register. 20.6.3.1 Device mode Table 306. USB Command register in device mode (USBCMD_D - address 0x4000 6140) bit description Bit Symbol Value Description Access Reset value 0 RS 0 1 Run/Stop Writing a 0 to this bit will cause a detach event. Writing a one to this bit will cause the device controller to enable a pull-up on USB_DP and initiate an attach event. This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. Software should use this bit to prevent an attach event before the device controller has been properly initialized. R/W 0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 362 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R R A Table 306. USB Command register in device mode (USBCMD_D - address 0x4000 6140) bit description …continued D R A R A FT D R FT D R A R A A Bit Symbol Value Description Access Reset value FT D R A F FT D R A 1 RST Controller reset. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register. 0 1 Set to 0 by hardware when the reset process is complete. When software writes a one to this bit, the Device Controller resets its internal pipelines, timers, counters, state machines etc. to their initial values. Writing a one to this bit when the device is in the attached state is not recommended, since the effect on an attached host is undefined. In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0. Not used in device mode. Not used in device mode. Not used in device mode. R/W 0 FT D R A FT D R A FT D 3:2 4 5 6 7 9:8 10 11 12 13 SUTW - - 0 0 0 0 0 0 Not used in device mode. Writing a one to this bit when the device mode is selected, will have undefined results. Reserved. These bits should be set to 0. Not used in Device mode. Reserved.These bits should be set to 0. Not used in Device mode. Reserved.These bits should be set to 0. Setup trip wire During handling a setup packet, this bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. If the setup lockout mode is off (see USBMODE register) then there exists a hazard when new setup data arrives while the DCD is copying the setup data payload from the QH for a previous setup packet. This bit is set and cleared by software and will be cleared by hardware when a hazard exists. (See Section 20.10). R/W 14 ATDTW Add dTD trip wire This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoint’s linked list. This bit is set and cleared by software during the process of adding a new dTD. See also Section 20.10. This bit shall also be cleared by hardware when its state machine is hazard region for which adding a dTD to a primed endpoint may go unrecognized. R/W 0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 363 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R R A Table 306. USB Command register in device mode (USBCMD_D - address 0x4000 6140) bit description …continued D R A R A FT D R FT D R A R A A Bit Symbol Value Description Access Reset value FT D R A F FT D R A 15 23:16 ITC Not used in device mode. Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames. R/W - FT D 0x8 FT D R A FT D R A 31:24 - Reserved 0 20.6.3.2 Host mode Table 307. USB Command register in host mode (USBCMD_H - address 0x4000 6140) bit description - host mode Bit Symbol Value Description Access Reset value 0 RS 0 Run/Stop When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the Host Controller has finished the transaction and has entered the stopped state. Software should not write a one to this field unless the host controller is in the Halted state (i.e. HCHalted in the USBSTS register is a one). When set to a 1, the Host Controller proceeds with the execution of the schedule. The Host Controller continues execution as long as this bit is set to a one. R/W 0 1 1 RST Controller reset. R/W Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register. 0 1 This bit is set to zero by hardware when the reset process is complete. When software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. Attempting to reset an actively running host controller will result in undefined behavior. Bit 0 of the Frame List Size bits. See Table 308. This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. Note that this field is made up from USBCMD bits 15, 3, and 2. 0 2 FS0 0 3 FS1 Bit 1 of the Frame List Size bits. See Table 308. All information provided in this document is subject to legal disclaimers. 0 © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 364 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R R A Table 307. USB Command register in host mode (USBCMD_H - address 0x4000 6140) bit description - host mode D R A R A FT D R FT D R A R A A Bit Symbol Value Description Access Reset value FT D R A F FT D R A 4 PSE 0 1 This bit controls whether the host controller skips processing the periodic schedule. Do not process the periodic schedule. Use the PERIODICLISTBASE register to access the periodic schedule. This bit controls whether the host controller skips processing the asynchronous schedule. 0 1 Do not process the asynchronous schedule. Use the ASYNCLISTADDR to access the asynchronous schedule. This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. 0 1 The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one. Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule states, it sets the Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results. R/W 0 FT D R A FT D R A FT D 5 ASE R/W 0 6 IAA R/W 0 7 9:8 ASP1_0 - Reserved Asynchronous schedule park mode R/W Contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. Valid values are 0x1 to 0x3. Remark: Software must not write 00 to this bit when Park Mode Enable is one as this will result in undefined behavior. 0 11 10 11 ASPE 0 1 Reserved. Asynchronous Schedule Park Mode Enable Park mode is disabled. Park mode is enabled. Reserved. Not used in Host mode. Reserved. R/W 0 1 12 13 14 - - - 0 0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 365 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R R A Table 307. USB Command register in host mode (USBCMD_H - address 0x4000 6140) bit description - host mode D R A R A FT D R FT D R A R A A Bit Symbol Value Description Access Reset value FT D R A F FT D R A 15 23:16 FS2 ITC Bit 2 of the Frame List Size bits. See Table 308. Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames. R/W 0 FT D 0x8 FT D R A FT D R A 31:24 - Reserved Table 308. Frame list size values USBCMD bit 15 USBCMD bit 3 USBCMD bit 2 Frame list size 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1024 elements (4096 bytes) - default value 512 elements (2048 bytes) 256 elements (1024 bytes) 128 elements (512 bytes) 64 elements (256 bytes) 32 elements (128 bytes) 16 elements (64 bytes) 8 elements (32 bytes) 20.6.4 USB Status register (USBSTS) This register indicates various states of the Host/Device controller and any pending interrupts. Software sets a bit to zero in this register by writing a one to it. Remark: This register does not indicate status resulting from a transaction on the serial bus. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 366 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R A D R A R A FT D R FT 20.6.4.1 Device mode Bit Symbol Value Description Reset value D R Table 309. USB Status register in device mode (USBSTS_D - address 0x4000 6144) register bit description R A FT D R R A F D R A FT Access A FT A FT D R D 0 UI 0 1 USB interrupt This bit is cleared by software writing a one to it. This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes. 0 R/WC A FT D R A 1 UEI 0 1 USB error interrupt This bit is cleared by software writing a one to it. When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. The device controller detects resume signaling only (see Section 20.10.11.6). Port change detect. 0 1 This bit is cleared by software writing a one to it. The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. When the port controller exits the full or high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit (URI) and the DCSuspend bits (SLI) respectively. Not used in Device mode. Reserved. Not used in Device mode. USB reset received 0 1 This bit is cleared by software writing a one to it. When the device controller detects a USB Reset and enters the default state, this bit will be set to a one. 0 R/WC 2 PCI 0 R/WC 3 4 5 6 AAI URI 0 0 0 R/WC All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 367 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R R A Table 309. USB Status register in device mode (USBSTS_D - address 0x4000 6144) register bit description D R A R A FT D R FT D R A R A A Bit Symbol Value Description Reset value Access FT D R A F FT D R A 7 SRI 0 1 SOF received This bit is cleared by software writing a one to it. When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. Therefore, this bit will be set roughly every 1 ms in device FS mode and every 125 s in HS mode and will be synchronized to the actual SOF that is received. Since the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp. DCSuspend 0 The device controller clears the bit upon exiting from a suspend state. This bit is cleared by software writing a one to it. When a device controller enters a suspend state from an active state, this bit will be set to a one. Reserved. Software should only write 0 to reserved bits. Not used in Device mode. Not used in Device mode. Not used in Device mode. Not used in Device mode. NAK interrupt bit 0 This bit is automatically cleared by hardware when the all the enabled TX/RX Endpoint NAK bits are cleared. It is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and the corresponding TX/RX Endpoint NAK Enable bit are set. Reserved. Software should only write 0 to reserved bits. Not used in Device mode. Not used in Device mode. Reserved. Software should only write 0 to reserved bits. 0 R/WC FT D R A FT D R A FT D 8 SLI 0 R/WC 1 11:9 12 13 14 15 16 NAKI - 0 0 0 0 0 RO 1 17 18 19 31:20 - - 0 0 0 - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 368 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R A D R A R A FT D R FT 20.6.4.2 Host mode Bit Symbol Value Description D R Table 310. USB Status register in host mode (USBSTS_H - address 0x4000 6144) register bit description Reset Access value R A FT D R R A F D R A FT A FT A FT D R D 0 UI 0 1 USB interrupt (USBINT) This bit is cleared by software writing a one to it. This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes. 0 R/WC A FT D R A 1 UEI 0 1 USB error interrupt (USBERRINT) This bit is cleared by software writing a one to it. When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. Port change detect. 0 1 This bit is cleared by software writing a one to it. The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port. Frame list roll-over 0 1 This bit is cleared by software writing a one to it. The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example, if the frame list size (as programmed in the Frame List Size field of the USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX bit 13 toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX bit 12 toggles (see Section 20.6.6). Reserved. Interrupt on async advance 0 1 This bit is cleared by software writing a one to it. System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the USBCMD register. This status bit indicates the assertion of that interrupt source. Not used by the Host controller. SOF received 0 1 This bit is cleared by software writing a one to it. In host mode, this bit will be set every 125 s and can be used by host controller driver as a time base. Not used by the Host controller. Reserved. 0 R/WC 2 PCI 0 R/WC 3 FRI 0 R/WC 4 5 AAI 0 R/WC 6 7 SRI - 0 0 R/WC R/WC 8 11:9 - - - - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 369 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R R A Table 310. USB Status register in host mode (USBSTS_H - address 0x4000 6144) register bit description …continued D R A R A FT D R FT D R A R A A Bit Symbol Value Description Reset Access value FT D R A F FT D R A 12 HCH 0 1 HCHalted The RS bit in USBCMD is set to zero. Set by the host controller. The Host Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g. because of an internal error). Reclamation 0 1 No empty asynchronous schedule detected. An empty asynchronous schedule is detected. Set by the host controller. Periodic schedule status This bit reports the current real status of the Periodic Schedule. The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (if both are 1) or disabled (if both are 0). 0 1 The periodic schedule status is disabled. The periodic schedule status is enabled. Asynchronous schedule status This bit reports the current real status of the Asynchronous Schedule. The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (if both are 1) or disabled (if both are 0). 0 1 Asynchronous schedule status is disabled. Asynchronous schedule status is enabled. Not used on Host mode. Reserved. USB host asynchronous interrupt (USBHSTASYNCINT) 0 1 This bit is cleared by software writing a one to it. This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the asynchronous schedule. This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes. USB host periodic interrupt (USBHSTPERINT) 0 1 This bit is cleared by software writing a one to it. This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes. 1 RO FT D R A FT D R A FT D 13 RCL 0 RO 14 PS 0 RO 15 AS 0 16 17 18 UAI 0 0 R/WC 19 UPI 0 R/WC 31:20 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 370 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R A D R A R A FT D R FT 20.6.5 USB Interrupt register (USBINTR) D R The software interrupts are enabled with this register. An interrupt is generated when a bit is set and the corresponding interrupt is active. The USB Status register (USBSTS) still shows interrupt sources even if they are disabled by the USBINTR register, allowing polling of interrupt events by the software. All interrupts must be acknowledged by software by clearing (that is writing a 1 to) the corresponding bit in the USBSTS register. D R A FT D R A FT R A F D R A FT D FT D R A R A A FT 20.6.5.1 Device mode Table 311. USB Interrupt register in device mode (USBINTR_D - address 0x4000 6148) bit description Bit Symbol Description Reset value Access 0 UE USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS. 0 R/W 1 UEE USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register. 0 R/W 2 PCE Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS. 0 R/W 3 4 5 6 URE Not used by the Device controller. Reserved Not used by the Device controller. USB reset enable When this bit is a one, and the USB Reset Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the USB Reset Received bit. 0 R/W 0 - 7 SRE SOF received enable When this bit is a one, and the SOF Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the SOF Received bit. 0 R/W 8 SLE Sleep enable When this bit is a one, and the DCSuspend bit in the USBSTS register transitions, the device controller will issue an interrupt. The interrupt is acknowledged by software writing a one to the DCSuspend bit. 0 R/W 15:9 16 NAKE Reserved NAK interrupt enable This bit is set by software if it wants to enable the hardware interrupt for the NAK Interrupt bit. If both this bit and the corresponding NAK Interrupt bit are set, a hardware interrupt is generated. 0 R/W 17 18 19 - Reserved Not used by the Device controller. Not used by the Device controller. Reserved All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. 31:20 User manual Rev. 00.13 — 20 July 2011 371 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R A D R A R A FT D R FT 20.6.5.2 Host mode Table 312. USB Interrupt register in host mode (USBINTR_H - address 0x4000 6148) bit description Bit Symbol Description D R Access Reset value R A FT D R R A F D R A FT A FT A FT D R D 0 UE USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS. R/W 0 A FT D R A 1 UEE USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register. R/W 0 2 PCE Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS. R/W 0 3 FRE Frame list rollover enable When this bit is a one, and the Frame List Rollover bit in the USBSTS register is a one, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Frame List Rollover bit. 4 5 AAE Reserved Interrupt on asynchronous advance enable When this bit is a one, and the Interrupt on Async Advance bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the Interrupt on Async Advance bit. R/W 0 0 6 7 SRE Not used by the Host controller. - 0 0 If this bit is one and the SRI bit in the USBSTS register is one, the host controller will issue an interrupt. In host mode, the SRI bit will be set every 125 s and can be used by the host controller as a time base. The interrupt is acknowledged by software clearing the SRI bit in the USBSTS register. Not used by the Host controller. Reserved Not used by the host controller. Reserved USB host asynchronous interrupt enable When this bit is a one, and the USBHSTASYNCINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTASYNCINT bit. R/W R/W - 8 15:9 16 17 18 UAIE 0 0 0 19 UPIA USB host periodic interrupt enable When this bit is a one, and the USBHSTPERINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTPERINT bit. R/W 0 31:20 - Reserved All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 372 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R A D R A R A FT D R FT 20.6.6 Frame index register (FRINDEX) 20.6.6.1 Device mode D R In Device mode this register is read only, and the device controller updates the FRINDEX[13:3] register from the frame number indicated by the SOF marker. Whenever a SOF is received by the USB bus, FRINDEX[13:3] will be checked against the SOF marker. If FRINDEX[13:3] is different from the SOF marker, FRINDEX[13:3] will be set to the SOF value and FRINDEX[2:0] will be set to zero (i.e. SOF for 1 ms frame). If FRINDEX [13:3] is equal to the SOF value, FRINDEX[2:0] will be incremented (i.e. SOF for 125 s micro-frame) by hardware. FT D Table 313. USB frame index register in device mode (FRINDEX_D - address 0x4000 614C) bit description Bit Symbol Description Reset value Access R A FT D R R A F D R A FT D R A FT D R A A FT A 2:0 13:3 31:14 FRINDEX2_0 FRINDEX13_3 - Current micro frame number Current frame number of the last frame transmitted Reserved N/A N/A N/A RO RO 20.6.6.2 Host mode This register is used by the host controller to index the periodic frame list. The register updates every 125 s (once each micro-frame). Bits[N: 3] are used to select a particular entry in the Periodic Frame List during periodic schedule execution. The number of bits used for the index depends on the size of the frame list as set by system software in the Frame List Size field in the USBCMD register. This register must be written as a DWord. Byte writes produce undefined results. This register cannot be written unless the Host Controller is in the 'Halted' state as indicated by the HCHalted bit in the USBSTS register (host mode). A write to this register while the Run/Stop bit is set to a one produces undefined results. Writes to this register also affect the SOF value. Table 314. USB frame index register in host (FRINDEX_H - address 0x4000 614C) bit description Bit Symbol Description Reset value Access 2:0 12:3 31:13 FRINDEX2_0 FRINDEX12_3 - Current micro frame number Frame list current index. Reserved N/A N/A N/A R/W R/W Table 315. Number of bits used for the frame list index USBCMD USBCMD USBCMD Frame list size bit 15 bit 3 bit 2 N 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 1024 elements (4096 bytes). Default value. 512 elements (2048 bytes) 256 elements (1024 bytes) 128 elements (512 bytes) 64 elements (256 bytes) 12 11 10 9 8 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 373 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R A D R A R A FT D R FT Table 315. Number of bits used for the frame list index USBCMD USBCMD USBCMD Frame list size bit 15 bit 3 bit 2 D R R A N R A F A FT D R R A D FT A 1 1 1 0 1 1 1 0 1 32 elements (128 bytes) 16 elements (64 bytes) 8 elements (32 bytes) 7 6 5 FT D R A FT D R A FT D 20.6.7 Device address (DEVICEADDR - device) and Periodic List Base (PERIODICLISTBASE- host) registers 20.6.7.1 Device mode The upper seven bits of this register represent the device address. After any controller reset or a USB reset, the device address is set to the default address (0). The default address will match all incoming addresses. Software shall reprogram the address after receiving a SET_ADDRESS descriptor. The USBADRA bit is used to accelerate the SET_ADDRESS sequence by allowing the DCD to preset the USBADR register bits before the status phase of the SET_ADDRESS descriptor. Table 316. USB Device Address register in device mode (DEVICEADDR - address 0x4000 6154) bit description Bit Symbol Value Description Reset value Access 23:0 24 USBADRA 0 1 Reserved Device address advance Any write to USBADR are instantaneous. When the user writes a one to this bit at the same time or before USBADR is written, the write to USBADR fields is staged and held in a hidden register. After an IN occurs on endpoint 0 and is acknowledged, USBADR will be loaded from the holding register. Hardware will automatically clear this bit on the following conditions: 0 - • • • IN is ACKed to endpoint 0. USBADR is updated from the staging register. OUT/SETUP occurs on endpoint 0. USBADR is not updated. Device reset occurs. USBADR is set to 0. Remark: After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. This mechanism will ensure this specification is met when the DCD can not write the device address within 2 ms from the SET_ADDRESS status phase. If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), the USBADR will be programmed instantly at the correct time and meet the 2 ms USB requirement. 31:25 USBADR USB device address 0 R/W 20.6.7.2 Host mode This 32-bit register contains the beginning address of the Periodic Frame List in the system memory. The host controller driver (HCD) loads this register prior to starting the schedule execution by the Host Controller. The memory structure referenced by this All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 374 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R R A physical memory pointer is assumed to be 4 kB aligned. The contents of this register are combined with the Frame Index Register (FRINDEX) to enable the Host Controller to step through the Periodic Frame List in sequence. R A Table 317. USB Periodic List Base register in host mode (PERIODICLISTBASE - address 0x4000 6154) bit description Bit Symbol Description Reset value D R A R A FT D R FT D R A A FT D R A R A FT F FT D Access R A FT D FT D D R A 11:0 31:12 PERBASE31_12 Reserved Base Address (Low) These bits correspond to the memory address signals 31:12. - R/W 20.6.8 Endpoint List Address register (ENDPOINTLISTADDR - device) and Asynchronous List Address (ASYNCLISTADDR - host) registers 20.6.8.1 Device mode In device mode, this register contains the address of the top of the endpoint list in system memory. Bits[10:0] of this register cannot be modified by the system software and will always return a zero when read.The memory structure referenced by this physical memory pointer is assumed 64 byte aligned. Table 318. USB Endpoint List Address register in device mode (ENDPOINTLISTADDR - address 0x4000 6158) bit description Bit Symbol Description Reset value Access 10:0 31:11 EPBASE31_11 reserved Endpoint list pointer (low) These bits correspond to memory address signals 31:11, respectively. This field will reference a list of up to 4 Queue Heads (QH). (i.e. one queue head per endpoint and direction.) 0 - R/W 20.6.8.2 Host mode This 32-bit register contains the address of the next asynchronous queue head to be executed by the host. Bits [4:0] of this register cannot be modified by the system software and will always return a zero when read. Table 319. USB Asynchronous List Address register in host mode (ASYNCLISTADDR- address 0x4000 6158) bit description Bit Symbol Description Reset value Access 4:0 31:5 ASYBASE31_5 Reserved Link pointer (Low) LPL These bits correspond to memory address signals 31:5, respectively. This field may only reference a Queue Head (OH). 0 - R/W 20.6.9 TT Control register (TTCTRL) 20.6.9.1 Device mode This register is not used in device mode. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 375 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R A D R A R A FT D R FT 20.6.9.2 Host mode D R This register contains parameters needed for internal TT operations. This register is used by the host controller only. Writes must be in Dwords. FT D R A FT Table 320. USB TT Control register in host mode (TTCTRL - address 0x4000 615C) bit description Bit Symbol Description Reset value R A R A F D R A FT D R A FT D R A Access A FT D 23:0 30:24 31 TTHA - Reserved. Hub address when FS or LS device are connected directly. Reserved. 0 N/A 0 R/W 20.6.10 Burst Size register (BURSTSIZE) This register is used to control and dynamically change the burst size used during data movement on the master interface of the USB DMA controller. Writes must be in Dwords. The default for the length of a burst of 32-bit words for RX and TX DMA data transfers is 16 words each. Table 321. USB burst size register (BURSTSIZE - address 0x4000 6160) bit description - device/host mode Bit Symbol Description Reset value Access 7:0 RXPBURST Programmable RX burst length This register represents the maximum length of a burst in 32-bit words while moving data from the USB bus to system memory. 0x10 R/W 15:8 TXPBURST Programmable TX burst length This register represents the maximum length of a burst in 32-bit words while moving data from system memory to the USB bus. 0x10 R/W 31:16 - Reserved. - - 20.6.11 Transfer buffer Fill Tuning register (TXFILLTUNING) 20.6.11.1 Device controller This register is not used in device mode. 20.6.11.2 Host controller The fields in this register control performance tuning associated with how the host controller posts data to the TX latency FIFO before moving the data onto the USB bus. The specific areas of performance include the how much data to post into the FIFO and an estimate for how long that operation should take in the target system. Definitions: T0 = Standard packet overhead T1 = Time to send data payload Tff = Time to fetch packet into TX FIFO up to specified level Ts = Total packet flight time (send-only) packet; Ts = T0 + T1 Tp = Total packet time (fetch and send) packet; Tp = Tff + T0 + T1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 376 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R R A Upon discovery of a transmit (OUT/SETUP) packet in the data structures, host controller checks to ensure Tp remains before the end of the (micro) frame. If so it proceeds to pre-fill the TX FIFO. If at anytime during the pre-fill operation the time remaining the [micro]frame is < Ts then the packet attempt ceases and the packet is tried at a later time. Although this is not an error condition and the host controller will eventually recover, a mark will be made the scheduler health counter to note the occurrence of a “backoff” event. When a back-off event is detected, the partial packet fetched may need to be discarded from the latency buffer to make room for periodic traffic that will begin after the next SOF. Too many back-off events can waste bandwidth and power on the system bus and thus should be minimized (not necessarily eliminated). Backoffs can be minimized with use of the TSCHHEALTH (Tff) described below. R A Table 322. USB Transfer buffer Fill Tuning register in host mode (TXFILLTUNING - address 0x4000 6164) bit description Bit Symbol Description Reset value Access D R A R A FT D R FT D R A A FT D R A R A FT F FT D R A FT D D R A FT D 7:0 TXSCHOH FIFO burst threshold This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. The minimum value is 2 and this value should be a low as possible to maximize USB performance. A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. This value is ignored if the Stream Disable bit in USBMODE register is set. 0x2 R/W 12:8 TXSCHEATLTH Scheduler health counter This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES before running out of time to send the packet before the next Start-Of-Frame . This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. Writing to this register will clear the counter. The maximum value is 31. 0x0 R/W 15:13 21:16 TXFIFOTHRES reserved Scheduler overhead This register adds an additional fixed offset to the schedule time estimator described above as Tff. As an approximation, the value chosen for this register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. The time unit represented in this register is 1.267 s when a device is connected in High-Speed Mode for OTG and SPH. The time unit represented in this register is 6.333 s when a device is connected in Low/Full Speed Mode for OTG and SPH. 0x0 R/W 31:22 - reserved 20.6.12 BINTERVAL register This register defines the bInterval value which determines the length of the virtual frame (see Section 20.7.7). All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 377 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R A D R A R A FT D R FT D Table 323. USB BINTERVAL register (BINTERVAL - address 0x4000 6174) bit description Bit Symbol Description R Reset value R A FT D R R A F D R A Access A FT A 3:0 31:4 BINT - bInterval value (see Section 20.7.7) reserved 0x00 - R/W - FT D R A FT D R FT D 20.6.13 USB Endpoint NAK register (ENDPTNAK) 20.6.13.1 Device mode This register indicates when the device sends a NAK handshake on an endpoint. Each Tx and Rx endpoint has a bit in the EPTN and EPRN field respectively. A bit in this register is cleared by writing a 1 to it. Table 324. USB endpoint NAK register (ENDPTNAK - address 0x4000 6178) bit description Bit Symbol Description Reset value Access A 5:0 EPRN Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0. 0x00 R/WC 15:6 21:16 EPTN Reserved Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0. 0x00 R/WC 31:22 - reserved - - 20.6.13.2 Host mode This register is not used in host mode. 20.6.14 USB Endpoint NAK Enable register (ENDPTNAKEN) 20.6.14.1 Device mode Each bit in this register enables the corresponding bit in the ENDPTNAK register. Each Tx and Rx endpoint has a bit in the EPTNE and EPRNE field respectively. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 378 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D Table 325. USB Endpoint NAK Enable register (ENDPTNAKEN - address 0x4000 617C) bit description Bit Symbol Description D R A R A FT D R R Reset value A FT D R R A FT D R R A F D R A Access A FT A 5:0 EPRNE Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0. 0x00 R/W FT D R A FT D R A FT D 15:6 21:16 EPTNE Reserved Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0. 0x00 R/W 31:22 - Reserved - - 20.6.14.2 Host mode This register is not used in host mode. 20.6.15 Port Status and Control register (PORTSC1) 20.6.15.1 Device mode The device controller implements one port register, and it does not support power control. Port control in device mode is used for status port reset, suspend, and current connect status. It is also used to initiate test mode or force signaling. This register allows software to put the PHY into low-power Suspend mode and disable the PHY clock. Table 326. Port Status and Control register in device mode (PORTSC1_D - address 0x4000 6184) bit description Bit Symbol Value Description Reset value Access 0 CCS 0 Current connect status Device not attached A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or suspended. 1 Device attached. A one indicates that the device successfully attached and is operating in either high-speed mode or full-speed mode as indicated by the High Speed Port bit in this register. 0 RO 1 2 3 PE PEC - Not used in device mode Port enable. This bit is always 1. The device port is always enabled. Port enable/disable change This bit is always 0. The device port is always enabled. 0 1 0 RO RO All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 379 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R R A Table 326. Port Status and Control register in device mode (PORTSC1_D - address 0x4000 6184) bit description D R A R A FT D R FT D R A R A A Bit Symbol Value Description Reset value Access FT D R A F FT D R A 5:4 6 FPR - Reserved Force port resume After the device has been in Suspend State for 5 ms or more, software must set this bit to one to drive resume signaling before clearing. The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. The bit will be cleared when the device returns to normal operation. When this bit transitions to a one because a J-to-K transition detected, the Port Change Detect bit in the USBSTS register is set to one as well. 0 0 RO FT D R/W FT D R A FT D R A 0 1 7 SUSP 0 1 8 PR No resume (K-state) detected/driven on port. Resume detected/driven on port. Suspend In device mode, this is a read-only status bit . Port not in suspend state Port in suspend state Port reset In device mode, this is a read-only status bit. A device reset from the USB bus is also indicated in the USBSTS register. 0 RO 0 RO 0 1 9 HSP Port is not in the reset state. Port is in the reset state. High-speed status Remark: This bit is redundant with bits 27:26 (PSPD) in this register. It is implemented for compatibility reasons. 0 RO 0 1 11:10 12 13 - Host/device connected to the port is not in High-speed mode. Host/device connected to the port is in High-speed mode. Not used in device mode. Not used in device mode. Reserved Port indicator control Writing to this field effects the value of the USB0_IND[1:0] pins. 00 R/W 15:14 PIC1_0 0x0 0x1 0x2 0x3 Port indicators are off. amber green undefined All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 380 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R R A Table 326. Port Status and Control register in device mode (PORTSC1_D - address 0x4000 6184) bit description D R A R A FT D R FT D R A R A A Bit Symbol Value Description Reset value Access FT D R A F FT D R A 19:16 PTC3_0 Port test control 0000 Any value other than 0000 indicates that the port is operating in test mode. The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_HS/FS/LS values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0111 to 1111 are not valid. 0x0 0x1 0x2 0x3 0x4 0x5 0x6 TEST_MODE_DISABLE J_STATE K_STATE SE0 (host)/NAK (device) Packet FORCE_ENABLE_HS FORCE_ENABLE_FS Not used in device mode. This bit is always 0 in device mode. Not used in device mode. This bit is always 0 in device mode. Not used in device mode. This bit is always 0 in device mode. PHY low power suspend - clock disable (PLPSCD) In device mode, The PHY can be put into Low Power Suspend – Clock Disable when the device is not running (USBCMD Run/Stop = 0) or the host has signaled suspend (PORTSC SUSPEND = 1). Low power suspend will be cleared automatically when the host has signaled resume. Before forcing a resume from the device, the device controller driver must clear this bit. 0 1 Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled). Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled). Port force full speed connect 0 1 Port connects at any speed. Writing this bit to a 1 will force the port to only connect at full speed. It disables the chirp sequence that allows the port to identify itself as High-speed. This is useful for testing FS configurations with a HS host, hub or device. reserved Port speed This register field indicates the speed at which the port is operating. 0x0 0x1 0x2 Full-speed invalid in device mode High-speed Reserved 0 0 0 0 0 0 R/W FT D R A FT D R A FT D 20 21 22 23 PHCD - R/W 24 PFSC R/W 25 - - 27:26 PSPD RO 31:28 - - - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 381 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R A D R A R A FT D R FT 20.6.15.2 Host mode D R The host controller uses one port. The register is only reset when power is initially applied or in response to a controller reset. The initial conditions of the port are: FT D R A FT R A R A F D R A FT A FT • No device connected • Port disabled D If the port has power control, this state remains until software applies power to the port by setting port power to one in the PORTSC register. Table 327. Port Status and Control register in host mode (PORTSC1_H - address 0x4000 6184) bit description Bit Symbol Value Description Reset value Access D R A FT D R A 0 CCS Current connect status This value reflects the current state of the port and may not correspond directly to the event that caused the CSC bit to be set. This bit is 0 if PP (Port Power bit) is 0. Software clears this bit by writing a 1 to it. 0 1 No device is present. Device is present on the port. Connect status change Indicates a change has occurred in the port’s Current Connect Status. The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be setting an already-set bit (i.e., the bit will remain set). Software clears this bit by writing a one to it. This bit is 0 if PP (Port Power bit) is 0 0 1 No change in current status. Change in current status. Port enable. Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. When the port is disabled. downstream propagation of data is blocked except for reset. This bit is 0 if PP (Port Power bit) is 0. 0 1 Port disabled. Port enabled. 0 R/WC 1 CSC 0 R/WC 2 PE 0 R/W All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 382 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R R A Table 327. Port Status and Control register in host mode (PORTSC1_H - address 0x4000 6184) bit description D R A R A FT D R FT D R A R A A Bit Symbol Value Description Reset value Access FT D R A F FT D R A 3 PEC Port disable/enable change For the root hub, this bit gets set to a one only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). Software clears this by writing a one to it. This bit is 0 if PP (Port Power bit) is 0, 0 1 No change. Port enabled/disabled status has changed. Over-current active This bit will automatically transition from 1 to 0 when the over-current condition is removed. 0 1 The port does not have an over-current condition. The port has currently an over-current condition. Over-current change This bit gets set to one when there is a change to Over-current Active. Software clears this bit by writing a one to this bit position. 0 R/WC FT D R A FT D R A FT D 4 OCA 0 RO 5 OCC 0 R/WC 6 FPR Force port resume Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. This bit will automatically change to zero after the resume sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. The resume signaling (Full-speed K) is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. Writing a zero has no affect because the port controller will time the resume operation clear the bit the port control state switches to HS or FS idle. This bit is 0 if PP (Port Power bit) is 0. 0 1 No resume (K-state) detected/driven on port. Resume detected/driven on port. 0 R/W All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 383 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R R A Table 327. Port Status and Control register in host mode (PORTSC1_H - address 0x4000 6184) bit description D R A R A FT D R FT D R A R A A Bit Symbol Value Description Reset value Access FT D R A F FT D R A 7 SUSP Suspend Together with the PE (Port enabled bit), this bit describes the port states, see Table 328. The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. If host software sets this bit to a one when the port is not enabled (i.e. Port enabled bit is a zero) the results are undefined. This bit is 0 if PP (Port Power bit) is 0. 0 1 Port not in suspend state Port in suspend state When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. 0 R/W FT D R A FT D R A FT D 8 PR Port reset When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. This bit will automatically change to zero after the reset sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. This bit is 0 if PP (Port Power bit) is 0. 0 1 Port is not in the reset state. Port is in the reset state. High-speed status 0 1 Host/device connected to the port is not in High-speed mode. Host/device connected to the port is in High-speed mode. Line status These bits reflect the current logical levels of the USB_DP and USB_DM signal lines. USB_DP corresponds to bit 11 and USB_DM to bit 10. In host mode, the use of linestate by the host controller driver is not necessary for this controller (unlike EHCI) because the controller hardware manages the connection of LS and FS. 0x0 0x1 0x2 0x3 SE0 (USB_DP and USB_DM LOW) J-state (USB_DP HIGH and USB_DM LOW) K-state (USB_DP LOW and USB_DM HIGH) Undefined 0 R/W 9 HSP 0 RO 11:10 LS 0x3 RO All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 384 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R R A Table 327. Port Status and Control register in host mode (PORTSC1_H - address 0x4000 6184) bit description D R A R A FT D R FT D R A R A A Bit Symbol Value Description Reset value Access FT D R A F FT D R A 12 PP - Port power control Host/OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). When power is not available on a port (i.e. PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitioned by the host controller driver from a one to a zero (removing power from the port). 0 R/W FT D R A FT D R A FT D 0 1 13 15:14 PIC1_0 Port power off. Port power on. Reserved Port indicator control Writing to this field effects the value of the pins USB0_IND1 and USB0_IND0. 0 00 R/W 0x0 0x1 0x2 0x3 19:16 PTC3_0 Port indicators are off. Amber Green Undefined Port test control 0000 Any value other than 0000 indicates that the port is operating in test mode. The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0x8 to 0xF are reserved. R/W 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 20 WKCN 0 1 21 WKDC 0 1 TEST_MODE_DISABLE J_STATE K_STATE SE0 (host)/NAK (device) Packet FORCE_ENABLE_HS FORCE_ENABLE_FS FORCE_ENABLE_LS Wake on connect enable (WKCNNT_E) This bit is 0 if PP (Port Power bit) is 0 Disables the port to wake up on device connects. Writing this bit to a one enables the port to be sensitive to device connects as wake-up events. Wake on disconnect enable (WKDSCNNT_E) This bit is 0 if PP (Port Power bit) is 0. Disables the port to wake up on device disconnects. Writing this bit to a one enables the port to be sensitive to device disconnects as wake-up events. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. 0 R/W 0 R/W User manual Rev. 00.13 — 20 July 2011 385 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R R A Table 327. Port Status and Control register in host mode (PORTSC1_H - address 0x4000 6184) bit description D R A R A FT D R FT D R A R A A Bit Symbol Value Description Reset value Access FT D R A F FT D R A 22 WKOC 0 1 Wake on over-current enable (WKOC_E) Disables the port to wake up on over-current events. Writing a one to this bit enabled the port to be sensitive to over-current conditions as wake-up events. PHY low power suspend - clock disable (PLPSCD) In host mode, the PHY can be put into Low Power Suspend – Clock Disable when the downstream device has been put into suspend mode or when no downstream device is connected. Low power suspend is completely under the control of software. 0 1 Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled). Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled). Port force full speed connect 0 1 Port connects at any speed. Writing this bit to a 1 will force the port to only connect at Full Speed. It disables the chirp sequence that allows the port to identify itself as High Speed. This is useful for testing FS configurations with a HS host, hub or device. Reserved Port speed This register field indicates the speed at which the port is operating. For HS mode operation in the host controller and HS/FS operation in the device controller the port routing steers data to the Protocol engine. For FS and LS mode operation in the host controller, the port routing steers data to the Protocol Engine w/ Embedded Transaction Translator. 0x0 0x1 0x2 Full-speed Low-speed High-speed Reserved 0 R/W FT D R A FT D R A FT D 23 PHCD 0 R/W 24 PFSC 0 R/W 25 - - 27:26 PSPD 0 RO 31:28 - - - Table 328. Port states as described by the PE and SUSP bits in the PORTSC1 register PE bit SUSP bit Port state 0 1 1 0 or 1 0 1 disabled enabled suspend 20.6.16 OTG Status and Control register (OTGSC) The OTG register has four sections: • • • • OTG interrupt enables (R/W) OTG Interrupt status (R/WC) OTG status inputs (RO) OTG controls (R/W) All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 386 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R R Table 329. OTG Status and Control register (OTGSC - address 0x4000 61A4) bit description Bit Symbol Value Description Reset value The status inputs are debounced using a 1 msec time constant. Values on the status inputs that do not persist for more than 1 msec will not cause an update of the status input register or cause an OTG interrupt. R A A FT D R A FT D D R A R A FT D R FT D R A F R A FT D FT D R D A FT R A Access 0 1 VD VC VBUS_Discharge Setting this bit to 1 causes VBUS to discharge through a resistor. VBUS_Charge Setting this bit to 1 causes the VBUS line to be charged. This is used for VBUS pulsing during SRP. 0 0 R/W R/W A 2 HAAR 0 1 Hardware assist auto_reset Disabled Enable automatic reset after connect on host port. OTG termination This bit must be set to 1 when the OTG controller is in device mode. This controls the pull-down on USB_DM. 0 R/W 3 OT 0 R/W 4 DP Data pulsing Setting this bit to 1 causes the pull-up on USB_DP to be asserted for data pulsing during SRP. 0 R/W 5 IDPU 0 1 ID pull-up. This bit provides control over the pull-up resistor. Pull-up off. The ID bit will not be sampled. Pull-up on. Hardware assist data pulse Write a 1 to start data pulse sequence. Hardware assist B-disconnect to A-connect 0 1 Disabled. Enable automatic B-disconnect to A-connect sequence. USB ID 0 1 A-device B-device A-VBUS valid Reading 1 indicates that VBUS is above the A-VBUS valid threshold. A-session valid Reading 1 indicates that VBUS is above the A-session valid threshold. B-session valid Reading 1 indicates that VBUS is above the B-session valid threshold. B-session end Reading 1 indicates that VBUS is below the B-session end threshold. 1 millisecond timer toggle This bit toggles once per millisecond. Data bus pulsing status Reading a 1 indicates that data bus pulsing is detected on the port. reserved All information provided in this document is subject to legal disclaimers. 1 R/W 6 7 HADP HABA 0 0 R/W R/W 8 ID 0 RO 9 10 11 12 13 14 15 AVV ASV BSV BSE MS1T DPS - 0 0 0 0 0 0 0 RO RO RO RO RO RO © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 387 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D Table 329. OTG Status and Control register (OTGSC - address 0x4000 61A4) bit description …continued Bit Symbol Value Description Reset value D R A R A FT D R R R A FT D R A R A A Access FT D R A F FT D R A 16 IDIS USB ID interrupt status This bit is set when a change on the ID input has been detected. Software must write a 1 to this bit to clear it. 0 R/WC FT D R A FT D FT D 17 AVVIS A-VBUS valid interrupt status This bit is set then VBUS has either risen above or fallen below the A-VBUS valid threshold (4.4 V on an A-device). Software must write a 1 to this bit to clear it. 0 R/WC R A 18 ASVIS A-Session valid interrupt status This bit is set then VBUS has either risen above or fallen below the A-session valid threshold (0.8 V). Software must write a 1 to this bit to clear it. 0 R/WC 19 BSVIS B-Session valid interrupt status This bit is set then VBUS has either risen above or fallen below the B-session valid threshold (0.8 V). Software must write a 1 to this bit to clear it. 0 R/WC 20 BSEIS B-Session end interrupt status This bit is set then VBUS has fallen below the B-session end threshold. Software must write a 1 to this bit to clear it. 0 R/WC 21 ms1S 1 millisecond timer interrupt status This bit is set once every millisecond. Software must write a 1 to this bit to clear it. 0 R/WC 22 DPIS Data pulse interrupt status This bit is set when data bus pulsing occurs on DP or DM. Data bus pulsing is only detected when the CM bit in USBMODE = Host (11) and the PortPower bit in PORTSC = Off (0). Software must write a 1 to this bit to clear it. 0 R/WC 23 24 25 IDIE AVVIE - reserved USB ID interrupt enable Setting this bit enables the interrupt. Writing a 0 disables the interrupt. A-VBUS valid interrupt enable Setting this bit enables the A-VBUS valid interrupt. Writing a 0 disables the interrupt. 0 0 0 R/W R/W 26 ASVIE A-session valid interrupt enable Setting this bit enables the A-session valid interrupt. Writing a 0 disables the interrupt 0 R/W 27 BSVIE B-session valid interrupt enable Setting this bit enables the B-session valid interrupt. Writing a 0 disables the interrupt. 0 R/W 28 BSEIE B-session end interrupt enable Setting this bit enables the B-session end interrupt. Writing a 0 disables the interrupt. 0 R/W All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 388 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D Table 329. OTG Status and Control register (OTGSC - address 0x4000 61A4) bit description …continued Bit Symbol Value Description Reset value D R A R A FT D R R R A FT D R A R A A Access FT D R A F FT D R A 29 MS1E 1 millisecond timer interrupt enable Setting this bit enables the 1 millisecond timer interrupt. Writing a 0 disables the interrupt. 0 R/W FT D R A FT D FT D 30 DPIE Data pulse interrupt enable Setting this bit enables the data pulse interrupt. Writing a 0 disables the interrupt 0 R/W R A 31 - - Reserved 0 - 20.6.17 USB Mode register (USBMODE) The USBMODE register sets the USB mode for the OTG controller. The possible modes are Device, Host, and Idle mode for OTG operations. 20.6.17.1 Device mode Table 330. USB Mode register in device mode (USBMODE_D - address 0x4000 61A8) bit description Bit Symbol Value Description Reset value Access 1:0 CM1_0 Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register. 0x0 0x1 0x2 0x3 Idle Reserved Device controller Host controller Endian select This bit can change the byte ordering of the transfer buffers to match the host microprocessor bus architecture. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words. 0 1 Little endian: first byte referenced in least significant byte of 32-bit word. Big endian: first byte referenced in most significant byte of 32-bit word. Setup Lockout mode In device mode, this bit controls behavior of the setup lock mechanism. See Section 20.10.8. 0 1 Setup Lockouts on Setup Lockouts Off (DCD requires the use of Setup Buffer Tripwire in USBCMD) 00 R/ WO 2 ES 0 R/W 3 SLOM 0 R/W All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 389 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R R A Table 330. USB Mode register in device mode (USBMODE_D - address 0x4000 61A8) bit description …continued D R A R A FT D R FT D R A R A A Bit Symbol Value Description Reset value Access FT D R A F FT D R A 4 SDIS Stream disable mode Remark: The use of this feature substantially limits the overall USB performance that can be achieved. 0 R/W FT D R A FT D FT D 0 1 Not disabled Disabled. Setting this bit to one disables double priming on both RX and TX for low bandwidth systems. This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. Note: In High Speed Mode, all packets received will be responded to with a NYET handshake when stream disable is active. R A 5 31:6 - Not used in device mode. reserved 0 - 20.6.17.2 Host mode Table 331. USB Mode register in host mode (USBMODE_H - address 0x4000 61A8) bit description Bit Symbol Value Description Reset value Access 1:0 CM Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register. 0x0 0x1 0x2 0x3 Idle Reserved Device controller Host controller Endian select This bit can change the byte ordering of the transfer buffers. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words. 0 1 Little endian: first byte referenced in least significant byte of 32-bit word. Big endian: first byte referenced in most significant byte of 32-bit word. Not used in host mode 00 R/ WO 2 ES 0 R/W 3 - 0 - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 390 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R R A Table 331. USB Mode register in host mode (USBMODE_H - address 0x4000 61A8) bit description …continued D R A R A FT D R FT D R A R A A Bit Symbol Value Description Reset value Access FT D R A F FT D R A 4 SDIS Stream disable mode Remark: The use of this feature substantially limits the overall USB performance that can be achieved. 0 R/W FT D R A FT D FT D 0 1 Not disabled Disabled. Setting to a ‘1’ ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the the TX latency is filled to capacity before the packet is launched onto the USB. Note: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING to characterize the adjustments needed for the scheduler when using this feature. R A 5 VBPS 0 1 VBUS power select vbus_pwr_select is set LOW. vbus_pwr_select is set HIGH 0 R/WO 31:6 - - reserved - - 20.6.18 USB Endpoint Setup Status register (ENDPSETUPSTAT) Table 332. USB Endpoint Setup Status register (ENDPTSETUPSTAT - address 0x4000 61AC) bit description Bit Symbol Description Reset value Access 5:0 ENDPTSET Setup endpoint status for logical endpoints 0 to 5. 0 UPSTAT For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged. reserved - R/WC 31:6 - 20.6.19 USB Endpoint Prime register (ENDPTPRIME) For each endpoint, software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. Remark: These bits will be momentarily set by hardware during hardware endpoint re-priming operations when a dTD is retired and the dQH is updated. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 391 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R Table 333. USB Endpoint Prime register (ENDPTPRIME - address 0x4000 61B0) bit description Bit Symbol Description Reset value D R A R A FT D R FT D A R R A FT D R R A F Access A FT D R A A 5:0 PERB Prime endpoint receive buffer for physical OUT endpoints 5 to 0. 0 For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5 R/WS FT D R A FT D R A FT D 15:6 - reserved Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB5 = endpoint 5 0 R/WS 21:16 PETB 31:22 - reserved - - 20.6.20 USB Endpoint Flush register (ENDPTFLUSH) Writing a one to a bit(s) in this register will cause the associated endpoint(s) to clear any primed buffers. If a packet is in progress for one of the associated endpoints, then that transfer will continue until completion. Hardware will clear this register after the endpoint flush operation is successful. Table 334. USB Endpoint Flush register (ENDPTFLUSH - address 0x4000 61B4) bit description Bit Symbol Description Reset value Access 5:0 FERB Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5 0 R/WS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 392 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R Table 334. USB Endpoint Flush register (ENDPTFLUSH - address 0x4000 61B4) bit description Bit Symbol Description Reset value D R A R A FT D R FT D A R R A FT D R R A Access A FT D R F A A 15:6 - reserved Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB5 = endpoint 5 0 - FT D 21:16 FETB R/WS FT D R A FT D R A 31:22 - reserved - - 20.6.21 USB Endpoint Status register (ENDPTSTAT) One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay time varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. Remark: These bits will be momentarily cleared by hardware during hardware endpoint re-priming operations when a dTD is retired and the dQH is updated. Table 335. USB Endpoint Status register (ENDPTSTAT - address 0x4000 61B8) bit description Bit Symbol Description Reset value Access 5:0 ERBR Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5 0 RO 15:6 - reserved Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5 0 RO 21:16 ETBR 31:22 - reserved - - 20.6.22 USB Endpoint Complete register (ENDPTCOMPLETE) Each bit in this register indicates that a received/transmit event occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 393 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R A D R A R A FT D R FT Writing a one will clear the corresponding bit in this register. D R Table 336. USB Endpoint Complete register (ENDPTCOMPLETE - address 0x4000 61BC) bit description Bit Symbol Description Reset value R A FT D R R A F D R A FT Access A FT A FT D R D 5:0 ERCE Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5 0 R/WC A FT D R A 15:6 - reserved Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5 0 R/WC 21:16 ETCE 31:21 - reserved - - 20.6.23 USB Endpoint 0 Control register (ENDPTCTRL0) This register initializes endpoint 0 for control transfer. Endpoint 0 is always a control endpoint. Table 337. USB Endpoint 0 Control register (ENDPTCTRL0 - address 0x4000 61C0) bit description Bit Symbol Value Description Reset value Access 0 RXS 0 1 Rx endpoint stall Endpoint ok. Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1] 0 R/W 1 3:2 6:4 7 RXT1_0 RXE - reserved Endpoint type Endpoint 0 is always a control endpoint. 00 1 R/W RO - reserved Rx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1. 15:8 - - reserved - - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 394 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R R A Table 337. USB Endpoint 0 Control register (ENDPTCTRL0 - address 0x4000 61C0) bit description …continued D R A R A FT D R FT D R A R A A Bit Symbol Value Description Reset value Access FT D R A F FT D R A 16 TXS 0 1 Tx endpoint stall Endpoint ok. Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1] R/W FT D R A FT D R A FT D 17 - - reserved Endpoint type Endpoint 0 is always a control endpoint. 00 RO 19:18 TXT1_0 22:20 23 TXE - reserved Tx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1. 1 RO 31:24 [1] - reserved There is a slight delay (50 clocks max) between the ENPTSETUPSTAT being cleared and hardware continuing to clear this bit. In most systems it is unlikely that the DCD software will observe this delay. However, should the DCD notice that the stall bit is not set after writing a one to it, software should continually write this stall bit until it is set or until a new setup has been received by checking the associated ENDPTSETUPSTAT bit. 20.6.24 Endpoint 1 to 5 control registers Each endpoint that is not a control endpoint has its own register to set the endpoint type and enable or disable the endpoint. Remark: The reset value for all endpoint types is the control endpoint. If one endpoint direction is enabled and the paired endpoint of opposite direction is disabled, then the endpoint type of the unused direction must be changed from the control type to any other type (e.g. bulk). Leaving an unconfigured endpoint control will cause undefined behavior for the data PID tracking on the active endpoint. Table 338. USB Endpoint 1 to 5 control registers (ENDPTCTRL - address 0x4000 61C4 (ENDPTCTRL1) to 0x4000 61D4 (ENDPTCTRL5)) bit description Bit Symbol Value Description Reset value Access 0 RXS 0 Rx endpoint stall Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. 1 Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. 0 R/W All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 395 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R R A Table 338. USB Endpoint 1 to 5 control registers (ENDPTCTRL - address 0x4000 61C4 (ENDPTCTRL1) to 0x4000 61D4 (ENDPTCTRL5)) bit description …continued Bit Symbol Value Description Reset value D R A R A FT D R FT D R A R A FT Access A FT D R A F R A FT D FT 1 3:2 RXT 0x0 0x1 0x2 0x3 Reserved Endpoint type Control Isochronous Bulk Reserved Reserved Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID. 0 1 Disabled Enabled Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device. 0 00 R/W R/W D D R A FT D R A 4 5 RXI - 0 R/W 6 RXR 0 WS 7 RXE Rx endpoint enable Remark: An endpoint should be enabled only after it has been configured. 0 R/W 0 1 15:8 16 TXS 0 - Endpoint disabled. Endpoint enabled. reserved Tx endpoint stall Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. 0 R/W 1 Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. 17 - 0x0 0x1 0x2 0x3 Reserved Tx endpoint type Control Isochronous Bulk Interrupt reserved All information provided in this document is subject to legal disclaimers. 0 00 R/W 19:18 TXT1_0 20 - - © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 396 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R R A Table 338. USB Endpoint 1 to 5 control registers (ENDPTCTRL - address 0x4000 61C4 (ENDPTCTRL1) to 0x4000 61D4 (ENDPTCTRL5)) bit description …continued Bit Symbol Value Description Reset value D R A R A FT D R FT D R A R A FT Access A FT D R A F R A FT D FT 21 TXI Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID. 0 1 Enabled Disabled Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID’s between the host and device. 0 R/W D D R A FT D R A 22 TXR 1 WS 23 TXE Tx endpoint enable Remark: An endpoint should be enabled only after it has been configured 0 R/W 0 1 31:24 - Endpoint disabled. Endpoint enabled. reserved 0 20.7 Functional description 20.7.1 OTG core The OTG core forms the main digital part of the USB-OTG. See the USB EHCI specification for details about this core. 20.7.2 Host data structures See Chapter 4 of Enhanced Host Controller Interface Specification for Universal Serial Bus 1.0. 20.7.3 Host operational model See Chapter 3 of Enhanced Host Controller Interface Specification for Universal Serial Bus 1.0. 20.7.4 ATX_RGEN module There are a number of requirements for the reset signal towards the ATX transceiver, these are as follows: • it requires the clocks to be running for a reset to occur correctly. • it must see a rising edge of reset to correctly reset the clock generation module. • the reset must be a minimum of 133 ns (4  30 MHz clock cycles) in duration to reset all logic correctly. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 397 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R R A The ATX_RGEN module generates a reset signal towards the ATX fulfilling above 3 requirements, no matter how the AHB reset looks like. A FT D D R A R A FT D R FT D R A F R D A R A FT R A 20.7.5 ATX transceiver FT D FT D R A The USB-OTG has a USB transceiver with UTMI+ interface. It contains the required transceiver OTG functionality; this includes: FT D R A • VBUS sensing for producing the session-valid and VBUS-valid signals. • sampling of the USB_ID input for detection of A-device or B-device connection. • charging and discharging of VBUS for starting and ending a session as B-device. 20.7.6 Modes of operation In general, the USB-OTG can be operating either in host mode or in device mode. Software must put the core in the appropriate mode by setting the USBMODE.CM field (‘11’ for host mode, ‘10’ for device mode). The USBMODE.CM field can also be equal to ‘00’, which means that the core is in idle mode (neither host nor device mode). This will happen after the following: • a hardware reset. • a software reset via the USBCMD.RST bit; e.g. when switching from host mode to device mode as part of the HNP protocol (or vice versa), software must issue a software reset by which the core will be to the idle state; this will happen in a time frame dependent on the software. 20.7.7 SOF/VF indicator The USB-OTG generates a SOF/VF indicator signal, which can be used by user specific external logic. In FS mode, the SOF/VF indicator signal has a frequency equal to the frame frequency, which is about 1 kHz. The signal is high for half of the frame period and low for the other half of the frame period. The positive edge is aligned with the start of a frame (= SOF). In HS mode, the SOF/VF indicator signal has a frequency equal to the virtual frame frequency. The signal is high for half of the virtual frame period and low for the other half of the virtual frame period. The positive edge is aligned with the start of a virtual frame (= VF). The length of the virtual frame is defined as: VF = microframe  2bInterval; bInterval is specified in the 4-bit programmable BINTERVAL.BINT register field. The minimum value of bInterval is 0, the maximum value is 15. In suspend mode the SOF/VF indicator signal is turned off (= remains low). 20.7.8 Hardware assist The hardware assist provides automated response and sequencing that may not be possible in software if there are significant interrupt latency response times. The use of this additional circuitry is optional and can be used to assist the following three state transitions by setting the appropriate bits in the OTGSC register: All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 398 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R A D R A R A FT D R FT • Auto reset (set bit HAAR). • Data pulse (set bit HADP). • B-disconnect to A-connect (set bit HABA). 20.7.8.1 Auto reset D R When the HAAR in the OTGSC register is set to one, the host will automatically start a reset after a connect event. This shortcuts the normal process where software is notified of the connect event and starts the reset. Software will still receive notification of the connect event (CCS bit in the PORTSC register) but should not write the reset bit in the USBCMD register when the HAAR is set. Software will be notified again after the reset is complete via the enable change bit in the PORTSC register which causes a port change interrupt. This assist will ensure the OTG parameter TB_ACON_BSE0_MAX = 1 ms is met (see OTG specification for an explanation of the OTG timing requirements). R A FT D R R A F D R A FT A FT A FT D R A D FT D R A 20.7.8.2 Data pulse Writing a one to HADP in the OTGSC register will start a data pulse of approximately 7 ms in duration and then automatically cease the data pulsing. During the data pulse, the DP bit will be set and then cleared. This automation relieves software from accurately controlling the data-pulse duration. During the data pulse, the HCD can poll to see that the HADP and DP bit have returned low to recognize the completion, or the HCD can simply launch the data pulse and wait to see if a VBUS Valid interrupt occurs when the A-side supplies bus power. This assist will ensure data pulsing meets the OTG requirement of > 5 ms and < 10 ms. 20.7.8.3 B-disconnect to A-connect (Transition to the A-peripheral state) During HNP, the B-disconnect occurs from the OTG A_suspend state, and within 3 ms, the A-device must enable the pull-up on the DP leg in the A-peripheral state. For the hardware assist to begin the following conditions must be met: • HABA is set. • Host controller is in suspend mode. • Device is disconnecting. The hardware assist consists of the following steps: 1. Hardware resets the OTG controller (writes 1 to the RST bit in USBCMD). 2. Hardware selects the device mode (writes 10 to bits CM[1:0] in USBMODE). 3. Hardware sets the RS bit in USBCMD and enables the necessary interrupts: – USB reset enable (URE) - enables interrupt on USB bus reset to device. – Sleep enable (SLE) - enables interrupt on device suspend. – Port change detect enable (PCE) - enables interrupt on device connect. When software has enabled this hardware assist, it must not interfere during the transition and should not write any register in the OTG core until it gets an interrupt from the device controller signifying that a reset interrupt has occurred or until it has verified that the core has entered device mode. HCD/DCD must not activate the core soft reset at any time All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 399 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R R A since this action is performed by hardware. During the transition, the software may see an interrupt from the disconnect and/or other spurious interrupts (i.e. SOF/etc.) that may or may not cascade and my be cleared by the soft reset depending on the software response time. R A A FT D R A FT D After the core has entered device mode with help of the hardware assist, the DCD must ensure that the ENDPTLISTADDR is programmed properly before the host sends a setup packet. Since the end of the reset duration, which may be initiated quickly (a few microseconds) after connect, will require at a minimum 50 ms, this is the time for which the DCD must be ready to accept setup packets after having received notification that the reset has been detected or simply that the OTG is in device mode which ever occurs first. If the A-peripheral fails to see a reset after the controller enters device mode and engages the D+-pull-up, the device controller interrupts the DCD signifying that a suspend has occurred. This assist will ensure the parameter TA_BDIS_ACON_MAX = 3ms is met. D R A R A FT D R FT D R A F R A FT D FT D R A D FT R A 20.8 Deviations from EHCI standard For the purposes of a dual-role Host/Device controller with support for On-The-Go applications, it is necessary to deviate from the EHCI specification. Device operation and On-The-Go operation is not specified in the EHCI and thus the implementation supported in this core is specific to the LPC18xx. The host mode operation of the core is near EHCI compatible with few minor differences documented in this section. The particulars of the deviations occur in the areas summarized here: • Embedded Transaction Translator – Allows direct attachment of FS and LS devices in host mode without the need for a companion controller. • Device operation - In host mode the device operational registers are generally disabled and thus device mode is mostly transparent when in host mode. However, there are a couple exceptions documented in the following sections. • On-The-Go Operation - This design includes an On-The-Go controller. 20.8.1 Embedded Transaction Translator function The USB-HS OTG controller supports directly connected full and low speed devices without requiring a companion controller by including the capabilities of a USB 2.0 high speed hub transaction translator. Although there is no separate Transaction Translator block in the system, the transaction translator function normally associated with a high speed hub has been implemented within the DMA and Protocol engine blocks. The embedded transaction translator function is an extension to EHCI interface but makes use of the standard data structures and operational models that exist in the EHCI specification to support full and low speed devices. 20.8.1.1 Capability registers The following items have been added to the capability registers to support the embedded Transaction Translator Function: • N_TT bits added to HCSPARAMS – Host Control Structural Parameters (see Table 302). • N_PTT added to HCSPARAMS – Host Control Structural Parameters (see Table 302). All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 400 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R A D R A R A FT D R FT 20.8.1.2 Operational registers D R The following items have been added to the operational registers to support the embedded TT: R A FT D R R A F D R A FT A FT A FT • New register TTCTRL (see Section 20.6.9). • Two-bit Port Speed (PSPD) bits added to the PORTSC1 register (see Section 20.6.15). D D R A FT D R A 20.8.1.3 Discovery In a standard EHCI controller design, the EHCI host controller driver detects a Full speed (FS) or Low speed (LS) device by noting if the port enable bit is set after the port reset operation. The port enable will only be set in a standard EHCI controller implementation after the port reset operation and when the host and device negotiate a High-Speed connection (i.e. Chirp completes successfully). Since this controller has an embedded Transaction Translator, the port enable will always be set after the port reset operation regardless of the result of the host device chirp result and the resulting port speed will be indicated by the PSPD field in PORTSC1 (see Section 20.6.15). Table 339. Handling of directly connected full-speed and low-speed devices Standard EHCI model EHCI with embedded Transaction Translator After the port enable bit is set following a connection and reset sequence, the device/hub is assumed to be HS. FS and LS devices are assumed to be downstream from a HS hub thus, all port-level control is performed through the Hub Class to the nearest Hub. After the port enable bit is set following a connection and reset sequence, the device/hub speed is noted from PORTSC1. FS and LS device can be either downstream from a HS hub or directly attached. When the FS/LS device is downstream from a HS hub, then port-level control is done using the Hub Class through the nearest Hub. When a FS/LS device is directly attached, then port-level control is accomplished using PORTSC1. FS and LS device can be either downstream from a HS hub with HubAddr = X [HubAddr > 0] or directly attached, where HubAddr = TTHA (TTHA is programmable and defaults to 0) and HubAddr is the address of the Root Hub where the bus transitions from HS to FS/LS (i.e. Split target hub is the root hub). FS and LS devices are assumed to be downstream from a HS hub with HubAddr=X, where HubAddr > 0 and HubAddr is the address of the Hub where the bus transitions from HS to FS/LS (i.e. Split target hub). 20.8.1.4 Data structures The same data structures used for FS/LS transactions though a HS hub are also used for transactions through the Root Hub with sm embedded Transaction Translator. Here it is demonstrated how the Hub Address and Endpoint Speed fields should be set for directly attached FS/LS devices and hubs: 1. QH (for direct attach FS/LS) – Async. (Bulk/Control Endpoints) Periodic (Interrupt) – Hub Address = TTHA (default TTHA = 0) – Transactions to direct attached device/hub: QH.EPS = Port Speed – Transactions to a device downstream from direct attached FS hub: QH.EPS = Downstream Device Speed All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 401 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R R A Remark: When QH.EPS = 01 (LS) and PORTSCx.PSPD = 00 (FS), a LS-pre-pid will be sent before the transmitting LS traffic. R A Maximum Packet Size must be less than or equal 64 or undefined behavior may result. R A FT D D R A R A FT D R FT D R A A FT D R A F FT D FT D 2. siTD (for direct attach FS) – Periodic (ISO Endpoint) all FS ISO transactions: Hub Address = (default TTHA = 0) siTD.EPS = 00 (full speed) Maximum Packet Size must less than or equal to 1023 or undefined behavior may result. R A FT D R A 20.8.1.5 Operational model The operational models are well defined for the behavior of the Transaction Translator (see USB 2.0 specification) and for the EHCI controller moving packets between system memory and a USB-HS hub. Since the embedded Transaction Translator exists within the host controller there is no physical bus between EHCI host controller driver and the USB FS/LS bus. These sections will briefly discuss the operational model for how the EHCI and Transaction Translator operational models are combined without the physical bus between. The following sections assume the reader is familiar with both the EHCI and USB 2.0 Transaction Translator operational models. 20.8.1.5.1 Micro-frame pipeline The EHCI operational model uses the concept of H-frames and B-frames to describe the pipeline between the Host (H) and the Bus (B). The embedded Transaction Translator shall use the same pipeline algorithms specified in the USB 2.0 specification for a Hub-based Transaction Translator. It is important to note that when programming the S-mask and C-masks in the EHCI data structures to schedule periodic transfers for the embedded Transaction Translator, the EHCI host controller driver must follow the same rules specified in EHCI for programming the S-mask and C-mask for downstream Hub-based Transaction Translators. Once periodic transfers are exhausted, any stored asynchronous transfer will be moved. Asynchronous transfers are opportunistic in that they shall execute whenever possible and their operation is not tied to H-frame and B-frame boundaries with the exception that an asynchronous transfer can not babble through the SOF (start of B-frame 0.) 20.8.1.6 Split state machines The start and complete split operational model differs from EHCI slightly because there is no bus medium between the EHCI controller and the embedded Transaction Translator. Where a start or complete-split operation would occur by requesting the split to the HS hub, the start/complete split operation is simple an internal operation to the embedded Transaction Translator. The following table summarizes the conditions where handshakes are emulated from internal state instead of actual handshakes to HS split bus traffic. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 402 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R A D R A R A FT D R FT D Table 340. Split state machine properties Condition R Emulate TT response R A FT D R A F D A FT Start-split All asynchronous buffers full. All periodic buffers full. Success for start of Async. Transaction. Start Periodic Transaction. NAK ERR ACK No Handshake (Ok) Bus Time Out NYET R R A FT D R A FT D A FT D R A Complete-split Failed to find transaction in queue. Transaction in Queue is Busy. Transaction in Queue is Complete. [Actual Handshake from LS/FS device] 20.8.1.7 Asynchronous Transaction scheduling and buffer management The following USB 2.0 specification items are implemented in the embedded Transaction Translator: 1. USB 2.0 specification, section 11.17.3: Sequencing is provided & a packet length estimator ensures no full-speed/low-speed packet babbles into SOF time. 2. USB 2.0 specification, section 11.17.4: Transaction tracking for 2 data pipes. 3. USB 2.0 specification, section 11.17.5: Clear_TT_Buffer capability provided though the use of the TTCTRL register. 20.8.1.8 Periodic Transaction scheduling and buffer management The following USB 2.0 specification items are implemented in the embedded Transaction Translator: 1. USB 2.0 specs, section 11.18.6.[1-2]: – Abort of pending start-splits: EOF (and not started in micro-frames 6) Idle for more than 4 micro-frames – Abort of pending complete-splits: EOF Idle for more than 4 micro-frames 2. USB 2.0 specs, section 11.18.6.[7-8]: – Transaction tracking for up to 16 data pipes: Some applications may not require transaction tracking up to a maximum of 16 periodic data pipes. The option to limit the tracking to only 4 periodic data pipes exists in the by changing the configuration constant VUSB_HS_TT_PERIODIC_CONTEXTS to 4. The result is a significant gate count savings to the core given the limitations implied. Remark: Limiting the number of tracking pipes in the EMBedded TT to four (4) will impose the restriction that no more than 4 periodic transactions (INTERRUPT/ISOCHRONOUS) can be scheduled through the embedded TT per frame. The number 16 was chosen in the USB specification because it is sufficient to ensure that the high-speed to full- speed periodic pipeline can remain full. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 403 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R R A keeping the pipeline full puts no constraint on the number of periodic transactions that can be scheduled in a frame and the only limit becomes the flight time of the packets on the bus. R A A FT D R A D R A R A FT D R FT D R A F R A D FT – Complete-split transaction searching: FT D R A FT D R A There is no data schedule mechanism for these transactions other than micro-frame pipeline. The embedded TT assumes the number of packets scheduled in a frame does not exceed the frame duration (1 ms) or else undefined behavior may result. FT D 20.8.1.9 Multiple Transaction Translators The maximum number of embedded Transaction Translators that is currently supported is one as indicated by the N_TT field in the HCSPARAMS – Host Control Structural Parameters register. 20.8.2 Device operation The co-existence of a device operational controller within the host controller has little effect on EHCI compatibility for host operation except as noted in this section. 20.8.2.1 USBMODE register Given that the dual-role controller is initialized in neither host nor device mode, the USBMODE register must be programmed for host operation before the EHCI host controller driver can begin EHCI host operations. 20.8.2.2 Non-Zero Fields the register file Some of the reserved fields and reserved addresses in the capability registers and operational register have use in device mode, the following must be adhered to: • Write operations to all EHCI reserved fields (some of which are device fields) with the operation registers should always be written to zero. This is an EHCI requirement of the device controller driver that must be adhered to. • Read operations by the host controller must properly mask EHCI reserved fields (some of which are device fields) because fields that are used exclusive for device are undefined in host mode. 20.8.2.3 SOF interrupt This SOF Interrupt used for device mode is shared as a free running 125us interrupt for host mode. EHCI does not specify this interrupt but it has been added for convenience and as a potential software time base. See USBSTS (Section 20.6.4) and USBINTR (Section 20.6.5) registers. 20.8.3 Miscellaneous variations from EHCI 20.8.3.1 Discovery 20.8.3.1.1 Port reset The port connect methods specified by EHCI require setting the port reset bit in the PORTSCx register for a duration of 10 ms. Due to the complexity required to support the attachment of devices that are not high speed there are counter already present in the All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 404 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R R A design that can count the 10ms reset pulse to alleviate the requirement of the software to measure this duration. Therefore, the basic connection is then summarized as the following: R A A FT D R A FT D • [Port Change Interrupt] Port connect change occurs to notify the host controller driver that a device has attached. R A • Software shall write a ‘1’ to the reset the device. • Software shall write a ‘0’ to the reset the device after 10 ms. This step, which is necessary in a standard EHCI design, may be omitted with this implementation. Should the EHCI host controller driver attempt to write a ‘0’ to the reset bit while a reset is in progress the write will simple be ignored and the reset will continue until completion. • [Port Change Interrupt] Port enable change occurs to notify the host controller that the device in now operational and at this point the port speed has been determined. 20.8.3.1.2 Port speed detection After the port change interrupt indicates that a port is enabled, the EHCI stack should determine the port speed. Unlike the EHCI implementation which will re-assign the port owner for any device that does not connect at High-Speed, this host controller supports direct attach of non High-Speed devices. Therefore, the following differences are important regarding port speed detection: • Port Owner is read-only and always reads 0. • A 2-bit Port Speed indicator has been added to PORTSC to provide the current operating speed of the port to the host controller driver. • A 1-bit High Speed indicator has been added to PORTSC to signify that the port is in High-Speed vs. Full/Low Speed – This information is redundant with the 2-bit Port Speed indicator above. D R A R A FT D R FT D R A F R A FT D FT D R A D FT 20.9 Device data structures This section defines the interface data structures used to communicate control, status, and data between Device Controller Driver (DCD) Software and the Device Controller. The data structure definitions in this chapter support a 32-bit memory buffer address space. Remark: The Software must ensure that no interface data structure reachable by the Device controller crosses a 4k-page boundary The data structures defined in the chapter are (from the device controller’s perspective) a mix of read-only and read/ writable fields. The device controller must preserve the read-only fields on all data structure writes. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 405 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R R A D R A R A FT D R FT D R A R A FT FT A F Endpoint Queue Heads dQH Endpoint dQH5 - In Endpoint dQH5 - Out Endpoint Transfer Descriptors dTD D D R A FT D TRANSFER BUFFER R A FT D A FT D R A R transfer buffer pointer Endpoint dQH1 - Out Endpoint dQH0 - In Endpoint dQH0 - Out dTD dTD dTD TRANSFER BUFFER dTD transfer buffer pointer TRANSFER BUFFER transfer buffer pointer transfer buffer pointer ENDPOINTLISTADDR TRANSFER BUFFER Fig 37. Endpoint queue head organization Device queue heads are arranged in an array in a continuous area of memory pointed to by the ENDPOINTLISTADDR pointer. The even –numbered device queue heads in the list support receive endpoints (OUT/SETUP) and the odd-numbered queue heads in the list are used for transmit endpoints (IN/INTERRUPT). The device controller will index into this array based upon the endpoint number received from the USB bus. All information necessary to respond to transactions for all primed transfers is contained in this list so the Device Controller can readily respond to incoming requests without having to traverse a linked list. Remark: The Endpoint Queue Head List must be aligned to a 2k boundary. 20.9.1 Endpoint queue head (dQH) The device Endpoint Queue Head (dQH) is where all transfers are managed. The dQH is a 48-byte data structure, but must be aligned on 64-byte boundaries. During priming of an endpoint, the dTD (device transfer descriptor) is copied into the overlay area of the dQH, which starts at the nextTD pointer DWord and continues through the end of the buffer pointers DWords. After a transfer is complete, the dTD status DWord is updated in the dTD pointed to by the currentTD pointer. While a packet is in progress, the overlay area of the dQH is used as a staging area for the dTD so that the Device Controller can access needed information with little minimal latency. 20.9.1.1 Endpoint capabilities and characteristics This DWord specifies static information about the endpoint, in other words, this information does not change over the lifetime of the endpoint. Device Controller software should not attempt to modify this information while the corresponding endpoint is enabled. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 406 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R A D R A R A FT D R FT D Table 341. Endpoint capabilities and characteristics Access Bit Name Description R R A FT D R A F D A FT RO 31:30 MULT Number of packets executed per transaction descriptor R 00 - Execute N transactions as demonstrated by the USB variable length protocol where N is computed using Max_packet_length and the Total_bytes field in the dTD. 01 - Execute one transaction 10 - Execute two transactions 11 - Execute three transactions Remark: Non-isochronous endpoints must set MULT = 00. Remark: Isochronous endpoints must set MULT = 01, 10, or 11 as needed. R A FT D R A FT D A FT D R A RO 29 ZLT Zero length termination select This bit is used for non-isochronous endpoints to indicate when a zero-length packet is received to terminate transfers in case the total transfer length is “multiple”. 0 - Enable zero-length packet to terminate transfers equal to a multiple of Max_packet_length (default). 1 - Disable zero-length packet on transfers that are equal in length to a multiple Max_packet_length. RO RO RO 28:27 26:16 Max_packet _length 15 IOS reserved Maximum packet size of the associated endpoint (< 1024) Interrupt on setup This bit is used on control type endpoints to indicate if USBINT is set in response to a setup being received. RO 14:0 - reserved All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 407 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R R A D R A R A FT D R FT D R A R A FT FT D R A D A F R A device Queue Head (dQH) offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C Total_bytes 31 bit 0 transfer overlay FT D R A FT D ENDPOINT CAPABILITIES/CHARACTERISTICS CURRENT dTD POINTER NEXT dTD POINTER IOC MulO STATUS CURR_OFFS T Total_bytes endpoint transfer descriptor (dTD) NEXT dTD POINTER IOC MulO STATUS CURR_OFFS FRAME_N T FT D R A BUFFER POINTER PAGE 0 BUFFER POINTER PAGE 1 BUFFER POINTER PAGE 2 BUFFER POINTER PAGE 3 BUFFER POINTER PAGE 4 RESERVED BUFFER POINTER PAGE 0 BUFFER POINTER PAGE 1 BUFFER POINTER PAGE 2 BUFFER POINTER PAGE 3 BUFFER POINTER PAGE 4 SET-UP BUFFER: BYTES 3:0 SET-UP BUFFER: BYTES 7:4 Fig 38. Endpoint queue head data structure 20.9.1.2 Transfer overlay The seven DWords in the overlay area represent a transaction working space for the device controller. The general operational model is that the device controller can detect whether the overlay area contains a description of an active transfer. If it does not contain an active transfer, then it will not read the associated endpoint. After an endpoint is readied, the dTD will be copied into this queue head overlay area by the device controller. Until a transfer is expired, software must not write the queue head overlay area or the associated transfer descriptor. When the transfer is complete, the device controller will write the results back to the original transfer descriptor and advance the queue. See dTD for a description of the overlay fields. 20.9.1.3 Current dTD pointer The current dTD pointer is used by the device controller to locate the transfer in progress. This word is for Device Controller (hardware) use only and should not be modified by DCD software. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 408 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R A D R A R A FT D R FT D Table 342. Current dTD pointer Access Bit Name Description R R A FT D R A F D A FT R/W 31:5 (hardware only) Current_TD_pointer Current dTD pointer R This field is a pointer to the dTD that is represented in the transfer overlay area. This field will be modified by the device controller to the next dTD pointer during endpoint priming or queue advance. reserved R A FT D R A FT D A FT D R A - 4:0 20.9.1.4 Set-up buffer The set-up buffer is dedicated storage for the 8-byte data that follows a set-up PID. Remark: Each endpoint has a TX and an RX dQH associated with it, and only the RX queue head is used for receiving setup data packets. Table 343. Set-up buffer Dword Access Bit Name Description 1 R/W 31:0 BUF0 Setup buffer 0 This buffer contains bytes 3 to 0 of an incoming setup buffer packet and is written by the device controller to be read by software. 2 R/W 31:0 BUF1 Setup buffer 1 This buffer contains bytes 7 to 4 of an incoming setup buffer packet and is written by the device controller to be read by software. 20.9.2 Endpoint transfer descriptor (dTD) The dTD describes to the device controller the location and quantity of data to be sent/received for given transfer. The DCD should not attempt to modify any field in an active dTD except the Next Link Pointer, which should only be modified as described in Section 20.10.11. Table 344. Next dTD pointer Access Bit Name Description RO 31:5 Next_link_pointer Next link pointer This field contains the physical memory address of the next dTD to be processed. The field corresponds to memory address signals [31:5], respectively. 4:1 0 T reserved Terminate This bit indicates to the device controller when there are no more valid entries in the queue. 1 - pointer is invalid 0 - Pointer is valid, i.e. pointer points to a valid transfer element descriptor. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 409 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R A D R A R A FT D R FT D Table 345. dTD token Access Bit Name Description R R A FT D R A F D A FT R/W 31 30:16 Total_bytes reserved Total bytes R This field specifies the total number of bytes to be moved with this transfer descriptor. This field is decremented by the number of bytes actually moved during the transaction and it is decremented only when the transaction has been completed successfully. The maximum value software can write into this field is 0x5000 (5 x 4 kB) for the maximum number of bytes five page pointers can access. Although it is possible to create a transfer up to 20 kB this assumes that the first offset into the first page is zero. When the offset cannot be predetermined, crossing past the fifth page can be guaranteed by limiting the total bytes to 16 kB. Therefore, the maximum recommended Total-Bytes = 16 kB (0x4000). If Total_bytes = 0 when the host controller fetches this transfer descriptor and the active bit is set in the Status field of this dTD, the device controller executes a zero-length transaction and retires the dTD. Remark: For IN transfers, it is not a requirement that Total_bytes is an even multiple of Max_packet_length. If software builds such a dTD, the last transaction will always be less than Max_packet_length. R A FT D R A FT D A FT D R A RO 15 IOC Interrupt on complete This bit is used to indicate if USBINT will be set when the device controller is finished with this dTD. 1 - USBINT set. 0 - USBINT not set. - 14:12 - reserved All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 410 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R A D R A R A FT D R FT Table 345. dTD token …continued Access Bit Name Description D R R A FT D R A F D A FT RO 11:10 MultO Multiplier Override (see Section 20.9.2.1 for an example) R This field can be used for transmit ISOs to override the MULT field in the dQH. This field must be zero for all packet types that are not transmit-ISO. 00 - Execute N transactions as demonstrated by the USB variable length protocol where N is computed using Max_packet_length and the Total_bytes field in the dTD. 01 - Execute one transaction 10 - Execute two transactions 11 - Execute three transactions Remark: Non-ISO and Non-TX endpoints must set MultO=”00”. R A A FT D R A FT D FT D R A 9:8 R/W 7:0 Status reserved Status This field is used by the device controller to communicate individual execution states back to the software. This field contains the status of the last transaction performed on this dTD. Bit 7 = 1 - status: Active Bit 6 = 1 - status: Halted Bit 5 = 1 - status: Buffer Error Bit 4 - reserved Bit 3 = 1 - status: Transaction Error Bit 2 - reserved Bit 1 - reserved Bit 0 - reserved Table 346. dTD buffer page pointer list Access Bit Name Description RO 31:12 BUFF_P Selects the page offset in memory for the packet buffer. Non-virtual memory systems will typically set the buffer pointers to a series of incrementing integers. Offset into the 4 kB buffer where the packet is to begin. Written by the device controller to indicate the frame number in which a packet finishes. This is typically used to correlate relative completion times of packets on an isochronous endpoint. page 0: 11:0 page 1: 10:0 CURR_OFFS FRAME_N 20.9.2.1 Determining the number of packets for Isochronous IN endpoints The following examples show how the MULT field in the dQH and the MultO in the dTD are used to control the number of packets sent in an In-transaction for an isochronous endpoint: Example 1 MULT = 3; Max_packet_size = 8; Total_bytes = 15; MultO = 0 (default) All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 411 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R R A In this case three packets are sent: Data2 (8 bytes), Data1 (7 bytes), Data0 (0 bytes). A FT D R A R A FT D R FT D R A F R A FT Example 2 MULT = 3; Max_packet_size = 8; Total_bytes = 15; MultO = 2 In this case two packets are sent: Data1 (8 bytes), Data0 (7 bytes). D To optimize efficiency for IN transfers, software should compute MultO = greatest integer of (Total_bytes/Max_packet_size). If Total_bytes = 0, then MultO should be 1. D R A FT D R A FT D A FT D R A R 20.10 Device operational model The function of the device operation is to transfer a request in the memory image to and from the Universal Serial Bus. Using a set of linked list transfer descriptors, pointed to by a queue head, the device controller will perform the data transfers. The following sections explain the use of the device controller from the device controller driver (DCD) point-of-view and further describe how specific USB bus events relate to status changes in the device controller programmer's interface. 20.10.1 Device controller initialization After hardware reset, the device is disabled until the Run/Stop bit is set to a ‘1’. In the disabled state, the pull-up on the USB_DM is not active which prevents an attach event from occurring. At a minimum, it is necessary to have the queue heads setup for endpoint zero before the device attach occurs. Shortly after the device is enabled, a USB reset will occur followed by setup packet arriving at endpoint 0. A Queue head must be prepared so that the device controller can store the incoming setup packet. In order to initialize a device, the software should perform the following steps: 1. Set Controller Mode in the USBMODE register to device mode. Remark: Transitioning from host mode to device mode requires a device controller reset before modifying USBMODE. 2. Allocate and Initialize device queue heads in system memory (see Section 20.9). Minimum: Initialize device queue heads 0 Tx & 0 Rx. Remark: All device queue heads associated with control endpoints must be initialized before the control endpoint is enabled. Non-Control device queue heads must be initialized before the endpoint is used and not necessarily before the endpoint is enabled. 3. Configure ENDPOINTLISTADDR Pointer (see Section 20.6.8). 4. Enable the microprocessor interrupt associated with the USB-HS core. Recommended: enable all device interrupts including: USBINT, USBERRINT, Port Change Detect, USB Reset Received, DCSuspend (see Table 311). 5. Set Run/Stop bit to Run Mode. After the Run bit is set, a device reset will occur. The DCD must monitor the reset event and adjust the software state as described in the Bus Reset section of the following Port State and Control section below. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 412 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R R A Remark: Endpoint 0 is designed as a control endpoint only and does not need to be configured using ENDPTCTRL0 register. R A A FT D R A FT It is also not necessary to initially prime Endpoint 0 because the first packet received will always be a setup packet. The contents of the first setup packet will require a response in accordance with USB device framework command set (see USB Specification Rev. 2.0, chapter 9). D D R A R A FT D R FT D R A F R A FT D FT D R A D FT R A 20.10.2 Port state and control From a chip or system reset, the device controller enters the powered state. A transition from the powered state to the attach state occurs when the Run/Stop bit is set to a ‘1’. After receiving a reset on the bus, the port will enter the defaultFS or defaultHS state in accordance with the reset protocol described in Appendix C.2 of the USB Specification Rev. 2.0. The following state diagram depicts the state of a USB 2.0 device. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 413 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R R A D R A R A FT D R FT D R A R A FT A active state F FT D R A D R A FT D R D FT powered set Run/Stop bit to Run mode power interruption attach inactive state A FT D R A reset bus inactive default FS/HS when the host resets, the device returns to default state Su spend FS/HS bus activity address asigned bus inactive address FS/HSS bus activity suspend FS/HS device deconfigured device configured bus inactive configured FS/HS software only state bus activity suspend FS/HS Fig 39. Device state diagram The states powered, attach, default FS/HS, suspend FS/HS are implemented in the device controller and are communicated to the DCD using the following status bits: • • • • DCSuspend - see Table 309. USB reset received - see Table 309. Port change detect - see Table 309. High-speed port - see Table 326. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 414 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R R A It is the responsibility of the DCD to maintain a state variable to differentiate between the DefaultFS/HS state and the Address/Configured states. Change of state from Default to Address and the configured states is part of the enumeration process described in the device framework section of the USB 2.0 Specification. R A As a result of entering the Address state, the device address register (DEVICEADDR) must be programmed by the DCD. Entry into the Configured indicates that all endpoints to be used in the operation of the device have been properly initialized by programming the ENDPTCTRLx registers and initializing the associated queue heads. D R A R A FT D R FT D R A A FT D R A R A FT F FT D R A FT D D R A FT D 20.10.3 Bus reset A bus reset is used by the host to initialize downstream devices. When a bus reset is detected, the device controller will renegotiate its attachment speed, reset the device address to 0, and notify the DCD by interrupt (assuming the USB Reset Interrupt Enable is set). After a reset is received, all endpoints (except endpoint 0) are disabled and any primed transactions will be cancelled by the device controller. The concept of priming will be clarified below, but the DCD must perform the following tasks when a reset is received: • Clear all setup token semaphores by reading the ENDPTSETUPSTAT register and writing the same value back to the ENDPTSETUPSTAT register. • Clear all the endpoint complete status bits by reading the ENDPTCOMPLETE register and writing the same value back to the ENDPTCOMPLETE register. • Cancel all primed status by waiting until all bits in the ENDPTPRIME are 0 and then writing 0xFFFFFFFF to ENDPTFLUSH. • Read the reset bit in the PORTSCx register and make sure that it is still active. A USB reset will occur for a minimum of 3 ms and the DCD must reach this point in the reset cleanup before end of the reset occurs, otherwise a hardware reset of the device controller is recommended (rare). Remark: A hardware reset can be performed by writing a one to the device controller reset bit in the USBCMD reset. Note: a hardware reset will cause the device to detach from the bus by clearing the Run/Stop bit. Thus, the DCD must completely re-initialize the device controller after a hardware reset. • Free all allocated dTDs because they will no longer be executed by the device controller. If this is the first time the DCD is processing a USB reset event, then it is likely that no dTDs have been allocated. At this time, the DCD may release control back to the OS because no further changes to the device controller are permitted until a Port Change Detect is indicated. • After a Port Change Detect, the device has reached the default state and the DCD can read the PORTSCx to determine if the device is operating in FS or HS mode. At this time, the device controller has reached normal operating mode and DCD can begin enumeration according to the USB2.0 specification Chapter 9 - Device Framework. Remark: The device DCD may use the FS/HS mode information to determine the bandwidth mode of the device. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 415 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R R A In some applications, it may not be possible to enable one or more pipes while in FS mode. Beyond the data rate issue, there is no difference in DCD operation between FS and HS modes. R A FT D R A D R A R A FT D R FT D R A F D R A FT D A FT FT 20.10.4 Suspend/resume 20.10.4.1 Suspend In order to conserve power, USB devices automatically enter the suspended state when the device has observed no bus traffic for a specified period. When suspended, the USB device maintains any internal status, including its address and configuration. Attached devices must be prepared to suspend at any time they are powered, regardless of if they have been assigned a non-default address, are configured, or neither Bus activity may cease due to the host entering a suspend mode of its own. In addition, a USB device shall also enter the suspended state when the hub port it is attached to is disabled. A USB device exits suspend mode when there is bus activity. A USB device may also request the host to exit suspend mode or selective suspend by using electrical signaling to indicate remote wake-up. The ability of a device to signal remote wake-up is optional. If the USB device is capable of remote wake-up signaling, the device must support the ability of the host to enable and disable this capability. When the device is reset, remote wake-up signaling must be disabled. 20.10.4.1.1 Operational model The device controller moves into the suspend state when suspend signaling is detected or activity is missing on the upstream port for more than a specific period. After the device controller enters the suspend state, the DCD is notified by an interrupt (assuming DC Suspend Interrupt is enabled). When the DCSuspend bit in the PORTSCx is set to a ‘1’, the device controller is suspended. DCD response when the device controller is suspended is application specific and may involve switching to low power operation. Information on the bus power limits in suspend state can be found in USB 2.0 specification. D R A FT D R A 20.10.4.2 Resume If the device controller is suspended, its operation is resumed when any non-idle signaling is received on its upstream facing port. In addition, the device can signal the system to resume operation by forcing resume signaling to the upstream port. Resume signaling is sent upstream by writing a ‘1’ to the Resume bit in the in the PORTSCx while the device is in suspend state. Sending resume signal to an upstream port should cause the host to issue resume signaling and bring the suspended bus segment (one more devices) back to the active condition. Remark: Before resume signaling can be used, the host must enable it by using the Set Feature command defined in device framework (chapter 9) of the USB 2.0 Specification. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 416 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R A D R A R A FT D R FT 20.10.5 Managing endpoints D R The USB 2.0 specification defines an endpoint, also called a device endpoint or an address endpoint as a uniquely addressable portion of a USB device that can source or sink data in a communications channel between the host and the device. The endpoint address is specified by the combination of the endpoint number and the endpoint direction. D R A FT The channel between the host and an endpoint at a specific device represents a data pipe. Endpoint 0 for a device is always a control type data channel used for device discovery and enumeration. Other types of endpoints support by USB include bulk, interrupt, and isochronous. Each endpoint type has specific behavior related to packet response and error handling. More detail on endpoint operation can be found in the USB 2.0 specification. The LPC18xx supports up to six endpoints. Each endpoint direction is essentially independent and can be configured with differing behavior in each direction. For example, the DCD can configure endpoint 1-IN to be a bulk endpoint and endpoint 1- OUT to be an isochronous endpoint. This helps to conserve the total number of endpoints required for device operation. The only exception is that control endpoints must use both directions on a single endpoint number to function as a control endpoint. Endpoint 0 is, for example, is always a control endpoint and uses the pair of directions. Each endpoint direction requires a queue head allocated in memory. If the maximum of 4 endpoint numbers, one for each endpoint direction are being used by the device controller, then 8 queue heads are required. The operation of an endpoint and use of queue heads are described later in this document. R A FT R A F D R A FT D R A FT D R A A FT D 20.10.5.1 Endpoint initialization After hardware reset, all endpoints except endpoint zero are un-initialized and disabled. The DCD must configure and enable each endpoint by writing to configuration bit in the ENDPTCTRLx register (see Table 338). Each 32-bit ENDPTCTRLx is split into an upper and lower half. The lower half of ENDPTCTRLx is used to configure the receive or OUT endpoint and the upper half is likewise used to configure the corresponding transmit or IN endpoint. Control endpoints must be configured the same in both the upper and lower half of the ENDPTCTRLx register otherwise the behavior is undefined. The following table shows how to construct a configuration word for endpoint initialization. Table 347. Device controller endpoint initialization Field Value Data Toggle Reset Data Toggle Inhibit Endpoint Type 1 0 00 - control 01 - isochronous 10 - bulk 11 - interrupt Endpoint Stall 0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 417 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R A D R A R A FT D R FT 20.10.5.2 Stalling D R There are two occasions where the device controller may need to return to the host a STALL: FT D R A 1. The first occasion is the functional stall, which is a condition set by the DCD as described in the USB 2.0 device framework (chapter 9). A functional stall is only used on non-control endpoints and can be enabled in the device controller by setting the endpoint stall bit in the ENDPTCTRLx register associated with the given endpoint and the given direction. In a functional stall condition, the device controller will continue to return STALL responses to all transactions occurring on the respective endpoint and direction until the endpoint stall bit is cleared by the DCD. 2. A protocol stall, unlike a function stall, is used on control endpoints is automatically cleared by the device controller at the start of a new control transaction (setup phase). When enabling a protocol stall, the DCD should enable the stall bits (both directions) as a pair. A single write to the ENDPTCTRLx register can ensure that both stall bits are set at the same instant. Remark: Any write to the ENDPTCTRLx register during operational mode must preserve the endpoint type field (i.e. perform a read-modify-write). Table 348. Device controller stall response matrix USB packet Endpoint STALL bit Effect on STALL bit USB response R A R A F D R A FT D R A FT D R A A FT D FT SETUP packet received by a non-control endpoint. IN/OUT/PING packet received by a non-control endpoint. IN/OUT/PING packet received by a non-control endpoint. IN/OUT/PING packet received by a control endpoint. IN/OUT/PING packet received by a control endpoint. N/A 1 0 None None None Cleared None None STALL STALL ACK/NAK/NYET ACK STALL ACK/NAK/NYET SETUP packet received by a control endpoint. N/A 1 0 20.10.5.3 Data toggle Data toggle is a mechanism to maintain data coherency between host and device for any given data pipe. For more information on data toggle, refer to the USB 2.0 specification. 20.10.5.3.1 Data toggle reset The DCD may reset the data toggle state bit and cause the data toggle sequence to reset in the device controller by writing a ‘1’ to the data toggle reset bit in the ENDPTCTRLx register. This should only be necessary when configuring/initializing an endpoint or returning from a STALL condition. 20.10.5.3.2 Data toggle inhibit Remark: This feature is for test purposes only and should never be used during normal device controller operation. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 418 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R R A Setting the data toggle Inhibit bit active (‘1’) causes the device controller to ignore the data toggle pattern that is normally sent and accept all incoming data packets regardless of the data toggle state. In normal operation, the device controller checks the DATA0/DATA1 bit against the data toggle to determine if the packet is valid. If Data PID does not match the data toggle state bit maintained by the device controller for that endpoint, the Data toggle is considered not valid. If the data toggle is not valid, the device controller assumes the packet was already received and discards the packet (not reporting it to the DCD). To prevent the host controller from re-sending the same packet, the device controller will respond to the error packet by acknowledging it with either an ACK or NYET response. R A A FT D R A FT D D R A R A FT D R FT D R A F R A FT D FT D R A D FT R A 20.10.6 Operational model for packet transfers All transactions on the USB bus are initiated by the host and in turn, the device must respond to any request from the host within the turnaround time stated in the USB 2.0 Specification. At USB 1.1 Full or Low Speed rates, this turnaround time was significant and the USB 1.1 device controllers were designed so that the device controller could access main memory or interrupt a host protocol processor in order to respond to the USB 1.1 transaction. The architecture of the USB 2.0 device controller must be different because same methods will not meet USB 2.0 High-speed turnaround time requirements by simply increasing clock rate. A USB host will send requests to the device controller in an order that can not be precisely predicted as a single pipeline, so it is not possible to prepare a single packet for the device controller to execute. However, the order of packet requests is predictable when the endpoint number and direction is considered. For example, if endpoint 3 (transmit direction) is configured as a bulk pipe, then we can expect the host will send IN requests to that endpoint. This device controller is designed in such a way that it can prepare packets for each endpoint/direction in anticipation of the host request. The process of preparing the device controller to send or receive data in response to host initiated transaction on the bus is referred to as “priming” the endpoint. This term will be used throughout the following documentation to describe the device controller operation so the DCD can be designed properly to use priming. Further, note that the term “flushing” is used to describe the action of clearing a packet that was queued for execution. 20.10.6.1 Priming transmit endpoints Priming a transmit endpoint will cause the device controller to fetch the device transfer descriptor (dTD) for the transaction pointed to by the device queue head (dQH). After the dTD is fetched, it will be stored in the dQH until the device controller completes the transfer described by the dTD. Storing the dTD in the dQH allows the device controller to fetch the operating context needed to handle a request from the host without the need to follow the linked list, starting at the dQH when the host request is received. After the device has loaded the dTD, the leading data in the packet is stored in a FIFO in the device controller. This FIFO is split into virtual channels so that the leading data can be stored for any endpoint up to four endpoints. After a priming request is complete, an endpoint state of primed is indicated in the ENDPTSTATUS register. For a primed transmit endpoint, the device controller can respond to an IN request from the host and meet the stringent bus turnaround time of High Speed USB. Since only the leading data is stored in the device controller FIFO, it is necessary for the device controller to begin filling in behind leading data after the All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 419 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R R A transaction starts. The FIFO must be sized to account for the maximum latency that can be incurred by the system memory bus. On the LPC18xx, 128 x 36 bit dual port memory FIFOs are used for each IN endpoint. R A A FT D R A FT D R A R A FT D R FT D R A F R A FT D FT 20.10.6.2 Priming receive endpoints D Priming receive endpoints is identical to priming of transmit endpoints from the point of view of the DCD. At the device controller the major difference in the operational model is that there is no data movement of the leading packet data simply because the data is to be received from the host. Note as part of the architecture, the FIFO for the receive endpoints is not partitioned into multiple channels like the transmit FIFO. Thus, the size of the RX FIFO does not scale with the number of endpoints. D R A FT D R A 20.10.7 Interrupt/bulk endpoint operational model The behaviors of the device controller for interrupt and bulk endpoints are identical. All valid IN and OUT transactions to bulk pipes will handshake with a NAK unless the endpoint had been primed. Once the endpoint has been primed, data delivery will commence. A dTD will be retired by the device controller when the packets described in the transfer descriptor have been completed. Each dTD describes N packets to be transferred according to the USB Variable Length transfer protocol. The formula and table on the following page describe how the device controller computes the number and length of the packets to be sent/received by the USB vary according to the total number of bytes and maximum packet length. With Zero Length Termination (ZLT) = 0 N = INT(Number Of Bytes/Max. Packet Length) + 1 With Zero Length Termination (ZLT) = 1 N = MAXINT(Number Of Bytes/Max. Packet Length) Table 349. Variable length transfer protocol example (ZLT = 0) Bytes (dTD) Max Packet Length (dQH) N P1 P2 P3 511 512 512 256 256 512 2 3 2 256 256 512 255 256 0 0 - Table 350. Variable length transfer protocol example (ZLT = 1) Bytes (dTD) Max Packet N Length (dQH) P1 P2 P3 511 512 512 256 256 512 2 2 1 256 256 512 255 256 - - Remark: The MULT field in the dQH must be set to “00” for bulk, interrupt, and control endpoints. TX-dTD is complete when all packets described dTD were successfully transmitted.Total bytes in dTD will equal zero when this occurs. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 420 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R A D R A R A FT D R FT RX-dTD is complete when: zero when this occurs. D R • All packets described in dTD were successfully received. Total bytes in dTD will equal • A short packet (number of bytes < maximum packet length) was received. This is a D R A FT D successful transfer completion; DCD must check Total Bytes in dTD to determine the number of bytes that are remaining. From the total bytes remaining in the dTD, the DCD can compute the actual bytes received. received > total bytes specified). This is an error condition. The device controller will discard the remaining packet, and set the Buffer Error bit in the dTD. In addition, the endpoint will be flushed and the USBERR interrupt will become active. • A long packet was received (number of bytes > maximum packet size) OR (total bytes On the successful completion of the packet(s) described by the dTD, the active bit in the dTD will be cleared and the next pointer will be followed when the Terminate bit is clear. When the Terminate bit is set, the device controller will flush the endpoint/direction and cease operations for that endpoint/direction. On the unsuccessful completion of a packet (see long packet above), the dQH will be left pointing to the dTD that was in error. In order to recover from this error condition, the DCD must properly reinitialize the dQH by clearing the active bit and update the nextTD pointer before attempting to re-prime the endpoint. Remark: All packet level errors such as a missing handshake or CRC error will be retried automatically by the device controller. There is no required interaction with the DCD for handling such errors. R A FT R A F D R A FT D R A FT D R A A FT 20.10.7.1 Interrupt/bulk endpoint bus response matrix Table 351. Interrupt/bulk endpoint bus response matrix Token type STALL Not primed Primed Underflow Overflow Setup In Out Ping Invalid [1] [2] [3] Ignore STALL STALL STALL Ignore Ignore NAK NAK NAK Ignore Ignore Transmit Receive and NYET/ACK ACK Ignore n/a BS error n/a n/a Ignore n/a n/a NAK n/a Ignore BS error = Force Bit Stuff Error NYET/ACK – NYET unless the Transfer Descriptor has packets remaining according to the USB variable length protocol then ACK. SYSERR – System error should never occur when the latency FIFOs are correctly sized and the DCD is responsive. 20.10.8 Control endpoint operational model 20.10.8.1 Setup phase All requests to a control endpoint begin with a setup phase followed by an optional data phase and a required status phase. The device controller will always accept the setup phase unless the setup lockout is engaged. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 421 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R R A The setup lockout will engage so that future setup packets are ignored. Lockout of setup packets ensures that while software is reading the setup packet stored in the queue head, that data is not written as it is being read potentially causing an invalid setup packet. R A In hardware the setup lockout mechanism can be disabled and a new tripwire type semaphore will ensure that the setup packet payload is extracted from the queue head without being corrupted by an incoming setup packet. This is the preferred behavior because ignoring repeated setup packets due to long software interrupt latency would be a compliance issue. D D R A R A FT D R FT D R A A FT D R A R A FT F FT D R A FT FT D D R A 20.10.8.1.1 Setup Packet Handling using setup lockout mechanism After receiving an interrupt and inspecting USBMODE to determine that a setup packet was received on a particular pipe: 1. Duplicate contents of dQH.SsetupBuffer into local software byte array. 2. Write '1' to clear corresponding ENDPTSETUPSTAT bit and thereby disabling Setup Lockout (i.e. the Setup Lockout activates as soon as a setup arrives. By writing to the ENDPTSETUPSTAT, the device controller will accept new setup packets.). 3. Process setup packet using local software byte array copy and execute status/handshake phases. Remark: After receiving a new setup packet the status and/or handshake phases may still be pending from a previous control sequence. These should be flushed & deallocated before linking a new status and/or handshake dTD for the most recent setup packet. 4. Before priming for status/handshake phases ensure that ENDPTSETUPSTAT is ‘0’. The time from writing a ‘1’ to ENDPTSETUPSTAT and reading back a ‘0’ may vary according to the type of traffic on the bus up to nearly a 1ms, however the it is absolutely necessary to ensure ENDPTSETUPSTAT has transitioned to ‘0’ after step 1) and before priming for the status/handshake phases. Remark: To limit the exposure of setup packets to the setup lockout mechanism (if used), the DCD should designate the priority of responding to setup packets above responding to other packet completions 20.10.8.1.2 Setup Packet Handling using trip wire mechanism • Disable Setup Lockout by writing ‘1’ to Setup Lockout Mode (SLOM) in USBMODE. (once at initialization). Setup lockout is not necessary when using the tripwire as described below. Remark: Leaving the Setup Lockout Mode As ‘0’ will result in pre-2.3 hardware behavior. • After receiving an interrupt and inspecting ENDPTSETUPSTAT to determine that a setup packet was received on a particular pipe: a. Write '1' to clear corresponding bit ENDPTSETUPSTAT. b. Duplicate contents of dQH.SetupBuffer into local software byte array. c. Write ‘1’ to Setup Tripwire (SUTW) in USBCMD register. d. Read Setup TripWire (SUTW) in USBCMD register. (if set - continue; if cleared - go to b). e. Write '0' to clear Setup Tripwire (SUTW) in USBCMD register. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 422 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R R A f. Process setup packet using local software byte array copy and execute status/handshake phases. g. Before priming for status/handshake phases ensure that ENDPTSETUPSTAT is ‘0’. R A • A poll loop should be used to wait until ENDPTSETUPSTAT transitions to ‘0’ after step a) above and before priming for the status/handshake phases. • The time from writing a ‘1’ to ENDPTSETUPSTAT and reading back a ‘0’ is very short (~1-2 us) so a poll loop in the DCD will not be harmful. Remark: After receiving a new setup packet the status and/or handshake phases may still be pending from a previous control sequence. These should be flushed & deallocated before linking a new status and/or handshake dTD for the most recent setup packet. D R A R A FT D R FT D R A R A FT D D FT D R A A FT F R A FT D FT D R A 20.10.8.2 Data phase Following the setup phase, the DCD must create a device transfer descriptor for the data phase and prime the transfer. After priming the packet, the DCD must verify a new setup packet has not been received by reading the ENDPTSETUPSTAT register immediately verifying that the prime had completed. A prime will complete when the associated bit in the ENDPTPRIME register is zero and the associated bit in the ENDPTSTATUS register is a one. If a prime fails, i.e. The ENDPTPRIME bit goes to zero and the ENDPTSTATUS bit is not set, then the prime has failed. This can only be due to improper setup of the dQH, dTD or a setup arriving during the prime operation. If a new setup packet is indicated after the ENDPTPRIME bit is cleared, then the transfer descriptor can be freed and the DCD must reinterpret the setup packet. Should a setup arrive after the data stage is primed, the device controller will automatically clear the prime status (ENDPTSTATUS) to enforce data coherency with the setup packet. Remark: The MULT field in the dQH must be set to “00” for bulk, interrupt, and control endpoints. Remark: Error handling of data phase packets is the same as bulk packets described previously. 20.10.8.3 Status phase Similar to the data phase, the DCD must create a transfer descriptor (with byte length equal zero) and prime the endpoint for the status phase. The DCD must also perform the same checks of the ENDPTSETUPSTAT as described above in the data phase. Remark: The MULT field in the dQH must be set to “00” for bulk, interrupt, and control endpoints. Remark: Error handling of data phase packets is the same as bulk packets described previously. 20.10.8.4 Control endpoint bus response matrix Shown in the following table is the device controller response to packets on a control endpoint according to the device controller state. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 423 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R A D R A R A FT D R FT D Table 352. Control endpoint bus response matrix Token type Endpoint sate STALL Not primed Primed Underflow Overflow R Setup lockout R A FT D R R A F D R A FT A FT A FT D D Setup In Out Ping Invalid [1] [2] [3] ACK ACK ACK Transmit Receive and NYET/ACK ACK Ignore n/a BS error n/a n/a Ignore SYSERR n/a NAK n/a Ignore n/a n/a n/a ignore R A FT STALL NAK STALL NAK STALL NAK Ignore Ignore D R A BS error = Force Bit Stuff Error NYET/ACK – NYET unless the Transfer Descriptor has packets remaining according to the USB variable length protocol then ACK. SYSERR – System error should never occur when the latency FIFOs are correctly sized and the DCD is responsive. 20.10.9 Isochronous endpoint operational model Isochronous endpoints are used for real-time scheduled delivery of data, and their operational model is significantly different than the host throttled Bulk, Interrupt, and Control data pipes. Real time delivery by the device controller is accomplished by the following: • Exactly MULT Packets per (micro) Frame are transmitted/received. Note: MULT is a two-bit field in the device Queue Head. The variable length packet protocol is not used on isochronous endpoints. • NAK responses are not used. Instead, zero length packets are sent in response to an IN request to an unprimed endpoints. For unprimed RX endpoints, the response to an OUT transaction is to ignore the packet within the device controller. • Prime requests always schedule the transfer described in the dTD for the next (micro) frame. If the ISO-dTD is still active after that frame, then the ISO-dTD will be held ready until executed or canceled by the DCD. An EHCI compatible host controller uses the periodic frame list to schedule data exchanges to Isochronous endpoints. The operational model for device mode does not use such a data structure. Instead, the same dTD used for Control/Bulk/Interrupt endpoints is also used for isochronous endpoints. The difference is in the handling of the dTD. The first difference between bulk and ISO-endpoints is that priming an ISO-endpoint is a delayed operation such that an endpoint will become primed only after a SOF is received. After the DCD writes the prime bit, the prime bit will be cleared as usual to indicate to software that the device controller completed a priming the dTD for transfer. Internal to the design, the device controller hardware masks that prime start until the next frame boundary. This behavior is hidden from the DCD but occurs so that the device controller can match the dTD to a specific (micro) frame. Another difference with isochronous endpoints is that the transaction must wholly complete in a (micro) frame. Once an ISO transaction is started in a (micro) frame it will retire the corresponding dTD when MULT transactions occur or the device controller finds All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 424 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R R A a fulfillment condition. The transaction error bit set in the status field indicates a fulfillment error condition. When a fulfillment error occurs, the frame after the transfer failed to complete wholly, the device controller will force retire the ISO-dTD and move to the next ISO-dTD. R A It is important to note that fulfillment errors are only caused due to partially completed packets. If no activity occurs to a primed ISO-dTD, the transaction will stay primed indefinitely. This means it is up to software discard transmit ISO-dTDs that pile up from a failure of the host to move the data. Finally, the last difference with ISO packets is in the data level error handling. When a CRC error occurs on a received packet, the packet is not retried similar to bulk and control endpoints. Instead, the CRC is noted by setting the Transaction Error bit and the data is stored as usual for the application software to sort out. TX packet retired D R A R A FT D R FT D R A A FT D R A R A FT F FT D R A FT D D R A FT D • MULT counter reaches zero. • Fulfillment Error [Transaction Error bit is set]. • # Packets Occurred > 0 AND # Packets Occurred < MULT. Remark: For TX-ISO, MULT Counter can be loaded with a lesser value in the dTD Multiplier Override field. If the Multiplier Override is zero, the MULT Counter is initialized to the Multiplier in the QH. RX packet retired • MULT counter reaches zero. • Non-MDATA Data PID is received. Remark: Exit criteria only valid in hardware version 2.3 or later. Previous to hardware version 2.3, any PID sequence that did not match the MULT field exactly would be flagged as a transaction error due to PID mismatch or fulfillment error. • Overflow Error: – Packet received is > maximum packet length. [Buffer Error bit is set]. – Packet received exceeds total bytes allocated in dTD. [Buffer Error bit is set]. • Fulfillment error [Transaction Error bit is set]: # Packets Occurred > 0 AND # Packets Occurred < MULT. • CRC Error [Transaction Error bit is set] Remark: For ISO, when a dTD is retired, the next dTD is primed for the next frame. For continuous (micro) frame to (micro) frame operation the DCD should ensure that the dTD linked-list is out ahead of the device controller by at least two (micro) frames. 20.10.9.1 Isochronous pipe synchronization When it is necessary to synchronize an isochronous data pipe to the host, the (micro) frame number (FRINDEX register) can be used as a marker. To cause a packet transfer to occur at a specific (micro) frame number [N], the DCD should interrupt on SOF during frame N-1. When the FRINDEX=N–1, the DCD must write the prime bit. The device controller will prime the isochronous endpoint in (micro) frame N–1 so that the device controller will execute delivery during (micro) frame N. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 425 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R R A Remark: Priming an endpoint towards the end of (micro) frame N-1 will not guarantee delivery in (micro) frame N. The delivery may actually occur in (micro) frame N+1 if device controller does not have enough time to complete the prime before the SOF for packet N is received. R A A FT D R A FT D D R A R A FT D R FT D R A F R A FT D D FT R 20.10.9.2 Isochronous endpoint bus response matrix Table 353. Isochronous endpoint bus response matrix Token type STALL Not primed Primed Underflow Overflow A FT D R A Setup In Out Ping Invalid [1] [2] STALL NULL packet Ignore Ignore Ignore STALL NULL packet Ignore Ignore Ignore STALL Transmit Receive Ignore Ignore n/a BS error n/a Ignore Ignore n/a n/a Drop packet Ignore Ignore BS error = Force Bit Stuff Error NULL packet = Zero length packet. 20.10.10 Managing queue heads Endpoint Queue Heads dQH Endpoint Transfer Descriptors dTD transfer buffer pointer Endpoint dQH1 - Out Endpoint dQH0 - In Endpoint dQH0 - Out dTD dTD dTD transfer buffer pointer dTD transfer buffer pointer TRANSFER BUFFER TRANSFER BUFFER transfer buffer pointer TRANSFER BUFFER TRANSFER BUFFER ENDPOINTLISTADDR Fig 40. Endpoint queue head diagram The device queue head (dQH) points to the linked list of transfer tasks, each depicted by the device Transfer Descriptor (dTD). An area of memory pointed to by ENDPOINTLISTADDR contains a group of all dQH’s in a sequential list as shown Figure 40. The even elements in the list of dQH’s are used for receive endpoints (OUT/SETUP) and the odd elements are used for transmit endpoints (IN/INTERRUPT). Device transfer descriptors are linked head to tail starting at the queue head and ending at a terminate bit. Once the dTD has been retired, it will no longer be part of the linked list All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 426 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R R A from the queue head. Therefore, software is required to track all transfer descriptors since pointers will no longer exist within the queue head once the dTD is retired (see Section 20.10.11.1). R A In addition to the current and next pointers and the dTD overlay examined in section Operational Model For Packet Transfers, the dQH also contains the following parameters for the associated endpoint: Multiplier, Maximum Packet Length, Interrupt On Setup. The complete initialization of the dQH including these fields is demonstrated in the next section. D D R A R A FT D R FT D R A A FT D R A R A FT F FT D R A FT FT D D R A 20.10.10.1 Queue head initialization One pair of device queue heads must be initialized for each active endpoint. To initialize a device queue head: • Write the wMaxPacketSize field as required by the USB Chapter 9 or application specific protocol. • Write the multiplier field to 0 for control, bulk, and interrupt endpoints. For ISO endpoints, set the multiplier to 1,2, or 3 as required bandwidth and in conjunction with the USB Chapter 9 protocol. Note: In FS mode, the multiplier field can only be 1 for ISO endpoints. • Write the next dTD Terminate bit field to “1”. • Write the Active bit in the status field to “0”. • Write the Halt bit in the status field to “0”. Remark: The DCD must only modify dQH if the associated endpoint is not primed and there are no outstanding dTD’s. 20.10.10.2 Operational model for setup transfers As discussed in section Control Endpoint Operational Model (Section 20.10.8), setup transfer requires special treatment by the DCD. A setup transfer does not use a dTD but instead stores the incoming data from a setup packet in an 8-byte buffer within the dQH. Upon receiving notification of the setup packet, the DCD should handle the setup transfer as demonstrated here: 1. Copy setup buffer contents from dQH - RX to software buffer. 2. Acknowledge setup backup by writing a “1” to the corresponding bit in ENDPTSETUPSTAT. Remark: The acknowledge must occur before continuing to process the setup packet. Remark: After the acknowledge has occurred, the DCD must not attempt to access the setup buffer in the dQH – RX. Only the local software copy should be examined. 3. Check for pending data or status dTD’s from previous control transfers and flush if any exist as discussed in section Flushing/De-priming an Endpoint. Remark: It is possible for the device controller to receive setup packets before previous control transfers complete. Existing control packets in progress must be flushed and the new control packet completed. 4. Decode setup packet and prepare data phase [optional] and status phase transfer as require by the USB Specification Chapter 9 or application specific protocol. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 427 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R A D R A R A FT D R FT 20.10.11 Managing transfers with transfer descriptors 20.10.11.1 Software link pointers D R It is necessary for the DCD software to maintain head and tail pointers to the linked list of dTDs for each respective queue head. This is necessary because the dQH only maintains pointers to the current working dTD and the next dTD to be executed. The operations described in next section for managing dTD will assume the DCD can use reference the head and tail of the dTD linked list. Remark: To conserve memory, the reserved fields at the end of the dQH can be used to store the Head & Tail pointers but it still remains the responsibility of the DCD to maintain the pointers. FT D R A FT D R R A F D R A FT D R A FT D R A A FT A Head Pointer Endpoint QH current Tail Pointer next completed dTDs queued dTDs Fig 41. Software link pointers 20.10.11.2 Building a transfer descriptor Before a transfer can be executed from the linked list, a dTD must be built to describe the transfer. Use the following procedure for building dTDs: Allocate 8-DWord dTD block of memory aligned to 8-DWord boundaries. Example: bit address 4:0 would be equal to “00000”. Write the following fields: 1. Initialize first 7 DWords to 0. 2. Set the terminate bit to “1”. 3. Fill in total bytes with transfer size. 4. Set the interrupt on complete if desired. 5. Initialize the status field with the active bit set to “1” and all remaining status bits set to “0”. 6. Fill in buffer pointer page 0 and the current offset to point to the start of the data buffer. 7. Initialize buffer pointer page 1 through page 4 to be one greater than each of the previous buffer pointer. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 428 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R A D R A R A FT D R FT 20.10.11.3 Executing a transfer descriptor D R To safely add a dTD, the DCD must follow this procedure which will handle the event where the device controller reaches the end of the dTD list at the same time a new dTD is being added to the end of the list. FT D R A FT D Determine whether the link list is empty: Check DCD driver to see if pipe is empty (internal representation of linked-list should indicate if any packets are outstanding). Link list is empty 1. Write dQH next pointer AND dQH terminate bit to 0 as a single DWord operation. 2. Clear active and halt bits in dQH (in case set from a previous error). 3. Prime endpoint by writing ‘1’ to correct bit position in ENDPTPRIME. Link list is not empty 1. Add dTD to end of the linked list. 2. Read correct prime bit in ENDPTPRIME – if ‘1’ DONE. 3. Set ATDTW bit in USBCMD register to ‘1’. 4. Read correct status bit in ENDPTSTAT. (Store in temp variable for later). 5. Read ATDTW bit in USBCMD register. – If ‘0’ go to step 3. – If ‘1’ continue to step 6. 6. Write ATDTW bit in USBCMD register to ‘0’. 7. If status bit read in step 4 (ENDPSTAT reg) indicates endpoint priming is DONE (corresponding ERBRx or ETBRx is one): DONE. 8. If status bit read in step 4 is 0 then go to Linked list is empty: Step 1. R A R A F D R A FT D FT D R A R A A FT 20.10.11.4 Transfer completion After a dTD has been initialized and the associated endpoint primed the device controller will execute the transfer upon the host-initiated request. The DCD will be notified with a USB interrupt if the Interrupt On Complete bit was set or alternately, the DCD can poll the endpoint complete register to find when the dTD had been executed. After a dTD has been executed, DCD can check the status bits to determine success or failure. Remark: Multiple dTD can be completed in a single endpoint complete notification. After clearing the notification, DCD must search the dTD linked list and retire all dTDs that have finished (Active bit cleared). By reading the status fields of the completed dTDs, the DCD can determine if the transfers completed successfully. Success is determined with the following combination of status bits: Active = 0 Halted = 0 Transaction Error = 0 Data Buffer Error = 0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 429 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R R A Should any combination other than the one shown above exist, the DCD must take proper action. Transfer failure mechanisms are indicated in the Device Error Matrix (see Table 354). R A In addition to checking the status bit, the DCD must read the Transfer Bytes field to determine the actual bytes transferred. When a transfer is complete, the Total Bytes transferred is decremented by the actual bytes transferred. For Transmit packets, a packet is only complete after the actual bytes reaches zero, but for receive packets, the host may send fewer bytes in the transfer according the USB variable length packet protocol. D R A R A FT D R FT D R A A FT D R A R A FT F FT D R A FT D FT D D R A 20.10.11.5 Flushing/De-priming an endpoint It is necessary for the DCD to flush to de-prime one more endpoints on a USB device reset or during a broken control transfer. There may also be application specific requirements to stop transfers in progress. The following procedure can be used by the DCD to stop a transfer in progress: 1. Write a ‘1’ to the corresponding bit(s) in ENDPTFLUSH. 2. Wait until all bits in ENDPTFLUSH are ‘0’. Remark: Software note: This operation may take a large amount of time depending on the USB bus activity. It is not desirable to have this wait loop within an interrupt service routine. 3. Read ENDPTSTAT to ensure that for all endpoints commanded to be flushed, that the corresponding bits are now ‘0’. If the corresponding bits are ‘1’ after step #2 has finished, then the flush failed as described in the following: In very rare cases, a packet is in progress to the particular endpoint when commanded flush using ENDPTFLUSH. A safeguard is in place to refuse the flush to ensure that the packet in progress completes successfully. The DCD may need to repeatedly flush any endpoints that fail to flush by repeating steps 1-3 until each endpoint is successfully flushed. 20.10.11.6 Device error matrix The Table 354 summarizes packet errors that are not automatically handled by the Device Controller. The following errors can occur: Overflow: Number of bytes received exceeded max. packet size or total buffer length. This error will also set the Halt bit in the dQH, and if there are dTDs remaining in the linked list for the endpoint, then those will not be executed. ISO packet error: CRC Error on received ISO packet. Contents not guaranteed to be correct. ISO fulfillment error: Host failed to complete the number of packets defined in the dQH mult field within the given (micro) frame. For scheduled data delivery the DCD may need to readjust the data queue because a fulfillment error will cause Device Controller to cease data transfers on the pipe for one (micro) frame. During the “dead” (micro) frame, the Device Controller reports error on the pipe and primes for the following frame All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 430 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R A D R A R A FT D R FT D Table 354. Device error matrix Error Direction Packet type R Data buffer error Transaction bit error bit R A FT D R R A F D R A A FT A Overflow ISO packet error ISO fulfillment error Rx Rx Both Any ISO ISO 1 0 0 0 1 1 FT D R A FT D R A FT D 20.10.12 Servicing interrupts The interrupt service routine must consider that there are high-frequency, low-frequency operations, and error operations and order accordingly. 20.10.12.1 High-frequency interrupts High frequency interrupts in particular should be handed in the order below. The most important of these is listed first because the DCD must acknowledge a setup buffer in the timeliest manner possible. Table 355. High-frequency interrupt events Execution order Interrupt Action 1a USB interrupt: Copy contents of setup buffer and acknowledge ENDPTSETUPSTATUS setup packet (as indicated in Section 20.10.10). [1] Process setup packet according to USB 2.0 Chapter 9 or application specific protocol. USB interrupt: ENDPTCOMPLETE[1] SOF interrupt Handle completion of dTD as indicated in Section 20.10.10. Action as deemed necessary by application. This interrupt may not have a use in all applications. 1b 2 [1] It is likely that multiple interrupts to stack up on any call to the Interrupt Service Routine AND during the Interrupt Service Routine. 20.10.12.2 Low-frequency interrupts The low frequency events include the following interrupts. These interrupt can be handled in any order since they don’t occur often in comparison to the high-frequency interrupts. Table 356. Low-frequency interrupt events Interrupt Action Port change Sleep enable (Suspend) Reset Received Change software state information. Change software state information. Low power handling as necessary. Change software state information. Abort pending transfers. 20.10.12.3 Error interrupts Error interrupts will be least frequent and should be placed last in the interrupt service routine. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 431 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R A D R A R A FT D R FT D Table 357. Error interrupt events Interrupt Action R R A FT D R A F D A FT USB error interrupt This error is redundant because it combines USB Interrupt and an error status in the dTD. The DCD will more aptly handle packet-level errors by checking dTD status field upon receipt of USB Interrupt (w/ ENDPTCOMPLETE). R R A A FT D R A FT FT D System error Unrecoverable error. Immediate Reset of core; free transfers buffers in progress and restart the DCD. D R A 20.11 USB power optimization The USB-HS core is a fully synchronous static design. The power used by the design is dependent on the implementation technology used to fabricate the design and on the application usage of the core. Applications that transfer more data or use a greater number of packets to be sent will consume a greater amount of power. Because the design is synchronous and static, power may be conserved by reducing the transitions of the clock net. This may be done in several ways. 1. Reduce the clock frequency to the core. The clock frequency may not be reduced below the minimum recommended operating frequency of the core without first disabling the USB operation. 2. Reduce transition on the clock net through the use of clock gating methods. (The LPC18xx is synthesized using this mechanism). 3. The clock may be shut off to the core entirely to conserve power. Again this may only be done after the USB operations on the bus have been disabled. A device may suspend operations autonomously by disconnecting from the USB, or, in response to the suspend signaling, the USB has moved it into the suspend state. A host can suspend operation autonomously, or it can command portions or the entire USB to transition into the suspend state. 20.11.1 USB power states The USB provides a mechanism to place segments of the USB or the entire USB into a low-power suspend state. USB bus powered devices are required to respond to a 3ms lack of activity on the USB bus by going into a suspend state. In the USB-HS core software is notified of the suspend condition via the transition in the PORTSC register. Optionally an interrupt can be generated which is controlled by the port change Detect Enable bit in the USBINTR control register. Software then has 7 ms to transition a bus powered device into the suspend state. In the suspend state, a USB device has a maximum USB bus power budget of 500A. In general, to achieve that level of power conservation, most of the device circuits will need to be switched off, or clock at an extremely low frequency. This can be accomplished by suspending the clock. The implementation of low power states in the USB-HS core is dependant on the use of the device role (host or peripheral), whether the device is bus powered, and the selected clock architecture of the core. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 432 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R R A Bus powered peripheral devices are required by the USB specification to support a low power suspend state. Self powered peripheral devices and hosts set their own power management strategies based on their system level requirements. The clocking architecture selected is important to consider as it determines what portions of the design will remain active when transitioned into the low power state. R A Before the system clock is suspended or set to a frequency that is below the operational frequency of the USB-HS core, the core must be moved from the operational state to a low power state. The power strategies designed into the USB-HS core allow for the most challenging case, a self powered device that is clocked entirely by the transceiver clock. D R A R A FT D R FT D R A A FT D R A R A FT F FT D R A FT D D R A FT D 20.11.2 Device power states A bus powered peripheral device must move through the power states as directed by the host. Optionally autonomously directed low power states may be implemented. Host directed Autonomous operational Low-power request resume interrupt received 3 ms idle prepare for Suspend SW sets Suspend bit SW sets Suspend bit disconnect user-defined wakeup Suspend disconnect Suspend Resume user-defined wakeup Lock power states (clock may be suspended) start Resume Fig 42. Device power state diagram In the operational state both the transceiver clock and system clocks are running. Software can initiate a low power mode autonomously by disconnecting from the host to go into the disconnect state. Once in this state, the software can set the Suspend bit to All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 433 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R R A turn off the transceiver clock putting the system in to the disconnect-suspend state. Since software cannot depend on the presents of a clock to clear the Suspend bit, a wake-up event must be defined which would clear the Suspend bit and allow the transceiver clock to resume. R A The device can also go into suspend mode as a result of a suspend command from the host. Suspend is signaled on the bus by 3ms of idle time on the bus. This will generate a suspend interrupt to the software at which point the software must prepare to go into suspend then set the suspend bit. Once the Suspend bit is set the transceiver clock may turn off and the device will be in the suspended state. The device has two ways of getting out of suspend. 1. If remote wake-up is enabled, a wake-up event could be defined which would clear the Suspend bit. The software would then initiate the resume by setting the Resume bit in the port controller then waiting for a port change interrupt indicating that the port is in an operational state. 2. If the host puts resume signaling on the bus, it will clear the Suspend bit and generate a port change interrupt when the resume is finished. In either case the system designer must insure an orderly restoration of the power and clocks to the suspended circuitry. D R A R A FT D R FT D R A A FT D R A R A FT F FT D R A FT D D R A FT D All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 434 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R A D R A R A FT D R FT 20.11.3 Host power states D R R A FT D R R A F D R A FT A FT A FT D D operational Low-power request all devices disconnected R A FT D R A signal Suspend disconnect wait for 3 ms SW sets Suspend bit user-defined wakeup Suspend disconnect Suspend user-defined wakeup connect interrupt Resume or Reset K-state on bus Lock power states (clock may be suspended) Wait Resume Fig 43. Host/OTG power state diagram From an operational state when a host gets a low power request, it must set the suspend bit in the port controller. This will put an idle on the bus, block all traffic through the port, and turn off the transceiver clock. There are two ways for a host controller to get out of the suspend state. If it has enabled remote wake-up, a K-state on the bus will turn the transceiver clock and generate an interrupt. The software will then have to wait 20 ms for the resume to complete and the port to go back to an active state. Alternatively an external event could clear the suspend bit and start the transceiver clock running again. The software can then initiate a resume by setting the resume bit in the port controller, or force a reconnect by setting the reset bit in the port controller. If all devices have disconnected from the host, the host can go into a low power mode by the software setting the suspend bit. From the disconnect-suspend state a connect event would start the transceiver clock and interrupt the software. The software would then need to set the reset bit to start the connect process. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 435 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 20: LPC18xx USB0 Host/Device/OTG controller FT D R A D R A R A FT D R FT 20.11.4 Susp_CTRL module D R The SUSP_CTRL module implements the power management logic of USB-OTG. It controls the suspend input of the transceiver. Asserting this suspend signal will put the transceiver in suspend mode and the generation of the 30 MHz clock and 60 MHz clock will be switched off. A suspend control input of the transceiver (otg_on) that was previously tied high and prevented the transceiver to go into full suspend mode, has been connected to . This bit is low by default and only needs to be set high in OTG Host mode operation. In suspend mode, the transceiver will raise an output signal indicating that the PLL generating the 480 MHz clock can be switched off. The SUSP_CTRL module also generates an output signal indicating whether the AHB clock is needed or not. If '0' the AHB clock is allowed to be switched off or reduced in frequency in order to save power. The core will enter the low power state if: D R A FT R A FT R A F D R A FT D A FT D R A R A FT D • Software sets the PORTSC.PHCD bit. When operating in host mode, the core will leave the low power state on one of the following conditions: • • • • • • • software clears the PORTSC.PHCD bit a device is connected and the PORTSC.WKCN bit is set a device is disconnected an the PORTSC.WKDC bit is set an over-current condition occurs and the PORTSC.WKOC bit is set a remote wake-up from the attached device occurs (when USB bus was in suspend) a change on vbusvalid occurs (= VBUS threshold at 4.4 V is crossed) a change on bvalid occurs (=VBUS threshold at 4.0 V is crossed). When operating in device mode, the core will leave the low power state on one of the following conditions: • • • • software clears the PORTSC.PHCD bit. a change on the USB data lines (dp/dm) occurs. a change on vbusvalid occurs (= VBUS threshold at 4.4 V is crossed). a change on bvalid occurs (= VBUS threshold at 4.0 V is crossed). The vbusvalid and bvalid signals coming from the transceiver are not filtered in the SUSP_CTRL module. Any change on those signals will cause a wake-up event. Input signals 'host_wakeup_n' and 'dev_wakeup_n' are extra external wake-up signals (for host mode and device mode respectively). However the detection of all USB related wake-up events is already handled in the SUSP_CTRL mode. Therefore in normal situations these signals can be tied high (= inactive). All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 436 of 1164 D R A FT D R A FT D R A FT D R A FT D R A FT UM10430 Rev. 00.13 — 20 July 2011 D D Chapter 21: LPC18xx USB1 Host/Device controller D R A FT D D R A FT D R A FT D R A FT D R R A FT D R A FT D A FT R A R A FT D R A FT D R A F R A FT D FT R User manual 21.1 How to read this chapter The USB1 Host/Device controller is available on parts LPC1850 and LPC1830. D D R A FT D R A 21.2 Basic configuration The USB1 controller is configured as follows: • See Table 358 for clocking and power control. • The USB1 is reset by a USB1_RST (reset # 18). • The USB1 OTG interrupt is connected to interrupt slot # 9 in the NVIC. The USB wake-up interrupt is connected to slot # 10 in the event router. • In the SFSUSB register, the USB_ESEA bit must be set to 1 for the USB1 to operate (see Table 204). Table 358. USB1 clocking and power control Base clock Branch clock Maximum Notes frequency USB1 clock BASE_USB1_CLK CLK_USB1 150 MHz Uses PLL1 only. CLK_USB1 must be 60 MHz when the USB1 is operated at low-speed and full-speed modes. In high-speed mode, the clock is provided by the ULPI PHY. USB1 register interface clock BASE_M3_CLK CLK_M3_USB1 150 MHz 21.2.1 Full-speed mode without external PHY In Full-speed mode, use CLK_USB1 to generate a clock for the USB1 interface. 21.2.2 High-speed mode with ULPI interface In High-speed mode, the external PHY generates the clock for the USB1 interface, and the USB1_ULPI_CLK must be enabled on pins PC_0 or P8_8 through their respective pin configuration registers in the system configuration block. The USB1 branch clock CLK_USB1 must be disabled. 21.3 Features • • • • Complies with Universal Serial Bus specification 2.0. Complies with Enhanced Host Controller Interface Specification. Supports auto USB 2.0 mode discovery. Supports all high-speed USB-compliant peripherals if connected to external ULPI PHY. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 437 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 21: LPC18xx USB1 Host/Device controller FT D R A D R A R A FT D R FT • Supports all full-speed USB-compliant peripherals. • Supports interrupts. • This module has its own, integrated DMA engine. D R R A FT D R R A F D R A FT A FT A FT D R D 21.4 General description The High Speed-On-The-Go Controller is a peripheral for embedded applications containing digital circuitry to provide USB2.0 On-The-Go functionality. USB2.0 provides plug-and-play connection of peripheral devices to a host with three different data speeds: High-Speed with a data rate of 480 Mbps, Full-Speed with a data rate of 12 Mbps, Low-Speed with a data rate of 1.5 Mbps. Many portable devices can benefit from the ability to communicate to each other over the USB interface without intervention of a host PC. The addition of the On-The-Go functionality to USB makes this possible without losing the benefits of the standard USB protocol. Support of the High-Speed data rate and the OTG functionality requires an external USB HS OTG PHY that connects to the USB controller via the ULPI interface. Full-Speed or Low-Speed is supported through the on-chip Full-speed PHY. A FT D R A 21.5 Pin description Table 359. USB1 pin description Function name Direction Description USB1_DP USB1_DM USB1_VBUS USB1_VBUS_EN USB1_IND0 USB1_IND1 USB1_PWR_FAULT I/O I/O I O O O I USB1 bidirectional D+ line. USB1 bidirectional D line. VBUS pin (power on USB cable). VBUS power enable. Port indicator LED control output 0. Port indicator LED control output 1. Port power fault signal indicating over-current condition; this signal monitors over-current on the USB bus (external circuitry required to detect over-current condition). ULPI link 8-bit bidirectional data bus timed on the rising clock edge. ULPI link STP signal. Asserted to end or interrupt transfers to the PHY. ULPI link NXT signal. Data flow control signal from the PHY. ULPI link DIR signal. Controls the DATA bus direction. ULPI link CLK signal. 60 MHz clock generated by the PHY. ULPI pins ULPI_DATA[7:0] ULPI_STP ULPI_NXT ULPI_DIR ULPI_CLK I/O O I I I All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 438 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 21: LPC18xx USB1 Host/Device controller FT D R A D R A R A FT D R FT 21.6 Register description D R Remark: For Full-speed operation with on-chip Full-speed PHY, the pads of the PHY need to be configured. For configuration of these pads see Section 19.3.4 “USB1 DP1/DM1 pins”. R Remark: For operations with an external PHY connected through the ULPI interface the interface needs to be selected in the PTS bits of the PORTSC1 register (Section 21.6.15). Table 360. Register access abbreviations Abbreviation Description R A FT D R A F D R A FT D A FT A FT D R A FT D R A R/W R/WC R/WO RO WO Read/Write Read/Write one to Clear Read/Write Once Read Only Write Only Table 361. Register overview: USB1 host/device controller (register base address 0x4000 7000) Name Access Address offset Description Reset value - - 0x000 0x0FF 0x100 0x104 0x108 0x120 0x124 0x128 0x13C 0x140 0x140 0x144 0x144 0x148 0x148 0x14C 0x14C 0x150 0x154 0x154 0x158 0x158 Reserved Device/host capability registers CAPLENGTH HCSPARAMS HCCPARAMS DCIVERSION DCCPARAMS - RO RO RO RO RO - Capability register length Host controller structural parameters Host controller capability parameters Device interface version number Reserved 0x0001 0040 0x0001 0011 0x0000 0005 0x0000 0001 Device controller capability parameters 0x0000 0184 Device/host operational registers USBCMD_D USBCMD_H USBSTS_D USBSTS_H USBINTR_D USBINTR_H FRINDEX_D FRINDEX_H DEVICEADDR PERIODICLISTBASE ENDPOINTLISTADDR ASYNCLISTADDR R/W R/W R/W R/W R/W R/W RO R/W R/W R/W R/W R/W USB command (device mode) USB command (host mode) USB status (device mode) USB status (host mode) USB interrupt enable (device mode) USB interrupt enable (host mode) USB frame index (device mode) USB frame index (host mode) Reserved USB device address Frame list base address Address of endpoint list in memory (device mode) Address of endpoint list in memory (host mode) 0x0004 0000 0x0004 00B0 0x0000 0000 0x0000 1000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 439 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 21: LPC18xx USB1 Host/Device controller FT D R R A Table 361. Register overview: USB1 host/device controller (register base address 0x4000 7000) …continued D R A R A FT D R FT D R A R A A Name Access Address offset Description Reset value FT D R R A A F FT D TTCTRL BURSTSIZE TXFILLTUNING ULPIVIEWPORT BINTERVAL ENDPTNAK ENDPTNAKEN CONFIGFLAG PORTSC1_D PORTSC1_H USBMODE_D USBMODE_H Device endpoint registers R/W R/W R/W R/W R/W R/W R/W RO R/W R/W R/W R/W R/W R/W R/W RO R/W R/W R/W R/W R/W 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C 0x180 0x184 0x184 0x188 0x1A0 0x1A4 0x1A8 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC 0x1C0 0x1C4 0x1C8 0x1CC Asynchronous buffer status for embedded TT (host mode) Programmable burst size Host transmit pre-buffer packet tuning (host mode) Reserved ULPI viewport Length of virtual frame Endpoint NAK (device mode) Endpoint NAK Enable (device mode) Configured flag register Port 1 status/control (device mode) Port 1 status/control (host mode) USB mode (device mode) USB mode (host mode) Endpoint setup status Endpoint initialization Endpoint de-initialization Endpoint status Endpoint complete Endpoint control 0 Endpoint control 1 Endpoint control 2 Endpoint control 3 0x0000 0000 0x0000 0000 0x0000 0000 FT D R A FT D R A FT D 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 ENDPTSETUPSTAT ENDPTPRIME ENDPTFLUSH ENDPTSTAT ENDPTCOMPLETE ENDPTCTRL0 ENDPTCTRL1 ENDPTCTRL2 ENDPTCTRL3 21.6.1 Device/host capability registers Table 362. CAPLENGTH register (CAPLENGTH - address 0x4000 7100) bit description Bit Symbol Description Reset value Access 7:0 CAPLENGTH Indicates offset to add to the register base address at the beginning of the Operational Register BCD encoding of the EHCI revision number supported by this host controller. 0x40 RO 23:8 31:24 HCIVERSION - 0x100 RO - These bits are reserved and should be set to zero. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 440 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 21: LPC18xx USB1 Host/Device controller FT D R R A Table 363. HCSPARAMS register (HCSPARAMS - address 0x4000 7104) bit description D R A R A FT D R FT D R A R A FT A FT F Bit Symbol Description Reset value Access D D 3:0 N_PORTS Number of downstream ports. This field 0x1 specifies the number of physical downstream ports implemented on this host controller. Port Power Control. This field indicates whether the host controller implementation includes port power control. These bits are reserved and should be set to zero. 0x1 RO R R A FT D R A FT D A FT 4 PPC RO D R A 7:5 11:8 N_PCC - RO Number of Ports per Companion Controller. 0x0 This field indicates the number of ports supported per internal Companion Controller. Number of Companion Controller. This field 0x0 indicates the number of companion controllers associated with this USB2.0 host controller. Port indicators. This bit indicates whether the ports support port indicator control. These bits are reserved and should be set to zero. 0x1 - 15:12 N_CC RO 16 19:17 23:20 PI N_PTT RO RO Number of Ports per Transaction Translator. 0x0 This field indicates the number of ports assigned to each transaction translator within the USB2.0 host controller. Number of Transaction Translators. This field indicates the number of embedded transaction translators associated with the USB2.0 host controller. These bits are reserved and should be set to zero. 0x0 27:24 N_TT RO 31:28 - - - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 441 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 21: LPC18xx USB1 Host/Device controller FT D R R A Table 364. HCCPARAMS register (HCCPARAMS - address 0x4000 7108) bit description D R A R A FT D R FT D R A R A FT A FT F Bit Symbol Description Reset value Access D D 0 1 ADC PFL 64-bit Addressing Capability. If zero, no 64-bit addressing capability is supported. Programmable Frame List Flag. If set to one, then the system software can specify and use a smaller frame list and configure the host controller via the USBCMD register Frame List Size field. The frame list must always be aligned on a 4K-boundary. This requirement ensures that the frame list is always physically contiguous. 0 1 RO R RO R A A FT D R A FT D FT D R A 2 ASP Asynchronous Schedule Park Capability. If this bit is 1 set to a one, then the host controller supports the park feature for high-speed queue heads in the Asynchronous Schedule.The feature can be disabled or enabled and set to a specific level by using the Asynchronous Schedule Park Mode Enable and Asynchronous Schedule Park Mode Count fields in the USBCMD register. Isochronous Scheduling Threshold. This field indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule. EHCI Extended Capabilities Pointer. This optional field indicates the existence of a capabilities list. These bits are reserved and should be set to zero. 0 RO 7:4 IST RO 15:8 31:9 EECP - 0 - RO - Table 365. DCIVERSION register (DCIVERSION - address 0x4000 7120) bit description Bit Symbol Description Reset value Access 15:0 DCIVERSION The device controller interface conforms to the 0x1 two-byte BCD encoding of the interface version number contained in this register. These bits are reserved and should be set to zero. - RO 31:16 - Table 366. DCCPARAMS (address 0x4000 7124) Bit Symbol Description Reset value Access 4:0 6:5 7 8 31:9 DEN DC HC - Device Endpoint Number. These bits are reserved and should be set to zero. Device Capable. Host Capable. These bits are reserved and should be set to zero. 0x4 0x1 0x1 - RO RO RO - 21.6.2 USB Command register (USBCMD) The host/device controller executes the command indicated in this register. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 442 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 21: LPC18xx USB1 Host/Device controller FT D R A D R A R A FT D R FT 21.6.2.1 Device mode Bit Symbol Value Description D R Table 367. USB Command register in device mode (USBCMD_D - address 0x4000 7140) bit description Reset Access value R A FT D R R A F D R A FT A FT A FT D R D 0 RS 0 1 Run/Stop Writing a 0 to this bit will cause a detach event. Writing a one to this bit will cause the device controller to enable a pull-up on USB_DP and initiate an attach event. This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. Software should use this bit to prevent an attach event before the device controller has been properly initialized. Controller reset. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register. 0 1 Set to 0 by hardware when the reset process is complete. When software writes a one to this bit, the Device Controller resets its internal pipelines, timers, counters, state machines etc. to their initial values. Writing a one to this bit when the device is in the attached state is not recommended, since the effect on an attached host is undefined. In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0. Not used in device mode. Not used in device mode. Not used in device mode. 0 R/W A FT D R A 1 RST 0 R/W 3:2 4 5 6 7 9:8 10 11 12 13 SUTW - 0 0 0 R/W Not used in device mode. Writing a one to this bit when the device mode is selected, will have undefined results. Reserved. These bits should be set to 0. Not used in Device mode. Reserved.These bits should be set to 0. Not used in Device mode. Reserved.These bits should be set to 0. Setup trip wire During handling a setup packet, this bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. If the setup lockout mode is off (see USBMODE register) then there exists a hazard when new setup data arrives while the DCD is copying the setup data payload from the QH for a previous setup packet. This bit is set and cleared by software and will be cleared by hardware when a hazard exists. (See Section 20.10). 0 0 0 14 ATDTW Add dTD trip wire This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoint’s linked list. This bit is set and cleared by software during the process of adding a new dTD. See also Section 20.10. This bit shall also be cleared by hardware when its state machine is hazard region for which adding a dTD to a primed endpoint may go unrecognized. 0 R/W All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 443 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 21: LPC18xx USB1 Host/Device controller FT D R R A Table 367. USB Command register in device mode (USBCMD_D - address 0x4000 7140) bit description …continued D R A R A FT D R FT D R A R A A Bit Symbol Value Description Reset Access value FT D R A F FT D R A 15 23:16 FS2 ITC Not used in device mode. Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames. 0x8 R/W FT D R A FT D R A FT D 31:24 - Reserved 0 21.6.2.2 Host mode Table 368. USB Command register in host mode (USBCMD_H - address 0x4000 7140) bit description Bit Symbol Value Description Reset Access value 0 RS 0 Run/Stop When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the Host Controller has finished the transaction and has entered the stopped state. Software should not write a one to this field unless the host controller is in the Halted state (i.e. HCHalted in the USBSTS register is a one). When set to a 1, the Host Controller proceeds with the execution of the schedule. The Host Controller continues execution as long as this bit is set to a one. 0 R/W 1 1 RST Controller reset. 0 Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register. 0 1 This bit is set to zero by hardware when the reset process is complete. When software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. Attempting to reset an actively running host controller will result in undefined behavior. Bit 0 of the Frame List Size bits. See Table 369. This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. Note that this field is made up from USBCMD bits 15, 3, and 2. 0 R/W 2 FS0 3 FS1 Bit 1 of the Frame List Size bits. See Table 369 All information provided in this document is subject to legal disclaimers. 0 © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 444 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 21: LPC18xx USB1 Host/Device controller FT D R R A Table 368. USB Command register in host mode (USBCMD_H - address 0x4000 7140) bit description …continued D R A R A FT D R FT D R A R A A Bit Symbol Value Description Reset Access value FT D R A F FT D R A 4 PSE 0 1 This bit controls whether the host controller skips processing the periodic schedule. Do not process the periodic schedule. Use the PERIODICLISTBASE register to access the periodic schedule. This bit controls whether the host controller skips processing the asynchronous schedule. 0 1 Do not process the asynchronous schedule. Use the ASYNCLISTADDR to access the asynchronous schedule. This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. 0 1 The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one. Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule states, it sets the Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results. 0 R/W FT D R A FT D R A FT D 5 ASE 0 R/W 6 IAA 0 R/W 7 9:8 ASP1_0 - Reserved 0 R/W Asynchronous schedule park mode. 11 Contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. Valid values are 0x1 to 0x3. Remark: Software must not write 00 to this bit when Park Mode Enable is one as this will result in undefined behavior. 10 11 ASPE 0 1 Reserved. Asynchronous Schedule Park Mode Enable Park mode is disabled. Park mode is enabled. Reserved. Not used in Host mode. Reserved. 0 1 R/W 12 13 14 - - 0 0 - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 445 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 21: LPC18xx USB1 Host/Device controller FT D R R A Table 368. USB Command register in host mode (USBCMD_H - address 0x4000 7140) bit description …continued D R A R A FT D R FT D R A R A A Bit Symbol Value Description Reset Access value FT D R A F FT D R A 15 23:16 FS2 ITC Bit 2 of the Frame List Size bits. See Table 369. Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames. 0 0x8 - FT D R/W FT D R A FT D R A 31:24 - Reserved Table 369. Frame list size values USBCMD bit 15 USBCMD bit 3 USBCMD bit 2 Frame list size 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1024 elements (4096 bytes) - default value 512 elements (2048 bytes) 256 elements (1024 bytes) 128 elements (512 bytes) 64 elements (256 bytes) 32 elements (128 bytes) 16 elements (64 bytes) 8 elements (32 bytes) 21.6.3 USB Status register (USBSTS) This register indicates various states of the Host/Device controller and any pending interrupts. Software sets a bit to zero in this register by writing a one to it. Remark: This register does not indicate status resulting from a transaction on the serial bus. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 446 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 21: LPC18xx USB1 Host/Device controller FT D R A D R A R A FT D R FT 21.6.3.1 Device mode Bit Symbol Value Description Reset value D R Table 370. USB Status register in device mode (USBSTS_D - address 0x4000 7144) register bit description R A FT D R R A F D R A FT Access A FT A FT D R D 0 UI 0 1 USB interrupt This bit is cleared by software writing a one to it. This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes. 0 R/WC A FT D R A 1 UEI 0 1 USB error interrupt This bit is cleared by software writing a one to it. When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. The device controller detects resume signaling only (see Section 20.10.11.6). Port change detect. 0 1 This bit is cleared by software writing a one to it. The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. When the port controller exits the full or high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit (URI) and the DCSuspend bits (SLI) respectively. Not used in Device mode. 0 Reserved. Not used in Device mode. USB reset received 0 1 This bit is cleared by software writing a one to it. When the device controller detects a USB Reset and enters the default state, this bit will be set to a one. 0 R/WC 2 PCI 0 R/WC 3 4 5 6 URI 0 0 R/WC All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 447 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 21: LPC18xx USB1 Host/Device controller FT D R R A Table 370. USB Status register in device mode (USBSTS_D - address 0x4000 7144) register bit description D R A R A FT D R FT D R A R A A Bit Symbol Value Description Reset value Access FT D R A F FT D R A 7 SRI 0 1 SOF received This bit is cleared by software writing a one to it. When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. Therefore, this bit will be set roughly every 1 ms in device FS mode and every 125 s in HS mode and will be synchronized to the actual SOF that is received. Since the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp. DCSuspend 0 The device controller clears the bit upon exiting from a suspend state. This bit is cleared by software writing a one to it. When a device controller enters a suspend state from an active state, this bit will be set to a one. Reserved. Software should only write 0 to reserved bits. Not used in Device mode. Not used in Device mode. Not used in Device mode. Not used in Device mode. NAK interrupt bit 0 This bit is automatically cleared by hardware when the all the enabled TX/RX Endpoint NAK bits are cleared. It is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and the corresponding TX/RX Endpoint NAK Enable bit are set. Reserved. Software should only write 0 to reserved bits. Not used in Device mode. Not used in Device mode. Reserved. Software should only write 0 to reserved bits. 0 R/WC FT D R A FT D R A FT D 8 SLI 0 R/WC 1 11:9 12 13 14 15 16 NAKI - 0 0 0 0 0 0 RO 1 17 18 19 31:20 - - 0 0 0 - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 448 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 21: LPC18xx USB1 Host/Device controller FT D R A D R A R A FT D R FT 21.6.3.2 Host mode Bit Symbol Value Description D R Table 371. USB Status register in host mode (USBSTS_H - address 0x4000 7144) register bit description Reset Access value R A FT D R R A F D R A FT A FT A FT D R D 0 UI 0 1 USB interrupt (USBINT) This bit is cleared by software writing a one to it. This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes. 0 R/WC A FT D R A 1 UEI 0 1 USB error interrupt (USBERRINT) This bit is cleared by software writing a one to it. When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. Port change detect. 0 1 This bit is cleared by software writing a one to it. The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port. Frame list roll-over 0 1 This bit is cleared by software writing a one to it. The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example, if the frame list size (as programmed in the Frame List Size field of the USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX [13] toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX bit 12 toggles (see Section 21.6.5). Reserved. Interrupt on async advance 0 1 This bit is cleared by software writing a one to it. System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the USBCMD register. This status bit indicates the assertion of that interrupt source. Not used by the Host controller. SOF received 0 1 This bit is cleared by software writing a one to it. In host mode, this bit will be set every 125 s and can be used by host controller driver as a time base. Not used by the Host controller. Reserved. 0 R/WC 2 PCI 0 R/WC 3 FRI 0 R/WC 4 5 AAI 0 0 R/WC 6 7 SRI - 0 0 R/WC R/WC 8 11:9 SLI - - - - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 449 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 21: LPC18xx USB1 Host/Device controller FT D R R A Table 371. USB Status register in host mode (USBSTS_H - address 0x4000 7144) register bit description …continued D R A R A FT D R FT D R A R A A Bit Symbol Value Description Reset Access value FT D R A F FT D R A 12 HCH 0 1 HCHalted The RS bit in USBCMD is set to zero. Set by the host controller. The Host Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g. because of an internal error). Reclamation 0 1 No empty asynchronous schedule detected. An empty asynchronous schedule is detected. Set by the host controller. Periodic schedule status This bit reports the current real status of the Periodic Schedule. The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (if both are 1) or disabled (if both are 0). 0 1 The periodic schedule status is disabled. The periodic schedule status is enabled. Asynchronous schedule status This bit reports the current real status of the Asynchronous Schedule. The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (if both are 1) or disabled (if both are 0). 0 1 Asynchronous schedule status is disabled. Asynchronous schedule status is enabled. Not used on Host mode. Reserved. USB host asynchronous interrupt (USBHSTASYNCINT) 0 1 This bit is cleared by software writing a one to it. This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the asynchronous schedule. This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes. USB host periodic interrupt (USBHSTPERINT) 0 1 This bit is cleared by software writing a one to it. This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes. Reserved. All information provided in this document is subject to legal disclaimers. 1 RO FT D R A FT D R A FT D 13 RCL 0 RO 14 PS 0 RO 15 AS 0 16 17 18 UAI 0 0 R/WC 19 UPI 0 R/WC 31:20 - Rev. 00.13 — 20 July 2011 450 of 1164 © NXP B.V. 2011. All rights reserved. User manual D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 21: LPC18xx USB1 Host/Device controller FT D R A D R A R A FT D R FT 21.6.4 USB Interrupt register (USBINTR) D R The software interrupts are enabled with this register. An interrupt is generated when a bit is set and the corresponding interrupt is active. The USB Status register (USBSTS) still shows interrupt sources even if they are disabled by the USBINTR register, allowing polling of interrupt events by the software. All interrupts must be acknowledged by software by clearing (that is writing a 1 to) the corresponding bit in the USBSTS register. D R A FT D R A FT R A F D R A FT D FT D R A R A A FT 21.6.4.1 Device mode Table 372. USB Interrupt register in device mode (USBINTR_D - address 0x4000 7148) bit description Bit Symbol Description Reset value Access 0 UE USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS. 0 R/W 1 UEE USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register. 0 R/W 2 PCE Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS. 0 R/W 3 4 5 6 URE Not used by the Device controller. Reserved Not used by the Device controller. USB reset enable When this bit is a one, and the USB Reset Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the USB Reset Received bit. 0 R/W 0 - 7 SRE SOF received enable When this bit is a one, and the SOF Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the SOF Received bit. 0 R/W 8 SLE Sleep enable When this bit is a one, and the DCSuspend bit in the USBSTS register transitions, the device controller will issue an interrupt. The interrupt is acknowledged by software writing a one to the DCSuspend bit. 0 R/W 15:9 16 NAKE Reserved NAK interrupt enable This bit is set by software if it wants to enable the hardware interrupt for the NAK Interrupt bit. If both this bit and the corresponding NAK Interrupt bit are set, a hardware interrupt is generated. 0 R/W 17 18 19 UAIE UPIA Reserved Not used by the Device controller. Not used by the Device controller. Reserved All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. 31:20 User manual Rev. 00.13 — 20 July 2011 451 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 21: LPC18xx USB1 Host/Device controller FT D R A D R A R A FT D R FT 21.6.4.2 Host mode Table 373. USB Interrupt register in host mode (USBINTR_H - address 0x4000 7148) bit description Bit Symbol Description D R Access Reset value R A FT D R R A F D R A FT A FT A FT D R D 0 UE USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS. R/W 0 A FT D R A 1 UEE USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register. R/W 0 2 PCE Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS. R/W 0 3 FRE Frame list rollover enable When this bit is a one, and the Frame List Rollover bit in the USBSTS register is a one, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Frame List Rollover bit. 4 5 AAE Reserved Interrupt on asynchronous advance enable When this bit is a one, and the Interrupt on Async Advance bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the Interrupt on Async Advance bit. R/W 0 0 6 7 SRE Not used by the Host controller. - 0 0 If this bit is one and the SRI bit in the USBSTS register is one, the host controller will issue an interrupt. In host mode, the SRI bit will be set every 125 s and can be used by the host controller as a time base. The interrupt is acknowledged by software clearing the SRI bit in the USBSTS register. Not used by the Host controller. Reserved Not used by the host controller. Reserved USB host asynchronous interrupt enable When this bit is a one, and the USBHSTASYNCINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTASYNCINT bit. R/W R/W - 8 15:9 16 17 18 UAIE 0 0 0 19 UPIA USB host periodic interrupt enable When this bit is a one, and the USBHSTPERINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTPERINT bit. R/W 0 31:20 - Reserved All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 452 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 21: LPC18xx USB1 Host/Device controller FT D R A D R A R A FT D R FT 21.6.5 Frame index register (FRINDEX) 21.6.5.1 Device mode D R In Device mode this register is read only, and the device controller updates the FRINDEX[13:3] register from the frame number indicated by the SOF marker. Whenever a SOF is received by the USB bus, FRINDEX[13:3] will be checked against the SOF marker. If FRINDEX[13:3] is different from the SOF marker, FRINDEX[13:3] will be set to the SOF value and FRINDEX[2:0] will be set to zero (i.e. SOF for 1 ms frame). If FRINDEX [13:3] is equal to the SOF value, FRINDEX[2:0] will be incremented (i.e. SOF for 125 s micro-frame) by hardware. FT D Table 374. USB frame index register in device mode (FRINDEX_D - address 0x4000 714C) bit description Bit Symbol Description Reset value Access R A FT D R R A F D R A FT D R A FT D R A A FT A 2:0 13:3 31:14 FRINDEX2_0 FRINDEX13_3 - Current micro frame number Current frame number of the last frame transmitted Reserved - RO RO 21.6.5.2 Host mode This register is used by the host controller to index the periodic frame list. The register updates every 125 s (once each micro-frame). Bits[N: 3] are used to select a particular entry in the Periodic Frame List during periodic schedule execution. The number of bits used for the index depends on the size of the frame list as set by system software in the Frame List Size field in the USBCMD register. This register must be written as a DWord. Byte writes produce undefined results. This register cannot be written unless the Host Controller is in the 'Halted' state as indicated by the HCHalted bit in the USBSTS register (host mode). A write to this register while the Run/Stop bit is set to a one produces undefined results. Writes to this register also affect the SOF value. Table 375. USB frame index register in host mode (FRINDEX_H - address 0x4000 714C) bit description Bit Symbol Description Reset value Access 2:0 12:3 31:13 FRINDEX2_0 FRINDEX12_3 - Current micro frame number Frame list current index for 1024 elements. Reserved - R/W R/W Table 376. Number of bits used for the frame list index USBCMD USBCMD USBCMD Frame list size bit 15 bit 3 bit 2 Size of FRINDEX12_3 bit field 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 1024 elements (4096 bytes). Default value. 512 elements (2048 bytes) 256 elements (1024 bytes) 128 elements (512 bytes) 64 elements (256 bytes) 12 11 10 9 8 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 453 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 21: LPC18xx USB1 Host/Device controller FT D R A D R A R A FT D R FT Table 376. Number of bits used for the frame list index USBCMD USBCMD USBCMD Frame list size bit 15 bit 3 bit 2 D R Size of FRINDEX12_3 bit field R A FT D R R A F D R A FT A FT A FT 1 1 1 0 1 1 1 0 1 32 elements (128 bytes) 16 elements (64 bytes) 8 elements (32 bytes) 7 6 5 D D R A FT D R A 21.6.6 Device address (DEVICEADDR) and Periodic List Base (PERIODICLISTBASE) registers 21.6.6.1 Device mode The upper seven bits of this register represent the device address. After any controller reset or a USB reset, the device address is set to the default address (0). The default address will match all incoming addresses. Software shall reprogram the address after receiving a SET_ADDRESS descriptor. The USBADRA bit is used to accelerate the SET_ADDRESS sequence by allowing the DCD to preset the USBADR register bits before the status phase of the SET_ADDRESS descriptor. Table 377. USB Device Address register in device mode (DEVICEADDR - address 0x4000 7154) bit description Bit Symbol Value Description Reset value Access 23:0 24 USBADRA 0 1 reserved Device address advance Any write to USBADR are instantaneous. When the user writes a one to this bit at the same time or before USBADR is written, the write to USBADR fields is staged and held in a hidden register. After an IN occurs on endpoint 0 and is acknowledged, USBADR will be loaded from the holding register. Hardware will automatically clear this bit on the following conditions: 0 - • • • IN is ACKed to endpoint 0. USBADR is updated from the staging register. OUT/SETUP occurs on endpoint 0. USBADR is not updated. Device reset occurs. USBADR is set to 0. Remark: After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. This mechanism will ensure this specification is met when the DCD can not write the device address within 2 ms from the SET_ADDRESS status phase. If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), the USBADR will be programmed instantly at the correct time and meet the 2 ms USB requirement. 31:25 USBADR USB device address 0 R/W 21.6.6.2 Host mode This 32-bit register contains the beginning address of the Periodic Frame List in the system memory. The host controller driver (HCD) loads this register prior to starting the schedule execution by the Host Controller. The memory structure referenced by this All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 454 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 21: LPC18xx USB1 Host/Device controller FT D R R A physical memory pointer is assumed to be 4 kB aligned. The contents of this register are combined with the Frame Index Register (FRINDEX) to enable the Host Controller to step through the Periodic Frame List in sequence. R A Table 378. USB Periodic List Base register in host mode (PERIODICLISTBASE - address 0x4000 7154) bit description Bit Symbol Description Reset value D R A R A FT D R FT D R A A FT D R A R A FT F FT D Access R A FT D FT D D R A 11:0 31:12 PERBASE31_12 Reserved Base Address (Low) These bits correspond to the memory address signals[31:12]. N/A N/A R/W 21.6.7 Endpoint List Address register (ENDPOINTLISTADDR) and Asynchronous List Address (ASYNCLISTADDR) registers 21.6.7.1 Device mode In device mode, this register contains the address of the top of the endpoint list in system memory. Bits[10:0] of this register cannot be modified by the system software and will always return a zero when read.The memory structure referenced by this physical memory pointer is assumed 64 byte aligned. Table 379. USB Endpoint List Address register in device mode (ENDPOINTLISTADDR - address 0x4000 7158) bit description Bit Symbol Description Reset value Access 10:0 31:11 EPBASE31_11 reserved Endpoint list pointer (low) These bits correspond to memory address signals 31:11, respectively. This field will reference a list of up to 4 Queue Heads (QH). (i.e. one queue head per endpoint and direction.) 0 N/A R/W 21.6.7.2 Host mode This 32-bit register contains the address of the next asynchronous queue head to be executed by the host. Bits [4:0] of this register cannot be modified by the system software and will always return a zero when read. Table 380. USB Asynchronous List Address register in host mode (ASYNCLISTADDR- address 0x4000 7158) bit description Bit Symbol Description Reset value Access 4:0 31:5 ASYBASE31_5 Reserved Link pointer (Low) LPL These bits correspond to memory address signals 31:5, respectively. This field may only reference a Queue Head (OH). 0 - R/W 21.6.8 TT Control register (TTCTRL) 21.6.8.1 Device mode This register is not used in device mode. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 455 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 21: LPC18xx USB1 Host/Device controller FT D R A D R A R A FT D R FT 21.6.8.2 Host mode D R This register contains parameters needed for internal TT operations. This register is used by the host controller only. Writes must be in Dwords. FT D R A FT Table 381. USB TT Control register in host mode (TTCTRL - address 0x4000 715C) bit description Bit Symbol Description Reset value R A R A F D R A FT D R A FT D R A Access A FT D 23:0 30:24 31 TTHA - Reserved. Hub address when FS or LS device are connected directly. Reserved. 0 N/A 0 R/W 21.6.9 Burst Size register (BURSTSIZE) This register is used to control and dynamically change the burst size used during data movement on the master interface of the USB DMA controller. Writes must be in Dwords. The default for the length of a burst of 32-bit words for RX and TX DMA data transfers is 16 words each. Table 382. USB burst size register in device/host mode (BURSTSIZE - address 0x4000 7160) bit description Bit Symbol Description Reset value Access 7:0 RXPBURST Programmable RX burst length This register represents the maximum length of a burst in 32-bit words while moving data from the USB bus to system memory. 0x10 R/W 15:8 TXPBURST Programmable TX burst length This register represents the maximum length of a burst in 32-bit words while moving data from system memory to the USB bus. 0x10 R/W 31:16 - reserved - - 21.6.10 Transfer buffer Fill Tuning register (TXFILLTUNING) 21.6.10.1 Device controller This register is not used in device mode. 21.6.10.2 Host controller The fields in this register control performance tuning associated with how the host controller posts data to the TX latency FIFO before moving the data onto the USB bus. The specific areas of performance include the how much data to post into the FIFO and an estimate for how long that operation should take in the target system. Definitions: T0 = Standard packet overhead T1 = Time to send data payload Tff = Time to fetch packet into TX FIFO up to specified level Ts = Total packet flight time (send-only) packet; Ts = T0 + T1 Tp = Total packet time (fetch and send) packet; Tp = Tff + T0 + T1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 456 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 21: LPC18xx USB1 Host/Device controller FT D R R A Upon discovery of a transmit (OUT/SETUP) packet in the data structures, host controller checks to ensure Tp remains before the end of the (micro) frame. If so it proceeds to pre-fill the TX FIFO. If at anytime during the pre-fill operation the time remaining the [micro]frame is < Ts then the packet attempt ceases and the packet is tried at a later time. Although this is not an error condition and the host controller will eventually recover, a mark will be made the scheduler health counter to note the occurrence of a “backoff” event. When a back-off event is detected, the partial packet fetched may need to be discarded from the latency buffer to make room for periodic traffic that will begin after the next SOF. Too many back-off events can waste bandwidth and power on the system bus and thus should be minimized (not necessarily eliminated). Backoffs can be minimized with use of the TSCHHEALTH (Tff) described below. R A Table 383. USB Transfer buffer Fill Tuning register in host mode (TXFILLTUNING - address 0x4000 7164) bit description Bit Symbol Description Reset value Access D R A R A FT D R FT D R A A FT D R A R A FT F FT D R A FT D D R A FT D 7:0 TXSCHOH FIFO burst threshold This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. The minimum value is 2 and this value should be a low as possible to maximize USB performance. A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. This value is ignored if the Stream Disable bit in USBMODE register is set. 0x2 R/W 12:8 TXSCHEATLTH Scheduler health counter This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES before running out of time to send the packet before the next Start-Of-Frame . This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. Writing to this register will clear the counter. The maximum value is 31. 0x0 R/W 15:13 21:16 TXFIFOTHRES Reserved Scheduler overhead This register adds an additional fixed offset to the schedule time estimator described above as Tff. As an approximation, the value chosen for this register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. The time unit represented in this register is 1.267 s when a device is connected in High-Speed Mode. The time unit represented in this register is 6.333 s when a device is connected in Low/Full Speed Mode. 0x0 R/W 31:22 - Reserved 21.6.11 USB ULPI viewport register (ULPIVIEWPORT) The register provides indirect access to the ULPI PHY register set. Although the core performs access to the ULPI PHY register set, there may be extraordinary circumstances where software may need direct access. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 457 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 21: LPC18xx USB1 Host/Device controller FT D R R Table 384. USB ULPI viewport register (ULPIVIEWPORT - address 0x4000 7170) bit description Bit Symbol Value Description Access Reset value Remark: WRITES TO THE ULPI THROUGH THE VIEWPORT CAN SUBSTANTIALLY HARM STANDARD USB OPERATIONS. CURRENTLY NO USAGE MODEL HAS BEEN DEFINED WHERE SOFTWARE SHOULD NEED TO EXECUTE WRITES DIRECTLY TO THE ULPI – SEE EXCEPTION REGARDING OPTIONAL FEATURES BELOW. R A Remark: EXECUTING READ OPERATIONS THOUGH THE ULPI VIEWPORT SHOULD HAVE NO HARMFUL SIDE EFFECTS TO STANDARD USB OPERATIONS. There are two operations that can be performed with the ULPI Viewport, wakeup and read /write operations. The wakeup operation is used to put the ULPI interface into normal operation mode and reenable the clock if necessary. A wakeup operation is required before accessing the registers when the ULPI interface is operating in low power mode, serial mode, or carkit mode. The ULPI state can be determined by reading the sync. state bit (ULPISS). If this bit is a one, then ULPI interface is running in normal operation mode and can accept read/write operations. If the ULPISS indicates a 0 then then read/write operations will not be able execute. Undefined behavior will result if ULPISS = 0 and a read or write operation is performed. To execute a wakeup operation, write all 32-bits of the ULPI Viewport where ULPIPORT is constructed appropriately and the ULPIWU bit is a 1 and ULPIRUN bit is a 0. Poll the ULPI Viewport until ULPIWU is zero for the operation to complete. To execute a read or write operation, write all 32-bits of the ULPI Viewport where ULPIDATWR, ULPIADDR, ULPIPORT, ULPIRW are constructed appropriately and the ULPIRUN bit is a 1. Poll the ULPI Viewport until ULPIRUN is zero for the operation to complete. Once ULPIRUN is zero, the ULPIDATRD will be valid if the operation was a read. The polling method above could also be replaced and interrupt driven using the ULPI interrupt defined in the USBSTS and USBINTR registers. When a wakeup or read/write operation complete, the ULPI interrupt will be set. D R A R A FT D R FT D R A A A FT D R A R A FT F FT D R A FT D D R A FT D 7:0 15:8 23:16 26:24 27 ULPIDATWR ULPIDATRD ULPIADDR ULPIPORT ULPISS 0 1 When a write operation is commanded, the data to be sent is written to this field. After a read operation completes, the result is placed in this field. When a read or write operation is commanded, the address of the operation is written to this field. For the wakeup or read/write operation to be executed, this value must be written as 0. ULPI sync state. This bit represents the state of the ULPI interface. In another state (ie. carkit, serial, low power) Normal Sync. State. Reserved R/W R R/W R/W R 0 0 0 000 0 28 - - - - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 458 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 21: LPC18xx USB1 Host/Device controller FT D R R A Table 384. USB ULPI viewport register (ULPIVIEWPORT - address 0x4000 7170) bit description …continued D R A R A FT D R FT D R A R A A Bit Symbol Value Description Access Reset value FT D R A F FT D R A 29 ULPIRW 0 1 ULPI Read/Write control. This bit selects between running a read or write operation. Read Write ULPI Read/Write Run. Writing the 1 to this bit will begin the read/write operation. The bit will automatically transition to 0 after the read/write is complete. Once this bit is set, the driver can not set it back to 0. Remark: The driver must never executue a wakeup and a read/write operation at the same time. R/W 0 FT D R A FT D R A FT D 30 ULPIRUN R/W - 31 ULPIWU ULPI Wake-up. Writing the 1 to this bit will begin the wakeup operation. The bit will automatically transition to 0 after the wakeup is complete. Once this bit is set, the driver can not set it back to 0. Remark: The driver must never executue a wakeup and a read/write operation at the same time. R/W 0 21.6.12 BINTERVAL register This register defines the bInterval value which determines the length of the virtual frame (see Section 20.7.7). Table 385. USB BINTERVAL register (BINTERVAL - address 0x4000 7174) bit description in device/host mode Bit Symbol Description Reset value Access 3:0 31:4 BINT - bInterval value Reserved 0x00 - R/W - 21.6.13 USB Endpoint NAK register (ENDPTNAK) 21.6.13.1 Device mode This register indicates when the device sends a NAK handshake on an endpoint. Each Tx and Rx endpoint has a bit in the EPTN and EPRN field respectively. A bit in this register is cleared by writing a 1 to it. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 459 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 21: LPC18xx USB1 Host/Device controller FT D R R A Table 386. USB endpoint NAK register in device mode (ENDPTNAK - address 0x4000 7178) bit description D R A R A FT D R FT D R A R A FT A FT F Bit Symbol Description Reset value Access D D R A R A 3:0 EPRN Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0. 0x00 R/WC FT D R A FT D R A FT D 15:6 19:16 EPTN Reserved Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0. 0x00 R/WC 31:20 - Reserved - - 21.6.13.2 Host mode This register is not used in host mode. 21.6.14 USB Endpoint NAK Enable register (ENDPTNAKEN) 21.6.14.1 Device mode Each bit in this register enables the corresponding bit in the ENDPTNAK register. Each Tx and Rx endpoint has a bit in the EPTNE and EPRNE field respectively. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 460 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 21: LPC18xx USB1 Host/Device controller FT D R R A Table 387. USB Endpoint NAK Enable register in device mode (ENDPTNAKEN - address 0x4000 717C) bit description Bit Symbol Description Reset value D R A R A FT D R FT D R A R A FT D D Access A FT R A F R A FT D FT 3:0 EPRNE Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0. 0x00 R/W D R A FT D R A 15:4 19:16 EPTNE Reserved Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0. 0x00 R/W 31:20 - Reserved - - 21.6.14.2 Host mode This register is not used in host mode. 21.6.15 Port Status and Control register (PORTSC1) 21.6.15.1 Device mode The device controller implements one port register, and it does not support power control. Port control in device mode is used for status port reset, suspend, and current connect status. It is also used to initiate test mode or force signaling. This register allows software to put the PHY into low-power Suspend mode and disable the PHY clock. Table 388. Port Status and Control register in device mode (PORTSC1_D - address 0x4000 7184) bit description Bit Symbol Value Description Reset value Access 0 CCS 0 Current connect status Device not attached A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or suspended. 1 Device attached. A one indicates that the device successfully attached and is operating in either high-speed mode or full-speed mode as indicated by the High Speed Port bit in this register. 0 RO 1 2 CSC PE 1 Not used in device mode Port enable. This bit is always 1. The device port is always enabled. 0 1 RO All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 461 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 21: LPC18xx USB1 Host/Device controller FT D R R A Table 388. Port Status and Control register in device mode (PORTSC1_D - address 0x4000 7184) bit description D R A R A FT D R FT D R A R A A Bit Symbol Value Description Reset value Access FT D R A F FT D R A 3 5:4 6 PEC FPR 0 - Port enable/disable change This bit is always 0. The device port is always enabled. Reserved Force port resume After the device has been in Suspend State for 5 ms or more, software must set this bit to one to drive resume signaling before clearing. The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. The bit will be cleared when the device returns to normal operation. When this bit transitions to a one because a J-to-K transition detected, the Port Change Detect bit in the USBSTS register is set to one as well. 0 0 0 RO RO FT D R A FT D R A R/W FT D 0 1 7 SUSP 0 1 8 PR No resume (K-state) detected/driven on port. Resume detected/driven on port. Suspend In device mode, this is a read-only status bit . Port not in suspend state Port in suspend state Port reset In device mode, this is a read-only status bit. A device reset from the USB bus is also indicated in the USBSTS register. 0 RO 0 RO 0 1 9 HSP Port is not in the reset state. Port is in the reset state. High-speed status Remark: This bit is redundant with bits 27:26 (PSPD) in this register. It is implemented for compatibility reasons. 0 RO 0 1 11:10 LS 12 13 PP - Host/device connected to the port is not in High-speed mode. Host/device connected to the port is in High-speed mode. Not used in device mode. Not used in device mode. Reserved Port indicator control Writing to this field effects the value of the USB1_IND1:0 pins. 00 R/W 15:14 PIC1_0 0x0 0x1 0x2 0x3 Port indicators are off. amber green undefined All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 462 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 21: LPC18xx USB1 Host/Device controller FT D R R A Table 388. Port Status and Control register in device mode (PORTSC1_D - address 0x4000 7184) bit description D R A R A FT D R FT D R A R A A Bit Symbol Value Description Reset value Access FT D R A F FT D R A 19:16 PTC3_0 Port test control 0000 Any value other than 0000 indicates that the port is operating in test mode. The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_HS/FS/LS values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0x7 to 0xF are reserved. 0x0 0x1 0x2 0x3 0x4 0x5 0x6 TEST_MODE_DISABLE J_STATE K_STATE SE0 (host)/NAK (device) Packet FORCE_ENABLE_HS FORCE_ENABLE_FS Not used in device mode. This bit is always 0 in device mode. Not used in device mode. This bit is always 0 in device mode. Not used in device mode. This bit is always 0 in device mode. PHY low power suspend - clock disable (PLPSCD) In device mode, The PHY can be put into Low Power Suspend – Clock Disable when the device is not running (USBCMD Run/Stop = 0) or the host has signaled suspend (PORTSC SUSPEND = 1). Low power suspend will be cleared automatically when the host has signaled resume. Before forcing a resume from the device, the device controller driver must clear this bit. 0 1 Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled). Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled). Port force full speed connect 0 1 Port connects at any speed. Writing this bit to a 1 will force the port to only connect at full speed. It disables the chirp sequence that allows the port to identify itself as High-speed. This is useful for testing FS configurations with a HS host, hub or device. Reserved Port speed This register field indicates the speed at which the port is operating. 0x1 0x2 0x3 Full-speed invalid in device mode High-speed Reserved Parallel transceiver select. All other values are reserved. 0x2 0x3 ULPI Serial/ 1.1 PHY (Full-speed only) All information provided in this document is subject to legal disclaimers. R/W FT D R A FT D R A FT D 20 21 22 23 PHCD - 0 0 0 0 R/W 24 PFSC 0 R/W 25 - - 27:26 PSPD 0 RO 29:28 31:30 PTS - R/W © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 463 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 21: LPC18xx USB1 Host/Device controller FT D R A D R A R A FT D R FT 21.6.15.2 Host mode D R The host controller uses one port. The register is only reset when power is initially applied or in response to a controller reset. The initial conditions of the port are: FT D R A FT R A R A F D R A FT A FT • No device connected • Port disabled D If the port has power control, this state remains until software applies power to the port by setting port power to one in the PORTSC register. Table 389. Port Status and Control register in host mode (PORTSC1_H - address 0x4000 7184) bit description Bit Symbol Value Description Reset value Access D R A FT D R A 0 CCS Current connect status This value reflects the current state of the port and may not correspond directly to the event that caused the CSC bit to be set. This bit is 0 if PP (Port Power bit) is 0. Software clears this bit by writing a 1 to it. 0 1 No device is present. Device is present on the port. Connect status change Indicates a change has occurred in the port’s Current Connect Status. The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be ‘setting’ an already-set bit (i.e., the bit will remain set). Software clears this bit by writing a one to it. This bit is 0 if PP (Port Power bit) is 0 0 1 No change in current status. Change in current status. Port enable. Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. When the port is disabled. downstream propagation of data is blocked except for reset. This bit is 0 if PP (Port Power bit) is 0. 0 1 Port disabled. Port enabled. 0 R/WC 1 CSC 0 R/WC 2 PE 0 R/W All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 464 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 21: LPC18xx USB1 Host/Device controller FT D R R A Table 389. Port Status and Control register in host mode (PORTSC1_H - address 0x4000 7184) bit description D R A R A FT D R FT D R A R A A …continued FT F FT Bit Symbol Value Description Reset value Access D D R R A A FT FT 3 PEC 0 Port disable/enable change For the root hub, this bit gets set to a one only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). Software clears this by writing a one to it. This bit is 0 if PP (Port Power bit) is 0, 0 R/WC D D R A FT D R A 0 1 4 OCA No change. Port enabled/disabled status has changed. Over-current active This bit will automatically transition from 1 to 0 when the over-current condition is removed. 0 RO 0 1 5 OCC The port does not have an over-current condition. The port has currently an over-current condition. Over-current change This bit gets set to one when there is a change to Over-current Active. Software clears this bit by writing a one to this bit position. 0 R/WC 6 FPR Force port resume Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. This bit will automatically change to zero after the resume sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. The resume signaling (Full-speed ‘K’) is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. Writing a zero has no affect because the port controller will time the resume operation clear the bit the port control state switches to HS or FS idle. This bit is 0 if PP (Port Power bit) is 0. 0 1 No resume (K-state) detected/driven on port. Resume detected/driven on port. 0 R/W All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 465 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 21: LPC18xx USB1 Host/Device controller FT D R R A Table 389. Port Status and Control register in host mode (PORTSC1_H - address 0x4000 7184) bit description D R A R A FT D R FT D R A R A A …continued FT F FT Bit Symbol Value Description Reset value Access D D R R A A FT FT 7 SUSP Suspend Together with the PE (Port enabled bit), this bit describes the port states, see Table 390 “Port states as described by the PE and SUSP bits in the PORTSC1 register”. The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. If host software sets this bit to a one when the port is not enabled (i.e. Port enabled bit is a zero) the results are undefined. This bit is 0 if PP (Port Power bit) is 0. 0 1 Port not in suspend state Port in suspend state When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. 0 R/W D D R A FT D R A 8 PR Port reset When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. This bit will automatically change to zero after the reset sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. This bit is 0 if PP (Port Power bit) is 0. 0 1 Port is not in the reset state. Port is in the reset state. High-speed status 0 1 Host/device connected to the port is not in High-speed mode. Host/device connected to the port is in High-speed mode. Line status These bits reflect the current logical levels of the USB_DP and USB_DM signal lines. USB_DP corresponds to bit 11 and USB_DM to bit 10. In host mode, the use of linestate by the host controller driver is not necessary for this controller (unlike EHCI) because the controller hardware manages the connection of LS and FS. 0x0 0x1 0x2 0x3 SE0 (USB_DP and USB_DM LOW) J-state (USB_DP HIGH and USB_DM LOW) K-state (USB_DP LOW and USB_DM HIGH) Undefined 0 R/W 9 HSP 0 RO 11:10 LS 0x3 RO All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 466 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 21: LPC18xx USB1 Host/Device controller FT D R R A Table 389. Port Status and Control register in host mode (PORTSC1_H - address 0x4000 7184) bit description D R A R A FT D R FT D R A R A A …continued FT F FT Bit Symbol Value Description Reset value Access D D R R A A FT FT 12 PP - Port power control Host controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). When power is not available on a port (i.e. PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitioned by the host controller driver from a one to a zero (removing power from the port). 0 R/W D D R A FT D R A 0 1 13 15:14 PIC1_0 Port power off. Port power on. Reserved Port indicator control Writing to this field controls the value of the pins USB1_IND1 and USB1_IND0. 0 00 R/W 0x0 0x1 0x2 0x3 19:16 PTC3_0 Port indicators are off. Amber Green Undefined Port test control 0000 Any value other than 0000 indicates that the port is operating in test mode. The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0x8 to 0xF are reserved. R/W 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 20 WKCN 0 1 TEST_MODE_DISABLE J_STATE K_STATE SE0 (host)/NAK (device) Packet FORCE_ENABLE_HS FORCE_ENABLE_FS FORCE_ENABLE_LS Wake on connect enable (WKCNNT_E) This bit is 0 if PP (Port Power bit) is 0 Disables the port to wake up on device connects. Writing this bit to a one enables the port to be sensitive to device connects as wake-up events. 0 R/W All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 467 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 21: LPC18xx USB1 Host/Device controller FT D R R A Table 389. Port Status and Control register in host mode (PORTSC1_H - address 0x4000 7184) bit description D R A R A FT D R FT D R A R A A …continued FT F FT Bit Symbol Value Description Reset value Access D D R R A A FT FT 21 WKDC 0 1 Wake on disconnect enable (WKDSCNNT_E) This bit is 0 if PP (Port Power bit) is 0. Disables the port to wake up on device disconnects. Writing this bit to a one enables the port to be sensitive to device disconnects as wake-up events. Wake on over-current enable (WKOC_E) 0 1 Disables the port to wake up on over-current events. Writing a one to this bit enabled the port to be sensitive to over-current conditions as wake-up events. PHY low power suspend - clock disable (PLPSCD) In host mode, the PHY can be put into Low Power Suspend – Clock Disable when the downstream device has been put into suspend mode or when no downstream device is connected. Low power suspend is completely under the control of software. 0 1 Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled). Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled). Port force full speed connect 0 1 Port connects at any speed. Writing this bit to a 1 will force the port to only connect at Full Speed. It disables the chirp sequence that allows the port to identify itself as High Speed. This is useful for testing FS configurations with a HS host, hub or device. Reserved Port speed This register field indicates the speed at which the port is operating. For HS mode operation in the host controller and HS/FS operation in the device controller the port routing steers data to the Protocol engine. For FS and LS mode operation in the host controller, the port routing steers data to the Protocol Engine w/ Embedded Transaction Translator. 0x0 0x1 0x2 Full-speed Low-speed High-speed Reserved Parallel transceiver select. All other values are reserved. 0x2 0x3 ULPI Serial/ 1.1 PHY (Full-speed only) 0 R/W D D R A FT D R A 22 WKOC 0 R/W 23 PHCD 0 R/W 24 PFSC 0 R/W 25 - - 27:26 PSPD 0 RO 29:28 31:30 PTS - R/W All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 468 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 21: LPC18xx USB1 Host/Device controller FT D R R A Table 390. Port states as described by the PE and SUSP bits in the PORTSC1 register D R A R A FT D R FT D R A R A FT A FT F PE bit SUSP bit Port state D D 0 1 1 0 or 1 0 1 disabled enabled suspend R R A FT D R A FT D A FT D R A 21.6.16 USB Mode register (USBMODE) The USBMODE register sets the USB mode for the USB controller. The possible modes are Device, Host, and Idle mode. 21.6.16.1 Device mode Table 391. USB Mode register in device mode (USBMODE_D - address 0x4000 71A8) bit description Bit Symbol Value Description Reset value Access 1:0 CM1_0 Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register. 0x0 0x1 0x2 0x3 Idle Reserved Device controller Host controller Endian select This bit can change the byte ordering of the transfer buffers to match the host microprocessor bus architecture. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words. 0 1 Little endian: first byte referenced in least significant byte of 32-bit word. Big endian: first byte referenced in most significant byte of 32-bit word. Setup Lockout mode In device mode, this bit controls behavior of the setup lock mechanism. See Section 20.10.8. 0 1 Setup Lockouts on Setup Lockouts Off (DCD requires the use of Setup Buffer Tripwire in USBCMD) 00 R/ WO 2 ES 0 R/W 3 SLOM 0 R/W All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 469 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 21: LPC18xx USB1 Host/Device controller FT D R R A Table 391. USB Mode register in device mode (USBMODE_D - address 0x4000 71A8) bit description …continued D R A R A FT D R FT D R A R A A Bit Symbol Value Description Reset value Access FT D R A F FT D R A 4 SDIS Stream disable mode Remark: The use of this feature substantially limits the overall USB performance that can be achieved. 0 R/W FT D R A FT D FT D 0 1 Not disabled Disabled. Setting this bit to one disables double priming on both RX and TX for low bandwidth systems. This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. Note: In High Speed Mode, all packets received will be responded to with a NYET handshake when stream disable is active. R A 5 31:6 - Not used in device mode. Reserved 0 - 21.6.16.2 Host mode Table 392. USB Mode register in host mode (USBMODE_H - address 0x4000 71A8) bit description Bit Symbol Value Description Reset value Access 1:0 CM1_0 Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register. 0x0 0x1 0x2 0x3 Idle Reserved Device controller Host controller Endian select This bit can change the byte ordering of the transfer buffers. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words. 0 1 Little endian: first byte referenced in least significant byte of 32-bit word. Big endian: first byte referenced in most significant byte of 32-bit word. Not used in host mode 00 R/ WO 2 ES 0 R/W 3 - 0 - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 470 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 21: LPC18xx USB1 Host/Device controller FT D R R A Table 392. USB Mode register in host mode (USBMODE_H - address 0x4000 71A8) bit description …continued D R A R A FT D R FT D R A R A A Bit Symbol Value Description Reset value Access FT D R A F FT D R A 4 SDIS Stream disable mode Remark: The use of this feature substantially limits the overall USB performance that can be achieved. 0 R/W FT D R A FT D FT D 0 1 Not disabled Disabled. Setting to a 1 ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the the TX latency is filled to capacity before the packet is launched onto the USB. Note: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING to characterize the adjustments needed for the scheduler when using this feature. R A 5 VBPS 0 1 VBUS power select vbus_pwr_select is set LOW. vbus_pwr_select is set HIGH 0 R/WO 31:6 - - Reserved - - 21.6.17 USB Endpoint Setup Status register (ENDPSETUPSTAT) Table 393. USB Endpoint Setup Status register (ENDPTSETUPSTAT - address 0x4000 71AC) bit description Bit Symbol Description Reset value Access 3:0 ENDPT SETUP STAT Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged. Reserved 0 R/WC 31:4 - - - 21.6.18 USB Endpoint Prime register (ENDPTPRIME) For each endpoint, software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. Remark: These bits will be momentarily set by hardware during hardware endpoint re-priming operations when a dTD is retired and the dQH is updated. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 471 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 21: LPC18xx USB1 Host/Device controller FT D R Table 394. USB Endpoint Prime register (ENDPTPRIME - address 0x4000 71B0) bit description Bit Symbol Description Reset value D R A R A FT D R FT D A R R A FT D R R A F Access A FT D R A A 3:0 PERB Prime endpoint receive buffer for physical OUT endpoints. 0 For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3 R/WS FT D R A FT D R A FT D 15:4 - Reserved Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB3 = endpoint 3 0 R/WS 19:16 PETB 31:20 - Reserved - - 21.6.19 USB Endpoint Flush register (ENDPTFLUSH) Writing a one to a bit(s) in this register will cause the associated endpoint(s) to clear any primed buffers. If a packet is in progress for one of the associated endpoints, then that transfer will continue until completion. Hardware will clear this register after the endpoint flush operation is successful. Table 395. USB Endpoint Flush register (ENDPTFLUSH - address 0x4000 71B4) bit description Bit Symbol Description Reset value Access 3:0 FERB Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3 0 R/WS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 472 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 21: LPC18xx USB1 Host/Device controller FT D R Table 395. USB Endpoint Flush register (ENDPTFLUSH - address 0x4000 71B4) bit description Bit Symbol Description Reset value D R A R A FT D R FT D A R R A FT D R R A Access A FT D R F A A 15:4 - Reserved Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB3 = endpoint 3 0 - FT D 19:16 FETB R/WS FT D R A FT D R A 31:20 - Reserved - - 21.6.20 USB Endpoint Status register (ENDPTSTAT) One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay time varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. Remark: These bits will be momentarily cleared by hardware during hardware endpoint re-priming operations when a dTD is retired and the dQH is updated. Table 396. USB Endpoint Status register (ENDPTSTAT - address 0x4000 71B8) bit description Bit Symbol Description Reset value Access 3:0 ERBR Endpoint receive buffer ready for physical OUT endpoints. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR3 = endpoint 3 0 RO 15:4 - Reserved Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR3 = endpoint 3 0 RO 19:16 ETBR 31:20 - Reserved - - 21.6.21 USB Endpoint Complete register (ENDPTCOMPLETE) Each bit in this register indicates that a received/transmit event occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 473 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 21: LPC18xx USB1 Host/Device controller FT D R A D R A R A FT D R FT Writing a one will clear the corresponding bit in this register. D R Table 397. USB Endpoint Complete register (ENDPTCOMPLETE - address 0x4000 71BC) bit description Bit Symbol Description Reset value R A FT D R R A F D R A FT Access A FT A FT D R D 3:0 ERCE Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3 0 R/WC A FT D R A 15:4 - Reserved Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3 0 R/WC 19:16 ETCE 31:20 - Reserved - - 21.6.22 USB Endpoint 0 Control register (ENDPTCTRL0) This register initializes endpoint 0 for control transfer. Endpoint 0 is always a control endpoint. Table 398. USB Endpoint 0 Control register (ENDPTCTRL0 - address 0x4000 71C0) bit description Bit Symbol Value Description Reset value Access 0 RXS 0 1 Rx endpoint stall Endpoint ok. Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1] 0 R/W 1 3:2 6:4 7 RXT RXE 0x0 1 Reserved Endpoint type Endpoint 0 is always a control endpoint. Reserved Rx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1. 1 RO 0 R/W 15:8 - - Reserved - - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 474 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 21: LPC18xx USB1 Host/Device controller FT D R R A Table 398. USB Endpoint 0 Control register (ENDPTCTRL0 - address 0x4000 71C0) bit description …continued D R A R A FT D R FT D R A R A A Bit Symbol Value Description Reset value Access FT D R A F FT D R A 16 TXS 0 1 Tx endpoint stall Endpoint ok. Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1] R/W FT D R A FT D R A FT D 17 - 0x0 1 Reserved Endpoint type Endpoint 0 is always a control endpoint. Reserved Tx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1. 1 RO 0 RO 19:18 TXT 22:20 23 TXE 31:24 [1] - Reserved There is a slight delay (50 clocks max) between the ENPTSETUPSTAT being cleared and hardware continuing to clear this bit. In most systems it is unlikely that the DCD software will observe this delay. However, should the DCD notice that the stall bit is not set after writing a one to it, software should continually write this stall bit until it is set or until a new setup has been received by checking the associated ENDPTSETUPSTAT bit. 21.6.23 Endpoint 1 to 3 control registers Each endpoint that is not a control endpoint has its own register to set the endpoint type and enable or disable the endpoint. Remark: The reset value for all endpoint types is the control endpoint. If one endpoint direction is enabled and the paired endpoint of opposite direction is disabled, then the endpoint type of the unused direction must be changed from the control type to any other type (e.g. bulk). Leaving an unconfigured endpoint control will cause undefined behavior for the data PID tracking on the active endpoint. Table 399. USB Endpoint 1 to 3 control registers (ENDPTCTRL - address 0x4000 71C4 (ENDPTCTRL1) to 0x4000 71CC (ENDPTCTRL3)) bit description Bit Symbol Value Description Reset value Access 0 RXS 0 Rx endpoint stall Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. 1 Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1] 0 R/W All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 475 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 21: LPC18xx USB1 Host/Device controller FT D R R A Table 399. USB Endpoint 1 to 3 control registers (ENDPTCTRL - address 0x4000 71C4 (ENDPTCTRL1) to 0x4000 71CC (ENDPTCTRL3)) bit description …continued Bit Symbol Value Description Reset value D R A R A FT D R FT D R A R A FT Access A FT D R A F R A FT D FT 1 3:2 RXT 0x0 0x1 0x2 0x3 Reserved Endpoint type Control Isochronous Bulk Reserved Reserved Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID. 0 1 Disabled Enabled Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device. 0 00 R/W R/W D D R A FT D R A 4 5 RXI - 0 R/W 6 RXR 0 WS 7 RXE Rx endpoint enable Remark: An endpoint should be enabled only after it has been configured. 0 R/W 0 1 15:8 16 TXS 0 - Endpoint disabled. Endpoint enabled. Reserved Tx endpoint stall Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. 0 R/W 1 Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1] 17 - 0x0 0x1 0x2 0x3 Reserved Tx endpoint type Control Isochronous Bulk Interrupt Reserved All information provided in this document is subject to legal disclaimers. 0 00 R/W 19:18 TXT 20 - - © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 476 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 21: LPC18xx USB1 Host/Device controller FT D R R A Table 399. USB Endpoint 1 to 3 control registers (ENDPTCTRL - address 0x4000 71C4 (ENDPTCTRL1) to 0x4000 71CC (ENDPTCTRL3)) bit description …continued Bit Symbol Value Description Reset value D R A R A FT D R FT D R A R A FT Access A FT D R A F R A FT D FT 21 TXI Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID. 0 1 Enabled Disabled Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID’s between the host and device. 0 R/W D D R A FT D R A 22 TXR 1 WS 23 TXE Tx endpoint enable Remark: An endpoint should be enabled only after it has been configured 0 R/W 0 1 31:24 [1] Endpoint disabled. Endpoint enabled. Reserved 0 - For control endpoints only: There is a slight delay (50 clocks max) between the ENPTSETUPSTAT being cleared and hardware continuing to clear this bit. In most systems it is unlikely that the DCD software will observe this delay. However, should the DCD notice that the stall bit is not set after writing a one to it, software should continually write this stall bit until it is set or until a new setup has been received by checking the associated ENDPTSETUPSTAT bit. 21.7 Functional description For details on the device data structures, see Section 20.9. For the device operational model, see Section 20.10. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 477 of 1164 D R A FT D R A FT D R A FT D R A FT D R A FT UM10430 Chapter 22: LPC18xx Ethernet Rev. 00.13 — 20 July 2011 D D D R A FT D D R A FT D R A FT D R A R A FT D R A R A FT D R A FT D R A F R A FT D R R D User manual FT D R A FT FT A FT 22.1 How to read this chapter The Ethernet controller is available on parts LPC1850 and LPC1830. D D R A FT D R A 22.2 Basic configuration The Ethernet controller is configured as follows: • See Table 400 for clocking and power control. • The Ethernet is reset by the ETHERNET_RST (reset # 22). • The Ethernet interrupt is connected to interrupt slot # 5 in the NVIC, and the is connected to slot # 8 in the event router. • Set the Ethernet mode to RMII or MII in the CREG6 register in the CREG block (see Table 37). Table 400. Ethernet clocking and power control Base clock Branch clock Maximum frequency Notes Ethernet register interface clock Ethernet PHY clock BASE_M3_CLK CLK_M3_ 150 MHz ETHERNET 75 MHz - BASE_PHY_ RX_CLK Select the clock pin ENET_RX_CLK as clock source for this base clock in the OUTCLK_7_CTRL register in the CGU. Select the clock pin ENET_TX_CLK as clock source for this base clock in the OUTCLK_8_CTRL register in the CGU. Ethernet PHY clock BASE_PHY_ TX_CLK - 75 MHz 22.3 Features • • • • • • • • 10/100 Mbit/s TCP/IP hardware checksum IP checksum DMA support IEEE 1588 time stamping block IEEE 1588 advanced time stamp support (IEEE 1588-2008 v2) Power management remote wake-up frame and magic packet detection Supports both full-duplex and half-duplex operation – Supports CSMA/CD Protocol for half-duplex operation. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 478 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R A – Supports IEEE 802.3x flow control for full-duplex operation. – Optional forwarding of received pause control frames to the user application in full-duplex operation. FT D R A D R A R A FT D R FT D R R A R A F D R A FT A FT FT – Back-pressure support for half-duplex operation. D – Automatic transmission of zero-quanta pause frame on deassertion of flow control input in full-duplex operation. D R A FT D R A 22.4 General description 22.5 Pin description Table 401. Ethernet pin description Function name MIIM interface Direction Description ENET_MDIO ENET_MDC ENET_RXD[1:0] ENET_TXD[1:0] ENET_RX_DV ENET_REF_CLK ENET_TX_EN MII interface I/O O I O I I O I O I I O I I/O I I Ethernet MIIM Data Input and Iutput. Ethernet MIIM Clock. Ethernet Receive Data. Ethernet Transmit Tata. Ethernet Receive Data Valid. Ethernet Reference Clock. Ethernet Transmit Data Enable. Ethernet Receive Data. Ethernet Transmit Tata. Ethernet Collision detect. Ethernet Carrier Sense. Ethernet Transmit Error. Ethernet Transmit Clock. Ethernet Receive Clock. Ethernet Receive Data Valid. Ethernet Receive Error. RMII interface (also used for MII interface) ENET_RXD[3:2] ENET_TXD[3:2] ENET_COL ENET_CRS ENET_TX_ER ENET_TX_CLK ENET_RX_CLK ENET_RX_DV ENET_RX_ER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 479 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R A D R A R A FT D R FT 22.6 Register description Table 402. Register overview: Ethernet MAC and DMA (base address 0x4001 0000) Name Access Address offset Description D R Reset value R A FT D R R A F D R A FT A FT A FT D R A D FT MAC_CONFIG MAC_FRAME_FILTER MAC_HASHTABLE_HIGH MAC_HASHTABLE_LOW MAC_MII_ADDR MAC_MII_DATA MAC_FLOW_CTRL MAC_VLAN_TAG MAC_VER MAC_DEBUG MAC_RWAKE_FRFLT MAC_PMT_CTRL_STAT MAC_INTR MAC_INTR_MASK MAC_ADDR0_HIGH MAC_ADDR0_LOW MAC_TIMESTP_CTRL DMA_BUS_MODE DMA_TRANS_POLL_DEMAND DMA_REC_POLL_DEMAND DMA_REC_DES_ADDR DMA_TRANS_DES_ADDR DMA_STAT DMA_OP_MODE DMA_INT_EN DMA_MFRM_BUFOF DMA_REC_INT_WDT DMA_CURHOST_TRANS_DES DMA_CURHOST_REC_DES - 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 0x0038 0x003C 0x0040 0x0044 0x0048 0x06FC 0x0700 0x0704 0x0FFC 0x1000 0x1004 0x1008 0x100C 0x1010 0x1014 0x1018 0x101C 0x1020 0x1024 0x1028 0x1044 0x1048 0x104C MAC configuration register MAC frame filter Hash table high register Hash table low register MII address register MII data register Flow control register VLAN tag register Version register Debug register Remote wake-up frame filter PMT control and status Reserved Interrupt status register Interrupt mask register MAC address 0 high register MAC address 0 low register Reserved Time stamp control register Reserved Bus Mode Register Transmit poll demand register Receive poll demand register Receive descriptor list address register Status register Operation mode register Interrupt enable register Missed frame and buffer overflow register Receive interrupt watchdog timer register Reserved 0x0000 8000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 1036 0x0000 0000 0x0000 0000 0x0000 0000 D R A 0x0000 0000 0x0000 0000 0x8000 FFFF 0xFFFF FFFF 0x0000 2000 0x0002 0100 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 Transmit descriptor list address register 0x0000 0000 Current host transmit descriptor register 0x0000 0000 Current host receive descriptor register 0x0000 0000 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 480 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R A D R A R A FT D R FT Table 402. Register overview: Ethernet MAC and DMA (base address 0x4001 0000) Name Access Address offset Description D R Reset value R A FT D R R A F D R A A FT A DMA_CURHOST_TRANS_BUF DMA_CURHOST_REC_BUF DMA_HW_FEATURE 0x1050 0x1054 0x1058 Current host transmit buffer address register Current host receive buffer address register HW feature register 0x0000 0000 FT D R A FT D R A 0x0000 0000 0x0105 2715 FT D 22.6.1 MAC Configuration register The MAC Configuration register establishes receive and transmit operating modes. Table 403. MAC Configuration register (MAC_CONFIG, address 0x4001 0000) bit description Bit Symbol Description Reset Access value 1:0 2 RE Reserved Receiver enable When this bit is set, the receiver state machine of the MAC is enabled for receiving frames from the MII. When this bit is reset, the MAC receive state machine is disabled after the completion of the reception of the current frame, and will not receive any further frames from the MII. 00 0 RO R/W 3 TE Transmitter Enable When this bit is set, the transmit state machine of the MAC is enabled for transmission on the MII. When this bit is reset, the MAC transmit state machine is disabled after the completion of the transmission of the current frame, and will not transmit any further frames. 0 R/W 4 DF Deferral Check When this bit is set, the deferral check function is enabled in the MAC. The MAC will issue a Frame Abort status, along with the excessive deferral error bit set in the transmit frame status when the transmit state machine is deferred for more than 24,288 bit times in 10/100-Mbps mode. If the Core is configured for 1000 Mbps operation, or if the Jumbo frame mode is enabled in 10/100-Mbps mode, the threshold for deferral is 155,680 bits times. Deferral begins when the transmitter is ready to transmit, but is prevented because of an active CRS (carrier sense) signal on the MII. Defer time is not cumulative. If the transmitter defers for 10,000 bit times, then transmits, collides, backs off, and then has to defer again after completion of back-off, the deferral timer resets to 0 and restarts. When this bit is reset, the deferral check function is disabled and the MAC defers until the CRS signal goes inactive. This bit is applicable only in Half-Duplex mode and is reserved (RO) in Full-Duplex-only configuration. 0 R/W All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 481 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D Table 403. MAC Configuration register (MAC_CONFIG, address 0x4001 0000) bit description …continued Bit Symbol Description D R A R A FT D R R R A FT D R A R A FT Reset Access value A F FT D D R R A A 6:5 BL Back-Off Limit The Back-Off limit determines the random integer number (r) of slot time delays (4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps) the MAC waits before rescheduling a transmission attempt during retries after a collision. This bit is applicable only to Half-Duplex mode and is reserved (RO) in Full-Duplex-only configuration. 0 R/W FT D R A FT D R A FT D • • • • 7 ACS 00: k = min (n, 10) 01: k = min (n, 8) 10: k = min (n, 4) 11: k = min (n, 1) where n = retransmission attempt. The random integer r takes the value in the range 0  r  2k. Automatic Pad/CRC Stripping When this bit is set, the MAC strips the Pad/FCS field on incoming frames only if the length’s field value is less than or equal to 1,500 bytes. All received frames with length field greater than or equal to 1,501 bytes are passed to the application without stripping the Pad/FCS field. When this bit is reset, the MAC will pass all incoming frames to the Host unmodified. 8 Link Up/Down Indicates whether the link is up or down during the transmission of configuration in SMII interface: 0 = Link down 1 = Link up 9 DR Disable Retry When this bit is set, the MAC will attempt only 1 transmission. When a collision occurs on the MII, the MAC will ignore the current frame transmission and report a Frame Abort with excessive collision error in the transmit frame status. When this bit is reset, the MAC will attempt retries based on the settings of BL. This bit is applicable only to Half-Duplex mode and is reserved (RO with default value) in Full- Duplex-only configuration. 10 IPC Checksum Offload When this bit is set, the MAC calculates the 16-bit one’s complement of the one’s complement sum of all received Ethernet frame payloads. It also checks whether the IPv4 Header checksum (assumed to be bytes 25–26 or 29–30 (VLAN-tagged) of the received Ethernet frame) is correct for the received frame and gives the status in the receive status word. The MAC core also appends the 16-bit checksum calculated for the IP header datagram payload (bytes after the IPv4 header) and appends it to the Ethernet frame transferred to the application (when Type 2 COE is deselected). When this bit is reset, this function is disabled. When Type 2 COE is selected, this bit, when set, enables IPv4 checksum checking for received frame payload’s TCP/UDP/ICMP headers. When this bit is reset, the COE function in the receiver is disabled and the corresponding PCE and IP HCE status bits (see ) are always cleared. 11 DM Duplex Mode When this bit is set, the MAC operates in a Full-Duplex mode where it can transmit and receive simultaneously. 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 482 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D Table 403. MAC Configuration register (MAC_CONFIG, address 0x4001 0000) bit description …continued Bit Symbol Description D R A R A FT D R R R A FT D R A R A FT Reset Access value A F FT D D R R A A 12 LM Loopback Mode When this bit is set, the MAC operates in loopback mode at MII. The (G)MII Receive clock input is required for the loopback to work properly, as the Transmit clock is not looped-back internally. 0 R/W FT D R A FT D R A FT D 13 DO Disable Receive Own When this bit is set, the MAC disables the reception of frames in Half-Duplex mode. When this bit is reset, the MAC receives all packets that are given by the PHY while transmitting. This bit is not applicable if the MAC is operating in Full-Duplex mode. 0 R/W 14 FES Speed Indicates the speed in Fast Ethernet (MII) mode: 0 = 10 Mbps 1 = 100 Mbps . 0 15 PS Port select 1 = MII (100 Mbp) - this is the only allowed value. 1 RO 16 DCRS Disable carrier sense during transmission When set high, this bit makes the MAC transmitter ignore the (G)MII CRS signal during frame transmission in Half-Duplex mode. This request results in no errors generated due to Loss of Carrier or No Carrier during such transmission. When this bit is low, the MAC transmitter generates such errors due to Carrier Sense and will even abort the transmissions. 0 R/W 19:17 IFG Inter-frame gap These bits control the minimum IFG between frames during transmission. 000 = 96 bit times 001 = 88 bit times 010 = 80 bit times ... 000 = 40 bit times Note that in Half-Duplex mode, the minimum IFG can be configured for 64 bit times (IFG = 100) only. Lower values are not considered 000 R//W 20 JE Jumbo Frame Enable When this bit is set, MAC allows Jumbo frames of 9,018 bytes (9,022 bytes for VLAN tagged frames) without reporting a giant frame error in the receive frame status. 0 R/W 21 - Reserved. 0 RO All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 483 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D Table 403. MAC Configuration register (MAC_CONFIG, address 0x4001 0000) bit description …continued Bit Symbol Description D R A R A FT D R R R A FT D R A R A FT Reset Access value A F FT D D R R A A 22 JD Jabber Disable When this bit is set, the MAC disables the jabber timer on the transmitter, and can transfer frames of up to 16,384 bytes. When this bit is reset, the MAC cuts off the transmitter if the application sends out more than 2,048 bytes of data (10,240 if JE is set high) during transmission. 0 R/W FT D R A FT D R A FT D 23 WD Watchdog Disable When this bit is set, the MAC disables the watchdog timer on the receiver, and can receive frames of up to 16,384 bytes. When this bit is reset, the MAC allows no more than 2,048 bytes (10,240 if JE is set high) of the frame being received and cuts off any bytes received after that. 0 R/W 31:24 - Reserved. 0x00 RO 22.6.2 MAC Frame filter register The MAC Frame Filter register contains the filter controls for receiving frames. Some of the controls from this register go to the address check block of the MAC, which performs the first level of address filtering. The second level of filtering is performed on the incoming frame, based on other controls such as Pass Bad Frames and Pass Control Frames. Table 404. MAC Frame filter register (MAC_FRAME_FILTER, address 0x4001 0004) bit description Bit Symbol Description Reset Access value 0 PR Promiscuous Mode When this bit is set, the Address Filter module passes all incoming frames regardless of its destination or source address. The SA/DA Filter Fails status bits of the Receive Status Word will always be cleared when PR is set. 0 R/W 1 2 3 DAIF reserved reserved DA Inverse Filtering When this bit is set, the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast frames. When reset, normal filtering of frames is performed. 0 0 0 RO RO R/W 4 PM Pass All Multicast When set, this bit indicates that all received frames with a multicast destination address (first bit in the destination address field is '1') are passed. When reset, filtering of multicast frame depends on HMC bit. 0 R/W 5 DBF Disable Broadcast Frames When this bit is set, the AFM module filters all incoming broadcast frames. When this bit is reset, the AFM module passes all received broadcast frames. 0 R/W All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 484 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R R A Table 404. MAC Frame filter register (MAC_FRAME_FILTER, address 0x4001 0004) bit description …continued D R A R A FT D R FT D R A R A A Bit Symbol Description Reset Access value FT D R A F FT D R A 7:6 PCF Pass Control Frames These bits control the forwarding of all control frames (including unicast and multicast PAUSE frames). Note that the processing of PAUSE control frames depends only on RFE of Flow Control Register[2]. 00 = MAC filters all control frames from reaching the application. 01 = MAC forwards all control frames except PAUSE control frames to application even if they fail the Address filter. 10 = MAC forwards all control frames to application even if they fail the Address Filter. 11 = MAC forwards control frames that pass the Address Filter. 00 R/W FT D R A FT D R A FT D 8 SAIF SA Inverse Filtering When this bit is set, the Address Check block operates in inverse filtering mode for the SA address comparison. The frames whose SA matches the SA registers will be marked as failing the SA Address filter. When this bit is reset, frames whose SA does not match the SA registers will be marked as failing the SA Address filter. 0 R/W 9 SAF Source Address Filter Enable The MAC core compares the SA field of the received frames with the values programmed in the enabled SA registers. If the comparison matches, then the SAMatch bit of RxStatus Word is set high. When this bit is set high and the SA filter fails, the MAC drops the frame. When this bit is reset, then the MAC Core forwards the received frame to the application and with the updated SA Match bit of the RxStatus depending on the SA address comparison. 0 R/W 30:10 31 RA Reserved Receive all When this bit is set, the MAC Receiver module passes to the Application all frames received irrespective of whether they pass the address filter. The result of the SA/DA filtering is updated (pass or fail) in the corresponding bits in the Receive Status Word. When this bit is reset, the Receiver module passes to the Application only those frames that pass the SA/DA address filter. 0 0 RO R/W 22.6.3 MAC Hash table high register The 64-bit Hash table is used for group address filtering. For hash filtering, the contents of the destination address in the incoming frame is passed through the CRC logic, and the upper 6 bits of the CRC register are used to index the contents of the Hash table. The most significant bit determines the register to be used (Hash Table High/Hash Table Low), and the other 5 bits determine which bit within the register. A hash value of 00000 selects Bit 0 of the selected register, and a value of 11111 selects Bit 31 of the selected register. For example, if the DA of the incoming frame is received as 0x1F52419CB6AF (0x1F is the first byte received on MII interface), then the internally calculated 6-bit Hash value is 0x2C and the HTH register bit[12] is checked for filtering. If the DA of the incoming frame is received as 0xA00A98000045, then the calculated 6- bit Hash value is 0x07 and the HTL register bit[7] is checked for filtering. If the corresponding bit value of the register is 1, the frame is accepted. Otherwise, it is rejected. If the PM (Pass All Multicast) bit is set in the MAC_CONFIG register, then all multicast frames are accepted regardless of the multicast hash values. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 485 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R R A If the Hash Table register is configured to be double-synchronized to the (G)MII clock domain, the synchronization is triggered only when Bits[31:24] (in Little-Endian mode) or Bits[7:0] (in Big-Endian mode) of the Hash Table High/Low registers are written to. Please note that consecutive writes to these register should be performed only after at least 4 clock cycles in the destination clock domain when double synchronization is enabled. R A A FT D R A FT D The Hash Table High register contains the higher 32 bits of the Hash table. Table 405. MAC Hash table high register (MAC_HASHTABLE_HIGH, address 0x4001 0008) bit description Bit Symbol Description Reset Access value D R A R A FT D R FT D R A F R A FT D FT D R A D FT R A 31:0 HTH Hash table high This field contains the upper 32 bits of Hash table. 0 R/W 22.6.4 MAC Hash table low register The Hash Table Low register contains the lower 32 bits of the Hash table. Table 406. MAC Hash table low register (MAC_HASHTABLE_LOW, address 0x4001 0008) bit description Bit Symbol Description Reset Access value 31:0 HTL Hash table low This field contains the upper 32 bits of Hash table. 0 R/W 22.6.5 MAC MII Address register The MII Address register controls the management cycles to the external PHY through the management interface. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 486 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R Table 407. MAC MII Address register (MAC_MII_ADDR, address 0x4001 0010) bit description Bit Symbol Description D R A R A FT D R FT D A R Reset Access value R A FT D R R A F D R A A FT A 0 GB MII busy This bit should read a logic 0 before writing to this register and the MAC_MII_DATA register. This bit must also be set to 0 during a Write to this register. During a PHY register access, this bit will be set to 1 by the Application to indicate that a Read or Write access is in progress. The MAC_MII_DATA register should be kept valid until this bit is cleared by the MAC during a PHY Write operation. The MAC_MII_DATA register is invalid until this bit is cleared by the MAC during a PHY Read operation. This register should not be written to until this bit is cleared. 0 R_WS_ SC FT D A FT D R A FT D R 1 W MII write When set, this bit tells the PHY that this will be a Write operation using the MII Data register. If this bit is not set, this will be a Read operation, placing the data in the MII Data register. 0 R/W 5:2 CR CSR clock range The CSR Clock Range selection determines the frequency of the MDC clock . The suggested range of clk_csr_i frequency applicable for each value below (when Bit[5] = 0) ensures that the MDC clock is approximately between the frequency range 1.0 MHz - 2.5 MHz. When bit 5 is set, you can achieve MDC clock of frequency higher than the IEEE 802.3 specified frequency limit of 2.5 MHz and program a clock divider of lower value. For example, when clk_csr_i is of frequency 100 Mhz and you program these bits as 1010, then the resultant MDC clock will be of 12.5 Mhz which is outside the limit of IEEE 802.3 specified range. Please program the values given below only if the interfacing chips supports faster MDC clocks. See Table 408 for bit values. 0 R/W 10:6 15:11 31:16 GR PA - MII register These bits select the desired MII register in the selected PHY device. Physical layer address This field tells which of the 32 possible PHY devices are being accessed. Reserved Table 408. CSR clock range values Bits 5:2 clk_csr_i MDC clock 0 0 0 R/W R/W RO 0000 0001 0010 0011 0100 0101 0110, 0111 1000 1001 1010 1011 1100 60 - 100 MHz 100 - 150 MHz 20 - 35 MHz 35 - 60 MHz 150 - 250 MHz 250 - 300 MHz Reserved All information provided in this document is subject to legal disclaimers. clk_csr_i/42 clk_csr_i/62 clk_csr_i/16 clk_csr_i/26 clk_csr_i/102 clk_csr_i/124 clk_csr_i/42 clk_csr_i/62 clk_csr_i/16 clk_csr_i/26 clk_csr_i/102 © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 487 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R A D R A R A FT D R FT Table 408. CSR clock range values Bits 5:2 clk_csr_i MDC clock D R R A FT D R A F D A FT 1101 1110 1111 - clk_csr_i/124 clk_csr_i/42 clk_csr_i/62 R R A FT D R A FT D A FT D R 22.6.6 MAC MII Data register The MII Data register stores Write data to be written to the PHY register located at the address specified in the MAC_MII_ADDR register. This register also stores Read data from the PHY register located at the address specified by the MAC_MII_ADDR register. Table 409. MII Data register (MAC_MII_DATA, address 0x4001 0014) bit description Bit Symbol Description Reset Access value A 15:0 GD MII data This contains the 16-bit data value read from the PHY after a Management Read operation or the 16-bit data value to be written to the PHY before a Management Write operation. 0 R/W 31:16 - Reserved 0 RO 22.6.7 MAC Flow control register The Flow Control register controls the generation and reception of the Control (Pause Command) frames by the MAC’s Flow control module. A Write to a register with the Busy bit set to 1 triggers the Flow Control block to generate a Pause Control frame. The fields of the control frame are selected as specified in the 802.3x specification, and the Pause Time value from this register is used in the Pause Time field of the control frame. The Busy bit remains set until the control frame is transferred onto the cable. The Host must make sure that the Busy bit is cleared before writing to the register. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 488 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R Table 410. MAC Flow control register (MAC_FLOW_CTRL, address 0x4001 0018) bit description Bit Symbol Description D R A R A FT D R FT D A R Reset Access value R A FT D R R A F D R A A FT A 0 FCB Flow Control Busy/Backpressure Activate This bit initiates a Pause Control frame in Full-Duplex mode. In Full-Duplex mode, this bit should be read as 0 before writing to the Flow Control register. To initiate a Pause control frame, the Application must set this bit to 1. During a transfer of the Control Frame, this bit will continue to be set to signify that a frame transmission is in progress. After the completion of Pause control frame transmission, the MAC will reset this bit to 0. The Flow Control register should not be written to until this bit is cleared. In Half-Duplex mode, when this bit is set (and TFE is set), then backpressure is asserted by the MAC Core. During backpressure, when the MAC receives a new frame, the transmitter starts sending a JAM pattern resulting in a collision. This control register bit is logically OR’ed with the mti_flowctrl_i input signal for the backpressure function. When the MAC is configured to Full- Duplex mode, the BPA is automatically disabled. 0 R/WS/ SC FT D R A FT D R A FT D 1 TFE Transmit Flow Control Enable In Full-Duplex mode, when this bit is set, the MAC enables the flow control operation to transmit Pause frames. When this bit is reset, the flow control operation in the MAC is disabled, and the MAC will not transmit any Pause frames. In Half-Duplex mode, when this bit is set, the MAC enables the back-pressure operation. When this bit is reset, the backpressure feature is disabled. 0 R/W 2 RFE Receive Flow Control Enable When this bit is set, the MAC will decode the received Pause frame and disable its transmitter for a specified (Pause Time) time. When this bit is reset, the decode function of the Pause frame is disabled. 0 R/W 3 UP Unicast Pause Frame Detect When this bit is set, the MAC will detect the Pause frames with the station’s unicast address specified in MAC Address0 High Register and MAC Address0 Low Register, in addition to the detecting Pause frames with the unique multicast address. When this bit is reset, the MAC will detect only a Pause frame with the unique multicast address specified in the 802.3x standard. 0 R/W 5:4 PLT Pause Low Threshold This field configures the threshold of the PAUSE timer at which the input flow control is checked for automatic retransmission of PAUSE Frame. The threshold values should be always less than the Pause Time configured in Bits[31:16]. For example, if PT = Ox100 (256 slot-times), and PLT = 01, then a second PAUSE frame is automatically transmitted if the flow control signal is asserted at 228 (256 – 28) slot-times after the first PAUSE frame is transmitted. 00 R/W 6 7 DZPQ Reserved Disable Zero-Quanta Pause When set, this bit disables the automatic generation of Zero-Quanta Pause Control frames on the deassertion of the flow-control signal from the FIFO layer . When this bit is reset, normal operation with automatic Zero-Quanta Pause Control frame generation is enabled. 0x000 RO 0 R/W 15:8 31:16 PT Reserved Pause time This field holds the value to be used in the Pause Time field in the transmit control frame. If the Pause Time bits is configured to be double-synchronized to the (G)MII clock domain, then consecutive writes to this register should be performed only after at least 4 clock cycles in the destination clock domain. 0 RO 0x000 R/W 0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 489 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R A D R A R A FT D R FT 22.6.8 MAC VLAN tag register D R The VLAN Tag register contains the IEEE 802.1Q VLAN Tag to identify the VLAN frames. The MAC compares the 13th and 14th bytes of the receiving frame (Length/Type) with 0x8100, and the following 2 bytes are compared with the VLAN tag; if a match occurs, it sets the received VLAN bit in the receive frame status. The legal length of the frame is increased from 1518 bytes to 1522 bytes. If the VLAN Tag register is configured to be double-synchronized to the MII clock domain, then consecutive writes to these register should be performed only after at least 4 clock cycles in the destination clock domain. Table 411. MAC VLAN tag register (MAC_VLAN_TAG, address 0x4001 01C) bit description Bit Symbol Description Reset Access value R A FT D R R A F D R A FT D FT D R A A FT R A A FT D 15:0 VL VLAN Tag Identifier for Receive Frames This contains the 802.1Q VLAN tag to identify VLAN frames, and is compared to the fifteenth and sixteenth bytes of the frames being received for VLAN frames. Bits[15:13] are the User Priority, Bit[12] is the Canonical Format Indicator (CFI) and bits[11:0] are the VLAN tag’s VLAN Identifier (VID) field. When the ETV bit is set, only the VID (Bits[11:0]) is used for comparison. If VL (VL[11:0] if ETV is set) is all zeros, the MAC does not check the fifteenth and sixteenth bytes for VLAN tag comparison, and declares all frames with a Type field value of 0x8100 to be VLAN frames. 0x000 R/W 0 16 ETV Enable 12-Bit VLAN Tag Comparison When this bit is set, a 12-bit VLAN identifier, rather than the complete 16-bit VLAN tag, is used for comparison and filtering. Bits[11:0] of the VLAN tag are compared with the corresponding field in the received VLAN-tagged frame. When this bit is reset, all 16 bits of the received VLAN frame’s fifteenth and sixteenth bytes are used for comparison. 0 R/W 31:17 - Reserved 0x000 RO 0 22.6.9 MAC Debug register This debug register gives the status of all the main modules of the transmit and receive data-paths and the FIFOs. An all-zero status indicates that the MAC core is in idle state (and FIFOs are empty) and no activity is going on in the data-paths. Table 412. MAC Debug register (MAC_DEBUG, address 0x4001 0024) bit description Bit Symbol Description Reset Access value 0 2:1 3 4 RXIDLES When high, it indicates that the MAC MII receive protocol engine is actively receiving TAT data and not in IDLE state. FIFOSTA When high, it indicates the active state of the small FIFO Read and Write controllers T0 respectively of the MAC receive Frame Controller module. RXFIFO STAT1 Reserved When high, it indicates that the MTL RxFIFO Write Controller is active and transferring a received frame to the FIFO. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 490 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R Table 412. MAC Debug register (MAC_DEBUG, address 0x4001 0024) bit description …continued Bit Symbol Description D R A R A FT D R FT D A R Reset Access value R A FT D R R A F D R A A FT A 6:5 RXFIFO STAT State of the RxFIFO read Controller: 00 = idle state 01 = reading frame data 10 = reading frame status (or time stamp) 11 = flushing the frame data and status FT D R A FT D R A FT D 7 9:8 - Reserved RXFIFOL Status of the RxFIFO Fill-level VL 00 = RxFIFO Empty 01 = RxFIFO fill-level below flow-control de-activate threshold 10 = RxFIFO fill-level above flow-control activate threshold 11 = RxFIFO Full 15:10 16 18:17 - Reserved - RO TXIDLES When high, it indicates that the MAC MII transmit protocol engine is actively TAT transmitting data and not in IDLE state. TXSTAT State of the MAC Transmit Frame Controller module: 00 = idle 01 = Waiting for Status of previous frame or IFG/backoff period to be over 10 = Generating and transmitting a PAUSE control frame (in full duplex mode) 11 = Transferring input frame for transmission 19 21:20 PAUSE When high, it indicates that the MAC transmitter is in PAUSE condition (in full-duplex only) and hence will not schedule any frame for transmission. TXFIFOS State of the TxFIFO read Controller TAT 00 = idle state 01 = READ state (transferring data to MAC transmitter) 10 = Waiting for TxStatus from MAC transmitter 11 = Writing the received TxStatus or flushing the TxFIFO 22 23 24 25 31:26 TXFIFOS When high, it indicates that the MTL TxFIFO Write Controller is active and TAT1 transferring data to the TxFIFO. Reserved TXFIFOL When high, it indicates that the MTL TxFIFO is not empty and has some data left for VL transmission. TXFIFOF When high, it indicates that the MTL TxStatus FIFO is full and hence the MTL will not ULL be accepting any more frames for transmission. 22.6.10 MAC Remote wake-up frame filter register This is the address through which the remote Wake-up Frame Filter registers (WKUPFMFILTER) are written/read by the Application. WKUPFMFILTER is actually a pointer to eight (not transparent) such WKUPFMFILTER registers. Eight sequential Writes to this address (0x028) will write all WKUPFMFILTER registers. Eight sequential Reads from this address (0x028) will read all WKUPFMFILTER registers. See Section 22.7.1.1 for details. Remark: Do not use bit-banding for this register. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 491 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R R A Table 413. MAC Remote wake-up frame filter register (MAC_RWAKE_FRFLT, address 0x4001 0028) bit description D R A R A FT D R FT D R A R A A FT D F FT D Bit Symbol Description Reset Access value R R A A FT D FT 31:0 ADDR WKUPFMFILTER address - R/W D R A FT D 22.6.11 MAC PMT control and status register The PMT control and status registers programs the request wake-up events and monitors the wake-up events. See Section 22.7.1 for details. Table 414. MAC PMT control and status register (MAC_PMT_CTRL_STAT, address 0x4001 002C) bit description Bit Symbol Description Reset Access value R A 0 PD Power-down When set, all received frames will be dropped. This bit is cleared automatically when a magic packet or Wake-Up frame is received, and Power-Down mode is disabled. Frames received after this bit is cleared are forwarded to the application.This bit must only be set when either the Magic Packet Enable or Wake- Up Frame Enable bit is set high. 0 R/WS/ SC 1 MPE Magic packet enable When set, enables generation of a power management event due to Magic Packet reception. 0 R/W 2 WFE Wake-up frame enable When set, enables generation of a power management event due to wake-up frame reception. 0 R/W 4:3 5 MPR Reserved Magic Packet Received When set, this bit indicates the power management event was generated by the reception of a Magic Packet. This bit is cleared by a Read into this register. 00 0 RO R/SS/R C R/SS/R C 6 WFR Wake-up Frame Received When set, this bit indicates the power management event was generated due to reception of a wake-up frame. This bit is cleared by a Read into this register. 0 8:7 9 GU Reserved Global Unicast When set, enables any unicast packet filtered by the MAC (DAF) address recognition to be a wake-up frame. 0 0 RO R/W 30:10 31 - Reserved 0x00 0000 0 RO R/WS/ SC WFFRPR Wake-up Frame Filter Register Pointer Reset When set, resets the Remote Wake-up Frame Filter register pointer to 000. It is automatically cleared after 1 clock cycle. 22.6.12 MAC Interrupt status register The Interrupt Status register contents identify the events in the MAC-CORE that can generate interrupt. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 492 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R R A Table 415. MAC Interrupt status register (MAC_INTR, address 0x4001 0038) bit description D R A R A FT D R FT D R A R A A FT FT F Bit Symbol Description Reset Access value D D R R A A 31:0 - Reserved 0 RO FT D R A FT FT D 22.6.13 MAC Interrupt mask register The Interrupt Mask Register bits enables the user to mask the interrupt signal due to the corresponding event in the Interrupt Status Register. Table 416. MAC Interrupt mask register (MAC_INTR_MASK, address 0x4001 003C) bit description Bit Symbol Description Reset Access value D R A 2:0 3 - Reserved This bit when set, will disable the assertion of the interrupt signal due to the setting of PMT Interrupt Status bit in Table 415. 0 0 RO R/W PMTMSK PMT Interrupt Mask 31:4 Reserved 0 R/W 22.6.14 MAC Address 0 high register The MAC Address 0 High register holds the upper 16 bits of the 6-byte first MAC address of the station. Note that the first DA byte that is received on the (G)MII interface corresponds to the LS Byte (Bits [7:0]) of the MAC Address Low register. For example, if 0x112233445566 is received (0x11 is the first byte) on the (G)MII as the destination address, then the MacAddress0 Register [47:0] is compared with 0x665544332211. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then the synchronization is triggered only when Bits[31:24] (in Little-Endian mode) or Bits[7:0] (in Big-Endian mode) of the MAC Address Low Register (Register 17) are written to. Please note that consecutive writes to this Address Low Register should be performed only after at least 4 clock cycles in the destination clock domain for proper synchronization updates. Table 417. MAC Address 0 high register (MAC_ADDR0_HIGH, address 0x4001 0040) bit description Bit Symbol Description Reset value Access 15:0 A47_32 MAC Address0 [47:32] This field contains the upper 16 bits (47:32) of the 6-byte first MAC address. This is used by the MAC for filtering for received frames and for inserting the MAC address in the Transmit Flow Control (PAUSE) Frames. 0xFFFF R/W 30:16 31 MO Reserved Always 1 0x0000 RO 1 RO 22.6.15 MAC Address 0 low register The MAC Address 0 Low register holds the lower 32 bits of the 6-byte first MAC address of the station. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 493 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R R A Table 418. MAC Address 0 low register (MAC_ADDR0_LOW, address 0x4001 0044) bit description D R A R A FT D R FT D R A R A FT D A F FT D Bit Symbol Description Reset value Access R R A A FT FT D 31:0 A31_0 MAC Address0 [31:0] This field contains the lower 32 bits of the 6-byte first MAC address. This is used by the MAC for filtering for received frames and for inserting the MAC address in the Transmit Flow Control (PAUSE) Frames. 0xFFFF FFFF R/W D R A FT D R A 22.6.16 MAC IEEE1588 time stamp control register This register controls the operation of the System Time generator and the snooping of PTP packets for time-stamping in the Receiver. Table 419. MAC IEEE1588 time stamp control register (MAC_TIMESTP_CTRL, address 0x4001 0700) bit description Bit Symbol Description Reset Access value 0 TSENA Time Stamp Enable When this bit, is set the timestamping is enabled for transmit and receive frames. When disabled timestamp is not added for transmit and receive frames and the TimeStamp Generator is also suspended. User has to always initialize the TimeStamp (system time) after enabling this mode. 0 R/W 1 TSCFUP Time Stamp Fine or Coarse Update DT When set, indicates that the system times update to be done using fine update method. When reset it indicates the system time stamp update to be done using Coarse method. This bit is reserved if the fine correction option is not enabled. TSINIT Time Stamp Initialize When set, the system time is initialized (over-written) with the value specified in the Time Stamp High Update and Time Stamp Low Update registers. This register bit should be read zero before updating it. This bit is reset once the initialize is complete. 0 R/W 2 0 R/W/S C 3 TSUPDT Time Stamp Update When set, the system time is updated (added/subtracted) with the value specified in the Time Stamp High Update and Time Stamp Low Update registers. This register bit should be read zero before updating it. This bit is reset once the update is completed in hardware. 0 R/W/S C 4 TSTRIG Time Stamp Interrupt Trigger Enable When set, the Time Stamp interrupt is generated when the System Time becomes greater than the value written in Target Time register. This bit is reset after the generation of Time Stamp Trigger Interrupt. 0 R/WSC 5 TSADDR Addend Reg Update EG When set, the contents of the Time Stamp Addend register is updated in the PTP block for fine correction. This is cleared when the update is completed. This register bit should be zero before setting it. This is a reserved bit when only coarse correction option is selected. TSENAL L Reserved Enable Time Stamp for All Frames When set, the time stamp snapshot is enabled for all frames received by the core. 0 R/W 7:6 8 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 494 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R R A Table 419. MAC IEEE1588 time stamp control register (MAC_TIMESTP_CTRL, address 0x4001 0700) bit description D R A R A FT D R FT D R A R A A Bit Symbol Description Reset Access value FT D R A F FT D R A 9 TSCTRL SSR Time Stamp Digital or Binary rollover control When set, the Time Stamp Low register rolls over after 0x3B9A_C9FF value (i.e., 1 nanosecond accuracy) and increments the Time Stamp (High) seconds. When reset, the rollover value of sub-second register is 0x7FFF_FFFF. The sub-second increment has to be programmed correctly depending on the PTP reference clock frequency and this bit value. Enable PTP packet snooping for version 2 format When set, the PTP packets are snooped using the 1588 version 2 format else snooped using the version 1 format. 0 R/W FT D R A FT D R A FT D 10 TSVER2 ENA 0 R/W 11 TSIPENA Enable Time Stamp Snapshot for PTP over Ethernet frames When set, the time stamp snapshot is taken for frames which have PTP messages in Ethernet frames (PTP over Ethernet) also. By default snapshots are taken for UDP-IP-Ethernet PTP packets. 0 R/W 12 13 14 TSIPV6E Enable Time Stamp Snapshot for IPv6 frames NA When set, the time stamp snapshot is taken for IPv6 frames. TSIPV4E Enable Time Stamp Snapshot for IPv4 frames NA When set, the time stamp snapshot is taken for IPv4 frames. TSEVNT ENA Enable Time Stamp Snapshot for Event Messages When set, the time stamp snapshot is taken for event messages only . When reset snapshot is taken for all other messages except Announce, Management and Signaling. 0 1 0 R/W R/W R/W 15 TSMSTR Enable Snapshot for Messages Relevant to Master 0 ENA When set, the snapshot is taken for messages relevant to master node only else snapshot is taken for messages relevant to slave node. This is valid only for ordinary clock and boundary clock node. TSCLKT YPE Select the type of clock node The following are the options to select the type of clock node: 00 = ordinary clock 01 = boundary clock 10 = end-to-end transparent clock 11 = peer-to-peer transparent clock 00 R/W 17:16 R/W 18 TSENMA Enable MAC address for PTP frame filtering 0 CADDR When set, uses the DA MAC address (that matches any MAC Address register except the default MAC address 0) to filter the PTP frames when PTP is sent directly over Ethernet. R/W 31:19 Table 420 indicates the messages, for which a snapshot is taken depending on the clock, enable master and enable snapshot for event message register settings. Table 420. Time stamp snapshot dependency on register bits TSCLKTYPE TSMSTRENA TSEVNTENA Messages for which snapshot is taken 00 or 01 00 or 01 00 or 01 10 x 1 0 N/A 0 1 1 0 SYNC, Follow_Up, Delay_Req, Delay_Resp Delay_req SYNC SYNC, Follow_Up, Delay_Req, Delay_Resp © NXP B.V. 2011. All rights reserved. All information provided in this document is subject to legal disclaimers. User manual Rev. 00.13 — 20 July 2011 495 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R A D R A R A FT D R FT Table 420. Time stamp snapshot dependency on register bits TSCLKTYPE TSMSTRENA TSEVNTENA D R Messages for which snapshot is taken R A FT D R A F D A FT 10 11 11 N/A N/A N/A 1 0 1 SYNC, Follow_Up R SYNC, Follow_Up, Delay_Req, Delay_Resp, Pdelay_Req, Pdelay_Resp SYNC, Pdelay_Req, Pdelay_Resp R A FT D R A FT D A FT D R A 22.6.17 DMA Bus mode register The Bus Mode register establishes the bus operating modes for the DMA. Table 421. DMA Bus mode register (DMA_BUS_MODE, address 0x4001 1000) bit description Bit Symbol Description Reset Access value 0 SWR Software reset When this bit is set, the MAC DMA Controller resets all MAC Subsystem internal registers and logic. It is cleared automatically after the reset operation has completed in all of the core clock domains. Read a 0 value in this bit before re-programming any register of the core. Remark: The reset operation is completed only when all the resets in all the active clock domains are de-asserted. Hence it is essential that all the PHY inputs clocks (applicable for the selected PHY interface) are present for software reset completion. 0 R/WS/ SC 1 DA DMA arbitration scheme 0 = Round-robin with Rx:Tx priority given in bits [15:14] 1 = Rx has priority over Tx 0 R/W 6:2 DSL Descriptor skip length This bit specifies the number of Word/Dword/Lword (depending on 32/64/128-bit bus) to skip between two unchained descriptors. The address skipping starts from the end of current descriptor to the start of next descriptor. When DSL value equals zero, then the descriptor table is taken as contiguous by the DMA, in Ring mode. 0 R/W 7 ATDS Alternate (Enhanced) descriptor size When set, the alternate (enhanced) descriptor (see Section 22.9) size is increased to 32 bytes (8 DWORDS). This is required when the Advanced Time-Stamp feature or Full IPC Offload Engine is enabled in the receiver. When reset, the descriptor size reverts back to 4 DWORDs (16 bytes). This bit is present only when Alternate Descriptor feature is selected and either Advanced Time Stamp or IPC Full Checksum Offload (type 2) feature is selected during configuration. Otherwise, this bit is reserved and read-only. 0 R/W All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 496 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R Table 421. DMA Bus mode register (DMA_BUS_MODE, address 0x4001 1000) bit description …continued Bit Symbol Description D R A R A FT D R FT D A R Reset Access value R A FT D R R A F D R A A FT A 13:8 PBL Programmable burst length These bits indicate the maximum number of beats to be transferred in one DMA transaction. This will be the maximum value that is used in a single block Read/Write. The DMA will always attempt to burst as specified in PBL each time it starts a Burst transfer on the host bus. PBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. Any other value will result in undefined behavior. When USP is set high, this PBL value is applicable for TxDMA transactions only. The PBL values have the following limitations. The maximum number of beats (PBL) possible is limited by the size of the Tx FIFO and Rx FIFO in the MTL layer and the data bus width on the DMA. The FIFO has a constraint that the maximum beat supported is half the depth of the FIFO, except when specified (as given below). For different data bus widths and FIFO sizes, the valid PBL range (including x8 mode) is provided in the following table. If the PBL is common for both transmit and receive DMA, the minimum Rx FIFO and Tx FIFO depths must be considered. Do not program out-of-range PBL values, because the system may not behave properly. 1 R/W FT D R A FT D R A FT D 15:14 PR Rx-to-Tx priority ratio RxDMA requests given priority over TxDMA requests in the following ratio. This is valid only when the DA bit is reset. 00 = 1-to-1 01 = 2-to-1 10 = 3-to-1 11 = 4-to-1 00 R/W 16 FB Fixed burst This bit controls whether the AHB Master interface performs fixed burst transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations. 0 R/W 22:17 RPBL RxDMA PBL These bits indicate the maximum number of beats to be transferred in one RxDMA transaction. This will be the maximum value that is used in a single block Read/Write. The RxDMA will always attempt to burst as specified in RPBL each time it starts a Burst transfer on the host bus. RPBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. Any other value will result in undefined behavior. These bits are valid and applicable only when USP is set high. 1 R/W 23 USP Use separate PBL When set high, it configures the RxDMA to use the value configured in bits [22:17] as PBL while the PBL value in bits [13:8] is applicable to TxDMA operations only. When reset to low, the PBL value in bits [13:8] is applicable for both DMA engines. 0 R/W 24 PBL8X 8 x PBL mode When set high, this bit multiplies the PBL value programmed (bits [22:17] and bits [13:8]) eight times. Thus the DMA will transfer data in to a maximum of 8, 16, 32, 64, 128, and 256 beats depending on the PBL value. Remark: This bit function is not backward compatible. Before version 3.50a, this bit was 4xPBL. 0 R/W All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 497 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R Table 421. DMA Bus mode register (DMA_BUS_MODE, address 0x4001 1000) bit description …continued Bit Symbol Description D R A R A FT D R FT D A R Reset Access value R A FT D R R A F D R A A FT A 25 AAL Address-aligned beats When this bit is set high and the FB bit equals 1, the AHB interface generates all bursts aligned to the start address LS bits. If the FB bit equals 0, the first burst (accessing the data buffer’s start address) is not aligned, but subsequent bursts are aligned to the address. 0 R/W FT D R A FT D R A FT D 26 MB Mixed burst When this bit is set high and FB bit is low, the AHB master interface will start all bursts of length more than 16 with INCR (undefined burst) whereas it will revert to fixed burst transfers (INCRx and SINGLE) for burst-length of 16 and below. 0 R/W 27 29:28 31:30 TXPR - When set, this bit indicates that the transmit DMA has higher priority than the 0 receive DMA during arbitration for the system-side bus. 0 Reserved Table 422. Programmable burst length settings Data bus width FIFO depth R/W RO RO 0 Valid PBL range in full duplex mode 32 bit 128 bytes 256 bytes 512 bytes 1 kB 2 kB and above 8 or less 32 or less 64 or less 128 or less all 22.6.18 DMA Transmit poll demand register The Transmit Poll Demand register enables the Transmit DMA to check whether or not the current descriptor is owned by DMA. The Transmit Poll Demand command is given to wake up the TxDMA if it is in Suspend mode. The TxDMA can go into Suspend mode due to an Underflow error in a transmitted frame or due to the unavailability of descriptors owned by Transmit DMA. You can give this command anytime and the TxDMA will reset this command once it starts re-fetching the current descriptor from host memory. Table 423. DMA Transmit poll demand register (DMA_TRANS_POLL_DEMAND, address 0x4001 1004) bit description Bit Symbol Description Reset Access value 31:0 TPD Transmit poll demand When these bits are written with any value, the DMA reads the current descriptor pointed to by the Current Host Transmit Descriptor register (Section 22.6.27). If that descriptor is not available (owned by Host), transmission returns to the Suspend state and bit 2 in the DMA_STAT Register is asserted. If the descriptor is available, transmission resumes. 0 RO/WT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 498 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R A D R A R A FT D R FT 22.6.19 DMA Receive poll demand register D R The Receive Poll Demand register enables the receive DMA to check for new descriptors. This command is given to wake up the RxDMA from SUSPEND state. The RxDMA can go into SUSPEND state only due to the unavailability of descriptors owned by it. Table 424. DMA Receive poll demand register (DMA_REC_POLL_DEMAND, address 0x4001 1008) bit description Bit Symbol Description Reset Access value R A FT D R 0 R A F D R A FT D FT D R A A FT R A RO/WT A FT D 31:0 RPD Receive poll demand When these bits are written with any value, the DMA reads the current descriptor pointed to by the Current Host Receive Descriptor register (Section 22.6.28). If that descriptor is not available (owned by Host), reception returns to the Suspended state and bit 7 in the DMA_STAT Register is not asserted. If the descriptor is available, the Receive DMA returns to active state. 22.6.20 DMA Receive descriptor list address register The Receive Descriptor List Address register points to the start of the Receive Descriptor List. The descriptor lists reside in the host’s physical memory space and must be Word/Dword/Lword-aligned (for 32/64/128- bit data bus). The DMA internally converts it to bus width aligned address by making the corresponding LS bits low. Writing to this register is permitted only when reception is stopped. When stopped, this register must be written to before the receive Start command is given. Table 425. DMA Receive descriptor list address register (DMA_REC_DES_ADDR, address 0x4001 100C) bit description Bit Symbol Description Reset Access value 31:0 SRL Start of receive list This field contains the base address of the First Descriptor in the Receive Descriptor list. The LSB bits [1/2/3:0] for 32/64/128-bit bus width) will be ignored and taken as all-zero by the DMA internally. Hence these LSB bits are Read Only. 0 R/W 22.6.21 DMA Transmit descriptor list address register The Transmit Descriptor List Address register points to the start of the Transmit Descriptor List. The descriptor lists reside in the host’s physical memory space and must be Word/DWORD/LWORD-aligned (for 32/64/128-bit data bus). The DMA internally converts it to bus width aligned address by making the corresponding LSB to low. Writing to this register is permitted only when transmission has stopped. When stopped, this register can be written before the transmission Start command is given. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 499 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R R A Table 426. DMA Transmit descriptor list address register (DMA_TRANS_DES_ADDR, address 0x4001 1010) bit description D R A R A FT D R FT D R A R A FT D A F FT D Bit Symbol Description Reset Access value R R A A FT D FT 31:0 SRL Start of transmit list This field contains the base address of the First Descriptor in the Transmit Descriptor list. The LSB bits [1/2/3:0] for 32/64/128-bit bus width) will be ignored and taken as all-zero by the DMA internally. Hence these LSB bits are Read Only. 0 R/W D R A FT D R A 22.6.22 DMA Status register The Status register contains all the status bits that the DMA reports to the host. This register is usually read by the Software driver during an interrupt service routine or polling. Most of the fields in this register cause the host to be interrupted. The bits in this register are not cleared when read. Writing 1 to (unreserved) bits in this register (bits [16:0]) clears them and writing 0 has no effect. Each field (bits[16:0]) can be masked by masking the appropriate bit in the DMA_INT_EN register. Table 427. DMA Status register (DMA_STAT, address 0x4001 1014) bit description Bit Symbol Description Reset Access value 0 TI Transmit interrupt This bit indicates that frame transmission is finished and TDES1[31] is set in the First Descriptor. 0 R/SS/ WC R/SS/ WC R/SS/ WC 1 2 TPS TU Transmit process stopped This bit is set when the transmission is stopped. Transmit buffer unavailable This bit indicates that the Next Descriptor in the Transmit List is owned by the host and cannot be acquired by the DMA. Transmission is suspended. Bits[22:20] explain the Transmit Process state transitions. To resume processing transmit descriptors, the host should change the ownership of the bit of the descriptor and then issue a Transmit Poll Demand command. 0 0 3 TJT Transmit jabber timeout This bit indicates that the Transmit Jabber Timer expired, meaning that the transmitter had been excessively active. The transmission process is aborted and placed in the Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to assert. 0 R/SS/ WC 4 OVF Receive overflow This bit indicates that the Receive Buffer had an Overflow during frame reception. If the partial frame is transferred to application, the overflow status is set in RDES0[11]. 0 R/SS/ WC R/SS/ WC R/SS/ WC 5 UNF Transmit underflow This bit indicates that the Transmit Buffer had an Underflow during frame transmission. Transmission is suspended and an Underflow Error TDES0[1] is set. 0 6 RI Receive interrupt This bit indicates the completion of frame reception. Specific frame status information has been posted in the descriptor. Reception remains in the Running state. 0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 500 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R Table 427. DMA Status register (DMA_STAT, address 0x4001 1014) bit description …continued Bit Symbol Description D R A R A FT D R FT D A R Reset Access value R A FT D R R A F D R A A FT A 7 RU Receive buffer unavailable This bit indicates that the Next Descriptor in the Receive List is owned by the host and cannot be acquired by the DMA. Receive Process is suspended. To resume processing Receive descriptors, the host should change the ownership of the descriptor and issue a Receive Poll Demand command. If no Receive Poll Demand is issued, Receive Process resumes when the next recognized incoming frame is received. This bit is set only when the previous Receive Descriptor was owned by the DMA. 0 R/SS/ WC FT D R A FT D R A FT D 8 9 RPS RWT Received process stopped This bit is asserted when the Receive Process enters the Stopped state. Receive watchdog timeout This bit is asserted when a frame with a length greater than 2,048 bytes is received (10,240 when Jumbo Frame mode is enabled). 0 0 R/SS/ WC R/SS/ WC R/SS/ WC RO R/SS/ WC R/SS/ WC 10 ETI Early transmit interrupt This bit indicates that the frame to be transmitted was fully transferred to the MTL Transmit FIFO. 0 12:11 13 FBI Reserved Fatal bus error interrupt This bit indicates that a bus error occurred, as detailed in bits [25:23]. When this bit is set, the corresponding DMA engine disables all its bus accesses. 0 0 14 ERI Early receive interrupt This bit indicates that the DMA had filled the first data buffer of the packet. Receive Interrupt bit 6 in this register automatically clears this bit. 0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 501 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R Table 427. DMA Status register (DMA_STAT, address 0x4001 1014) bit description …continued Bit Symbol Description D R A R A FT D R FT D A R Reset Access value R A FT D R R A F D R A A FT A 15 AIE Abnormal interrupt summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_INT_EN register: DMA_STAT register, bit 1: Transmit process stopped DMA_STAT register, bit 3: Transmit jabber timeout DMA_STAT register, bit 4: Receive overflow DMA_STAT register, bit 5: Transmit underflow DMA_STAT register, bit 7: Receiver buffer unavailable DMA_STAT register, bit 8: Receive process stopped DMA_STAT register, bit 9: Receive watchdog timeout DMA_STAT register, bit 10: Early transmit interrupt DMA_STAT register, bit 13: Fatal bus error Only unmasked bits affect the Abnormal Interrupt Summary bit. This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared. 0 R/SS/ WC FT D R A FT D R A FT D 16 NIS Normal interrupt summary Normal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_INT_EN register: DMA_STAT register, bit 0: Transmit interrupt DMA_STAT register, bit 2: Transmit buffer unavailable DMA_STAT register, bit 6: Receive interrupt DMA_STAT register, bit 14: Early receive interrupt Only unmasked bits affect the Normal Interrupt Summary bit. This is a sticky bit and must be cleared (by writing a 1 to this bit) each time a corresponding bit that causes NIS to be set is cleared. 0 R/SS/ WC 31:17 - Reserved 0 RO 22.6.23 DMA Operation mode register The Operation Mode register establishes the Transmit and Receive operating modes and commands. This register should be the last CSR to be written as part of DMA initialization. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 502 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D Table 428. DMA operation mode register (DMA_OP_MODE, address 0x4001 1018) bit description Bit Symbol Description D R A R A FT D R R R A FT D R A R A FT Reset Access value A FT D R A F R A D 0 1 SR Reserved Start/stop receive When this bit is set, the Receive process is placed in the Running state. The DMA attempts to acquire the descriptor from the Receive list and processes incoming frames. Descriptor acquisition is attempted from the current position in the list, which is the address set by the DMA_REC_DES_ADDR register or the position retained when the Receive process was previously stopped. If no descriptor is owned by the DMA, reception is suspended and Receive Buffer Unavailable bit (bit 7 in DMA_STAT register) is set. The Start Receive command is effective only when reception has stopped. If the command was issued before setting the DMA_REC_DES_ADDR, DMA behavior is unpredictable. 0 0 RO FT D R/W FT D R A FT D R A 2 OSF Operate on second frame When this bit is set, this bit instructs the DMA to process a second frame of Transmit data even before status for first frame is obtained. 0 R/W 4:3 RTC Receive threshold control These two bits control the threshold level of the MTL Receive FIFO. Transfer (request) to DMA starts when the frame size within the MTL Receive FIFO is larger than the threshold. In addition, full frames with a length less than the threshold are transferred automatically. Note that value of 11 is not applicable if the configured Receive FIFO size is 128 bytes. These bits are valid only when the RSF bit is zero, and are ignored when the RSF bit is set to 1. 00 = 64 01 = 32 10 = 96 11 = 128 0 R/W 5 6 FUF Reserved Forward undersized good frames When set, the Rx FIFO will forward Undersized frames (frames with no Error and length less than 64 bytes) including pad-bytes and CRC). When reset, the Rx FIFO will drop all frames of less than 64 bytes, unless it is already transferred due to lower value of Receive Threshold (e.g., RTC = 01). 0 0 RO R/W 7 FEF Forward error frames When this bit is reset, the Rx FIFO drops frames with error status (CRC error, collision error, GMII_ER, giant frame, watchdog timeout, overflow). However, if the frame’s start byte (write) pointer is already transferred to the read controller side (in Threshold mode), then the frames are not dropped. . When FEF is set, all frames except runt error frames are forwarded to the DMA. But when RxFIFO overflows when a partial frame is written, then such frames are dropped even when FEF is set. 0 R/W 12:8 - Reserved 0 RO All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 503 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R R A Table 428. DMA operation mode register (DMA_OP_MODE, address 0x4001 1018) bit description …continued D R A R A FT D R FT D R A R A A Bit Symbol Description Reset Access value FT D R A F FT D R A 13 ST Start/Stop Transmission Command When this bit is set, transmission is placed in the Running state, and the DMA checks the Transmit List at the current position for a frame to be transmitted. Descriptor acquisition is attempted either from the current position in the list, which is the Transmit List Base Address set by the DMA_TRANS_DES_ADDR register or from the position retained when transmission was stopped previously. If the current descriptor is not owned by the DMA, transmission enters the Suspended state and Transmit Buffer Unavailable (DMA_STAT register, bit 2) is set. The Start Transmission command is effective only when transmission is stopped. If the command is issued before setting the DMA_TRANS_DES_ADDR register, then the DMA behavior is unpredictable. When this bit is reset, the transmission process is placed in the Stopped state after completing the transmission of the current frame. The Next Descriptor position in the Transmit List is saved, and becomes the current position when transmission is restarted. The stop transmission command is effective only the transmission of the current frame is complete or when the transmission is in the Suspended state. 0 R/W FT D R A FT D R A FT D 16:14 TTC Transmit threshold control These three bits control the threshold level of the MTL Transmit FIFO. Transmission starts when the frame size within the MTL Transmit FIFO is larger than the threshold. In addition, full frames with a length less than the threshold are also transmitted. These bits are used only when the TSF bit (Bit 21) is reset. 000 = 64 001 = 128 010 = 192 011 = 256 100 = 40 101 = 32 110 = 24 111 = 16 0 R/W 19:17 20 FTF Reserved Flush transmit FIFO When this bit is set, the transmit FIFO controller logic is reset to its default values and thus all data in the Tx FIFO is lost/flushed. This bit is cleared internally when the flushing operation is completed fully. The Operation Mode register should not be written to until this bit is cleared. The data which is already accepted by the MAC transmitter will not be flushed. It will be scheduled for transmission and will result in underflow and runt frame transmission. Remark: The flush operation completes only after emptying the TxFIFO of its contents and all the pending Transmit Status of the transmitted frames are accepted by the host. In order to complete this flush operation, the PHY transmit clock is required to be active. 0 0 RO R/WS/ SC 21 TSF Transmit store and forward When this bit is set, transmission starts when a full frame resides in the MTL Transmit FIFO. When this bit is set, the TTC values specified in this register (bits [16:14]) are ignored. This bit should be changed only when transmission is stopped. 0 R/W 23:22 - Reserved 0 RO All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 504 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R R A Table 428. DMA operation mode register (DMA_OP_MODE, address 0x4001 1018) bit description …continued D R A R A FT D R FT D R A R A A Bit Symbol Description Reset Access value FT D R A F FT D R A 24 DFF Disable flushing of received frames When this bit is set, the RxDMA does not flush any frames due to the unavailability of receive descriptors/buffers as it does normally when this bit is reset. (See ). 0 R/W FT D R A FT D R A FT D 25 RSF Receive store and forward When this bit is set, the MTL only reads a frame from the Rx FIFO after the complete frame has been written to it, ignoring RTC bits. When this bit is reset, the Rx FIFO operates in Cut-Through mode, subject to the threshold specified by the RTC bits. 0 R/W 26 DT Disable Dropping of TCP/IP Checksum Error Frames When this bit is set, the core does not drop frames that only have errors detected by the Receive Checksum Offload engine. Such frames do not have any errors (including FCS error) in the Ethernet frame received by the MAC but have errors in the encapsulated payload only. When this bit is reset, all error frames are dropped if the FEF bit is reset. 0 R/W 31:27 - Reserved 0 RO 22.6.24 DMA Interrupt enable register The Interrupt Enable register enables the interrupts reported by the DMA_STAT register. Setting a bit to 1 enables a corresponding interrupt. After a hardware or software reset, all interrupts are disabled. Table 429. DMA Interrupt enable register (DMA_INT_EN, address 0x4001 101C) bit description Bit Symbol Description Reset Access value 0 TIE Transmit interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Transmit Interrupt is enabled. When this bit is reset, Transmit Interrupt is disabled. 0 R/W 1 TSE Transmit stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Transmission Stopped Interrupt is enabled. When this bit is reset, Transmission Stopped Interrupt is disabled. 0 R/W 2 TUE Transmit buffer unavailable enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Transmit Buffer Unavailable Interrupt is enabled. When this bit is reset, Transmit Buffer Unavailable Interrupt is disabled. 0 R/W 3 TJE Transmit jabber timeout enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Transmit Jabber Timeout Interrupt is enabled. When this bit is reset, Transmit Jabber Timeout Interrupt is disabled. 0 R/W 4 OVE Overflow interrupt enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Receive Overflow Interrupt is enabled. When this bit is reset, Overflow Interrupt is disabled. 0 R/W 5 UNE Underflow interrupt enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Transmit Underflow Interrupt is enabled. When this bit is reset, Underflow Interrupt is disabled. 0 R/W All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 505 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R R A Table 429. DMA Interrupt enable register (DMA_INT_EN, address 0x4001 101C) bit description …continued D R A R A FT D R FT D R A R A A Bit Symbol Description Reset Access value FT D R A F FT D R A 6 RIE Receive interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Receive Interrupt is enabled. When this bit is reset, Receive Interrupt is disabled. 0 R/W FT D R A FT D FT D 7 RUE Receive buffer unavailable enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Receive Buffer Unavailable Interrupt is enabled. When this bit is reset, the Receive Buffer Unavailable Interrupt is disabled. 0 R/W R A 8 RSE Received stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Receive Stopped Interrupt is enabled. When this bit is reset, Receive Stopped Interrupt is disabled. 0 R/W 9 RWE Receive watchdog timeout enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), the Receive Watchdog Timeout Interrupt is enabled. When this bit is reset, Receive Watchdog Timeout Interrupt is disabled. 0 R/W 10 ETE Early transmit interrupt enable When this bit is set with an Abnormal Interrupt Summary Enable (bit 15 in this register), Early Transmit Interrupt is enabled. When this bit is reset, Early Transmit Interrupt is disabled. 0 R/W 12:11 13 FBE Reserved Fatal bus error enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), the Fatal Bus Error Interrupt is enabled. When this bit is reset, Fatal Bus Error Enable Interrupt is disabled. 0 0 RO R/W 14 ERE Early receive interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Early Receive Interrupt is enabled. When this bit is reset, Early Receive Interrupt is disabled. 0 R/W All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 506 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R R A Table 429. DMA Interrupt enable register (DMA_INT_EN, address 0x4001 101C) bit description …continued D R A R A FT D R FT D R A R A A Bit Symbol Description Reset Access value FT D R A F FT D R A 15 AIE Abnormal interrupt summary enable When this bit is set, an Abnormal Interrupt is enabled. When this bit is reset, an Abnormal Interrupt is disabled. This bit enables the following bits DMA_STAT register, bit 1: Transmit process stopped DMA_STAT register, bit 3: Transmit jabber timeout DMA_STAT register, bit 4: Receive overflow DMA_STAT register, bit 5: Transmit underflow DMA_STAT register, bit 7: Receiver buffer unavailable DMA_STAT register, bit 8: Receive process stopped DMA_STAT register, bit 9: Receive watchdog timeout DMA_STAT register, bit 10: Early transmit interrupt DMA_STAT register, bit 13: Fatal bus error 0 R/W FT D R A FT D R A FT D 16 NIE Normal interrupt summary enable When this bit is set, a normal interrupt is enabled. When this bit is reset, a normal interrupt is disabled. This bit enables the following bits: DMA_STAT register, bit 0: Transmit interrupt DMA_STAT register, bit 2: Transmit buffer unavailable DMA_STAT register, bit 6: Receive interrupt DMA_STAT register, bit 14: Early receive interrupt 0 R/W 31:17 - Reserved 0 RO The interrupt (sbd_intr_o_interrupt) is generated as shown in Figure 44. It is asserted when the NIS/AIS Status bit is asserted and the corresponding Interrupt Enable bits (NIE/AIE) are enabled. TI AND TIE ERI OR AND NIS AN D NIE ERE OR sbd _intr_o TPS AND TSE FBI OR AIS AN D AIE AND FBE Fig 44. Interrupt generation All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 507 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R A 22.6.25 DMA Missed frame and buffer overflow counter register The DMA maintains two counters to track the number of missed frames during reception. This register reports the current value of the counter. The counter is used for diagnostic purposes. Bits[15:0] indicate missed frames due to the host buffer being unavailable. Bits[27:17] indicate missed frames due to buffer overflow conditions (MTL and MAC) and runt frames (good frames of less than 64 bytes) dropped by the MTL. Table 430. DMA Missed frame and buffer overflow counter register (DMA_MFRM_BUFOF, address 0x4001 1020) bit description Bit Symbol Description Reset Access value D R A R A FT D R FT D R R A FT D R R A F D R A FT D FT D R A A FT R A A FT D 15:0 FMC Number of frames missed Indicates the number of frames missed by the controller due to the Host Receive Buffer being unavailable. This counter is incremented each time the DMA discards an incoming frame. The counter is cleared when this register is read with . 0 R/SS/RC 16 27:17 OC FMA Overflow bit for missed frame counter Number of frames missed by the application Indicates the number of frames missed by the application. This counter is incremented each time the MTL asserts the sideband signal mtl_rxoverflow_o. The counter is cleared when this register is read with . 0 0 R/SS/RC R/SS/RC 28 31:29 OF - Overflow bit for FIFO overflow counter Reserved 0 0 R/SS/RC RO 22.6.26 DMA Receive interrupt watchdog timer register This register, when written with non-zero value, will enable the watchdog timer for RI (bit 6 in the DMA_STAT register). Table 431. DMA Receive interrupt watchdog timer register (DMA_REC_INT_WDT, address 0x4001 1024) bit description Bit Symbol Description Reset Access value 7:0 RIWT RI watchdog timeout Indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set. The watchdog timer gets triggered with the programmed value after the RxDMA completes the transfer of a frame for which the RI status bit is not set due to the setting in the corresponding descriptor RDES1[31]. When the watch-dog timer runs out, the RI bit is set and the timer is stopped. The watchdog timer is reset when RI bit is set high due to automatic setting of RI as per RDES1[31] of any received frame. 0 R/W 31:8 - Reserved 0 RO 22.6.27 DMA Current host transmit descriptor register The Current Host Transmit Descriptor register points to the start address of the current Transmit Descriptor read by the DMA. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 508 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R R A Table 432. DMA Current host transmit descriptor register (DMA_CURHOST_TRANS_DES, address 0x4001 1048) bit description D R A R A FT D R FT D R A R A A FT D F FT D Bit Symbol Description Reset Access value R R A A FT D FT 31:0 HTD Host Transmit Descriptor Address Pointer Cleared on Reset. Pointer updated by DMA during operation. 0 RO D R A FT D R A 22.6.28 DMA Current host receive descriptor register The Current Host Receive Descriptor register points to the start address of the current Receive Descriptor read by the DMA. Table 433. DMA Current host receive descriptor register (DMA_CURHOST_REC_DES, address 0x4001 104C) bit description Bit Symbol Description Reset Access value 31:0 HRD Host Receive Descriptor Address Pointer Cleared on Reset. Pointer updated by DMA during operation. 0 RO 22.6.29 DMA Current host transmit buffer address register The Current Host Transmit Buffer Address register points to the current Transmit Buffer Address being read by the DMA. Table 434. DMA Current host transmit buffer address register (DMA_CURHOST_TRANS_BUF, address 0x4001 1050) bit description Bit Symbol Description Reset Access value 31:0 HTB Host Transmit Buffer Address Pointer Cleared on Reset. Pointer updated by DMA during operation. 0 RO 22.6.30 DMA Current host receive buffer address register The Current Host Receive Buffer Address register points to the current Receive Buffer address being read by the DMA. Table 435. DMA Current host receive buffer address register (DMA_CURHOST_REC_BUF, address 0x4001 1054) bit description Bit Symbol Description Reset Access value 31:0 HRB Host Receive Buffer Address Pointer Cleared on Reset. Pointer updated by DMA during operation. 0 RO 22.7 Functional description All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 509 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R A D R A R A FT D R FT 22.7.1 Power management block D R This section describes the power management (PMT) mechanisms supported by the MAC. PMT supports the reception of network (remote) wake-up frames and Magic Packet frames. PMT does not perform the clock gate function, but generates interrupts for wake-up frames and Magic Packets received by the MAC. The PMT block sits on the receiver path of the MAC and is enabled with remote wake-up frame enable and Magic Packet enable. These enables are in the PMT Control and Status register and are programmed by the Application. When the power-down mode is enabled in the PMT, then all received frames are dropped by the core and they are not forwarded to the application. The core comes out of the power down mode only when either a Magic Packet or a Remote Wake-up frame is received and the corresponding detection is enabled. D R A FT D R A FT R A F D R A FT D FT D R A R A A FT 22.7.1.1 Remote wake-up frame registers The register wkupfmfilter_reg, address (0x028), loads the Wake-up Frame Filter register. To load values in a Wake-up Frame Filter register, the entire register (WKUPFMFILTER_REG) must be written. The WKUPFMFILTER_REG register is loaded by sequentially loading the eight register values in address (0x028) for WKUPFMFILTER_REG0, WKUPFMFILTER_REG1,... WKUPFMFILTER_REG7, respectively. WKUPFMFILTER_REG is read in the same way. Remark: The internal counter to access the appropriate WKUPFMFILTER_REG is incremented when lane 3 (or lane 0 in big-endian) is accessed by the CPU. This should be kept in mind if you are accessing these registers in byte or half-word mode. WKUPFMFILTER0 WKUPFMFILTER1 Filter 0 Byte Mask Filter 1 Byte Mask Filter 2 Byte Mask Filter 3 Byte Mask RSVD WKUPFMFILTER2 WKUPFMFILTER3 WKUPFMFILTER4 Filter 3 Command RSVD Filter 2 Command RSVD Filter 1 Command RSVD Filter 0 Command WKUPFMFILTER5 WKUPFMFILTER6 Filter 3 Offset Filter 2 Offset Filter 1 Offset Filter 0 Offset Filter 1 CRC - 16 Filter 3 CRC - 16 Filter 0 CRC - 16 Filter 2 CRC - 16 WKUPFMFILTER7 Fig 45. Wake-up frame filter register Filter i byte mask All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 510 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R R A This register defines which bytes of the frame are examined by filter i (0, 1, 2, and 3) in order to determine whether or not the frame is a wake-up frame. The MSB (thirty-first bit) must be zero. Bit j [30:0] is the Byte Mask. If bit j (byte number) of the Byte Mask is set, then Filter i Offset + j of the incoming frame is processed by the CRC block; otherwise Filter i Offset + j is ignored. R A A FT D R A FT D D R A R A FT D R FT D R A F R A FT D FT D FT R A Filter i command This 4-bit command controls the filter i operation. Bit 3 specifies the address type, defining the pattern’s destination address type. When the bit is set, the pattern applies to only multicast frames; when the bit is reset, the pattern applies only to unicast frame. Bit 2 and Bit 1 are reserved. Bit 0 is the enable for filter i; if Bit 0 is not set, filter i is disabled. Filter i offset This register defines the offset (within the frame) from which filter i examines the frames. This 8-bit pattern offset is the offset for the filter i first byte to be examined. The minimum allowed is 12, which refers to the 13th byte of the frame. The offset value 0 refers to the first byte of the frame. Filter i CRC-16 This register contains the CRC_16 value calculated from the pattern, as well as the byte mask programmed to the wake-up filter register block. D R A 22.7.1.2 Remote wake-up detection When the MAC is in sleep mode and the remote wake-up bit is enabled in PMT Control and Status register (0x002C), normal operation is resumed after receiving a remote wake-up frame. The Application writes all eight wake-up filter registers by performing a sequential Write to address (0x0028). The Application enables remote wake-up by writing a 1 to Bit 2 of the PMT Control and Status register. PMT supports four programmable filters that allow support of different receive frame patterns. If the incoming frame passes the address filtering of Filter Command, and if Filter CRC-16 matches the incoming examined pattern, then the wake-up frame is received. Filter_offset (minimum value 12, which refers to the 13th byte of the frame) determines the offset from which the frame is to be examined. Filter Byte Mask determines which bytes of the frame must be examined. The thirty-first bit of Byte Mask must be set to zero. The remote wake-up CRC block determines the CRC value that is compared with Filter CRC-16. The wake-up frame is checked only for length error, FCS error, dribble bit error, MII error, collision, and to ensure that it is not a runt frame. Even if the wake-up frame is more than 512 bytes long, if the frame has a valid CRC value, it is considered valid. Wake-up frame detection is updated in the PMT Control and Status register for every remote Wake-up frame received. A PMT interrupt to the Application triggers a Read to the PMT Control and Status register to determine reception of a wake-up frame. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 511 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R A D R A R A FT D R FT 22.7.1.3 Magic packet detection D R The Magic Packet frame is based on a method that uses Advanced Micro Device’s Magic Packet technology to power up the sleeping device on the network. The MAC receives a specific packet of information, called a Magic Packet, addressed to the node on the network. Only Magic Packets that are addressed to the device or a broadcast address will be checked to determine whether they meet the wake-up requirements. Magic Packets that pass the address filtering (unicast or broadcast) will be checked to determine whether they meet the remote Wake-on-LAN data format of 6 bytes of all ones followed by a MAC Address appearing 16 times. FT D R A FT D The application enables Magic Packet wake-up by writing a 1 to Bit 1 of the PMT Control and Status register. The PMT block constantly monitors each frame addressed to the node for a specific Magic Packet pattern. Each frame received is checked for a 0xFFFF FFFF FFFF pattern following the destination and source address field. The PMT block then checks the frame for 16 repetitions of the MAC address without any breaks or interruptions. In case of a break in the 16 repetitions of the address, the 0xFFFF FFFF FFFF pattern is scanned for again in the incoming frame. The 16 repetitions can be anywhere in the frame, but must be preceded by the synchronization stream (0xFFFF FFFF FFFF). The device will also accept a multicast frame, as long as the 16 duplications of the MAC address are detected. If the MAC address of a node is 0x0011 2233 4455, then the MAC scans for the data sequence: 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 ...CRC Magic Packet detection is updated in the PMT Control and Status register for Magic Packet received. A PMT interrupt to the Application triggers a read to the PMT CSR to determine whether a Magic Packet frame has been received. R A R A F D R A FT D FT D R A R A A FT 22.7.1.4 System considerations during power-down MAC neither gates nor stops clocks when Power-down mode is enabled. Power saving by clock gating must be done outside the core by the application. The receive data path must be clocked with ENET_RX_CLK during Power-down mode because it is involved in magic packet/wake-on-LAN frame detection. However, the transmit path and the application path clocks can be gated off during Power-down mode. The PMT interrupt is asserted when a valid wake-up frame is received. This signal is generated in the receive clock domain The recommended power-down and wake-up sequence is as follows. 1. Disable the Transmit DMA and wait for any previous frame transmissions to complete. These transmissions can be detected when Transmit Interrupt (see DMA_STAT register bit NIS; Table 427) is received. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 512 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R R A 2. Disable the MAC transmitter and MAC receiver by clearing the appropriate bits in the MAC Configuration register. R A A FT D R A FT 3. Wait until the Receive DMA empties all the frames from the Rx FIFO (a software timer may be required). D 4. Enable Power-Down mode by appropriately configuring the PMT registers. 5. Enable the MAC Receiver and enter Power-Down mode. 6. Gate the application and transmit clock inputs to the core (and other relevant clocks in the system) to reduce power and enter Sleep mode. 7. On receiving a valid wake-up frame, the MAC PMT interrupt signal and exits Power-Down mode. 8. On receiving the interrupt, the system must enable the application and transmit clock inputs to the core. 9. Read the PMT Status register to clear the interrupt, then enable the other modules in the system and resume normal operation. Remark: D R A R A FT D R FT D R A F R A FT D FT D R A D FT R A 22.7.2 DMA arbiter functions If you have enabled the transmit (Tx) DMA and receive (Rx) DMA of a channel, you can specify which DMA gets the bus when the channel gets the control of the bus. You can set the priority between the corresponding Tx DMA and Rx DMA by using the bit 27 (TXPR: Transmit Priority) of the DMA Bus Mode Register). For round-robin arbitration, you can use the bits [15:14] (PR: Priority Ratio) of the Bus Mode Register to specify the weighted priority between the Tx DMA and Rx DMA. Table 436 provides information about the priority scheme between Tx DMA and Rx DMA. Table 436. Priority scheme for transmit and receive DMA Bit 27 Bit 15 Bit 14 Bit 1 Priority scheme 0 0 0 0 0 1 1 1 1 1 x 0 0 1 1 x 0 0 1 1 x 0 1 0 1 x 0 1 0 1 x 0 0 0 0 1 0 0 0 0 Rx always has priority over Tx Tx and Rx have equal priority. Rx gets the access first on simultaneous requests. Rx has priority over Tx in the ratio 2:1. Rx has priority over Tx in the ratio 3:1. Rx has priority over Tx in the ratio 4:1. Tx always has priority over Rx. Tx and Rx have equal priority. Tx gets the access first on simultaneous requests. Tx has priority over Rx in the ratio 2:1. Tx has priority over Rx in the ratio 3:1. Tx has priority over Rx in the ratio 4:1. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 513 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R A D R A R A FT D R FT 22.7.3 IPC Receive checksum offload engine D R In this mode, both IPv4 and IPv6 frames in the received Ethernet frames are detected and processed for data integrity.You can enable this module by setting the bit 10 (IPC) of the MAC configuration registe (Section 22.6.1). The MAC receiver identifies IPv4 or IPv6 frames by checking for value 0x0800 or 0x86DD, respectively, in the received Ethernet frames. Type field. This identification applies to VLAN-tagged frames as well. D R A FT D The Receive Checksum Offload engine calculates IPv4 header checksums and checks that they match the received IPv4 header checksums. The result of this operation (pass or fail) is given to the RFC module for insertion into the receive status word. The IP Header Error bit is set for any mismatch between the indicated payload type (Ethernet Type field) and the IP header version, or when the received frame does not have enough bytes, as indicated by the IPv4 header.s Length field (or when fewer than 20 bytes are available in an IPv4 or IPv6 header). This engine also identifies a TCP, UDP, or ICMP payload in the received IP datagrams (IPv4 or IPv6) and calculates the checksum of such payloads properly, as defined in the TCP, UDP, or ICMP specifications. This engine includes the TCP/UDP/ICMPv6 pseudo-header bytes for checksum calculation and checks whether the received checksum field matches the calculated value. The result of this operation is given as a Payload Checksum Error bit in the receive status word. This status bit is also set if the length of the TCP, UDP, or ICMP payload does not match the expected payload length given in the IP header. This engine bypasses the payload of fragmented IP datagrams, IP datagrams with security features, IPv6 routing headers, and payloads other than TCP, UDP or ICMP. R A FT R A F D R A FT D FT D R A R A A FT 22.8 DMA controller description The DMA has independent Transmit and Receive engines and a CSR space. The Transmit engine transfers data from system memory to the device port (MTL), while the Receive engine transfers data from the device port to the system memory. The controller use descriptors to efficiently move data from source to destination with minimal Host CPU intervention. The DMA is designed for packet-oriented data transfers such as frames in Ethernet. The controller can be programmed to interrupt the Host CPU for situations such as Frame Transmit and Receive transfer completion, and other normal/error conditions. The DMA and the Host driver communicate through two data structures: • Control and Status registers (CSR). See Section 22.6. • Descriptor lists and data buffers. See Section 22.9. The DMA transfers data frames received by the core to the Receive Buffer in the Host memory, and Transmit data frames from the Transmit Buffer in the Host memory. Descriptors that reside in the Host memory act as pointers to these buffers. There are two descriptor lists; one for reception, and one for transmission. The base address of each list is written into DMA Registers Table 425 and Table 426. A descriptor list is forward linked (either implicitly or explicitly). The last descriptor may point back to the first entry to create a ring structure. Explicit chaining of descriptors is accomplished by setting the second address chained in both Receive and Transmit descriptors (RDES1[24] and TDES1[24]). The descriptor lists resides in the Host physical memory address space. Each descriptor can point to a maximum of two buffers. This enables two buffers to be used, physically All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 514 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R A D R A R A FT D R FT addressed, rather than contiguous buffers in memory. D R A data buffer resides in the Host physical memory space, and consists of an entire frame or part of a frame, but cannot exceed a single frame. Buffers contain only data, buffer status is maintained in the descriptor. Data chaining refers to frames that span multiple data buffers. However, a single descriptor cannot span multiple frames. The DMA skips to the next frame buffer when end-of-frame is detected. Data chaining can be enabled or disabled. D R A FT D R A FT R A F D R A FT D FT D R A R A A FT Ring Structure Chain Structure Buffer 1 Descriptor 0 Buffer 2 Descriptor 0 Buffer 1 Buffer 1 Descriptor 1 Buffer 2 Descriptor 1 Buffer 1 Descriptor 2 Buffer 2 Buffer 1 Buffer 1 Descriptor 2 Buffer 1 Descriptor n Buffer 2 Next Descriptor Fig 46. Descriptor ring and chain structure 22.8.1 Initialization Follow these steps to initialize the ethernet controller: 1. Write to DMA Register Table 421 to set Host bus access parameters. 2. Write to DMA Register Table 429 to mask unnecessary interrupt causes. 3. The software driver creates the Transmit and Receive descriptor lists. Then it writes to both DMA Register Table 425 and DMA Register Table 426, providing the DMA with the starting address of each list. 4. Write to MAC Registers Table 404, Table 406, and Table 405 for desired filtering options. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 515 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R R A 5. Write to MAC Register Table 403 to configure the operating mode and enable the transmit operation (bit 3: Transmitter Enable). The PS and DM bits are set based on the auto-negotiation result (read from the PHY). R A 6. Write to DMA Register Table 428 to set bits 13 and 1 to start transmission and reception. 7. Write to MAC Register Table 403 to enable the Receive operation (bit 2: Receiver Enable). The Transmit and Receive engines enter the Running state and attempt to acquire descriptors from the respective descriptor lists. The Receive and Transmit engines then begin processing Receive and Transmit operations. The Transmit and Receive processes are independent of each other and can be started or stopped separately. D R A R A FT D R FT D R A A FT D R A R A FT F FT D R A FT D FT D D R A 22.8.1.1 Host bus burst access The DMA attempts to execute fixed-length Burst transfers on the AHB Master interface if configured to do so (FB bit of DMA Register 0). The maximum Burst length is indicated and limited by the PBL field (DMA Register 0[13:8]). The Receive and Transmit descriptors are always accessed in the maximum possible (limited by PBL or 16 x 8/bus width) burst-size for the 16-bytes to be read. The Transmit DMA initiates a data transfer only when sufficient space to accommodate the configured burst is available in MTL Transmit FIFO or the number of bytes till the end of frame (when it is less than the configured burst-length). The DMA indicates the start address and the number of transfers required to the AHB Master Interface. When the AHB Interface is configured for fixed-length burst, then it transfers data using the best combination of INCR4/8/16 and SINGLE transactions. Otherwise (no fixed-length burst), it transfers data using INCR (undefined length) and SINGLE transactions. The Receive DMA initiates a data transfer only when sufficient data to accommodate the configured burst is available in MTL Receive FIFO or when the end of frame (when it is less than the configured burst-length) is detected in the Receive FIFO. The DMA indicates the start address and the number of transfers required to the AHB Master Interface. When the AHB Interface is configured for fixed-length burst, then it transfers data using the best combination of INCR4/8/16 and SINGLE transactions. If the end-of frame is reached before the fixed-burst ends on the AHB interface, then dummy transfers are performed in order to complete the fixed-burst. Otherwise (FB bit of DMA Register Table 421 is reset), it transfers data using INCR (undefined length) and SINGLE transactions. When the AHB interface is configured for address-aligned beats, both DMA engines ensure that the first burst transfer the AHB initiates is less than or equal to the size of the configured PBL. Thus, all subsequent beats start at an address that is aligned to the configured PBL. The DMA can only align the address for beats up to size 16 (for PBL > 16), because the AHB interface does not support more than INCR16. 22.8.1.2 Host data buffer alignment The Transmit and Receive data buffers do not have any restrictions on start address alignment. For example, in systems with 32-bit memory, the start address for the buffers can be aligned to any of the four bytes. However, the DMA always initiates transfers with address aligned to the bus width with dummy data for the byte lanes not required. This typically happens during the transfer of the beginning or end of an Ethernet frame. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 516 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R A D R A R A FT D R FT Example: Buffer read D R If the Transmit buffer address is 0x00000FF2 (for 32-bit data bus), and 15 bytes need to be transferred, then the DMA reads five full words from address 0x00000FF0, but when transferring data to the MTL Transmit FIFO, the extra bytes (the first two bytes) are dropped or ignored. Similarly, the last 3 bytes of the last transfer are also ignored. The DMA always ensures it transfers a full 32-bit data to the MTL Transmit FIFO, unless it is the end-of-frame. FT D R A FT R A R A F D R A FT D A FT D R A R A FT D Example: Buffer write If the Receive buffer address is 0x0000FF2 (for 64-bit data bus) and 16 bytes of a received frame need to be transferred, then the DMA writes 3 full words from address 0x00000FF0. But the first 2 bytes of first transfer and the last 6 bytes of the third transfer have dummy data. 22.8.1.3 Buffer size calculations The DMA does not update the size fields in the Transmit and Receive descriptors. The DMA updates only the status fields (RDES and TDES) of the descriptors. The driver has to perform the size calculations. The transmit DMA transfers the exact number of bytes (indicated by buffer size field of TDES1) towards the MAC core. If a descriptor is marked as first (FS bit of TDES1 is set), then the DMA marks the first transfer from the buffer as the start of frame. If a descriptor is marked as last (LS bit of TDES1), then the DMA marks the last transfer from that data buffer as the end-of frame to the MTL. The Receive DMA transfers data to a buffer until the buffer is full or the end-of frame is received from the MTL. If a descriptor is not marked as last (LS bit of RDES0), then the descriptor’s corresponding buffer(s) are full and the amount of valid data in a buffer is accurately indicated by its buffer size field minus the data buffer pointer offset when the FS bit of that descriptor is set. The offset is zero when the data buffer pointer is aligned to the data bus width. If a descriptor is marked as last, then the buffer may not be full (as indicated by the buffer size in RDES1). To compute the amount of valid data in this final buffer, the driver must read the frame length (FL bits of RDES0[29:16]) and subtract the sum of the buffer sizes of the preceding buffers in this frame. The Receive DMA always transfers the start of next frame with a new descriptor. Remark: Even when the start address of a receive buffer is not aligned to the system bus’s data width, the system should allocate a receive buffer of a size aligned to the system bus width. For example, if the system allocates a 1,024-byte (1 KB) receive buffer starting from address 0x1000, the software can program the buffer start address in the Receive descriptor to have a 0x1002 offset. The Receive DMA writes the frame to this buffer with dummy data in the first two locations (0x1000 and 0x1001). The actual frame is written from location 0x1002. Thus, the actual useful space in this buffer is 1,022 bytes, even though the buffer size is programmed as 1,024 bytes, because of the start address offset. 22.8.1.4 DMA arbiter for MAC-DMA and MAC-AHB cores The arbiter inside the DMA module performs the arbitration between the Transmit and Receive channel accesses to the AHB Master interface. Two types of arbitrations are possible: round-robin, and fixed-priority. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 517 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R R A When round-robin arbitration is selected (DA bit of Register Table 421 (Bus Mode Register) is reset), the arbiter allocates the data bus in the ratio set by the PR bits of DMA Register Table 421, when both Transmit and Receive DMAs are requesting for access simultaneously. When the DA bit is set, the Receive DMA always gets priority over the Transmit DMA for data access by default. When the TXPR bit (bit 27 of DMA register Table 421) is also set, then the Transmit DMA gets priority over the Receive DMA as . R A A FT D R A FT D D R A R A FT D R FT D R A F R A FT D FT D R A D FT R A 22.8.2 Transmission 22.8.2.1 TxDMA operation: Default (non-OSF) mode The transmit DMA engine in default mode proceeds as follows: 1. The Host sets up the transmit descriptor (TDES0-TDES3) and sets the Own bit (TDES0[31]) after setting up the corresponding data buffer(s) with Ethernet Frame data. 2. Once the ST bit (DMA Register) is set, the DMA enters the Run state. 3. While in the Run state, the DMA polls the Transmit Descriptor list for frames requiring transmission. After polling starts, it continues in either sequential descriptor ring order or chained order. If the DMA detects a descriptor flagged as owned by the Host, or if an error condition occurs, transmission is suspended and both the Transmit Buffer Unavailable (DMA Register Table 427) and Normal Interrupt Summary (DMA Register Table 427) bits are set. The Transmit Engine proceeds to Step 9. 4. If the acquired descriptor is flagged as owned by DMA (TDES0[31] = 1), the DMA decodes the Transmit Data Buffer address from the acquired descriptor. 5. The DMA fetches the Transmit data from the Host memory and transfers the data to the MTL for transmission. 6. If an Ethernet frame is stored over data buffers in multiple descriptors, the DMA closes the intermediate descriptor and fetches the next descriptor. Steps 3, 4, and 5 are repeated until the end-of-Ethernet-frame data is transferred to the MTL. 7. When frame transmission is complete, if IEEE 1588 time stamping was enabled for the frame (as indicated in the transmit status) the timestamp value obtained from MTL is written to the transmit descriptor (TDES2 and TDES3) that contains the end-of-frame buffer. The status information is then written to this transmit descriptor (TDES0). Because the Own bit is cleared during this step, the Host now owns this descriptor. If time stamping was not enabled for this frame, the DMA does not alter the contents of TDES2 and TDES3. 8. Transmit Interrupt (DMA Register Table 427) is set after completing transmission of a frame that has Interrupt on Completion (TDES1[31]) set in its Last Descriptor. The DMA engine then returns to Step 3. 9. In the Suspend state, the DMA tries to re-acquire the descriptor (and thereby return to Step 3) when it receives a Transmit Poll demand and the Underflow Interrupt Status bit is cleared. The TxDMA transmission flow in default mode is shown in Figure 47. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 518 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R R A D R A R A FT D R FT D R A R A FT FT A F Start TxDMA Start Stop TxDMA D D R A FT D R A FT D R (Re-)fetch next descriptor A FT D R A Poll demand (AHB) error? No Yes TxDMA suspended No Own bit set? Yes Transfer data from buffer(s) (AHB) error? No Yes No Frame xfer complete? Yes Close intermediate descriptor Wait for Tx status Time stamp present? No Yes Write time stamp to TDES2 and TDES3 Write status word to TDES0 No (AHB) error? Yes No (AHB) error? Yes Fig 47. TxDMA operation in default mode 22.8.2.2 TxDMA operation: OSF mode While in the Run state, the transmit process can simultaneously acquire two frames without closing the Status descriptor of the first (if the OSF bit is set in DMA Operation mode register, bit 2). As the transmit process finishes transferring the first frame, it All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 519 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R R A immediately polls the Transmit Descriptor list for the second frame. If the second frame is valid, the transmit process transfers this frame before writing the first frame’s status information. R A In OSF mode, the Run state Transmit DMA operates in the following sequence: 1. The DMA operates as described in steps 1 to 6 of the TxDMA (default mode). 2. Without closing the previous frame’s last descriptor, the DMA fetches the next descriptor. 3. If the DMA owns the acquired descriptor, the DMA decodes the transmit buffer address in this descriptor. If the DMA does not own the descriptor, the DMA goes into Suspend mode and skips to Step 7. 4. The DMA fetches the Transmit frame from the Host memory and transfers the frame to the MTL until the End-of-Frame data is transferred, closing the intermediate descriptors if this frame is split across multiple descriptors. 5. The DMA waits for the previous frame’s frame transmission status and time stamp. Once the status is available, the DMA writes the time stamp to TDES2 and TDES3, if such time stamp was captured (as indicated by a status bit). The DMA then writes the status, with a cleared Own bit, to the corresponding TDES0, thus closing the descriptor. If time stamping was not enabled for the previous frame, the DMA does not alter the contents of TDES2 and TDES3. 6. If enabled, the Transmit interrupt is set, the DMA fetches the next descriptor, then proceeds to Step 3 (when Status is normal). If the previous transmission status shows an underflow error, the DMA goes into Suspend mode (Step 7). 7. In Suspend mode, if a pending status and time stamp are received from the MTL, the DMA writes the time stamp (if enabled for the current frame) to TDES2 and TDES3, then writes the status to the corresponding TDES0. It then sets relevant interrupts and returns to Suspend mode. 8. The DMA can exit Suspend mode and enter the Run state (go to Step 1 or Step 2 depending on pending status) only after receiving a Transmit Poll demand (DMA Transmit Poll Demand register). Remark: As the DMA fetches the next descriptor in advance before closing the current descriptor, the descriptor chain should have more than 2 different descriptors for correct and proper operation. The basic flow is described in Figure 48. D R A R A FT D R FT D R A A FT D R A R A FT F FT D R A FT D FT D D R A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 520 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R R A D R A R A FT D R FT D R A R A FT FT A F Start TxDMA Start Stop TxDMA D D R A FT D R A FT D R (Re-)fetch next descriptor A FT D R A Poll demand (AHB) error? No Yes TxDMA suspended No Own bit set? Yes Previous frame status available Transfer data from buffer(s) Time stamp present? Yes No (AHB) error? No Yes No Write time stamp to TDES2 & TDES3 for previous frame Frame xfer complete? No Yes Second frame? Yes Close intermediate descriptor Wait for previous frame’s Tx status (AHB) error? No Yes Time stamp present? No Yes Write time stamp to TDES2 & TDES3 for previous frame Write status word to prev. frame’s TDES0 Write status word to prev. frame’s TDES0 No (AHB) error? Yes No (AHB) error? Yes No (AHB) error? Yes Fig 48. TxDMA operation in OSF mode All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 521 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R A D R A R A FT D R FT 22.8.2.3 Transmit frame processing D R The Transmit DMA expects that the data buffers contain complete Ethernet frames, excluding preamble, pad bytes, and FCS fields. The DA, SA, and Type/Len fields contain valid data. If the Transmit Descriptor indicates that the MAC core must disable CRC or PAD insertion, the buffer must have complete Ethernet frames (excluding preamble), including the CRC bytes. Frames can be data-chained and can span several buffers. Frames must be delimited by the First Descriptor (TDES1[29]) and the Last Descriptor (TDES1[30]), respectively. FT D R A FT D As transmission starts, the First Descriptor must have (TDES1[29]) set. When this occurs, frame data transfers from the Host buffer to the MTL Transmit FIFO. Concurrently, if the current frame has the Last Descriptor (TDES1[30]) clear, the Transmit Process attempts to acquire the Next Descriptor. The Transmit Process expects this descriptor to have TDES1[29] clear. If TDES1[30] is clear, it indicates an intermediary buffer. If TDES1[30] is set, it indicates the last buffer of the frame. After the last buffer of the frame has been transmitted, the DMA writes back the final status information to the Transmit Descriptor 0 (TDES0) word of the descriptor that has the last segment set in Transmit Descriptor 1 (TDES1[30]). At this time, if Interrupt on Completion (TDES1[31]) was set, Transmit Interrupt (DMA Status register, bit 0) is set, the Next Descriptor is fetched, and the process repeats. The actual frame transmission begins after the MTL Transmit FIFO has reached either a programmable transmit threshold (DMA Operation Mode register, bits [16:14]), or a full frame is contained in the FIFO. There is also an option for Store and Forward Mode (DMA Operation Mode register, bit [21]). Descriptors are released (Own bit TDES0[31] clears) when the DMA finishes transferring the frame. Remark: To ensure proper transmission of a frame and the next frame, you must specify a non-zero buffer size for the transmit descriptor that has the Last Descriptor (TDES1[30]) set. R A R A F D R A FT D FT D R A R A A FT 22.8.2.4 Transmit polling suspended Transmit polling can be suspended by either of the following conditions: • The DMA detects a descriptor owned by the Host (TDES0[31]=0). To resume, the driver must give descriptor ownership to the DMA and then issue a Poll Demand command. • A frame transmission is aborted when a transmit error because of underflow is detected. The appropriate Transmit Descriptor 0 (TDES0) bit is set. If the second condition occur, both Abnormal Interrupt Summary (DMA Status register Table 427) and Transmit Underflow bits (DMA Status register Table 427) are set, and the information is written to Transmit Descriptor 0, causing the suspension. If the DMA goes into SUSPEND state because of the first condition, then both Normal Interrupt Summary (DMA Status register Table 427) and Transmit Buffer Unavailable (DMA Status register Table 427) are set. In both cases, the position in the Transmit List is retained. The retained position is that of the descriptor following the Last Descriptor closed by the DMA. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 522 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R R A The driver must explicitly issue a Transmit Poll Demand command after rectifying the suspension cause. A FT D R D R A R A FT D R FT D R A F R D R A FT 22.8.2.5 Reception A The Receive DMA engine’s reception sequence is shown in Figure 49 and proceeds as follows: 1. The host sets up Receive descriptors (RDES0-RDES3) and sets the Own bit (RDES0[31]). 2. Once the SR (DMA Operation Mode register Table 428) bit is set, the DMA enters the Run state. While in the Run state, the DMA polls the Receive Descriptor list, attempting to acquire free descriptors. If the fetched descriptor is not free (is owned by the host), the DMA enters the Suspend state and jumps to Step 9. 3. The DMA decodes the receive data buffer address from the acquired descriptors. 4. Incoming frames are processed and placed in the acquired descriptor’s data buffers. 5. When the buffer is full or the frame transfer is complete, the Receive engine fetches the next descriptor. 6. If the current frame transfer is complete, the DMA proceeds to Step 7. If the DMA does not own the next fetched descriptor and the frame transfer is not complete (EOF is not yet transferred), the DMA sets the Descriptor Error bit in the RDES0 (unless flushing is disabled). The DMA closes the current descriptor (clears the Own bit) and marks it as intermediate by clearing the Last Segment (LS) bit in the RDES0 value (marks it as Last Descriptor if flushing is not disabled), then proceeds to Step 8. If the DMA does own the next descriptor but the current frame transfer is not complete, the DMA closes the current descriptor as intermediate and reverts to Step 4. 7. If IEEE 1588 time stamping is enabled, the DMA writes the timestamp (if available) to the current descriptor’s RDES2 and RDES3. It then takes the receive frame’s status from the MTL and writes the status word to the current descriptor’s RDES0, with the Own bit cleared and the Last Segment bit set. 8. The Receive engine checks the latest descriptor’s Own bit. If the host owns the descriptor (Own bit is 0) the Receive Buffer Unavailable bit (DMA Status register Table 427) is set and the DMA Receive engine enters the Suspended state (Step 9). If the DMA owns the descriptor, the engine returns to Step 4 and awaits the next frame. 9. Before the Receive engine enters the Suspend state, partial frames are flushed from the Receive FIFO (You can control flushing using Bit 24 of DMA Operation MOde register Table 428). 10. The Receive DMA exits the Suspend state when a Receive Poll demand is given or the start of next frame is available from the MTL’s Receive FIFO. The engine proceeds to Step 2 and refetches the next descriptor. A FT D R A FT D FT D R A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 523 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R R A D R A R A FT D R FT D R A R A FT FT A F Start RxDMA Start Stop RxDMA D D R A FT D R A FT D Poll demand / new frame available (Re-)Fetch next descriptor R A FT D R A RxDMA suspended Yes Frame transfer complete? No Yes Flush disabled ? No Flush the remaining frame No (AHB) error? No Own bit set? Yes Frame data available ? Yes Write data to buffer(s) (AHB) error? No Fetch next descriptor No Yes Wait for frame data Yes (AHB) error? No Yes Flush disabled ? No No Own bit set for next desc? No Frame transfer complete? Yes Yes Yes Time stamp present? No Close RDES0 as last descriptor (AHB) error? Write time stamp to RDES2 & RDES3 Set descriptor error Close RDES0 as intermediate descriptor Yes No Yes (AHB) error? Yes No Fig 49. Receive DMA operation The DMA does not acknowledge accepting the status from the MTL until it has completed the time stamp write-back and is ready to perform status write-back to the descriptor. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 524 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R R A If software has enabled time stamping through CSR, when a valid time stamp value is not available for the frame (for example, because the receive FIFO was full before the time stamp could be written to it), the DMA writes all-ones to RDES2 and RDES3. Otherwise (that is, if time stamping is not enabled), the RDES2 and RDES3 remain unchanged. R A A FT D R A FT D D R A R A FT D R FT D R A F R A FT D D FT R 22.8.2.6 Receive descriptor acquisition The Receive Engine always attempts to acquire an extra descriptor in anticipation of an incoming frame. Descriptor acquisition is attempted if any of the following conditions is satisfied: A FT D R A • The receive Start/Stop bit (DMA Operation Mode register Table 428) has been set immediately after being placed in the Run state. • The data buffer of current descriptor is full before the frame ends for the current transfer. • The controller has completed frame reception, but the current Receive Descriptor is not yet closed. • The receive process has been suspended because of a host-owned buffer (RDES0[31] = 0) and a new frame is received. • A Receive poll demand has been issued. 22.8.2.7 Receive frame processing The MAC transfers the received frames to the Host memory only when the frame passes the address filter and frame size is greater than or equal to configurable threshold bytes set for the Receive FIFO of MTL, or when the complete frame is written to the FIFO in Store-and-Forward mode. If the frame fails the address filtering, it is dropped in the MAC block itself (unless Receive All bit 3 is set in the MAC Frame Filter register; Table 404). Frames that are shorter than 64 bytes, because of collision or premature termination, can be purged from the MTL Receive FIFO. After 64 (configurable threshold) bytes have been received, the MTL block requests the DMA block to begin transferring the frame data to the Receive Buffer pointed to by the current descriptor. The DMA sets First Descriptor (RDES0[9]) after the DMA Host Interface (AHB or MDC) becomes ready to receive a data transfer (if DMA is not fetching transmit data from the host), to delimit the frame. The descriptors are released when the Own (RDES[31]) bit is reset to 0, either as the Data buffer fills up or as the last segment of the frame is transferred to the Receive buffer. If the frame is contained in a single descriptor, both Last Descriptor (RDES[8]) and First Descriptor (RDES[9]) are set. The DMA fetches the next descriptor, sets the Last Descriptor (RDES[8]) bit, and releases the RDES0 status bits in the previous frame descriptor. Then the DMA sets Receive Interrupt (Register 5[6]). The same process repeats unless the DMA encounters a descriptor flagged as being owned by the host. If this occurs, the Receive Process sets Receive Buffer Unavailable (DMA Status register Table 427) and then enters the Suspend state. The position in the receive list is retained. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 525 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R A D R A R A FT D R FT 22.8.2.8 Receive process suspended D R If a new Receive frame arrives while the Receive Process is in Suspend state, the DMA refetches the current descriptor in the Host memory. If the descriptor is now owned by the DMA, the Receive Process re-enters the Run state and starts frame reception. If the descriptor is still owned by the host, by default, the DMA discards the current frame at the top of the MTL Rx FIFO and increments the missed frame counter. If more than one frame is stored in the MTL Rx FIFO, the process repeats. The discarding or flushing of the frame at the top of the MTL Rx FIFO can be avoided by setting Operation Mode register bit 24 (DFF) in Table 428. In such conditions, the receive process sets the Receive Buffer Unavailable status and returns to the Suspend state. FT D R A FT D R A R A F D R A FT D FT D R A R A A FT 22.8.2.9 Interrupts Interrupts can be generated as a result of various events. The DMA Status register (Table 427) contains all the bits that might cause an interrupt. Table 429 contains an enable bit for each of the events that can cause an interrupt. There are two groups of interrupts, Normal and Abnormal, as described in DMA Status register (Table 427). Interrupts are cleared by writing a 1 to the corresponding bit position. When all the enabled interrupts within a group are cleared, the corresponding summary bit is cleared. When both the summary bits are cleared, the interrupt signal is de-asserted. If the MAC core is the cause for assertion of the interrupt, then any of the GLI, GMI, or GPI bits of DMA Status register (Table 427) are set HIGH. Remark: The DMA Status register (Table 427) is the (interrupt) status register. The interrupt pin is asserted because of any event in this status register only if the corresponding interrupt enable bit is set in DMA Interrupt Enable Register (Table 429). Interrupts are not queued and if the interrupt event occurs before the driver has responded to it, no additional interrupts are generated. For example, the Receive Interrupt (bit 6 of the DMA Status Register (Table 427) indicates that one or more frames were transferred to the Host buffer. The driver must scan all descriptors, from the last recorded position to the first one owned by the DMA. An interrupt is generated only once for simultaneous, multiple events. The driver must scan the DMA Status register (Table 427) for the cause of the interrupt. The interrupt is not generated again unless a new interrupting event occurs, after the driver has cleared the appropriate bit in DMA Status register. For example, the controller generates a DMA Receive interrupt (bit 6 of the DMA Status register), and the driver begins reading DMA Status register . Next, Receive Buffer Unavailable (bit 7 of DMA Status register (Status Register)) occurs. The driver clears the Receive interrupt. Even then, the sbd_intr_o signal is not de-asserted, because of the active or pending Receive Buffer Unavailable interrupt. An interrupt timer RIWT (bits 7:0 in Receive Interrupt Watchdog Timer Register (Table 431)) is given for flexible control of Receive Interrupt. When this Interrupt timer is programmed with a non-zero value, it gets activated as soon as the RxDMA completes a transfer of a received frame to system memory without asserting the Receive Interrupt because it is not enabled in the corresponding Receive Descriptor (RDES1[31]. When this timer runs out as per the programmed value, RI bit is set and the interrupt is asserted if All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 526 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R R A the corresponding RI is enabled in DMA Interrupt Enable register (Table 429). This timer gets disabled before it runs out, when a frame is transferred to memory and the RI is set because it is enabled for that descriptor. R A A FT D R A FT D R A R A FT D R FT D R A F R A FT D FT 22.8.2.10 Error response to DMA D For any data transfer initiated by a DMA channel, if the slave replies with an error response, that DMA stops all operations and updates the error bits and the Fatal Bus Error bit in the DMA Status register (Table 427). That DMA controller can resume operation only after soft resetting or hard resetting the core and re-initializing the DMA. This DMA behavior is true for non-AHB interfaced DMAs that receive an error response. D R A FT D R A 22.9 Ethernet descriptors (enhanced format) The enhanced descriptor structure supports up to 8 DWORDS (32 bytes) and the IEEE 1588-2008 Advanced Timestamp feature or the AV feature. The features of the enhanced descriptor structure are: • Enhanced descriptor size can be 4 DWORDS (16 bytes) or 8 DWORDS (32 bytes) depending on the setting of the ATDS bit in the DMA Bus Mode register (Table 421). • Support buffers of up to 8 KB (useful for Jumbo frames). • The transmit descriptor stores the timestamp in TDES6 and TDES7 when you select the Advanced Timestamp. • This receive descriptor structure is also used for storing the extended status (RDES4) and timestamp (RDES6 and RDES7) when advanced timestamp feature or IPC full offload is selected. • When the enhanced descriptor mode is selected, and the Timestamp feature is enabled, the software needs to allocate 32-bytes (8 DWORDS) of memory for every descriptor. When Timestamping or Receive IPC FullOffload engine are not enabled, the extended descriptors are not required and the SW can use alternate descriptors with the default size of 16 bytes. The core also needs to be configured for this change using the bit 7 (ATDS: Alternate Descriptor Size) of DMA Bus Mode register (Table 421). • When an enhanced descriptor is chosen without Timestamp or Full IPC Offload feature, the descriptor size is always 4 DWORDs (DES0-DES3). The description or bit-mapping alternate descriptor structure (in little-endian mode) is given below. 22.9.1 Transmit descriptor The transmit descriptor structure is shown in Figure 50. The application software must program the control bits TDES0[31:20] during descriptor initialization. When the DMA updates the descriptor, it write backs all the control bits except the OWN bit (which it clears) and updates the status bits[19:0]. The contents of the transmitter descriptor word 0 (TDES0) through word 3 (TDES3) are given in Table 437 through Table 440, respectively. With the advance timestamp support, the snapshot of the timestamp to be taken can be enabled for a given frame by setting bit TTSE: Transmit Timestamp Enable. (bit-25 of TDES0). When the descriptor is closed (i.e. when the OWN bit is cleared), the time-stamp All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 527 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R R A is written into TDES6 and TDES7. This is indicated by the status bit TTSS: Transmit Timestamp Status. (bit-17 of TDES0). This is shown in Figure 50. The contents of TDES6 and TDES7 are mentioned in Table 441 to Table 442. R A A FT D R A FT D When either Advanced Timestamp or IPC Offload (Type 2) features is enabled, the SW should set the DMA Bus Mode register[7], so that the DMA operates with extended descriptor size. When this control bit is reset, the TDES4-TDES7 descriptor space are not valid. D R A R A FT D R FT D R A F R A FT D FT D R A D FT R A 31 O TDES0 W N R E S Ctrl [30:26] T T S E R E S Ctrl [23:20] R E S T T T S R E S 0 Status [16:0] TDES1 Buffer 2 Byte Count [28:16] Buffer 1 Byte Count [12:0] TDES2 Buffer 1 Address [31:0] TDES3 Buffer 2 Address [31:0] or Next Descriptor Address [31:0] TDES4 Reserved TDES5 Reserved TDES6 Transmit Time Stamp Low [31:0] TDES7 Transmit Time Stamp High [31:0] Fig 50. Transmitter descriptor fields - enhanced format The DMA always reads or fetches four DWORDS of the descriptor from system memory to obtain the buffer and control information as shown in Figure 51. When Advanced timestamp feature support is enabled, TDES0 has additional control bits[6:3] for channel 1 and channel 2. For channel 0, the bits 6:3 are ignored. The bits 6:3 are described in Table 437. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 528 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R R A D R A R A FT D R FT D R A R A FT FT D D A F R 31 O W TDES0 N R E S Ctrl [30:26] T T S E R E S Ctrl [23:20] R E S Reserved for Status [17:7] R E S SLOT Number [6:3] R 0 A A FT D R A FT D Reserved for Status [3:0] FT D R A TDES1 Buffer 2 Byte Count [28:16] Buffer 1 Byte Count [12:0] TDES2 Buffer 1 Address [31:0] TDES3 Buffer 2 Address [31:0] or Next Descriptor Address [31:0] Fig 51. Transmit descriptor fetch (read) for enhanced format Table 437. Transmit descriptor word 0 (TDES0) Bit Symbol Description 0 DB Deferred Bit When set, this bit indicates that the MAC defers before transmission because of the presence of carrier. This bit is valid only in Half-Duplex mode. Underflow Error When set, this bit indicates that the MAC aborted the frame because data arrived late from the Host memory. Underflow Error indicates that the DMA encountered an empty transmit buffer while transmitting the frame. The transmission process enters the Suspended state and sets both Transmit Underflow (Register 5[5]) and Transmit Interrupt (Register 5[0]). Excessive Deferral When set, this bit indicates that the transmission has ended because of excessive deferral of over 24,288 bit times (155,680 bits times in 1,000-Mbps mode or if Jumbo Frame is enabled) if the Deferral Check (DC) bit in the MAC Control register is set high. 1 UF 2 ED All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 529 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R A D R A R A FT D R FT Table 437. Transmit descriptor word 0 (TDES0) Bit Symbol Description D R R A FT D R A F D A FT 6:3 CC/ CC: Collision Count (Status field) SLOTNU These status bits indicate the number of collisions that occurred before the M frame was transmitted. This count is not valid when the Excessive Collisions bit (TDES0[8]) is set. The core updates this status field only in the half-duplex mode. SLOTNUM: Slot Number Control Bits in AV Mode These bits indicate the slot interval in which the data should be fetched from the corresponding buffers addressed by TDES2 or TDES3. When the transmit descriptor is fetched, the DMA compares the slot number value in this field with the slot interval maintained in the core (Register 11xx). It fetches the data from the buffers only if there is a match in values. These bits are valid only for the AV channels (not channel 0). R R A A FT D A FT D R A FT D R 7 VF VLAN Frame When set, this bit indicates that the transmitted frame was a VLAN-type frame. Excessive Collision When set, this bit indicates that the transmission was aborted after 16 successive collisions while attempting to transmit the current frame. If the DR (Disable Retry) bit in the MAC Configuration register is set, this bit is set after the first collision, and the transmission of the frame is aborted. Late Collision When set, this bit indicates that frame transmission was aborted due to a collision occurring after the collision window (64 byte-times, including preamble, in MII mode and 512 byte-times, including preamble and carrier extension, in MII mode). This bit is not valid if the Underflow Error bit is set. No Carrier When set, this bit indicates that the Carrier Sense signal form the PHY was not asserted during transmission. Loss of Carrier When set, this bit indicates that a loss of carrier occurred during frame transmission (that is, the gmii_crs_i signal was inactive for one or more transmit clock periods during frame transmission). This is valid only for the frames transmitted without collision when the MAC operates in Half-Duplex mode. IP Payload Error When set, this bit indicates that MAC transmitter detected an error in the TCP, UDP, or ICMP IP datagram payload. The transmitter checks the payload length received in the IPv4 or IPv6 header against the actual number of TCP, UDP, or ICMP packet bytes received from the application and issues an error status in case of a mismatch. Frame Flushed When set, this bit indicates that the DMA/MTL flushed the frame due to a software Flush command given by the CPU. Jabber Timeout When set, this bit indicates the MAC transmitter has experienced a jabber time-out. This bit is only set when the MAC configuration register’s JD bit is not set. 8 EC 9 LC 10 NC 11 LC 12 IPE 13 FF 14 JT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 530 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R A D R A R A FT D R FT Table 437. Transmit descriptor word 0 (TDES0) Bit Symbol Description D R R A FT D R A F D A FT 15 ES Error Summary Indicates the logical OR of the following bits: • TDES0[14]: Jabber Timeout • TDES0[13]: Frame Flush • TDES0[11]: Loss of Carrier • TDES0[10]: No Carrier • TDES0[9]: Late Collision • TDES0[8]: Excessive Collision • TDES0[2]: Excessive Deferral • TDES0[1]: Underflow Error • TDES0[16]: IP Header Error • TDES0[12]: IP Payload Error R R A FT D R A FT D A FT D R A 16 IHE IP Header Error When set, this bit indicates that the MAC transmitter detected an error in the IP datagram header. The transmitter checks the header length in the IPv4 packet against the number of header bytes received from the application and indicates an error status if there is a mismatch. For IPv6 frames, a header error is reported if the main header length is not 40 bytes. Furthermore, the Ethernet Length/Type field value for an IPv4 or IPv6 frame must match the IP header version received with the packet. For IPv4 frames, an error status is also indicated if the Header Length field has a value less than 0x5. Transmit Timestamp Status This field is used as a status bit to indicate that a timestamp was captured for the described transmit frame. When this bit is set, TDES2 and TDES3 have a timestamp value captured for the transmit frame. This field is only valid when the descriptor’s Last Segment control bit (TDES0[29]) is set. Reserved Second Address Chained When set, this bit indicates that the second address in the descriptor is the Next Descriptor address rather than the second buffer address. When TDES0[20] is set, TBS2 (TDES1[28:16]) is a “don’t care” value. TDES0[21] takes precedence over TDES0[20]. Transmit End of Ring When set, this bit indicates that the descriptor list reached its final descriptor. The DMA returns to the base address of the list, creating a descriptor ring. Checksum Insertion Control These bits control the checksum calculation and insertion. Bit encodings are as shown below. • 00: Checksum Insertion Disabled. • 01: Only IP header checksum calculation and insertion are enabled. • 10: IP header checksum and payload checksum calculation and insertion are enabled, but pseudo-header checksum is not calculated in hardware. • 11: IP Header checksum and payload checksum calculation and insertion are enabled, and pseudo-header checksum is calculated in hardware. This field is reserved when the IPC_FULL_OFFLOAD configuration parameter is not selected. Reserved Transmit Timestamp Enable When set, this bit enables IEEE1588 hardware time stamping for the transmit frame referenced by the descriptor. This field is valid only when the First Segment control bit (TDES0[28]) is set. 17 TTSS 19:18 20 TCH 21 TER 23:22 CIC 24 25 TTSE All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 531 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R A D R A R A FT D R FT Table 437. Transmit descriptor word 0 (TDES0) Bit Symbol Description D R R A FT D R A F D A FT 26 DP Disable Pad When set, the MAC does not automatically add padding to a frame shorter than 64 bytes. When this bit is reset, the DMA automatically adds padding and CRC to a frame shorter than 64 bytes, and the CRC field is added despite the state of the DC (TDES0[27]) bit. This is valid only when the first segment (TDES0[28]) is set. R R A A FT D R A FT D R A FT D 27 DC Disable CRC When this bit is set, the MAC does not append a cyclic redundancy check (CRC) to the end of the transmitted frame. This is valid only when the first segment (TDES0[28]) is set. First Segment When set, this bit indicates that the buffer contains the first segment of a frame. Last Segment When set, this bit indicates that the buffer contains the last segment of the frame. When this bit is set, the TBS1: Transmit Buffer 1 Size or TBS2: Transmit Buffer 2 Size field in TDES1 should have a non-zero value. Interrupt on Completion When set, this bit sets the Transmit Interrupt (Register 5[0]) after the present frame has been transmitted. Own Bit When set, this bit indicates that the descriptor is owned by the DMA. When this bit is reset, it indicates that the descriptor is owned by the Host. The DMA clears this bit either when it completes the frame transmission or when the buffers allocated in the descriptor are read completely. The ownership bit of the frame’s first descriptor must be set after all subsequent descriptors belonging to the same frame have been set. This avoids a possible race condition between fetching a descriptor and the driver setting an ownership bit. 28 FS 29 LS 30 IC 31 OWN Table 438. Transmit descriptor word 1 (TDES1) Bit Symbol Description 12:0 TBS1 Transmit buffer 1 size These bits indicate the first data buffer byte size, in bytes. If this field is 0, the DMA ignores this buffer and uses Buffer 2 or the next descriptor, depending on the value of TCH (TDES0[20]). Reserved These bits indicate the second data buffer size in bytes. This field is not valid if TDES0[20] is set. See Section 22.8.1.3. Reserved 15:13 28:16 31:29 TBS2 - Table 439. Transmit descriptor word 2 (TDES2) Bit Symbol Description 31:0 B1ADD Buffer 1 Address Pointer These bits indicate the physical address of Buffer 1. There is no limitation on the buffer address alignment. See Section 22.8.1.2 for further detail on buffer address alignment. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 532 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R A D R A R A FT D R FT D Table 440. Transmit descriptor word 3 (TDES3) Bit Symbol Description R R A FT D R A F D A FT 31:0 B2ADD Buffer 2 Address Pointer (Next Descriptor Address) Indicates the physical address of Buffer 2 when a descriptor ring structure is used. If the Second Address Chained (TDES1[24]) bit is set, this address contains the pointer to the physical memory where the Next Descriptor is present. The buffer address pointer must be aligned to the bus width only when TDES1[24] is set. (LSBs are ignored internally.) R R A A FT D A FT D R A FT D R Table 441. Transmit descriptor word 6 (TDES6) Bit Symbol Description 31:0 TTSL Transmit Frame Timestamp Low This field is updated by DMA with the least significant 32 bits of the timestamp captured for the corresponding transmit frame. This field has the timestamp only if the Last Segment bit (LS) in the descriptor is set and Timestamp status (TTSS) bit is set. Table 442. Transmit descriptor word 7 (TDES7) Bit Symbol Description 31:0 TTSH Transmit Frame Timestamp High This field is updated by DMA with the most significant 32 bits of the timestamp captured for the corresponding receive frame. This field has the timestamp only if the Last Segment bit (LS) in the descriptor is set and Timestamp status (TTSS) bit is set. 22.9.2 Receive descriptor The structure of the received descriptor is shown in Figure 52. This can have 32 bytes of descriptor data (8 DWORDs) when Advanced Timestamp or IPC Full Offload feature is selected. Remark: When either of these features is enabled, the SW should set the DMA Bus Mode register[7] so that the DMA operates with extended descriptor size. When this control bit is reset, RDES0[7] and RDES0[0] is always cleared and the RDES4-RDES7 descriptor space are not valid. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 533 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R R A D R A R A FT D R FT D R A R A FT FT A F 31 O W N RES Buffer 2 Byte Count [30:29] [28:16] Status [30:0] 0 D D R A FT D R A FT D A R RDES0 FT D R A RDES1 CTRL CTRL [15:14] RES Buffer 1 Byte Count [12:0] RDES2 Buffer 1 Address [31:0] RDES3 Buffer 2 Address [31:0] or Next Descriptor Address [31:0] RDES4 Extended Status [31:0] RDES5 Reserved RDES6 Receive Time Stamp Low [31:0] RDES7 Receive Time Stamp High [31:0] Fig 52. Receive descriptor fields - alternate (enhanced format) The contents of RDES0 are identified in Table 443. The contents of RDES1 through RDES3 are identified in Table 444 to Table 446. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 534 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R A D R A R A FT D R FT D Table 443. Receive descriptor fields 0 (RDES0) Bit Symbol Description R R A FT D R A F D A FT 0 ESA Extended Status Available/Rx MAC Address When either Advanced Timestamp or IP Checksum Offload (Type 2) is present, this bit, when set, indicates that the extended status is available in descriptor word 4 (RDES4). This is valid only when the Last Descriptor bit (RDES0[8]) is set. When Advance Timestamp Feature or IPC Full Offload is not selected, this bit indicates Rx MAC Address status. When set, this bit indicates that the Rx MAC Address registers value (1 to 31) matched the frame’s DA field. When reset, this bit indicates that the Rx MAC Address Register 0 value matched the DA field. R R A A FT D R A FT D R A FT D 1 CE CRC Error When set, this bit indicates that a Cyclic Redundancy Check (CRC) Error occurred on the received frame. This field is valid only when the Last Descriptor (RDES0[8]) is set. Dribble Bit Error When set, this bit indicates that the received frame has a non-integer multiple of bytes (odd nibbles). This bit is valid only in MII Mode. Receive Error When set, this bit indicates that the gmii_rxer_i signal is asserted while gmii_rxdv_i is asserted during frame reception. This error also includes carrier extension error in MII and Half-duplex mode. Error can be of less/no extension, or error (rxd  0f) during extension. Receive Watchdog Timeout When set, this bit indicates that the Receive Watchdog Timer has expired while receiving the current frame and the current frame is truncated after the Watchdog Timeout. Frame Type When set, this bit indicates that the Receive Frame is an Ethernet-type frame (the LT field is greater than or equal to 0x0600). When this bit is reset, it indicates that the received frame is an IEEE802.3 frame. This bit is not valid for Runt frames less than 14 bytes. Late Collision When set, this bit indicates that a late collision has occurred while receiving the frame in Half-Duplex mode. Timestamp Available/IP Checksum Error (Type1) /Giant Frame When Advanced Timestamp feature is present, when set, this bit indicates that a snapshot of the Timestamp is written in descriptor words 6 (RDES6) and 7 (RDES7). This is valid only when the Last Descriptor bit (RDES0[8]) is set. When IP Checksum Engine (Type 1) is selected, this bit, when set, indicates that the 16-bit IPv4 Header checksum calculated by the core did not match the received checksum bytes. Otherwise, this bit, when set, indicates the Giant Frame Status. Giant frames are larger-than-1,518-byte (or 1,522-byte for VLAN) normal frames and larger-than-9,018-byte (9,022-byte for VLAN) frame when Jumbo Frame processing is enabled. Last Descriptor When set, this bit indicates that the buffers pointed to by this descriptor are the last buffers of the frame First Descriptor When set, this bit indicates that this descriptor contains the first buffer of the frame. If the size of the first buffer is 0, the second buffer contains the beginning of the frame. If the size of the second buffer is also 0, the next Descriptor contains the beginning of the frame. 2 DE 3 RE 4 RWT 5 FT 6 LC 7 TSA 8 LS 9 FS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 535 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R A D R A R A FT D R FT Table 443. Receive descriptor fields 0 (RDES0) Bit Symbol Description D R R A FT D R A F D A FT 10 VLAN VLAN Tag When set, this bit indicates that the frame pointed to by this descriptor is a VLAN frame tagged by the MAC Core. R R A A FT D R A FT D 11 OE Overflow Error When set, this bit indicates that the received frame was damaged due to buffer overflow in MTL. Length Error When set, this bit indicates that the actual length of the frame received and that the Length/ Type field does not match. This bit is valid only when the Frame Type (RDES0[5]) bit is reset. Source Address Filter Fail When set, this bit indicates that the SA field of frame failed the SA Filter in the MAC Core. Descriptor Error When set, this bit indicates a frame truncation caused by a frame that does not fit within the current descriptor buffers, and that the DMA does not own the Next Descriptor. The frame is truncated. This field is valid only when the Last Descriptor (RDES0[8]) is set. ES: Error Summary Indicates the logical OR of the following bits: • RDES0[1]: CRC Error • RDES0[3]: Receive Error • RDES0[4]: Watchdog Timeout • RDES0[6]: Late Collision • RDES0[7]: Giant Frame • RDES4[4:3]: IP Header/Payload Error • RDES0[11]: Overflow Error • RDES0[14]: Descriptor Error This field is valid only when the Last Descriptor (RDES0[8]) is set. Frame Length These bits indicate the byte length of the received frame that was transferred to host memory (including CRC). This field is valid when Last Descriptor (RDES0[8]) is set and either the Descriptor Error (RDES0[14]) or Overflow Error bits are reset. The frame length also includes the two bytes appended to the Ethernet frame when IP checksum calculation (Type 1) is enabled and the received frame is not a MAC control frame. This field is valid when Last Descriptor (RDES0[8]) is set. When the Last Descriptor and Error Summary bits are not set, this field indicates the accumulated number of bytes that have been transferred for the current frame. Destination Address Filter Fail When set, this bit indicates a frame that failed in the DA Filter in the MAC Core. Own Bit When set, this bit indicates that the descriptor is owned by the DMA of the MAC Subsystem. When this bit is reset, this bit indicates that the descriptor is owned by the Host. The DMA clears this bit either when it completes the frame reception or when the buffers that are associated with this descriptor are full. FT D R A 12 LE 13 SAF 14 DE 15 ES 29:16 FL 30 AFM 31 OWN All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 536 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R A D R A R A FT D R FT D Table 444. Receive descriptor fields 1 (RDES1) Bit Symbol Description R R A FT D R A F D A FT 12:0 RBS1 Receive Buffer 1 Size Indicates the first data buffer size in bytes. The buffer size must be a multiple of 4, 8, or 16, depending upon the bus widths (32, 64, or 128), even if the value of RDES2 (buffer1 address pointer) is not aligned. When the buffer size is not a multiple of 4, 8, or 16, the resulting behavior is undefined. If this field is 0, the DMA ignores this buffer and uses Buffer 2 or next descriptor depending on the value of RCH (Bit 14). See Section 22.8.1.3 for further details on calculating buffer sizes. R R A A FT D A FT D R A FT D R 13 14 RCH Reserved Second Address Chained When set, this bit indicates that the second address in the descriptor is the Next Descriptor address rather than the second buffer address. When this bit is set, RBS2 (RDES1[28:16]) is a “don’t care” value. RDES1[15] takes precedence over RDES1[14]. Receive End of Ring When set, this bit indicates that the descriptor list reached its final descriptor. The DMA returns to the base address of the list, creating a descriptor ring. Receive Buffer 2 Size These bits indicate the second data buffer size, in bytes. The buffer size must be a multiple of 4, 8, or 16, depending on the bus widths (32, 64, or 128, respectively), even if the value of RDES3 (buffer2 address pointer) is not aligned to bus width. If the buffer size is not an appropriate multiple of 4, 8, or 16, the resulting behavior is undefined. This field is not valid if RDES1[14] is set. See Section 22.8.1.3 for further details on calculating buffer sizes. 15 RER 28:16 RBS2 Table 445. Receive descriptor fields 2 (RDES2) Bit Symbol Description 31:0 B1ADD Address Pointer These bits indicate the physical address of Buffer 1. There are no limitations on the buffer address alignment except for the following condition: The DMA uses the configured value for its address generation when the RDES2 value is used to store the start of frame. Note that the DMA performs a write operation with the RDES2[3/2/1:0] bits as 0 during the transfer of the start of frame but the frame data is shifted as per the actual Buffer address pointer. The DMA ignores RDES2[3/2/1:0] (corresponding to bus width of 128/64/32) if the address pointer is to a buffer where the middle or last part of the frame is stored. See Section 22.8.1.2for further details on buffer address alignment. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 537 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R A D R A R A FT D R FT D Table 446. Receive descriptor fields 3 (RDES3) Bit Symbol Description R R A FT D R A F D A FT 31:0 B2ADD Buffer 2 Address Pointer (Next Descriptor Address) These bits indicate the physical address of Buffer 2 when a descriptor ring structure is used. If the Second Address Chained (RDES1[24]) bit is set, this address contains the pointer to the physical memory where the Next Descriptor is present. If RDES1[24] is set, the buffer (Next Descriptor) address pointer must be bus width-aligned (RDES3[3, 2, or 1:0] = 0, corresponding to a bus width of 128, 64, or 32. LSBs are ignored internally.) However, when RDES1[24] is reset, there are no limitations on the RDES3 value, except for the following condition: The DMA uses the configured value for its buffer address generation when the RDES3 value is used to store the start of frame. The DMA ignores RDES3 [3, 2, or 1:0] (corresponding to a bus width of 128, 64, or 32) if the address pointer is to a buffer where the middle or last part of the frame is stored. R The extended status written is as shown in Table 447. The extended status is written only when there is status related to IPC or timestamp available. The availability of extended status is indicated by bit-0 of RDES0. This status is available only when Advance Timestamp or IPC Full Offload feature is selected. Table 447. Receive descriptor fields 4 (RDES4) Bit Symbol Description R A A FT D A FT D R A FT D R 2:0 IPPL IP Payload Type These bits indicate the type of payload encapsulated in the IP datagram processed by the Receive Checksum Offload Engine (COE). The COE also sets these bits to 00 if it does not process the IP datagram’s payload due to an IP header error or fragmented IP. • 000: Unknown or did not process IP payload • 001: UDP • 010: TCP • 011: ICMP • 1xx: Reserved IP Header Error When set, this bit indicates either that the 16-bit IPv4 header checksum calculated by the core does not match the received checksum bytes, or that the IP datagram version is not consistent with the Ethernet Type value. IP Payload Error When set, this bit indicates that the 16-bit IP payload checksum (that is, the TCP, UDP, or ICMP checksum) that the core calculated does not match the corresponding checksum field in the received segment. It is also set when the TCP, UDP, or ICMP segment length does not match the payload length value in the IP Header field. IP Checksum Bypassed When set, this bit indicates that the checksum offload engine is bypassed. 3 IPHE 4 IPPLE 5 IPCSB All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 538 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 22: LPC18xx Ethernet FT D R A D R A R A FT D R FT Table 447. Receive descriptor fields 4 (RDES4) Bit Symbol Description D R R A FT D R A F D A FT 6 7 11:8 IPv4 IPv6 MT IPv4 Packet Received When set, this bit indicates that the received packet is an IPv4 packet. IPv6 Packet Received When set, this bit indicates that the received packet is an IPv6 packet. R Message Type These bits are encoded to give the type of the message received. • 0000: No PTP message received • 0001: SYNC (all clock types) • 0010: Follow_Up (all clock types) • 0011: Delay_Req (all clock types) • 0100: Delay_Resp (all clock types) • 0101: Pdelay_Req (in peer-to-peer transparent clock) • 0110: Pdelay_Resp (in peer-to-peer transparent clock) • 0111: Pdelay_Resp_Follow_Up (in peer-to-peer transparent clock) • 1000: Announce • 1001: Management • 1010: Signaling • 1011-1110: Reserved • 1111: PTP packet with Reserved message type These bits are valid only when you select the Advance Timestamp feature. RDES6 and RDES7 contain the snapshot of the time-stamp. The availability of the snapshot of the time-stamp in RDES6 and RDES7 is indicated by bit-7 in the RDES0 descriptor. The contents of RDES6 and RDES7 are identified in Table 448 and Table 449. Table 448. Receive descriptor fields 6 (RDES6) Bit Symbol Description R A FT D R A FT D A FT D R A 31:0 RTSL Receive Frame Timestamp Low This field is updated by DMA with the least significant 32 bits of the timestamp captured for the corresponding receive frame. This field is updated by DMA only for the last descriptor of the receive frame which is indicated by Last Descriptor status bit (RDES0[8]). Table 449. Receive descriptor fields 7 (RDES7) Bit Symbol Description 31:0 RTSH Receive Frame Timestamp High This field is updated by DMA with the most significant 32 bits of the timestamp captured for the corresponding receive frame. This field is updated by DMA only for the last descriptor of the receive frame which is indicated by Last Descriptor status bit (RDES0[8]). All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 539 of 1164 D R A FT D R A FT D R A FT D R A FT D R A FT UM10430 Chapter 23: LPC18xx LCD Rev. 00.13 — 20 July 2011 D D D R A FT D D R A FT D R A FT D R A R A FT D R A R A FT D R A FT D R A F R A FT D R R D User manual FT D R A FT FT A FT 23.1 How to read this chapter The LCD controller is available on part LPC1850. D D R A FT D R A 23.2 Basic configuration The LCD controller is configured as follows: • See Table 450 for clocking and power control. • The LCD is reset by the LCD_RST (reset # 16). • The LCD interrupt is connected to interrupt slot # 7 in the NVIC. Table 450. LCD clocking and power control Base clock Branch clock Maximum frequency Notes LCD register interface clock BASE_M3_CLK CLK_M3_LCD 150 MHz - 23.3 Features • • • • AHB bus master interface to access frame buffer. Setup and control via a separate AHB slave interface. Dual 16-deep programmable 64-bit wide FIFOs for buffering incoming display data. Supports single and dual-panel monochrome Super Twisted Nematic (STN) displays with 4 or 8-bit interfaces. • Supports single and dual-panel color STN displays. • Supports Thin Film Transistor (TFT) color displays. • Programmable display resolution including, but not limited to: 320x200, 320x240, 640x200, 640x240, 640x480, 800x600, and 1024x768. • • • • • • • • • • • Hardware cursor support for single-panel displays. 15 gray-level monochrome, 3375 color STN, and 32K color palettized TFT support. 1, 2, or 4 bits-per-pixel (bpp) palettized displays for monochrome STN. 1, 2, 4, or 8 bpp palettized color displays for color STN and TFT. 16 bpp true-color non-palettized, for color STN and TFT. 24 bpp true-color non-palettized, for color TFT. Programmable timing for different display panels. 256 entry, 16-bit palette RAM, arranged as a 128x32-bit RAM. Frame, line, and pixel clock signals. AC bias signal for STN, data enable signal for TFT panels. Supports little and big-endian, and Windows CE data formats. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 540 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 23: LPC18xx LCD FT D R R A • LCD panel clock may be generated from the peripheral clock, or from a clock input R D R A R A FT D R FT D R pin. A A A FT D R A FT D R A F 23.4 General description 23.4.1 Programmable parameters The following key display and controller parameters can be programmed: FT D R A FT D R A FT D • • • • • • • • • • • • • • • • • Horizontal front and back porch Horizontal synchronization pulse width Number of pixels per line Vertical front and back porch Vertical synchronization pulse width Number of lines per panel Number of pixel clocks per line Hardware cursor control. Signal polarity, active HIGH or LOW AC panel bias Panel clock frequency Bits-per-pixel Display type: STN monochrome, STN color, or TFT STN 4 or 8-bit interface mode STN dual or single panel mode Little-endian, big-endian, or Windows CE mode Interrupt generation event 23.4.2 Hardware cursor support The hardware cursor feature reduces software overhead associated with maintaining a cursor image in the LCD frame buffer. Without this feature, software needed to: • Save an image of the area under the next cursor position. • Update the area with the cursor image. • Repair the last cursor position with a previously saved image. In addition, the LCD driver had to check whether the graphics operation had overwritten the cursor, and correct it. With a cursor size of 64x64 and 24-bit color, each cursor move involved reading and writing approximately 75 kB of data. The hardware cursor removes the requirement for this management by providing a completely separate image buffer for the cursor, and superimposing the cursor image on the LCD output stream at the current cursor (X,Y) coordinate. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 541 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 23: LPC18xx LCD FT D R R A To move the hardware cursor, the software driver supplies a new cursor coordinate. The frame buffer requires no modification. This significantly reduces software overhead. R A The cursor image is held in the LCD controller in an internal 256x32-bit buffer memory. A D R A R A FT D R FT D R A A FT D R A R F FT D R FT D FT D 23.4.3 Types of LCD panels supported The LCD controller supports the following types of LCD panel: A FT D R A • • • • • Active matrix TFT panels with up to 24-bit bus interface. Single-panel monochrome STN panels (4-bit and 8-bit bus interface). Dual-panel monochrome STN panels (4-bit and 8-bit bus interface per panel). Single-panel color STN panels, 8-bit bus interface. Dual-panel color STN panels, 8-bit bus interface per panel. 23.4.3.1 TFT panels TFT panels support one or more of the following color modes: • • • • • • 1 bpp, palettized, 2 colors selected from available colors. 2 bpp, palettized, 4 colors selected from available colors. 4 bpp, palettized, 16 colors selected from available colors. 8 bpp, palettized, 256 colors selected from available colors. 12 bpp, direct 4:4:4 RGB. 16 bpp, direct 5:5:5 RGB, with 1 bpp not normally used. This pixel is still output, and can be used as a brightness bit to connect to the Least Significant Bit (LSB) of RGB components of a 6:6:6 TFT panel. • 16 bpp, direct 5:6:5 RGB. • 24 bpp, direct 8:8:8 RGB, providing over 16 million colors. Each 16-bit palette entry is composed of 5 bpp (RGB), plus a common intensity bit. This provides better memory utilization and performance compared with a full 6 bpp structure. The total number of colors supported can be doubled from 32K to 64K if the intensity bit is used and applied to all three color components simultaneously. Alternatively, the 16 signals can be used to drive a 5:6:5 panel with the extra bit only applied to the green channel. 23.4.3.2 Color STN panels Color STN panels support one or more of the following color modes: • • • • • 1 bpp, palettized, 2 colors selected from 3375. 2 bpp, palettized, 4 colors selected from 3375. 4 bpp, palettized, 16 colors selected from 3375. 8 bpp, palettized, 256 colors selected from 3375. 16 bpp, direct 4:4:4 RGB, with 4 bpp not being used. 23.4.3.3 Monochrome STN panels Monochrome STN panels support one or more of the following modes: All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 542 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 23: LPC18xx LCD FT D R A D R A R A FT D R FT • 1 bpp, palettized, 2 gray scales selected from 15. • 2 bpp, palettized, 4 gray scales selected from 15. • 4 bpp, palettized, 16 gray scales selected from 15. D R More than 4 bpp for monochrome panels can be programmed, but using these modes has no benefit because the maximum number of gray scales supported on the display is 15. D R A FT D R R A F D R A FT A FT A FT R A D FT D R A 23.5 Pin description The largest configuration for the LCD controller uses 31 pins. There are many variants using as few as 10 pins for a monochrome STN panel. Pins are allocated in groups based on the selected configuration. All LCD functions are shared with other chip functions. In Table 451, only the LCD related portion of the pin name is shown. Table 451. LCD controller pins Pin name Type Function LCDPWR LCDCLK Output LCD panel power enable. Output LCD panel clock. LCDENAB/LCDM Output STN AC bias drive or TFT data enable output. (LCDAC) LCDFP LCDLE LCDLP LCDVD[23:0] GP_CLKIN Output Frame pulse (STN). Vertical synchronization pulse (TFT) Output Line end signal Output Line synchronization pulse (STN). Horizontal synchronization pulse (TFT) Output LCD panel data. Bits used depend on the panel configuration. Input General purpose CGU input clock. Can be used as the LCD external clock LCDCLKIN. 23.5.1 Signal usage The signals that are used for various display types are identified in the following sections. 23.5.1.1 Signals used for single panel STN displays The signals used for single panel STN displays are shown in Table 452. UD refers to upper panel data. Table 452. Pins used for single panel STN displays Pin name 4-bit Monochrome (10 pins) 8-bit Monochrome (14 pins) Color (14 pins) LCDPWR LCDDCLK LCDENAB/ LCDM LCDFP LCDLE LCDLP Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 543 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 23: LPC18xx LCD FT D R A D R A R A FT D R FT Table 452. Pins used for single panel STN displays Pin name 4-bit Monochrome (10 pins) 8-bit Monochrome (14 pins) D R Color (14 pins) R A FT D R R A F D R A FT A FT A FT LCDVD[3:0] LCDVD[7:4] LCDVD[23:8] UD[3:0] - UD[3:0] UD[7:4] - UD[3:0] UD[7:4] - D D R A FT D R A 23.5.1.2 Signals used for dual panel STN displays The signals used for dual panel STN displays are shown in Table 453. UD refers to upper panel data, and LD refers to lower panel data. Table 453. Pins used for dual panel STN displays Pin name 4-bit Monochrome (14 pins) 8-bit Monochrome (22 pins) Color (22 pins) LCDPWR LCDDCLK LCDENAB/ LCDM LCDFP LCDLE LCDLP LCDVD[3:0] LCDVD[7:4] LCDVD[11:8] LCDVD[15:12] LCDVD[23:16] Y Y Y Y Y Y UD[3:0] LD[3:0] - Y Y Y Y Y Y UD[3:0] UD[7:4] LD[3:0] LD[7:4] - Y Y Y Y Y Y UD[3:0] UD[7:4] LD[3:0] LD[7:4] - 23.5.1.3 Signals used for TFT displays The signals used for TFT displays are shown in Table 454. Table 454. Pins used for TFT displays Pin name 12-bit, 4:4:4 mode (18 pins) 16-bit, 5:6:5 mode (22 pins) 16-bit, 1:5:5:5 mode (24 pins) 24-bit (30 pins) LCDPWR LCDDCLK LCDENAB/ LCDM LCDFP LCDLE LCDLP LCDVD[1:0] LCDVD[2] LCDVD[3] LCDVD[7:4] LCDVD[9:8] LCDVD[10] Y Y Y Y Y Y RED[3:0] - Y Y Y Y Y Y RED[0] RED[4:1] GREEN[0] Y Y Y Y Y Y Intensity RED[0] RED[4:1] Intensity Y Y Y Y Y Y RED[1:0] RED[2] RED[3] RED[7:4] GREEN[1:0] GREEN[2] © NXP B.V. 2011. All rights reserved. All information provided in this document is subject to legal disclaimers. User manual Rev. 00.13 — 20 July 2011 544 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 23: LPC18xx LCD FT D R A D R A R A FT D R FT Table 454. Pins used for TFT displays Pin name 12-bit, 4:4:4 mode (18 pins) 16-bit, 5:6:5 mode (22 pins) 16-bit, 1:5:5:5 mode (24 pins) D R R A 24-bit R A F A FT D R FT D (30 pins) FT D R A A FT D LCDVD[11] LCDVD[15:12] LCDVD[17:16] LCDVD[18] LCDVD[19] LCDVD[23:20] GREEN[3:0] BLUE[3:0] GREEN[1] GREEN[5:2] BLUE[0] BLUE[4:1] GREEN[0] GREEN[4:1] Intensity BLUE[0] BLUE[4:1] GREEN[3] GREEN[7:4] BLUE[1:0] BLUE[2] BLUE[3] BLUE[7:4] R A FT D R A 23.6 Register description Table 455 shows the registers associated with the LCD controller and a summary of their functions. Following the table are details for each register. Table 455. Register overview: LCD controller (base address: 0x4000 8000) Name Access Address offset Description Reset value [1] TIMH TIMV POL LE UPBASE LPBASE CTRL INTMSK INTRAW INTSTAT INTCLR UPCURR LPCURR PAL CRSR_IMG CRSR_CTRL CRSR_CFG CRSR_PAL0 CRSR_PAL1 CRSR_XY CRSR_CLIP CRSR_INTMSK R/W R/W R/W R/W R/W R/W R/W R/W RO RO WO RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 0x024 0x028 0x02C 0x030 0x034 to 0x1FC 0x200 to 0x3FC 0x400 to 0x7FC 0x800 to 0xBFC 0xC00 0xC04 0xC08 0xC0C 0xC10 0xC14 0xC20 Horizontal Timing Control register Vertical Timing Control register Clock and Signal Polarity Control register Line End Control register Upper Panel Frame Base Address register Lower Panel Frame Base Address register LCD Control register Interrupt Mask register Raw Interrupt Status register Masked Interrupt Status register Interrupt Clear register Upper Panel Current Address Value register Lower Panel Current Address Value register Reserved 256x16-bit Color Palette registers Reserved Cursor Image registers Cursor Control register Cursor Configuration register Cursor Palette register 0 Cursor Palette register 1 Cursor XY Position register Cursor Clip Position register Cursor Interrupt Mask register 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 545 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 23: LPC18xx LCD FT D R A D R A R A FT D R FT Table 455. Register overview: LCD controller (base address: 0x4000 8000) …continued Name Access Address offset Description D R R A FT D R R A F D R A FT Reset value [1] A FT A FT CRSR_INTCLR CRSR_INTRAW CRSR_INTSTAT [1] WO RO RO 0xC24 0xC28 0xC2C Cursor Interrupt Clear register Cursor Raw Interrupt Status register Cursor Masked Interrupt Status register 0x0 D D R A FT D 0x0 0x0 R A Reset Value reflects the data stored in used bits only. It does not include reserved bits content. 23.6.1 Horizontal Timing register The TIMH register controls the Horizontal Synchronization pulse Width (HSW), the Horizontal Front Porch (HFP) period, the Horizontal Back Porch (HBP) period, and the Pixels-Per-Line (PPL). Table 456. Horizontal Timing register (TIMH, address 0x4000 8000) bit description Bits Symbol Description Reset value 1:0 7:2 PPL Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Pixels-per-line. The PPL bit field specifies the number of pixels in each line or row of the screen. PPL is a 6-bit value that represents between 16 and 1024 pixels per line. PPL counts the number of pixel clocks that occur before the HFP is applied. Program the value required divided by 16, minus 1. Actual pixels-per-line = 16 * (PPL + 1). For example, to obtain 320 pixels per line, program PPL as (320/16) -1 = 19. 0x0 15:8 HSW Horizontal synchronization pulse width. The 8-bit HSW field specifies the pulse width of the line clock in passive mode, or the horizontal synchronization pulse in active mode. Program with desired value minus 1. 0x0 23:16 HFP Horizontal front porch. The 8-bit HFP field sets the number of pixel clock intervals at the end of each line or row of pixels, before the LCD line clock is pulsed. When a complete line of pixels is transmitted to the LCD driver, the value in HFP counts the number of pixel clocks to wait before asserting the line clock. HFP can generate a period of 1-256 pixel clock cycles. Program with desired value minus 1. 0x0 31:24 HBP Horizontal back porch. The 8-bit HBP field is used to specify the number of pixel clock periods inserted at the beginning of each line or row of pixels. After the line clock for the previous line has been deasserted, the value in HBP counts the number of pixel clocks to wait before starting the next display line. HBP can generate a delay of 1-256 pixel clock cycles. Program with desired value minus 1. 0x0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 546 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 23: LPC18xx LCD FT D R A D R A R A FT D R FT 23.6.1.1 Horizontal timing restrictions D R DMA requests new data at the start of a horizontal display line. Some time must be allowed for the DMA transfer and for data to propagate down the FIFO path in the LCD interface. The data path latency forces some restrictions on the usable minimum values for horizontal porch width in STN mode. The minimum values are HSW = 2 and HBP = 2. FT D R A FT D R A R A F D R A FT D FT R A A FT Single panel mode: D R A • • • • HSW = 3 pixel clock cycles HBP = 5 pixel clock cycles HFP = 5 pixel clock cycles Panel Clock Divisor (PCD) = 1 (LCDCLK / 3) Dual panel mode: • • • • HSW = 3 pixel clock cycles HBP = 5 pixel clock cycles HFP = 5 pixel clock cycles PCD = 5 (LCDCLK / 7) If enough time is given at the start of the line, for example, setting HSW = 6, HBP = 10, data does not corrupt for PCD = 4, the minimum value. 23.6.2 Vertical Timing register The TIMV register controls the Vertical Synchronization pulse Width (VSW), the Vertical Front Porch (VFP) period, the Vertical Back Porch (VBP) period, and the Lines-Per-Panel (LPP). All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 547 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 23: LPC18xx LCD FT D R Table 457. Vertical Timing register (TIMV, address 0x4000 8004) bit description Bits Symbol Description D R A R A FT D R FT D A R R A FT D R R A F D R A Reset value A FT A 9:0 LPP Lines per panel. This is the number of active lines per screen. The LPP field specifies the total number of lines or rows on the LCD panel being controlled. LPP is a 10-bit value allowing between 1 and 1024 lines. Program the register with the number of lines per LCD panel, minus 1. For dual panel displays, program the register with the number of lines on each of the upper and lower panels. 0x0 FT D R A FT D R A FT D 15:10 VSW Vertical synchronization pulse width. This is the number of horizontal synchronization lines. The 6-bit VSW field specifies the pulse width of the vertical synchronization pulse. Program the register with the number of lines required, minus one. The number of horizontal synchronization lines must be small (for example, program to zero) for passive STN LCDs. The higher the value the worse the contrast on STN LCDs. 0x0 23:16 VFP Vertical front porch. This is the number of inactive lines at the end of a frame, before the vertical synchronization period. The 8-bit VFP field specifies the number of line clocks to insert at the end of each frame. When a complete frame of pixels is transmitted to the LCD display, the value in VFP is used to count the number of line clock periods to wait. After the count has elapsed, the vertical synchronization signal, LCDFP, is asserted in active mode, or extra line clocks are inserted as specified by the VSW bit-field in passive mode. VFP generates 0–255 line clock cycles. Program to zero on passive displays for improved contrast. 0x0 31:24 VBP Vertical back porch. This is the number of inactive lines at the start of a frame, after the vertical synchronization period. The 8-bit VBP field specifies the number of line clocks inserted at the beginning of each frame. The VBP count starts immediately after the vertical synchronization signal for the previous frame has been negated for active mode, or the extra line clocks have been inserted as specified by the VSW bit field in passive mode. After this has occurred, the count value in VBP sets the number of line clock periods inserted before the next frame. VBP generates 0–255 extra line clock cycles. Program to zero on passive displays for improved contrast. 0x0 23.6.3 Clock and Signal Polarity register The POL register controls various details of clock timing and signal polarity. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 548 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 23: LPC18xx LCD FT D R R A Table 458. Clock and Signal Polarity register (POL, address 0x4000 8008) bit description D R A R A FT D R FT D R A R A A FT FT F Bits Symbol Description Reset value D D R R A A 4:0 PCD_LO Lower five bits of panel clock divisor. The ten-bit PCD field, comprising PCD_HI (bits 31:27 of this register) and PCD_LO, is used to derive the LCD panel clock frequency LCDDCLK from the input clock, LCDDCLK = LCDCLK/(PCD+2). For monochrome STN displays with a 4 or 8-bit interface, the panel clock is a factor of four and eight down from the actual individual pixel clock rate. For color STN displays, 22/3 pixels are output per LCDDCLK cycle, so the panel clock is 0.375 times the pixel rate. For TFT displays, the pixel clock divider can be bypassed by setting the BCD bit in this register. Note: data path latency forces some restrictions on the usable minimum values for the panel clock divider in STN modes: 0x0 FT D R A FT D R A FT D Single panel color mode, PCD = 1 (LCDDCLK = LCDCLK/3). Dual panel color mode, PCD = 4 (LCDDCLK = LCDCLK/6). Single panel monochrome 4-bit interface mode, PCD = 2(LCDDCLK = LCDCLK/4). Dual panel monochrome 4-bit interface mode and single panel monochrome 8-bit interface mode, PCD = 6(LCDDCLK = LCDCLK/8). Dual panel monochrome 8-bit interface mode, PCD = 14(LCDDCLK = LCDCLK/16). 5 CLKSEL Clock Select. This bit controls the selection of the source for LCDCLK. 0 = the clock source for the LCD block is CCLK. 1 = the clock source for the LCD block is LCDCLKIN (external clock input for the LVD). 10:6 ACB AC bias pin frequency. The AC bias pin frequency is only applicable to STN displays. These require the pixel voltage polarity to periodically reverse to prevent damage caused by DC charge accumulation. Program this field with the required value minus one to apply the number of line clocks between each toggle of the AC bias pin, LCDENAB. This field has no effect if the LCD is operating in TFT mode, when the LCDENAB pin is used as a data enable signal. 11 IVS Invert vertical synchronization. The IVS bit inverts the polarity of the LCDFP signal. 0 = LCDFP pin is active HIGH and inactive LOW. 1 = LCDFP pin is active LOW and inactive HIGH. 12 IHS Invert horizontal synchronization. The IHS bit inverts the polarity of the LCDLP signal. 0 = LCDLP pin is active HIGH and inactive LOW. 1 = LCDLP pin is active LOW and inactive HIGH. 0x0 0x0 0x0 0x0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 549 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 23: LPC18xx LCD FT D R R A Table 458. Clock and Signal Polarity register (POL, address 0x4000 8008) bit description D R A R A FT D R FT D R A R A A Bits Symbol Description Reset value FT D R A F FT D R A 13 IPC Invert panel clock. The IPC bit selects the edge of the panel clock on which pixel data is driven out onto the LCD data lines. 0 = Data is driven on the LCD data lines on the rising edge of LCDDCLK. 1 = Data is driven on the LCD data lines on the falling edge of LCDDCLK. 0x0 FT D R A FT D R A FT D 14 IOE Invert output enable. This bit selects the active polarity of the output enable signal in TFT mode. In this mode, the LCDENAB pin is used as an enable that indicates to the LCD panel when valid display data is available. In active display mode, data is driven onto the LCD data lines at the programmed edge of LCDDCLK when LCDENAB is in its active state. 0 = LCDENAB output pin is active HIGH in TFT mode. 1 = LCDENAB output pin is active LOW in TFT mode. 0x0 15 25:16 CPL Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Clocks per line. This field specifies the number of actual LCDDCLK clocks to the LCD panel on each line. This is the number of PPL divided by either 1 (for TFT), 4 or 8 (for monochrome passive), 2 2/3 (for color passive), minus one. This must be correctly programmed in addition to the PPL bit in the TIMH register for the LCD display to work correctly. 0x0 26 BCD Bypass pixel clock divider. Setting this to 1 bypasses the pixel clock divider logic. This is mainly used for TFT displays. 0x0 31:27 PCD_HI Upper five bits of panel clock divisor. See description for PCD_LO, in bits [4:0] of this register. 0x0 23.6.4 Line End Control register The LE register controls the enabling of line-end signal LCDLE. When enabled, a positive pulse, four LCDCLK periods wide, is output on LCDLE after a programmable delay, LED, from the last pixel of each display line. If the line-end signal is disabled it is held permanently LOW. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 550 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 23: LPC18xx LCD FT D R Table 459. Line End Control register (LE, address 0x4000 800C) bit description Bits Symbol Description D R A R A FT D R FT D A R R A FT D R R A F D R A Reset value A FT A 6:0 LED Line-end delay. Controls Line-end signal delay from the rising-edge of the last panel clock, LCDDCLK. Program with number of LCDCLK clock periods minus 1. 0x0 FT D R A FT D R A FT D 15:7 16 LEE Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. LCD Line end enable. 0 = LCDLE disabled (held LOW). 1 = LCDLE signal active. 0x0 31:17 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - 23.6.5 Upper Panel Frame Base Address register The UPBASE register is the color LCD upper panel DMA base address register, and is used to program the base address of the frame buffer for the upper panel. LCDUPBase (and LCDLPBase for dual panels) must be initialized before enabling the LCD controller. The base address must be doubleword aligned. Optionally, the value may be changed mid-frame to create double-buffered video displays. These registers are copied to the corresponding current registers at each LCD vertical synchronization. This event causes the LNBU bit and an optional interrupt to be generated. The interrupt can be used to reprogram the base address when generating double-buffered video. Table 460. Upper Panel Frame Base register (UPBASE, address 0x4000 8010) bit description Bits Symbol Description Reset value 2:0 31:3 LCDUPBASE Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. LCD upper panel base address. This is the start address of the upper panel frame data in memory and is doubleword aligned. 0x0 23.6.6 Lower Panel Frame Base Address register The LPBASE register is the color LCD lower panel DMA base address register, and is used to program the base address of the frame buffer for the lower panel. LCDLPBase must be initialized before enabling the LCD controller. The base address must be doubleword aligned. Optionally, the value may be changed mid-frame to create double-buffered video displays. These registers are copied to the corresponding current registers at each LCD vertical synchronization. This event causes the LNBU bit and an optional interrupt to be generated. The interrupt can be used to reprogram the base address when generating double-buffered video. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 551 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 23: LPC18xx LCD FT D R R A Table 461. Lower Panel Frame Base register (LPBASE, address 0x4000 8014) bit description Bits Symbol Description D R A R A FT D R FT D R A R A FT D D Reset value A FT R A F R A FT D FT 2:0 31:3 LCDLPBASE Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. LCD lower panel base address. This is the start address of the lower panel frame data in memory and is doubleword aligned. 0x0 D R A FT D R A 23.6.7 LCD Control register The CTRL register controls the LCD operating mode and the panel pixel parameters. Table 462. LCD Control register (CTRL, address 0x4000 8018) bit description Bits Symbol Description Reset value 0 LCDEN LCD enable control bit. 0 = LCD disabled. Signals LCDLP, LCDDCLK, LCDFP, LCDENAB, and LCDLE are low. 1 = LCD enabled. Signals LCDLP, LCDDCLK, LCDFP, LCDENAB, and LCDLE are high. See LCD power-up and power-down sequence for details on LCD power sequencing. 0x0 3:1 LCDBPP LCD bits per pixel: Selects the number of bits per LCD pixel: 000 = 1 bpp. 001 = 2 bpp. 010 = 4 bpp. 011 = 8 bpp. 100 = 16 bpp. 101 = 24 bpp (TFT panel only). 110 = 16 bpp, 5:6:5 mode. 111 = 12 bpp, 4:4:4 mode. 0x0 4 LCDBW STN LCD monochrome/color selection. 0 = STN LCD is color. 1 = STN LCD is monochrome. This bit has no meaning in TFT mode. 0x0 5 LCDTFT LCD panel TFT type selection. 0 = LCD is an STN display. Use gray scaler. 1 = LCD is a TFT display. Do not use gray scaler. 0x0 6 LCDMONO8 Monochrome LCD interface width. This bit controls whether a monochrome STN LCD uses a 4 or 8-bit parallel interface. It has no meaning in other modes and must be programmed to zero. 0 = monochrome LCD uses a 4-bit interface. 1 = monochrome LCD uses a 8-bit interface. 0x0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 552 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 23: LPC18xx LCD FT D R R A Table 462. LCD Control register (CTRL, address 0x4000 8018) bit description …continued D R A R A FT D R FT D R A R A A Bits Symbol Description Reset value FT D R A F FT D R A 7 LCDDUAL Single or Dual LCD panel selection. STN LCD interface is: 0 = single-panel. 1 = dual-panel. 0x0 FT D R A FT D R A FT D 8 BGR Color format selection. 0 = RGB: normal output. 1 = BGR: red and blue swapped. 0x0 9 BEBO Big-endian Byte Order. Controls byte ordering in memory: 0 = little-endian byte order. 1 = big-endian byte order. 0x0 10 BEPO Big-Endian Pixel Ordering. Controls pixel ordering within a byte: 0 = little-endian ordering within a byte. 1 = big-endian pixel ordering within a byte. The BEPO bit selects between little and big-endian pixel packing for 1, 2, and 4 bpp display modes, it has no effect on 8 or 16 bpp pixel formats. See Pixel serializer for more information on the data format. 0x0 11 LCDPWR LCD power enable. 0 = power not gated through to LCD panel and LCDV[23:0] signals disabled, (held LOW). 1 = power gated through to LCD panel and LCDV[23:0] signals enabled, (active). See LCD power-up and power-down sequence for details on LCD power sequencing. 0x0 13:12 LCDVCOMP LCD Vertical Compare Interrupt. Generate VComp interrupt at: 00 = start of vertical synchronization. 01 = start of back porch. 10 = start of active video. 11 = start of front porch. 0x0 15:14 16 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Controls when DMA requests are generated: 0 = An LCD DMA request is generated when either of the DMA FIFOs have four or more empty locations. 1 = An LCD DMA request is generated when either of the DMA FIFOs have eight or more empty locations. 0x0 WATERMARK LCD DMA FIFO watermark level. 31:17 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 553 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 23: LPC18xx LCD FT D R A D R A R A FT D R FT 23.6.8 Interrupt Mask register D R The INTMSK register controls whether various LCD interrupts occur.Setting bits in this register enables the corresponding raw interrupt INTRAW status bit values to be passed to the INTSTAT register for processing as interrupts. D R A FT Table 463. Interrupt Mask register (INTMSK, address 0x4000 801C) bit description Bits Function Description Reset value R A FT R A F D R A FT D A FT D R A R A FT D 0 1 FUFIM Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. FIFO underflow interrupt enable. 0: The FIFO underflow interrupt is disabled. 1: Interrupt will be generated when the FIFO underflows. 0x0 2 LNBUIM LCD next base address update interrupt enable. 0: The base address update interrupt is disabled. 1: Interrupt will be generated when the LCD base address registers have been updated from the next address registers. 0x0 3 VCOMPIM Vertical compare interrupt enable. 0: The vertical compare time interrupt is disabled. 1: Interrupt will be generated when the vertical compare time (as defined by LcdVComp field in the CTRL register) is reached. 0x0 4 BERIM AHB master error interrupt enable. 0: The AHB Master error interrupt is disabled. 1: Interrupt will be generated when an AHB Master error occurs. 0x0 31:5 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - 23.6.9 Raw Interrupt Status register The INTRAW register contains status flags for various LCD controller events. These flags can generate an interrupts if enabled by mask bits in the INTMSK register. Table 464. Raw Interrupt Status register (INTRAW, address 0x4000 8020) bit description Bits Function Description Reset value 0 1 FUFRIS Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. FIFO underflow raw interrupt status. Set when either the upper or lower DMA FIFOs have been read accessed when empty causing an underflow condition to occur. Generates an interrupt if the FUFIM bit in the INTMSK register is set. - 2 LNBURIS LCD next address base update raw interrupt status. Mode dependent. Set when the current base address registers have been successfully updated by the next address registers. Signifies that a new next address can be loaded if double buffering is in use. Generates an interrupt if the LNBUIM bit in the INTMSK register is set. 0x0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 554 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 23: LPC18xx LCD FT D R R A Table 464. Raw Interrupt Status register (INTRAW, address 0x4000 8020) bit description D R A R A FT D R FT D R A R A A Bits Function Description Reset value FT D R A F FT D R A 3 VCOMPRIS Vertical compare raw interrupt status. Set when one of the four vertical regions is reached, as selected by the LcdVComp bits in the CTRL register. Generates an interrupt if the VCompIM bit in the INTMSK register is set. 0x0 FT D R A FT D R A FT D 4 BERRAW AHB master bus error raw interrupt status. Set when the AHB master interface receives a bus error response from a slave. Generates an interrupt if the BERIM bit in the INTMSK register is set. 0x0 31:5 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - 23.6.10 Masked Interrupt Status register The INTSTAT register is Read-Only, and contains a bit-by-bit logical AND of the INTRAW register and the INTMASK register. A logical OR of all interrupts is provided to the system interrupt controller. Table 465. Masked Interrupt Status register (INTSTAT, address 0x4000 8024) bit description Bits Function Description Reset value 0 1 FUFMIS Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. FIFO underflow masked interrupt status. Set when the both the FUFRIS bit in the INTRAW register and the FUFIM bit in the INTMSK register are set. 0x0 2 LNBUMIS LCD next address base update masked interrupt status. Set when the both the LNBURIS bit in the INTRAW register and the LNBUIM bit in the INTMSK register are set. 0x0 3 VCOMPMIS Vertical compare masked interrupt status. Set when the both the VCompRIS bit in the INTRAW register and the VCompIM bit in the INTMSK register are set. 0x0 4 BERMIS AHB master bus error masked interrupt status. Set when the both the BERRAW bit in the INTRAW register and the BERIM bit in the INTMSK register are set. 0x0 31:5 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - 23.6.11 Interrupt Clear register The INTCLR register is Write-Only. Writing a logic 1 to the relevant bit clears the corresponding interrupt. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 555 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 23: LPC18xx LCD FT D R R A Table 466. Interrupt Clear register (INTCLR, address 0x4000 8028) bit description D R A R A FT D R FT D R A R A FT A FT F Bits Function Description Reset value D D R R A A 0 1 2 FUFIC LNBUIC Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. FIFO underflow interrupt clear. Writing a 1 to this bit clears the FIFO underflow interrupt. LCD next address base update interrupt clear. Writing a 1 to this bit clears the LCD next address base update interrupt. - FT D R A FT D R A 0x0 0x0 FT D 3 4 31:5 VCOMPIC BERIC - Vertical compare interrupt clear. Writing a 1 to this bit clears the vertical compare interrupt. AHB master error interrupt clear. Writing a 1 to this bit clears the AHB master error interrupt. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0x0 0x0 - 23.6.12 Upper Panel Current Address register The UPCURR register is Read-Only, and contains an approximate value of the upper panel data DMA address when read. Note: This register can change at any time and therefore can only be used as a rough indication of display position. The contents of the UPCURR register are described in Table 467. Table 467. Upper Panel Current Address register (UPCURR, address 0x4000 802C) bit description Bits Function Description Reset value 31:0 LCDUPCURR LCD Upper Panel Current Address. Contains the current LCD upper panel data DMA address. 0x0 23.6.13 Lower Panel Current Address register The LPCURR register is Read-Only, and contains an approximate value of the lower panel data DMA address when read. Note: This register can change at any time and therefore can only be used as a rough indication of display position. Table 468. Lower Panel Current Address register (LPCURR, address 0x4000 8030) bit description Bits Function Description Reset value 31:0 LCDLPCURR LCD Lower Panel Current Address. Contains the current LCD lower panel data DMA address. 0x0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 556 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 23: LPC18xx LCD FT D R A D R A R A FT D R FT 23.6.14 Color Palette registers D R The PAL register contain 256 palette entries organized as 128 locations of two entries per word. Each word location contains two palette entries. This means that 128 word locations are used for the palette. When configured for little-endian byte ordering, bits [15:0] are the lower numbered palette entry and [31:16] are the higher numbered palette entry. When configured for big-endian byte ordering this is reversed, because bits [31:16] are the low numbered palette entry and [15:0] are the high numbered entry. Note: Only TFT displays use all of the palette entry bits. The contents of the PAL register are described in Table 469. Table 469. Color Palette registers (PAL, address 0x4000 8200 (PAL0) to 0x4000 83FC (PAL255)) bit description Bits Function Description Reset value R A FT D R R A F D R A FT D FT D R A A FT R A A FT D 4:0 R04_0 Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields. 0x0 9:5 14:10 15 G04_0 B04_0 I0 Green palette data. Blue palette data. Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities. 0x0 0x0 0x0 20:16 R14_0 Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields. 0x0 25:21 30:26 31 G14_0 B14_0 I1 Green palette data. Blue palette data. Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities. 0x0 0x0 0x0 23.6.15 Cursor Image registers The CRSR_IMG register area contains 256-word wide values which are used to define the image or images overlaid on the display by the hardware cursor mechanism. The image must always be stored in LBBP mode (little-endian byte, big-endian pixel) mode, as described in Section 23.7.5.6. Two bits are used to encode color and transparency for each pixel in the cursor. Depending on the state of bit 0 in the CRSR_CFG register (see Cursor Configuration register description), the cursor image RAM contains either four 32x32 cursor images, or a single 64x64 cursor image. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 557 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 23: LPC18xx LCD FT D R R A The two colors defined for the cursor are mapped onto values from the CRSR_PAL0 and CRSR_PAL0 registers (see Cursor Palette register descriptions). R A A FT D R The contents of the CRSR_IMG register are described in Table 470. Table 470. Cursor Image registers (CRSR_IMG, address 0x4000 8800 (CRSR_IMG0) to 0x4000 8BFC (CRSR_IMG1)) bit description Bits Function Description D R A R A FT D R FT D R A F R A FT D D FT D R A FT R A Reset value A FT D 31:0 CRSR_IMG Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors. 0x0 23.6.16 Cursor Control register The CRSR_CTRL register provides access to frequently used cursor functions, such as the display on/off control for the cursor, and the cursor number. If a 32x32 cursor is selected, one of four 32x32 cursors can be enabled. The images each occupy one quarter of the image memory, with Cursor0 from location 0, followed by Cursor1 from address 0x100, Cursor2 from 0x200 and Cursor3 from 0x300. If a 64x64 cursor is selected only one cursor fits in the image buffer, and no selection is possible. Similar frame synchronization rules apply to the cursor number as apply to the cursor coordinates. If CrsrFramesync is 1, the displayed cursor image is only changed during the vertical frame blanking period. If CrsrFrameSync is 0, the cursor image index is changed immediately, even if the cursor is currently being scanned. The contents of the CRSR_CTRL register are described in Table 471. Table 471. Cursor Control register (CRSR_CTRL, address 0x4000 8C00) bit description Bits Function Description Reset value 0 CrsrOn Cursor enable. 0 = Cursor is not displayed. 1 = Cursor is displayed. 0x0 3:1 5:4 CRSRNUM1_0 Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Cursor image number. If the selected cursor size is 6x64, this field has no effect. If the selected cursor size is 32x32: 00 = Cursor0. 01 = Cursor1. 10 = Cursor2. 11 = Cursor3. 0x0 0x0 31:6 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0x0 23.6.17 Cursor Configuration register The CRSR_CFG register provides overall configuration information for the hardware cursor. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 558 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 23: LPC18xx LCD FT D R A The contents of the CRSR_CFG register are described in Table 472. Table 472. Cursor Configuration register (CRSR_CFG, address 0x4000 8C04) bit description D R A R A FT D R FT D R R A FT D R R A F D R A A FT Bits Function Description Reset value A FT D R FT D 0 CrsrSize Cursor size selection. 0 = 32x32 pixel cursor. Allows for 4 defined cursors. 1 = 64x64 pixel cursor. 0x0 A FT D R A 1 FRAMESYNC Cursor frame synchronization type. 0 = Cursor coordinates are asynchronous. 1 = Cursor coordinates are synchronized to the frame synchronization pulse. 0x0 31:2 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - 23.6.18 Cursor Palette register 0 The cursor palette registers provide color palette information for the visible colors of the cursor. Color0 maps through CRSR_PAL0. The register provides 24-bit RGB values that are displayed according to the abilities of the LCD panel in the same way as the frame-buffers palette output is displayed. In monochrome STN mode, only the upper 4 bits of the Red field are used. In STN color mode, the upper 4 bits of the Red, Blue, and Green fields are used. In 24 bits per pixel mode, all 24 bits of the palette registers are significant. The contents of the CRSR_PAL0 register are described in Table 473. Table 473. Cursor Palette register 0 (CRSR_PAL0, address 0x4000 8C08) bit description Bits Function Description Reset value 7:0 15:8 23:16 31:24 RED GREEN BLUE - Red color component Green color component Blue color component. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0x0 0x0 0x0 - 23.6.19 Cursor Palette register 1 The cursor palette registers provide color palette information for the visible colors of the cursor. Color1 maps through CRSR_PAL1. The register provides 24-bit RGB values that are displayed according to the abilities of the LCD panel in the same way as the frame-buffers palette output is displayed. In monochrome STN mode, only the upper 4 bits of the Red field are used. In STN color mode, the upper 4 bits of the Red, Blue, and Green fields are used. In 24 bits per pixel mode, all 24 bits of the palette registers are significant. The contents of the CRSR_PAL1 register are described in Table 474. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 559 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 23: LPC18xx LCD FT D R R A Table 474. Cursor Palette register 1 (CRSR_PAL1, address 0x4000 8C0C) bit description D R A R A FT D R FT D R A R A A FT FT F Bits Function Description Reset value D D R R A A 7:0 15:8 23:16 31:24 RED GREEN BLUE - Red color component Green color component Blue color component. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0x0 0x0 0x0 - FT D R A FT D R A FT D 23.6.20 Cursor XY Position register The CRSR_XY register defines the distance of the top-left edge of the cursor from the top-left side of the cursor overlay. Refer to the section on Cursor Clipping for more details. If the FrameSync bit in the CRSR_CFG register is 0, the cursor position changes immediately, even if the cursor is currently being scanned. If Framesync is 1, the cursor position is only changed during the next vertical frame blanking period. The contents of the CRSR_XY register are described in Table 475. Table 475. Cursor XY Position register (CRSR_XY, address 0x4000 8C10) bit description Bits Function Description Reset value 9:0 15:10 25:16 31:26 CRSRX CRSRY - X ordinate of the cursor origin measured in pixels. When 0, the left edge of the cursor is at the left of the display. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Y ordinate of the cursor origin measured in pixels. When 0, the top edge of the cursor is at the top of the display. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0x0 0x0 - 23.6.21 Cursor Clip Position register The CRSR_CLIP register defines the distance from the top-left edge of the cursor image, to the first displayed pixel in the cursor image. Different synchronization rules apply to the Cursor Clip registers than apply to the cursor coordinates. If the FrameSync bit in the CRSR_CFG register is 0, the cursor clip point is changed immediately, even if the cursor is currently being scanned. If the Framesync bit in the CRSR_CFG register is 1, the displayed cursor image is only changed during the vertical frame blanking period, providing that the cursor position has been updated since the Clip register was programmed. When programming, the Clip register must be written before the Position register (ClcdCrsrXY) to ensure that in a given frame, the clip and position information is coherent. The contents of the CRSR_CLIP register are described in Table 476. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 560 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 23: LPC18xx LCD FT D R R A Table 476. Cursor Clip Position register (CRSR_CLIP, address 0x4000 8C14) bit description D R A R A FT D R FT D R A R A A FT FT F Bits Function Description Reset value D D R 5:0 CRSRCLIPX Cursor clip position for X direction. Distance from the left edge of the cursor image to the first displayed pixel in the cursor. When 0, the first pixel of the cursor line is displayed. 0x0 R A A FT D R A FT D FT D R A 7:6 13:8 CRSRCLIPY Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Cursor clip position for Y direction. Distance from the top of the cursor image to the first displayed pixel in the cursor. When 0, the first displayed pixel is from the top line of the cursor image. 0x0 31:14 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - 23.6.22 Cursor Interrupt Mask register The CRSR_INTMSK register is used to enable or disable the cursor from interrupting the processor. The contents of the CRSR_INTMSK register are described in Table 477. Table 477. Cursor Interrupt Mask register (CRSR_INTMSK, address 0x4000 8C20) bit description Bits Function Description Reset value 0 CRSRIM Cursor interrupt mask. When clear, the cursor never interrupts the processor. When set, the cursor interrupts the processor immediately after reading of the last word of cursor image. 0x0 31:1 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - 23.6.23 Cursor Interrupt Clear register The CRSR_INTCLR register is used by software to clear the cursor interrupt status and the cursor interrupt signal to the processor. The contents of the CRSR_INTCLR register are described in Table 478. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 561 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 23: LPC18xx LCD FT D R R A Table 478. Cursor Interrupt Clear register (CRSR_INTCLR, address 0x4000 8C24) bit description D R A R A FT D R FT D R A R A FT D A F FT D Bits Function Description Reset value R R A A FT D FT 0 CRSRIC Cursor interrupt clear. Writing a 0 to this bit has no effect. Writing a 1 to this bit causes the cursor interrupt status to be cleared. 0x0 D R A FT D R A 31:1 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - 23.6.24 Cursor Raw Interrupt Status register The CRSR_INTRAW register is set to indicate a cursor interrupt. When enabled via the CrsrIM bit in the CRSR_INTMSK register, provides the interrupt to the system interrupt controller. The contents of the CRSR_INTRAW register are described in Table 479. Table 479. Cursor Raw Interrupt Status register (CRSR_INTRAW, address 0x4000 8C28) bit description Bits Function Description Reset value 0 CRSRRIS Cursor raw interrupt status. The cursor interrupt status is set immediately after the last data is read from the cursor image for the current frame. This bit is cleared by writing to the CrsrIC bit in the CRSR_INTCLR register. 0x0 31:1 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - 23.6.25 Cursor Masked Interrupt Status register The CRSR_INTSTAT register is set to indicate a cursor interrupt providing that the interrupt is not masked in the CRSR_INTMSK register. The contents of the CRSR_INTSTAT register are described in Table 480. Table 480. Cursor Masked Interrupt Status register (CRSR_INTSTAT, address 0x4000 8C2C) bit description Bits Function Description Reset value 0 CRSRMIS Cursor masked interrupt status. The cursor interrupt status is set immediately after the last data read from the cursor image for the current frame, providing that the corresponding bit in the CRSR_INTMSK register is set. The bit remains clear if the CRSR_INTMSK register is clear. This bit is cleared by writing to the CRSR_INTCLR register. 0x0 31:1 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 562 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 23: LPC18xx LCD FT D R A D R A R A FT D R FT 23.7 LCD controller functional description D R The LCD controller performs translation of pixel-coded data into the required formats and timings to drive a variety of single or dual panel monochrome and color LCDs. R A FT D Packets of pixel coded data are fed using the AHB interface, to two independent, programmable, 32-bit wide, DMA FIFOs that act as input data flow buffers. The buffered pixel coded data is then unpacked using a pixel serializer. Depending on the LCD type and mode, the unpacked data can represent: R A FT D R A F D R A FT D FT D R A R A A FT • An actual true display gray or color value. • An address to a 256x16 bit wide palette RAM gray or color value. In the case of STN displays, either a value obtained from the addressed palette location, or the true value is passed to the gray scaling generators. The hardware-coded gray scale algorithm logic sequences the activity of the addressed pixels over a programmed number of frames to provide the effective display appearance. For TFT displays, either an addressed palette value or true color value is passed directly to the output display drivers, bypassing the gray scaling algorithmic logic. In addition to data formatting, the LCD controller provides a set of programmable display control signals, including: • • • • LCD panel power enable Pixel clock Horizontal and vertical synchronization pulses Display bias The LCD controller generates individual interrupts for: • • • • Upper or lower panel DMA FIFO underflow Base address update signification Vertical compare Bus error There is also a single combined interrupt that is asserted when any of the individual interrupts become active. Figure 53 shows a simplified block diagram of the LCD controller. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 563 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 23: LPC18xx LCD FT D R R A D R A R A FT D R FT D R A R A FT FT D R A D AHB slave interface Upper panel DMA FIFO Timing controller Panel clock generator LCD control signals LCD panel clock LCDCLKIN A F R A FT D FT D R A FT D R A AHB Bus AHB master interface Input FIFO control Pixel serializer RAM palette (128x32) Gray scaler Upper panel formatter Upper panel output FIFO Upper STN Lower panel DMA FIFO Lower panel formatter Lower panel output FIFO Lower STN Hardware Cursor STN/TFT data select LCD panel data FIFO underflow AHB error Interrupt generation Interrupt Fig 53. LCD controller block diagram 23.7.1 AHB interfaces The LCD controller includes two separate AHB interfaces. The first, an AHB slave interface, is used primarily by the CPU to access control and data registers within the LCD controller. The second, an AHB master interface, is used by the LCD controller for DMA access to display data stored in memory elsewhere in the system. The LCD DMA controller can access any SRAM on AHB and the external memory. 23.7.1.1 AMBA AHB slave interface The AHB slave interface connects the LCD controller to the AHB bus and provides CPU accesses to the registers and palette RAM. 23.7.1.2 AMBA AHB master interface The AHB master interface transfers display data from a selected slave (memory) to the LCD controller DMA FIFOs. It can be configured to obtain data from any on-chip SRAM on AHB, various types of off-chip static memory, or off-chip SDRAM. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 564 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 23: LPC18xx LCD FT D R R A In dual panel mode, the DMA FIFOs are filled up in an alternating fashion via a single DMA request. In single panel mode, the DMA FIFOs are filled up in a sequential fashion from a single DMA request. R A The inherent AHB master interface state machine performs the following functions: • Loads the upper panel base address into the AHB address incrementer on recognition of a new frame. • Monitors both the upper and lower DMA FIFO levels and asserts a DMA request to request display data from memory, filling them to above the programmed watermark. the DMA request is reasserted when there are at least four locations available in either FIFO (dual panel mode). • Checks for 1 kB boundaries during fixed-length bursts, appropriately adjusting the address in such occurrences. • Generates the address sequences for fixed-length and undefined bursts. • Controls the handshaking between the memory and DMA FIFOs. It inserts busy cycles if the FIFOs have not completed their synchronization and updating sequence. • Fills up the DMA FIFOs, in dual panel mode, in an alternating fashion from a single DMA request. • Asserts the a bus error interrupt if an error occurs during an active burst. • Responds to retry commands by restarting the failed access. This introduces some busy cycles while it re-synchronizes. D R A R A FT D R FT D R A A FT D R A R A FT F FT D R A FT D FT D D R A 23.7.2 Dual DMA FIFOs and associated control logic The pixel data accessed from memory is buffered by two DMA FIFOs that can be independently controlled to cover single and dual-panel LCD types. Each FIFO is 16 words deep by 64 bits wide and can be cascaded to form an effective 32-Dword deep FIFO in single panel mode. Synchronization logic transfers the pixel data from the AHB clock domain to the LCD controller clock domain. The water level marks in each FIFO are set such that each FIFO requests data when at least four locations become available. An interrupt signal is asserted if an attempt is made to read either of the two DMA FIFOs when they are empty (an underflow condition has occurred). 23.7.3 Pixel serializer This block reads the 32-bit wide LCD data from the output port of the DMA FIFO and extracts 24, 16, 8, 4, 2, or 1 bpp data, depending on the current mode of operation. The LCD controller supports big-endian, little-endian, and Windows CE data formats. Depending on the mode of operation, the extracted data can be used to point to a color or gray scale value in the palette RAM or can actually be a true color value that can be directly applied to an LCD panel input. Table 481 through Table 483 show the structure of the data in each DMA FIFO word corresponding to the endianness and bpp combinations. For each of the three supported data formats, the required data for each panel display pixel must be extracted from the data word. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 565 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 23: LPC18xx LCD FT D R Table 481. FIFO bits for Little-endian Byte, Little-endian Pixel order FIFO bit 1 bpp 2 bpp 4 bpp 8 bpp 16 bpp D R A R A FT D R FT D A R R A FT D R A F 24 bpp A FT D 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p31 p30 p29 p28 p27 p26 p25 p24 p23 p22 p21 p20 p19 p18 p17 p16 p15 p14 p13 p12 p11 p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 p0 R R A A p15 p7 p14 p3 p13 p6 p12 p1 p11 p5 p10 p2 p9 p4 p8 p7 p3 p6 p1 p5 p2 p4 p0 p3 p1 p2 p0 p1 p0 p0 FT D R A FT D R A p0 FT D All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 566 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 23: LPC18xx LCD FT D R A D R A R A FT D R FT D Table 482. FIFO bits for Big-endian Byte, Big-endian Pixel order FIFO bit 1 bpp 2 bpp 4 bpp 8 bpp 16 bpp R R A FT D R A F 24 bpp A FT D 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p0 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 p16 p17 p18 p19 p20 p21 p22 p23 p24 p25 p26 p27 p28 p29 p30 p31 R R A A p0 p0 p1 p0 p2 p1 p3 p0 p4 p2 p5 p1 p6 p3 p7 p8 p4 p9 p2 p10 p5 p11 p1 p12 p6 p13 p3 p14 p7 p15 FT D R A FT D R A p0 FT D All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 567 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 23: LPC18xx LCD FT D R Table 483. FIFO bits for Little-endian Byte, Big-endian Pixel order FIFO bit 1 bpp 2 bpp 4 bpp 8 bpp 16 bpp D R A R A FT D R FT D A R R A FT D R A F 24 bpp A FT D 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p24 p25 p26 p27 p28 p29 p30 p31 p16 p17 p18 p19 p20 p21 p22 p23 p8 p9 p10 p11 p12 p13 p14 p15 p0 p1 p2 p3 p4 p5 p6 p7 R R A A p12 p6 p13 p3 p14 p7 p15 p1 p8 p4 p9 p2 p10 p5 p11 p4 p2 p5 p1 p6 p3 p7 p0 p0 p0 p1 p0 p2 p1 p3 FT D R A FT D R A p0 FT D Table 484 shows the structure of the data in each DMA FIFO word in RGB mode. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 568 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 23: LPC18xx LCD FT D R A D R A R A FT D R FT D Table 484. RGB mode data formats FIFO data 24-bit RGB 16-bit (1:5:5:5 RGB) 16-bit (5:6:5 RGB) R 16-bit (4:4:4 RGB) R A FT D R A F D A FT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p0, Blue 7 p0, Blue 6 p0, Blue 5 p0, Blue 4 p0, Blue 3 p0, Blue 2 p0, Blue 1 p0, Blue 0 p0, Green 7 p0, Green 6 p0, Green 5 p0, Green 4 p0, Green 3 p0, Green 2 p0, Green 1 p0, Green 0 p0, Red 7 p0, Red 6 p0, Red 5 p0, Red 4 p0, Red 3 p0, Red 2 p0, Red 1 p0, Red 0 p1 intensity bit p1, Blue 4 p1, Blue 3 p1, Blue 2 p1, Blue 1 p1, Blue 0 p1, Green 4 p1, Green 3 p1, Green 2 p1, Green 1 p1, Green 0 p1, Red 4 p1, Red 3 p1, Red 2 p1, Red 1 p1, Red 0 p0 intensity bit p0, Blue 4 p0, Blue 3 p0, Blue 2 p0, Blue 1 p0, Blue 0 p0, Green 4 p0, Green 3 p0, Green 2 p0, Green 1 p0, Green 0 p0, Red 4 p0, Red 3 p0, Red 2 p0, Red 1 p0, Red 0 p1, Blue 4 p1, Blue 3 p1, Blue 2 p1, Blue 1 p1, Blue 0 p1, Green 5 p1, Green 4 p1, Green 3 p1, Green 2 p1, Green 1 p1, Green 0 p1, Red 4 p1, Red 3 p1, Red 2 p1, Red 1 p1, Red 0 p0, Blue 4 p0, Blue 3 p0, Blue 2 p0, Blue 1 p0, Blue 0 p0, Green 5 p0, Green 4 p0, Green 3 p0, Green 2 p0, Green 1 p0, Green 0 p0, Red 4 p0, Red 3 p0, Red 2 p0, Red 1 p0, Red 0 p1, Blue 3 p1, Blue 2 p1, Blue 1 p1, Blue 0 R R A FT D R A FT D A FT D R A p1, Green 3 p1, Green 2 p1, Green 1 p1, Green 0 p1, Red 3 p1, Red 2 p1, Red 1 p1, Red 0 p0, Blue 3 p0, Blue 2 p0, Blue 1 p0, Blue 0 p0, Green 3 p0, Green 2 p0, Green 1 p0, Green 0 p0, Red 3 p0, Red 2 p0, Red 1 p0, Red 0 23.7.4 RAM palette The RAM-based palette is a 256 x 16 bit dual-port RAM physically structured as 128 x 32 bits. Two entries can be written into the palette from a single word write access. The Least Significant Bit (LSB) of the serialized pixel data selects between upper and lower halves of the palette RAM. The half that is selected depends on the byte ordering mode. In little-endian mode, setting the LSB selects the upper half, but in big-endian mode, the lower half of the palette is selected. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 569 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 23: LPC18xx LCD FT D R A Pixel data values can be written and verified through the AHB slave interface. For information on the supported colors, refer to the section on the related panel type earlier in this chapter. R The palette RAM is a dual port RAM with independent controls and addresses for each port. Port1 is used as a read/write port and is connected to the AHB slave interface. The palette entries can be written and verified through this port. Port2 is used as a read-only port and is connected to the unpacker and gray scaler. For color modes of less than 16 bpp, the palette enables each pixel value to be mapped to a 16-bit color: • For TFT displays, the 16-bit value is passed directly to the pixel serializer. • For STN displays, the 16-bit value is first converted by the gray scaler. Table 485 shows the bit representation of the palette data. The palette 16-bit output uses the TFT 1:5:5:5 data format. In 16 and 24 bpp TFT mode, the palette is bypassed and the output of the pixel serializer is used as the TFT panel data. Table 485. Palette data storage for TFT modes. Bit(s) Name (RGB format) Description (RGB format) Name (BGR format) Description (BGR format) D R A R A FT D R FT D R R A A A FT D R A R A FT F FT D R A FT D FT D D R A 31 30:26 25:21 20:16 15 14:10 9:5 4:0 I B[4:0] G[4:0] R[4:0] I B[4:0] G[4:0] R[4:0] Intensity / unused Blue palette data Green palette data Red palette data Intensity / unused Blue palette data Green palette data Red palette data I R[4:0] G[4:0] B[4:0] I R[4:0] G[4:0] B[4:0] Intensity / unused Red palette data Green palette data Blue palette data Intensity / unused Red palette data Green palette data Blue palette data The red and blue pixel data can be swapped to support BGR data format using a control register bit (bit 8 = BGR). See the CTRL register description for more information. Table 486 shows the bit representation of the palette data for the STN color modes. Table 486. Palette data storage for STN color modes. Bit(s) Name (RGB format) Description (RGB format) Name (BGR format) Description (BGR format) 31 30:27 26 25:22 21 20:17 16 15 14:11 10 9:6 B[3:0] G[3:0] R[3:0] I B[4:1] B[0] G[4:1] Unused Blue palette data Unused Green palette data Unused Red palette data Unused Unused Blue palette data Unused Green palette data R[3:0] G[3:0] B[3:0] I R[4:1] R[0] G[4:1] Unused Red palette data Unused Green palette data Unused Blue palette data Unused Unused Red palette data Unused Green palette data All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 570 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 23: LPC18xx LCD FT D R A D R A R A FT D R FT Table 486. Palette data storage for STN color modes. Bit(s) Name (RGB format) Description (RGB format) Name (BGR format) D R Description (BGR format) R A FT D R R A F D R A FT A FT A FT 5 4:1 0 G[0] R[4:1] R[0] Unused Red palette data Unused G[0] B[4:1] B[0] Unused Blue palette data Unused D For monochrome STN mode, only the red palette field bits [4:1] are used. However, in STN color mode the green and blue [4:1] are also used. Only 4 bits per color are used, because the gray scaler only supports 16 different shades per color. Table 487 shows the bit representation of the palette data for the STN monochrome mode. Table 487. Palette data storage for STN monochrome mode. Bit(s) Name Description D R A FT D R A 31 30:27 26 25:22 21 20:17 16 15 14:11 10 9:6 5 4:1 0 Y[3:0] Y[3:0] - Unused Unused Unused Unused Unused Intensity data Unused Unused Unused Unused Unused Unused Intensity data Unused 23.7.5 Hardware cursor The hardware cursor is an integral part of the LCD controller. It uses the LCD timing module to provide an indication of the current scan position coordinate, and intercepts the pixel stream between the palette logic and the gray scale/output multiplexer. All cursor programming registers are accessed through the LCD slave interface. This also provides a read/write port to the cursor image RAM. 23.7.5.1 Cursor operation The hardware cursor is contained in a dual port RAM. It is programmed by software through the AHB slave interface. The AHB slave interface also provides access to the hardware cursor control registers. These registers enable you to modify the cursor position and perform various other functions. When enabled, the hardware cursor uses the horizontal and vertical synchronization signals, along with a pixel clock enable and various display parameters to calculate the current scan coordinate. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 571 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 23: LPC18xx LCD FT D R R A When the display point is inside the bounds of the cursor image, the cursor replaces frame buffer pixels with cursor pixels. A FT D R When the last cursor pixel is displayed, an interrupt is generated that software can use as an indication that it is safe to modify the cursor image. This enables software controlled animations to be performed without flickering for frame synchronized cursors. A FT D D R A R A FT D R FT D R A F R A FT D FT D D R A FT R A 23.7.5.2 Cursor sizes Two cursor sizes are supported, as shown in Table 488. Table 488. Palette data storage for STN monochrome mode. X Pixels Y Pixels Bits per pixel Words per line Words in cursor image R A 32 64 32 64 2 2 2 4 64 256 23.7.5.3 Cursor movement The following descriptions assume that both the screen and cursor origins are at the top left of the visible screen (the first visible pixel scanned each frame). Figure 54 shows how each pixel coordinate is assumed to be the top left corner of the pixel. (0,0) CRSR_XY(X) Fig 54. Cursor movement 23.7.5.4 Cursor XY positioning The CRSR_XY register controls the cursor position on the cursor overlay (see Cursor XY Position register). This provides separate fields for X and Y ordinates. The CRSR_CFG register (see Cursor Configuration register) provides a FrameSync bit controlling the visible behavior of the cursor. CRSR_XY(Y) All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 572 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 23: LPC18xx LCD FT D R R A With FrameSync inactive, the cursor responds immediately to any change in the programmed CRSR_XY value. Some transient smearing effects may be visible if the cursor is moved across the LCD scan line. With FrameSync active, the cursor only updates its position after a vertical synchronization has occurred. This provides clean cursor movement, but the cursor position only updates once a frame. A FT D R D R A R A FT D R FT D R A F R A FT D FT D R A D R A FT D R A A FT 23.7.5.5 Cursor clipping The CRSR_XY register (see Cursor XY Position register) is programmed with positive binary values that enable the cursor image to be located anywhere on the visible screen image. The cursor image is clipped automatically at the screen limits when it extends beyond the screen image to the right or bottom (see X1,Y1 in Figure 55). The checked pattern shows the visible portion of the cursor. Because the CRSR_XY register values are positive integers, to emulate cursor clipping on the left and top of screen, a Clip Position register, CRSR_CLIP, is provided. This controls which point of the cursor image is positioned at the CRSR_CLIP coordinate. For clipping functions on the Y axis, CRSR_XY(X) is zero, and Clip(X) is programmed to provide the offset into the cursor image (X2 and X3). The equivalent function is provided to clip on the X axis at the top of the display (Y2). For cursors that are not clipped at the X=0 or Y=0 lines, program the Clip Position register X and Y fields with zero to display the cursor correctly. See Clip(X4,Y4) for the effect of incorrect programming. Clip(X2) Clip(Y2) Cursor(Y5) Cursor(X5) Clip(X3) Clip(X4) Cursor(X1) Fig 55. Cursor clipping All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 Cursor(Y1) Clip(Y4) 573 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 23: LPC18xx LCD FT D R A D R A R A FT D R FT 23.7.5.6 Cursor image format D R The LCD frame buffer supports three packing formats, but the hardware cursor image requirement has been simplified to support only LBBP. This is little-endian byte, big-endian pixel for Windows CE mode. FT D R A The Image RAM start address is offset by 0x800 from the LCD base address, as shown in the register description in this chapter. The displayed cursor coordinate system is expressed in terms of (X,Y). 64 x 64 is an extension of the 32 x 32 format shown in Figure 56. R A R A F D R A FT D R A FT D R A A FT D FT TOP (0, 0) (1, 0) (2, 0) (29, 0) (30, 0) (31, 0) (0, 1) (1, 1) (2, 1) (29, 1) (30, 1) (31, 1) (0, 2) (1, 2) (2, 2) (29, 2) (30, 2) (31, 2) LEFT RIGHT (0, 29) (1, 29) (2, 29) (29, 29) (30, 29) (31, 29) (0, 30) (1, 30) (2, 30) (29, 30) (30, 30) (31, 30) (0, 31) (1, 31) (2, 31) BOTTOM (29, 31) (30, 31) (31, 31) Fig 56. Cursor image format 32 by 32 pixel format Four cursors are held in memory, each with the same pixel format. Table 489 lists the base addresses for the four cursors. Table 489. Addresses for 32 x 32 cursors Address Description 0x4000 8800 0x4000 8900 0x4000 8A00 0x4000 8B00 Cursor 0 start address. Cursor 1 start address. Cursor 2 start address. Cursor 3 start address. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 574 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 23: LPC18xx LCD FT D R A D R A Offset into cursor memory R A FT D R FT Table 490 shows the buffer to pixel mapping for Cursor 0. Table 490. Buffer to pixel mapping for 32 x 32 pixel cursor format Data bits 0 4 (8 * y) (8 * y) +4 F8 D R R A FT D R R A F D R A FT A FT FC A FT D R A D 31:30 29:28 27:26 25:24 23:22 21:20 19:18 17:16 15:14 13:12 11:10 9:8 7:6 5:4 3:2 1:0 (12, 0) (13, 0) (14, 0) (15, 0) (8, 0) (9, 0) (10, 0) (11, 0) (4, 0) (5, 0) (6, 0) (7, 0) (0, 0) (1, 0) (2, 0) (3, 0) (28, 0) (29, 0) (30, 0) (31, 0) (24, 0) (25, 0) (26, 0) (27, 0) (20, 0) (21, 0) (22, 0) (23, 0) (16, 0) (17, 0) (18, 0) (19, 0) (12, y) (13, y) (14, y) (15, y) (8, y) (9, y) (10, y) (11, y) (4, y) (5, y) (6, y) (7, y) (0, y) (1, y) (2, y) (3, y) (28, y) (29, y) (30, y) (31, y) (24, y) (25, y) (26, y) (27, y) (20, y) (21, y) (22, y) (23, y) (16, y) (17, y) (18, y) (19, y) (12, 31) (13, 31) (14, 31) (15, 31) (8, 31) (9, 31) (10, 31) (11, 31) (4, 31) (5, 31) (6, 31) (7, 31) (0, 31) (1, 31) (2, 31) (3, 31) (28,31) (29, 31) (30, 31) (31, 31) (24, 31) (25, 31) (26, 31) (27, 31) (20, 31) (21, 31) (22, 31) (23, 31) (16, 31) (17, 31) (18, 31) (19, 31) FT D R A 64 by 64 pixel format Only one cursor fits in the memory space in 64 x 64 mode. Table 491 shows the 64 x 64 cursor format. Table 491. Buffer to pixel mapping for 64 x 64 pixel cursor format Offset into cursor memory Data bits 0 4 8 12 (16 * y) (16 * y) +4 (16 * y) + 8 (16 * y) + 12 FC 31:30 29:28 27:26 25:24 23:22 21:20 19:18 17:16 15:14 13:12 11:10 9:8 7:6 (12, 0) (13, 0) (14, 0) (15, 0) (8, 0) (9, 0) (10, 0) (11, 0) (4, 0) (5, 0) (6, 0) (7, 0) (0, 0) (28, 0) (29, 0) (30, 0) (31, 0) (24, 0) (25, 0) (26, 0) (27, 0) (20, 0) (21, 0) (22, 0) (23, 0) (16, 0) (44, 0) (45, 0) (46, 0) (47, 0) (40, 0) (41, 0) (42, 0) (43, 0) (36, 0) (37, 0) (38, 0) (39, 0) (32, 0) (60, 0) (61, 0) (62, 0) (63, 0) (56, 0) (57, 0) (58, 0) (59, 0) (52, 0) (53, 0) (54, 0) (55, 0) (48, 0) (12, y) (13, y) (14, y) (15, y) (8, y) (9, y) (10, y) (11, y) (4, y) (5, y) (6, y) (7, y) (0, y) (28, y) (29, y) (30, y) (31, y) (24, y) (25, y) (26, y) (27, y) (20, y) (21, y) (22, y) (23, y) (16, y) (44, y) (45, y) (46, y) (47, y) (40, y) (41, y) (42, y) (43, y) (36, y) (37, y) (38, y) (39, y) (32, y) (60, y) (61, y) (62, y) (63, y) (56, y) (57, y) (58, y) (59, y) (52, y) (53, y) (54, y) (55, y) (48, y) (60, 63) (61, 63) (62, 63) (63, 63) (56, 63) (57, 63) (58, 63) (59, 63) (52, 63) (53, 63) (54, 63) (55, 63) (48, 63) All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 575 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 23: LPC18xx LCD FT D R A D R A R A FT D R FT Table 491. Buffer to pixel mapping for 64 x 64 pixel cursor format Offset into cursor memory Data bits 0 4 8 12 (16 * y) (16 * y) +4 (16 * y) + 8 D R (16 * y) + 12 R A FT D R R A F D R A FT A FT FC A FT 5:4 3:2 1:0 (1, 0) (2, 0) (3, 0) (17, 0) (18, 0) (19, 0) (33, 0) (34, 0) (35, 0) (49, 0) (50, 0) (51, 0) (1, y) (2, y) (3, y) (17, y) (18, y) (19, y) (33, y) (34, y) (35, y) (49, y) (50, y) (51, y) (49, 63) (50, 63) (51, 63) D D R A FT D R A Cursor pixel encoding Each pixel of the cursor requires two bits of information. These are interpreted as Color0, Color1, Transparent, and Transparent inverted. In the coding scheme, bit 1 selects between color and transparent (AND mask) and bit 0 selects variant (XOR mask). Table 492 shows the pixel encoding bit assignments. Table 492. Pixel encoding Value Description 00 Color0. The cursor color is displayed according to the Red-Green-Blue (RGB) value programmed into the CRSR_PAL0 register. 01 Color1. The cursor color is displayed according to the RGB value programmed into the CRSR_PAL1 register. 10 Transparent. The cursor pixel is transparent, so is displayed unchanged. This enables the visible cursor to assume shapes that are not square. 11 Transparent inverted. The cursor pixel assumes the complementary color of the frame pixel that is displayed. This can be used to ensure that the cursor is visible regardless of the color of the frame buffer image. 23.7.6 Gray scaler A patented gray scale algorithm drives monochrome and color STN panels. This provides 15 gray scales for monochrome displays. For STN color displays, the three color components (RGB) are gray scaled simultaneously. This results in 3375 (15x15x15) colors being available. The gray scaler transforms each 4-bit gray value into a sequence of activity-per-pixel over several frames, relying to some degree on the display characteristics, to give the representation of gray scales and color. 23.7.7 Upper and lower panel formatters Formatters are used in STN mode to convert the gray scaler output to a parallel format as required by the display. For monochrome displays, this is either 4 or 8 bits wide, and for color displays, it is 8 bits wide. Table 493 shows a color display driven with 2 2/3 pixels worth of data in a repeating sequence. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 576 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 23: LPC18xx LCD FT D R A D R A R A FT D R FT D Table 493. Color display driven with 2 2/3 pixel data Byte CLD[7] CLD[6] CLD[5] CLD[4] CLD[3] CLD[2] CLD[1] R R A CLD[0] R A F A FT D D FT 0 1 2 P2[Green] P5[Red] P7[Blue] P2[Red] P4q[Blue] P7[Green] P1[Blue] P4[Green] P7[Red] P1[Green] P4[Red] P6[Blue] P1[Red] P3[Blue] P6[Green] P0[Blue] P3[Green] P6[Red] P0[Green] P3[Red] P5[Blue] P0[Red] R P2[Blue] P5[Green] Each formatter consists of three 3-bit (RGB) shift left registers. RGB pixel data bit values from the gray scaler are concurrently shifted into the respective registers. When enough data is available, a byte is constructed by multiplexing the registered data to the correct bit position to satisfy the RGB data pattern of LCD panel. The byte is transferred to the 3-byte FIFO, which has enough space to store eight color pixels. R A A FT D R A FT D FT D R A 23.7.8 Panel clock generator The output of the panel clock generator block is the panel clock, pin LCDDCLK. The panel clock can be based on either the peripheral clock for the LCD block or the external clock input for the LCD, pin LCDCLKIN. Whichever source is selected can be divided down in order to produce the internal LCD clock, LCDCLK. The panel clock generator can be programmed to output the LCD panel clock in the range of LCDCLK/2 to LCDCLK/1025 to match the bpp data rate of the LCD panel being used. The CLKSEL bit in the POL register determines whether the base clock used is CCLK or the LCDCLKIN pin. 23.7.9 Timing controller The primary function of the timing controller block is to generate the horizontal and vertical timing panel signals. It also provides the panel bias and enable signals. These timings are all register-programmable. 23.7.10 STN and TFT data select Support is provided for passive Super Twisted Nematic (STN) and active Thin Film Transistor (TFT) LCD display types: 23.7.10.1 STN displays STN display panels require algorithmic pixel pattern generation to provide pseudo gray scaling on monochrome displays, or color creation on color displays. 23.7.10.2 TFT displays TFT display panels require the digital color value of each pixel to be applied to the display data inputs. 23.7.11 Interrupt generation Four interrupts are generated by the LCD controller, and a single combined interrupt. The four interrupts are: • Master bus error interrupt. • Vertical compare interrupt. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 577 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 23: LPC18xx LCD FT D R A D R A R A FT D R FT • Next base address update interrupt. • FIFO underflow interrupt. D R Each of the four individual maskable interrupts is enabled or disabled by changing the mask bits in the INT_MSK register. These interrupts are also combined into a single overall interrupt, which is asserted if any of the individual interrupts are both asserted and unmasked. Provision of individual outputs in addition to a combined interrupt output enables use of either a global interrupt service routine, or modular device drivers to handle interrupts. The status of the individual interrupt sources can be read from the INTRAW register. A FT D R A FT D R R A F D R A FT D FT D R A R A A FT 23.7.11.1 Master bus error interrupt The master bus error interrupt is asserted when an ERROR response is received by the master interface during a transaction with a slave. When such an error is encountered, the master interface enters an error state and remains in this state until clearance of the error has been signaled to it. When the respective interrupt service routine is complete, the master bus error interrupt may be cleared by writing a 1 to the BERIC bit in the INTCLR register. This action releases the master interface from its ERROR state to the start of FRAME state, and enables fresh frame of data display to be initiated. 23.7.11.2 Vertical compare interrupt The vertical compare interrupt asserts when one of four vertical display regions, selected using the CTRL register, is reached. The interrupt can be made to occur at the start of: • • • • Vertical synchronization. Back porch. Active video. Front porch. The interrupt may be cleared by writing a 1 to the VcompIC bit in the INTCLR register. 23.7.11.2.1 Next base address update interrupt The LCD next base address update interrupt asserts when either the LCDUPBASE or LCDLPBASE values have been transferred to the LCDUPCURR or LCDLPCURR incrementers respectively. This signals to the system that it is safe to update the LCDUPBASE or the LCDLPBASE registers with new frame base addresses if required. The interrupt can be cleared by writing a 1 to the LNBUIC bit in the INTCLR register 23.7.11.2.2 FIFO underflow interrupt The FIFO underflow interrupt asserts when internal data is requested from an empty DMA FIFO. Internally, upper and lower panel DMA FIFO underflow interrupt signals are generated. The interrupt can be cleared by writing a 1 to the FUFIC bit in the INTCLR register. 23.7.12 LCD power-up and power-down sequence The LCD controller requires the following power-up sequence to be performed: All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 578 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 23: LPC18xx LCD FT D R A D R A R A FT D R FT 1. When power is applied, the following signals are held LOW: D R R A FT R A F A FT • • • • • • LCDLP LCDDCLK LCDFP LCDENAB/ LCDM LCDVD[23:0] LCDLE D 2. When LCD power is stabilized, a 1 is written to the LcdEn bit in the CTRL register. This enables the following signals into their active states: D R A FT D R A FT D A FT D R A R • • • • • LCDLP LCDDCLK LCDFP LCDENAB/ LCDM LCDLE The LCDV[23:0] signals remain in an inactive state. 3. When the signals in step 2 have stabilized, the contrast voltage (not controlled or supplied by the LCD controller) is applied to the LCD panel. 4. If required, a software or hardware timer can be used to provide the minimum display specific delay time between application of the control signals and power to the panel display. On completion of the time interval, power is applied to the panel by writing a 1 to the LcdPwr bit within the CTRL register that, in turn, sets the LCDPWR signal high and enables the LCDV[23:0] signals into their active states. The LCDPWR signal is intended to be used to gate the power to the LCD panel. The power-down sequence is the reverse of the above four steps and must be strictly followed, this time, writing the respective register bits with 0. Figure 57 shows the power-up and power-down sequences. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 579 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 23: LPC18xx LCD FT D R R A D R A R A FT D R FT D R A R A FT FT D D A F LCD on sequence Minimum 0 ms LCD Power Minimum 0 ms LCDLP, LCDCP, LCDFP, LCDAC, LCDLE Contrast Voltage LCDPWR, LCD[23:0] LCD off sequence Minimum 0 ms Minimum 0 ms R R A FT D R A FT D A FT D R A Display specific delay Display specific delay Fig 57. Power-up and power-down sequences All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 580 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 23: LPC18xx LCD FT D R A D R A R A FT D R FT 23.8 LCD timing diagrams one horizontal line D R R A FT D R R A F D R A FT A FT A FT D R A D FT pixel clock (internal) LCD_TIMH (HSW) LCDLP (line synch pulse) suppressed during LCDLP D R A LCDDCLK (panel clock) LCD_TIMH (HBP) 16  LCD_TIMH(PPL)  1 LCD_TIMH (HFP) horizontal back porch (defined in pixel clocks) LCDVD[15:0] (panel data) one horizontal line of LCD data horizontal front porch (defined in pixel clocks) (1) The active data lines will vary with the type of STN panel (4-bit, 8-bit, color, mono) and with single or dual frames. (2) The LCD panel clock is selected and scaled by the LCD controller and used to produce LCDCLK. (3) The duration of the LCDLP signal is controlled by the HSW field in the TIMH register. (4) The Polarity of the LCDLP signal is determined by the IHS bit in the POL register. Fig 58. Horizontal timing for STN displays All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 581 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 23: LPC18xx LCD FT D R R A D R A R A FT D R FT D R A R A FT FT A F one frame D D R A R A FT LCDDCLK (panel clock) FT panel data clock active D D R A FT D LCD_TIMV (VSW) LCDFP (vertical synch pulse) LCD_TIMV (VBP) LCD_TIMV(LPP) LCD_TIMV (VFP) R A back porch (defined in line clocks) all horizontal lines for one frame front porch (defined in line clocks) pixel data and horizontal controls for one frame see horizontal timing for STN displays (1) Signal polarities may vary for some displays. Fig 59. Vertical timing for STN displays one horizontal line pixel clock (internal) LCD_TIMH (HSW) LCDLP (lhorizontal synch pulse) LCDDCLK (panel clock) LCD_TIMH (HBP) LCD_TIMH(PPL) LCD_TIMH (HFP) LCDENAB horizontal back porch (defined in pixel clocks) LCDVD[23:0] (panel data) one horizontal line of LCD data horizontal front porch (defined in pixel clocks) (1) The active data lines will vary with the type of TFT panel. (2) The LCD panel clock is selected and scaled by the LCD controller and used to produce LCDCLK. (3) The duration of the LCDLP is controlled by the HSW field in the TIMH register. (4) The polarity of the LCDLP signal is determined by the IHS bit in the POL register. Fig 60. Horizontal timing for TFT displays All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 582 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 23: LPC18xx LCD FT D R R A D R A R A FT D R FT D R A R A FT FT A F one frame D D R A FT R A FT LCDDCLK (panel clock) panel data clock active D D R A FT D LCDENA (data enable) R data enable A LCD_TIMV (VSW) LCDFP (vertical synch pulse) LCD_TIMV (VBP) LCD_TIMV(LPP) LCD_TIMV (VFP) back porch (defined in line clocks) all horizontal lines for one frame front porch (defined in line clocks) pixel data and horizontal control signals for one frame see horizontal timing for TFT displays (1) Polarities may vary for some displays. Fig 61. Vertical timing for TFT displays 23.9 LCD panel signal usage Table 494. LCD panel connections for STN single panel mode External pin 4-bit mono STN single panel LPC18xx pin used LCD function 8-bit mono STN single panel LPC18xx pin used LCD function Color STN single panel LPC18xx pin used LCD function LCDVD23 LCDVD22 LCDVD21 LCDVD20 LCDVD19 LCDVD18 LCDVD17 LCDVD16 LCDVD15 LCDVD14 LCDVD13 LCDVD12 LCDVD11 LCDVD10 LCDVD9 - - - - - © NXP B.V. 2011. All rights reserved. All information provided in this document is subject to legal disclaimers. User manual Rev. 00.13 — 20 July 2011 583 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 23: LPC18xx LCD FT D R A D R A R A FT D R FT Table 494. LCD panel connections for STN single panel mode External pin 4-bit mono STN single panel LPC18xx pin used LCD function 8-bit mono STN single panel LPC18xx pin used LCD function LPC18xx pin used D R Color STN single panel LCD function R A FT D R R A F D R A FT D A FT A FT D LCDVD8 LCDVD7 LCDVD6 LCDVD5 LCDVD4 LCDVD3 LCDVD2 LCDVD1 LCDVD0 LCDLP LCDENAB/ LCDM LCDFP LCDDCLK LCDLE LCDPWR GP_CLKIN P4_2 P4_3 P4_4 P4_1 P7_6 P4_6 P4_5 P4_7 P7_0 P7_7 PF_4 UD[3] UD[2] UD[1] UD[0] LCDLP LCDENAB/ LCDM LCDFP LCDDCLK LCDLE CDPWR LCDCLKIN P8_4 P8_5 P8_6 P8_7 P4_2 P4_3 P4_4 P4_1 P7_6 P4_6 P4_5 P4_7 P7_0 P7_7 PF_4 UD[7] UD[6] UD[5] UD[4] UD[3] UD[2] UD[1] UD[0] LCDLP LCDENAB/ LCDM LCDFP LCDDCLK LCDLE LCDPWR LCDCLKIN P8_4 P8_5 P8_6 P8_7 P4_2 P4_3 P4_4 P4_1 P7_6 P4_6 P4_5 P4_7 P7_0 P7_7 PF_4 UD[7] UD[6] UD[5] UD[4] UD[3] UD[2] UD[1] UD[0] LCDLP LCDENAB/ LCDM LCDFP LCDDCLK LCDLE LCDPWR LCDCLKIN R A FT D R A Table 495. LCD panel connections for STN dual panel mode External pin 4-bit mono STN dual panel LPC18xx pin used LCD function 8-bit mono STN dual panel LPC18xx pin used LCD function Color STN dual panel LPC18xx pin used LCD function LCDVD23 LCDVD22 LCDVD21 LCDVD20 LCDVD19 LCDVD18 LCDVD17 LCDVD16 LCDVD15 LCDVD14 LCDVD13 LCDVD12 LCDVD11 LCDVD10 LCDVD9 LCDVD8 LCDVD7 LCDVD6 P4_9 P4_10 P4_8 P7_5 - LD[3] LD[2] LD[1] LD[0] - PB_4 PB_5 PB_6 P8_3 P4_9 P4_10 P4_8 P7_5 P8_5 LD[7] LD[6] LD[5] LD[4] LD[3] LD[2] LD[1] LD[0] UD[7] UD[6] PB_4 PB_5 PB_6 P8_3 P4_9 P4_10 P4_8 P7_5 P8_4 P8_5 LD[7] LD[6] LD[5] LD[4] LD[3] LD[2] LD[1] LD[0] UD[7] UD[6] © NXP B.V. 2011. All rights reserved. All information provided in this document is subject to legal disclaimers. User manual Rev. 00.13 — 20 July 2011 584 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 23: LPC18xx LCD FT D R A D R A R A FT D R FT Table 495. LCD panel connections for STN dual panel mode External pin 4-bit mono STN dual panel LPC18xx pin used LCD function 8-bit mono STN dual panel LPC18xx pin used LCD function LPC18xx pin used D R Color STN dual panel LCD function R A FT D R R A F D R A FT D A FT A FT D LCDVD5 LCDVD4 LCDVD3 LCDVD2 LCDVD1 LCDVD0 LCDLP LCDENAB/ LCDM LCDFP LCDDCLK LCDLE LCDPWR GP_CLKIN P4_2 P4_3 P4_4 P4_1 P7_6 P4_6 P4_5 P4_7 P7_0 P7_7 PF_4 UD[3] UD[2] UD[1] UD[0] LCDLP LCDENAB/ LCDM LCDFP LCDDCLK LCDLE LCDPWR LCDCLKIN P8_6 P8_7 P4_2 P4_3 P4_4 P4_1 P7_6 P4_6 P4_5 P4_7 P7_0 P7_7 PF_4 UD[5] UD[4] UD[3] UD[2] UD[1] UD[0] LCDLP LCDENAB/ LCDM LCDFP LCDDCLK LCDLE LCDPWR LCDCLKIN P8_6 P8_7 P4_2 P4_3 P4_4 P4_1 P7_6 P4_6 P4_5 P4_7 P7_0 P7_7 PF_4 UD[5] UD[4] UD[3] UD[2] UD[1] UD[0] LCDLP LCDENAB/ LCDM LCDFP LCDDCLK LCDLE LCDPWR LCDCLKIN R A FT D R A Table 496. LCD panel connections for TFT panels External pin TFT 12 bit (4:4:4 mode) TFT 16 bit (5:6:5 mode) LPC18xx pin used LCD function LPC18xx pin used LCD function TFT 16 bit (1:5:5:5 mode) TFT 24 bit LPC18xx pin LCD used function LPC18xx pin used LCD function LCDVD23 LCDVD22 LCDVD21 LCDVD20 LCDVD19 LCDVD18 LCDVD17 LCDVD16 LCDVD15 LCDVD14 LCDVD13 LCDVD12 LCDVD11 LCDVD10 LCDVD9 LCDVD8 LCDVD7 LCDVD6 LCDVD5 LCDVD4 PB_0 PB_1 PB_2 PB_3 PB_4 PB_5 PB_6 P8_3 P8_4 P8_5 P8_6 P8_7 BLUE3 BLUE2 BLUE1 BLUE0 GREEN3 GREEN2 GREEN1 GREEN0 RED3 RED2 RED1 RED0 PB_0 PB_1 PB_2 PB_3 P7_1 PB_4 PB_5 PB_6 P8_3 P4_9 P4_10 P8_4 P8_5 P8_6 P8_7 BLUE4 BLUE3 BLUE2 BLUE1 BLUE0 GREEN5 GREEN4 GREEN3 GREEN2 GREEN1 GREEN0 RED4 RED3 RED2 RED1 PB_0 PB_1 PB_2 PB_3 P7_1 P7_2 PB_4 PB_5 PB_6 P8_3 P4_9 P4_10 P8_4 P8_5 P8_6 P8_7 BLUE4 BLUE3 BLUE2 BLUE1 BLUE0 intensity GREEN4 GREEN3 GREEN2 GREEN1 GREEN0 intensity RED4 RED3 RED2 RED1 P7_3 P7_4 PB_4 PB_5 PB_6 P8_3 P4_9 P4_10 P4_8 P7_5 P8_4 P8_5 P8_6 P8_7 BLUE7 BLUE6 BLUE5 BLUE4 BLUE3 BLUE2 BLUE1 BLUE0 GREEN7 GREEN6 GREEN5 GREEN4 GREEN3 GREEN2 GREEN1 GREEN0 RED7 RED6 RED5 RED4 © NXP B.V. 2011. All rights reserved. All information provided in this document is subject to legal disclaimers. User manual Rev. 00.13 — 20 July 2011 585 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 23: LPC18xx LCD FT D R A D R A R A FT D R FT Table 496. LCD panel connections for TFT panels External pin TFT 12 bit (4:4:4 mode) TFT 16 bit (5:6:5 mode) LPC18xx pin used LCD function LPC18xx pin used LCD function TFT 16 bit (1:5:5:5 mode) TFT 24 bit LPC18xx pin LCD used function LPC18xx pin used D R R A FT D R R A F D R A FT A FT A FT D R A LCD function D LCDVD3 LCDVD2 LCDVD1 LCDVD0 LCDLP P7_6 LCDLP P4_2 P7_6 RED0 LCDLP LCDENAB/ LCDM LCDFP LCDDCLK LCDLE LCDPWR LCDCLKIN P4_2 P4_3 P7_6 P4_6 P4_5 P4_7 P7_0 P7_7 PF_4 RED0 intensity LCDLP P4_2 P4_3 P4_4 P4_1 P7_6 RED3 RED2 RED1 RED0 LCDLP LCDENAB/L CDM LCDFP LCDDCLK LCDLE LCDPWR LCDCLKIN FT D R A LCDENAB/ P4_6 LCDM LCDFP LCDDCLK LCDLE LCDPWR P4_5 P4_7 P7_0 P7_7 LCDENAB/ P4_6 LCDM LCDFP LCDDCLK LCDLE LCDPWR P4_5 P4_7 P7_0 P7_7 LCDENAB/ P4_6 LCDM LCDFP LCDDCLK LCDLE LCDPWR P4_5 P4_7 P7_0 P7_7 GP_CLKIN PF_4 LCDCLKIN PF_4 LCDCLKIN PF_4 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 586 of 1164 D R A FT D R A FT D R A FT D R A FT D R A FT UM10430 Rev. 00.13 — 20 July 2011 D D Chapter 24: LPC18xx State Configurable Timer (SCT) D R A FT D D R A FT D R A FT D R A FT D R FT D R A R A FT D A FT R A R A FT D R A FT D R A F R A FT D FT R User manual 24.1 How to read this chapter The SCT is available on all LPC18xx parts. The following configuration options apply to parts LPC1850_30_20_10 Rev ‘A’ only: D • The SCT inputs and outputs are connected to event-driven peripherals through the GIMA (see Section 14.3). D R A FT D R A 24.2 Basic configuration The SCT is configured as follows: • • • • See Table 497 for clocking and power control. The SCT is reset by the SCT_RST (reset #37). Connect inputs and outputs of the SCT through the GIMA (see Chapter 14). The SCT combined interrupt is connected to slot # 10 in the NVIC. SCT outputs 2, 6, 14 are ORed with timer match channels and connected to slots # 13, 14, 16 in the Event router (see Table 16). the CREG block (see Table 35) and enable the GPDMA channel in the DMA Channel Configuration registers Section 16.6.20. • For connecting the SCT outputs 0 and 1 to the GPDMA, use the DMAMUX register in Table 497. SCT clocking and power control Base clock Branch clock Maximum frequency SCT BASE_M3_CLK CLK_M3_SCT 150 MHz 24.3 Features • • • • • Two 16-bit counters or one 32-bit counter. Counter(s) clocked by bus clock or selected input. Up counter(s) or up-down counter(s). State variable allows sequencing across multiple counter cycles. Event can be defined by a counter match condition, an input (or output) condition, a combination of a match and/or and input/output condition in a specified state. • Events control outputs, interrupts, and DMA requests. • Selected event(s) can limit, halt, start, or stop a counter. • Supports: – 8 inputs – 16 outputs – 16 match/capture registers – 16 events All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 587 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 24: LPC18xx State Configurable Timer (SCT) FT D R A D R A R A FT D R FT – 32 states D R R A FT D R A F D A FT 24.4 General description R The State Configurable Timer (SCT) allows a wide variety of timing, counting, output modulation, and input capture operations. The most basic user-programmable option is whether a SCT operates as two 16-bit counters or a unified 32-bit counter. In the two-counter case, in addition to the counter value the following operational elements are independent for each half: R A FT D R A FT D A FT D R A • State variable • Limit, halt, stop, and start conditions • Values of Match/Capture registers, plus reload or capture control values In the two-counter case, the following operational elements are global to the SCT, but events, outputs, interrupts, and DMA requests can use match conditions from either counter: • • • • • • Clock selection Inputs Events Outputs Interrupts DMA requests Remark: This document uses the term “bus error” to indicate a SCT response that makes the processor take an exception. CLK_M3_SCT SCT clock prescaler(s) Fig 62. SCT block diagram All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 588 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 24: LPC18xx State Configurable Timer (SCT) FT D R R A D R A SCT clock R A FT D R FT D R A R A FT FT A F CLK_M3_SCT D D R A FT D R A FT D A FT D R A R prescaler H counter prescaler L counter Unified counter Fig 63. SCT counter and select logic 24.5 Pin description Table 498. SCT pin description Function name Direction Description CTIN_[7:0] CTOUT_[15:0] I O State Configurable Timer (SCT) inputs. State Configurable Timer (SCT) outputs. 24.6 Register description The register addresses of the State Configurable Timer are shown in Table 499. For most of the SCT registers, the register function depends on the setting of certain other register bits: 1. The UNIFY bit in the CONFIG register determines whether the SCT is used as one 32-bit register (for operation as one 32-bit counter/timer) or as two 16-bit counter/timers named L and H. The setting of the UNIFY bit is reflected in the register map: – UNIFY = 1: Only one register is used (for operation as one 32-bit counter/timer). – UNIFY = 0: The L and H registers can be accessed by a 32-bit read or write operation or can be read or written to individually (for operation as two 16-bit counter/timers). Typically, the UNIFY bit is configured by writing to the CONFIG register before any other registers are accessed. 2. The REGMODEn bits in the REGMODE register determine whether each set of Match/Capture registers uses the match or capture functionality: – REGMODEn = 1: Registers operate as match and reload registers. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 589 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 24: LPC18xx State Configurable Timer (SCT) FT D R R A – REGMODEn = 0: Registers operate as capture and capture control registers. A FT Table 499. Register overview: State Configurable Timer (base address 0x4000 0000) Name Access Address Description offset D R A R A FT D R FT D R A F D R A FT D R Reset value D R A FT R A FT D CONFIG CTRL CTRL_L CTRL_H LIMIT LIMIT_L LIMIT_H HALT HALT_L HALT_H STOP STOP_L STOP_H START START_L START_H COUNT COUNT_L COUNT_H STATE STATE_L STATE_H INPUT REGMODE REGMODE_L REGMODE_O OUTPUT OUTPUTDIRCTRL RES DMAREQ0 DMAREQ1 EVEN EVFLAG CONEN CONFLAG R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0x000 0x004 0x004 0x006 0x008 0x008 0x00A 0x00C 0x00C 0x00E 0x010 0x010 0x012 0x014 0x014 0x016 0x018 0x03C 0x040 0x040 0x042 0x044 0x044 0x046 0x048 0x04C 0x04C 0x04E 0x050 0x054 0x058 0x05C 0x060 0x064 0x0EC 0x0F0 0x0F4 0x0F8 0x0FC SCT configuration register SCT control register SCT control register low counter 16-bit SCT control register high counter 16-bit SCT limit register SCT limit register low counter 16-bit SCT limit register high counter 16-bit SCT halt condition register SCT halt condition register low counter 16-bit SCT halt condition register high counter 16-bit SCT stop condition register SCT stop condition register low counter 16-bit SCT stop condition register high counter 16-bit SCT start condition register SCT start condition register low counter 16-bit SCT start condition register high counter 16-bit Reserved SCT counter register SCT counter register low counter 16-bit SCT counter register high counter 16-bit SCT state register SCT state register low counter 16-bit SCT state register high counter 16-bit SCT input register SCT match/capture registers mode register SCT match/capture registers mode register low counter 16-bit SCT match/capture registers mode register high counter 16-bit SCT output register SCT output counter direction control register SCT conflict resolution register SCT DMA request 0 register SCT DMA request 1 register Reserved SCT event enable register SCT event flag register SCT conflict enable register SCT conflict flag register All information provided in this document is subject to legal disclaimers. 0x0000 7E00 0x0004 0004 0x0004 0004 0x0004 0004 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 A FT D R A 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 590 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 24: LPC18xx State Configurable Timer (SCT) FT D R Table 499. Register overview: State Configurable Timer (base address 0x4000 0000) …continued Name Access Address Description offset D R A R A FT D R FT D A R R A FT D R R A F D R A Reset value A FT A MATCH0 to MATCH15 MATCH0_L to MATCH15_L MATCH0_H to MATCH15_H CAP0 to CAP15 CAP0_L to CAP15_L CAP0_H to CAP15_H MATCHREL0 to MATCHREL15 MATCHREL0_L to MATCHREL15_L MATCHREL0_H to MATCHREL15_H CAPCTRL0 to CAPCTRL15 CAPCTRL0_L to CAPCTRL15_L CAPCTRL0 to CAPCTRL15 EVSTATEMSK0 EVCTRL0 EVSTATEMSK1 EVCTRL1 EVSTATEMSK2 EVCTRL2 EVSTATEMSK3 EVCTRL3 EVSTATEMSK4 EVCTRL4 EVSTATEMSK5 EVCTRL5 EVSTATEMSK6 EVCTRL6 EVSTATEMSK7 EVCTRL7 EVSTATEMSK8 EVCTRL8 EVSTATEMSK9 R/W R/W R/W 0x100 to SCT match value register of match channels 0 to 15; REGMOD0 0x0000 0000 0x13C to REGMODE15 = 0 0x100 to SCT match value register of match channels 0 to 15; low counter 0x0000 0000 0x13C 16-bit; REGMOD0_L to REGMODE15_L = 0 0x102 to SCT match value register of match channels 0 to 15; high 0x13E counter 16-bit; REGMOD0_H to REGMODE15_H = 0 0x100 to SCT capture register of capture channel 0 to 15; REGMOD0 to 0x13C REGMODE15 = 1 0x100 to SCT capture register of capture channel 0 to 15; low counter 0x13C 16-bit; REGMOD0_L to REGMODE15_L = 1 0x102 to SCT capture register of capture channel 0 to 15; high counter 0x13E 16-bit; REGMOD0_H to REGMODE15_H = 1 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 FT D A FT D R A FT D R R/W R/W R/W 0x200 to SCT match reload value register 0 to 15; REGMOD0 = 0 to 0x23C REGMODE15 = 0 0x200 to SCT match reload value register 0 to 15; low counter 16-bit; 0x23C REGMOD0_L = 0 to REGMODE15_L = 0 0x202 to SCT match reload value register 0 to 15; high counter 16-bit; 0x23E REGMOD0_H = 0 to REGMODE15_H = 0 0x200 to SCT capture control register 0 to 15; REGMOD0 = 1 to 0x23C REGMODE15 = 1 0x200 to SCT capture control register 0 to 15; low counter 16-bit; 0x23C REGMOD0_L = 1 to REGMODE15_L = 1 0x202 to SCT capture control register 0 to 15; high counter 16-bit; 0x23E REGMOD0 = 1 to REGMODE15 = 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C 0x340 0x344 0x348 SCT event state register 0 SCT event control register 0 SCT event state register 1 SCT event control register 1 SCT event state register 2 SCT event control register 2 SCT event state register 3 SCT event control register 3 SCT event state register 4 SCT event control register4 SCT event state register 5 SCT event control register 5 SCT event state register 6 SCT event control register 6 SCT event state register 7 SCT event control register 7 SCT event state register 8 SCT event control register 8 SCT event state register 9 All information provided in this document is subject to legal disclaimers. 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 591 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 24: LPC18xx State Configurable Timer (SCT) FT D R Table 499. Register overview: State Configurable Timer (base address 0x4000 0000) …continued Name Access Address Description offset D R A R A FT D R FT D A R R A FT D R R A F D R A Reset value A FT A EVCTRL9 EVSTATEMSK10 EVCTRL10 EVSTATEMSK11 EVCTRL11 EVSTATEMSK12 EVCTRL12 EVSTATEMSK13 EVCTRL13 EVSTATEMSK14 EVCTRL14 EVSTATEMSK15 EVCTRL15 OUTPUTSET0 OUTPUTCL0 OUTPUTSET1 OUTPUTCL1 OUTPUTSET2 OUTPUTCL2 OUTPUTSET3 OUTPUTCL3 OUTPUTSET4 OUTPUTCL4 OUTPUTSET5 OUTPUTCL5 OUTPUTSET6 OUTPUTCL6 OUTPUTSET7 OUTPUTCL7 OUTPUTSET8 OUTPUTCL8 OUTPUTSET9 OUTPUTCL9 OUTPUTSET10 OUTPUTCL10 OUTPUTSET11 OUTPUTCL11 OUTPUTSET12 OUTPUTCL12 OUTPUTSET13 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C 0x500 0x504 0x508 0x50C 0x510 0x514 0x518 0x51C 0x520 0x524 0x528 0x52C 0x530 0x534 0x538 0x53C 0x540 0x544 0x548 0x54C 0x550 0x554 0x558 0x55C 0x560 0x564 0x568 SCT event control register 9 SCT event state register 10 SCT event control register 10 SCT event state register 11 SCT event control register 11 SCT event state register 12 SCT event control register 12 SCT event state register 13 SCT event control register 13 SCT event state register 14 SCT event control register 14 SCT event state register 15 SCT event control register 15 SCT output 0 set register SCT output 0 clear register SCT output 1 set register SCT output 1 clear register SCT output 2 set register SCT output 2 clear register SCT output 3 set register SCT output 3 clear register SCT output 4 set register SCT output 4 clear register SCT output 5 set register SCT output 5 clear register SCT output 6 set register SCT output 6 clear register SCT output 7 set register SCT output 7 clear register SCT output 8 set register SCT output 8 clear register SCT output 9 set register SCT output 9 clear register SCT output 10 set register SCT output 10 clear register SCT output 11 set register SCT output 11 clear register SCT output 12 set register SCT output 12 clear register SCT output 13 set register All information provided in this document is subject to legal disclaimers. 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 © NXP B.V. 2011. All rights reserved. FT D A FT D R A FT D R User manual Rev. 00.13 — 20 July 2011 592 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 24: LPC18xx State Configurable Timer (SCT) FT D R Table 499. Register overview: State Configurable Timer (base address 0x4000 0000) …continued Name Access Address Description offset D R A R A FT D R FT D A R R A FT D R R A F D R A Reset value A FT A OUTPUTCL13 OUTPUTSET14 OUTPUTCL14 OUTPUTSET15 OUTPUTCL15 R/W R/W R/W R/W R/W 0x56C 0x570 0x574 0x578 0x57C SCT output 13 clear register SCT output 14 set register SCT output 14 clear register SCT output 15 set register SCT output 15 clear register 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 FT D A FT D R A FT D R 24.6.1 SCT configuration register This register configures the overall operation of the SCT and should be written before any other registers. Table 500. SCT configuration register (CONFIG - address 0x4000 0000) bit description Bit Symbol Value Description Reset value 0 UNIFY 0 1 SCT operation The SCT operates as two 16-bit counters named L and H. The SCT operates as a unified 32-bit counter. SCT clock mode 0x0 0x1 The SCT and prescaler(s) are clocked by the bus clock. The SCT clock is the bus clock, but the prescaler(s) is (are) enabled to count only when sampling of the input selected by the CKSEL field finds the selected edge. The minimum pulse width on the clock input is 1 bus clock period. This is the high-performance sampled-clock mode. The SCT and prescaler(s) are clocked by the input selected by CKSEL, synchronized to the bus clock and possibly inverted. The minimum pulse width on the clock input is 1 bus clock period. This is the low-power sampled-clock mode. The SCT and prescaler(s) are clocked by the input edge selected by the CKSEL field. In this mode the following is true: Most of the SCT is clocked by the (selected polarity of the) input. Outputs are switched synchronously to the input clock. The input clock rate must be at least half the bus clock rate and can be faster than the bus clock. 0 2:1 CLKMODE 00 0x2 0x3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 593 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 24: LPC18xx State Configurable Timer (SCT) FT D Table 500. SCT configuration register (CONFIG - address 0x4000 0000) bit description …continued Bit Symbol Value Description D R A R A FT D R R R A FT D R A R A A FT Reset value FT D R A F D R A 6:3 CLKSEL 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF SCT clock select Rising edges on input 0. Falling edges on input 0. Rising edges on input 1. Falling edges on input 1. Rising edges on input 2. Falling edges on input 2. Rising edges on input 3. Falling edges on input 3. Rising edges on input 4. Falling edges on input 4. Rising edges on input 5. Falling edges on input 5. Rising edges on input 6. Falling edges on input 6. Rising edges on input 7. Falling edges on input 7. 0000 FT D R A FT D R A FT D 7 NORELAODL_ NORELOADU - A 1 in this bit prevents the lower match registers from being reloaded from their 0 respective reload registers. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. A 1 in this bit prevents the higher match registers from being reloaded from their 0 respective reload registers. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set. Synchronization for input n (bit 9 = input 0, bit 10 = input 1,..., bit 16 = input 7). A 1 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock, before it is used to create an event. If an input is synchronous to the SCT clock, keep its bit 0 for faster response. When the CKMODE field is 1x, the bit in this field, corresponding to the input selected by the CKSEL field, is not used. 8 NORELOADH - 16:9 INSYNCn - 31:17 - Reserved - 24.6.2 SCT control register If UNIFY = 1 in the CONFIG register, only the _L bits are used. If UNIFY = 0 in the CONFIG register, this register can be written to as two registers CTRL_L (address 0x4000 4004) and CTRL_H (address 0x4000 4006). Both the L and H registers can be read or written in a single 32-bit read or write operation, or they can be read or written individually. All bits in this register can be written to when the counter is stopped or halted. When the counter is running, the only bits that can be written are STOP or HALT. (Other bits can be written in a subsequent write after HALT is set to 1.) All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 594 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 24: LPC18xx State Configurable Timer (SCT) FT D R A D R A R A FT D R FT D Table 501. SCT control register (CTRL - address 0x4000 0004) bit description Bit Symbol Value Description R R A FT D R R A F D R A Reset value A FT A 0 DOWN_L - This bit is 1 when the L or unified counter is counting down. It is set by hardware when the counter’s limit is reached and BIDIR is 1. It is cleared by hardware when the counter reaches 0. 0 FT D R A FT FT D 1 STOP_L - When this bit is 1 and HALT is 0, the L or unified counter does not run but I/O events 0 related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes. When this bit is 1, the L or unified counter does not run and no events can occur. This bit is set by reset. Remark: Once set, this bit can only be cleared by software to restore counter operation. D R A 2 HALT_L - 1 3 4 CLRCTR_L BIDIR_L 0 1 Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0. L or unified counter direction select The counter counts up to its limit condition, then is cleared to zero. The counter counts up to its limit, then counts down to 0. Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock. The counter clock will be clocked at the rate of the SCT clock divided by PRE_L+1. Remark: Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. 0 0 12:5 PRE_L - 0 15:13 16 DOWN_H - Reserved This bit is 1 when the H counter is counting down. It is set by hardware when the 0 counter’s limit is reached and BIDIR is 1. It is cleared by hardware when the counter reaches 0. When this bit is 1 and HALT is 0, the H counter does not run but I/O events related to 0 the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes. When this bit is 1, the H counter does not run and no events can occur. This bit is set 1 by reset. Remark: Once set, this bit can only be cleared by software to restore counter operation. 17 STOP_H - 18 HALT_H - 19 20 CLRCTR_H BIDIR_H 0 1 Writing a 1 to this bit clears the H counter. This bit always reads as 0. Direction select The H counter counts up to its limit condition, then is cleared to zero. The H counter counts up to its limit, then counts down to 0. Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. The counter clock will be clocked at the rate of the SCT clock divided by PRELH+1. Remark: Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. 0 0 28:21 PRE_H - 0 31:29 - Reserved 24.6.3 SCT limit register If UNIFY = 1 in the CONFIG register, only the _L bits are used. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 595 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 24: LPC18xx State Configurable Timer (SCT) FT D Table 502. SCT limit register (LIMIT - address 0x4000 0008) bit description Bit Symbol Description Reset value If UNIFY = 0 in the CONFIG register, this register can be written to as two registers LIMIT_L (address 0x4000 4008) and LIMIT_H (address 0x4000 400A). Both the L and H registers can be read or written in a single 32-bit read or write operation, or they can be read or written individually. R R A A FT D R A FT The bits in this register set which events act as counter limits. When a limit event occurs, the counter is cleared to zero in unidirectional mode or begins counting down in bidirectional mode. When the counter reaches all ones, this state is always treated as a limit event, and the counter is cleared in unidirectional mode or, in bidirectional mode, begins counting down on the next clock edge - even if no limit event as defined by the SCT limit register has occurred. D R A R A FT D R R A FT D R A F R A FT D A FT D R A D FT R D 15:0 LIMMSK_L If bit n is one, event n is used as a counter limit for the L or unified counter (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15). If bit n is one, event n is used as a counter limit for the H counter (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31). 0 31:16 LIMMSK_H 0 24.6.4 SCT halt condition register If UNIFY = 1 in the CONFIG register, only the _L bits are used. If UNIFY = 0 in the CONFIG register, this register can be written to as two registers HALT_L (address 0x4000 400C) and HALT_H (address 0x4000 400E). Both the L and H registers can be read or written in a single 32-bit read or write operation, or they can be read or written individually. Remark: Any event halting the counter disables its operation until software clears the HALT bit (or bits) in the CTRL register (Table 501). Table 503. SCT halt condition register (HALT - address 0x4000 000C) bit description Bit Symbol Description Reset value 15:0 HALTMSK_L If bit n is one, event n sets the HALT_L bit in the CTRL register 0 (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15). If bit n is one, event n sets the HALT_H bit in the CTRL register 0 (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31). 31:16 HALTMSK_H 24.6.5 SCT stop condition register If UNIFY = 1 in the CONFIG register, only the _L bits are used. If UNIFY = 0 in the CONFIG register, this register can be written to as two registers STOPT_L (address 0x4000 4010) and STOP_H (address 0x4000 4012). Both the L and H registers can be read or written in a single 32-bit read or write operation, or they can be read or written individually. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 596 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 24: LPC18xx State Configurable Timer (SCT) FT D R R A Table 504. SCT stop condition register (STOP - address 0x4000 0010) bit description D R A R A FT D R FT D R A R A FT A FT F Bit Symbol Description Reset value D D R R A A 15:0 STOPMSK_L If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15). 0 FT D R A FT D 31:16 STOPMSK_H If bit n is one, event n sets the STOP_H bit in the CTRL register 0 (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31). FT D R A 24.6.6 SCT start condition register If UNIFY = 1 in the CONFIG register, only the _L bits are used. If UNIFY = 0 in the CONFIG register, this register can be written to as two registers START_L (address 0x4000 4014) and START_H (address 0x4000 4016). Both the L and H registers can be read or written in a single 32-bit read or write operation, or they can be read or written individually. The bits in this register select which event(s), if any, clear the STOP bit in the Control register. (Since no events can occur when HALT is 1, HALT can only be cleared by software writing the Control register.) Table 505. SCT start condition register (START - address 0x4000 0014) bit description Bit Symbol Description Reset value 15:0 STARTMSK_L If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15). If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31). 0 0 31:16 STARTMSK_H 24.6.7 SCT counter register If UNIFY = 1 in the CONFIG register, the counter is a unified 32-bit register and both the _L and _H bits are used. If UNIFY = 0 in the CONFIG register, this register can be written to as two registers COUNT_L (address 0x4000 4040) and COUNT_H (address 0x4000 4042). Both the L and H registers can be read or written in a single 32-bit read or write operation, or they can be read or written individually. In this case, the L and H registers count independently under the control of the other registers. Attempting to write a counter while it is running will not affect the counter but will produce a bus error. Software can read the counter register(s) at any time. Table 506. SCT counter register (COUNT - address 0x4000 0040) bit description Bit Symbol Description Reset value 15:0 CTR_L When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write the lower 16 bits of the 32-bit unified counter. When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write the upper 16 bits of the 32-bit unified counter. 0 31:16 CTR_H 0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 597 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 24: LPC18xx State Configurable Timer (SCT) FT D R A D R A R A FT D R FT 24.6.8 SCT state register If UNIFY = 1 in the CONFIG register, only the _L bits are used. D R If UNIFY = 0 in the CONFIG register, this register can be written to as two registers STATE_L (address 0x4000 4044) and STATE_H (address 0x4000 4046). Both the L and H registers can be read or written in a single 32-bit read or write operation, or they can be read or written individually. FT D Software can read the state associated with a counter at any time. Writing the state is only allowed when the counter’s HALT bit is 1; when HALT is 0, a write attempt does not change the state and results in a bus error. The state variable is the main feature that distinguishes the SCT from other counter/timer/ PWM blocks. Events can be made to occur only in certain states. Events, in turn, can perform the following actions: R A FT D R R A F D R A FT D R A FT D R A A FT A • • • • set and clear outputs limit, stop, and start the counter cause interrupts and DMA requests modify the state variable The value of a state variable is completely under the control of the application. If an application does not use states, the value of the state variable remains zero, which is the default value. A state variable can be used to track and control multiple cycles of the associated counter in any desired operational sequence, and it is logically associated with a state machine diagram which represents the SCT configuration. See Section 24.6.23 and 24.6.24 for more about the relationship between states and events. All possible values for the state variable are set by the STATELD/STADEV fields in the event control registers of all defined events. The change of the state variable during multiple counter cycles reflects how the associated state machine moves from one state to the next. Table 507. SCT state register (STATE - address 0x4000 0044) bit description Bit Symbol Description Reset value 4:0 15:5 20:16 31:21 STATE_L STATE_H - State variable. Reserved. State variable. Reserved. 0 0 24.6.9 SCT input register Software can read the state of the SCT’s inputs in this read-only register in two slightly different forms. The only situation in which these will differ is if CLKMODE = 2 in the CONFIG register. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 598 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 24: LPC18xx State Configurable Timer (SCT) FT D Table 508. SCT input register (INPUT - address 0x4000 0048) bit description Bit Symbol Description D R A R A FT D R R R A FT D R A R A FT A FT D R A F Reset value D R A 0 1 2 3 4 5 6 7 15:8 16 17 18 19 20 21 22 23 31:24 AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 SIN0 SIN1 SIN2 SIN3 SIN4 SIN5 SIN6 SIN7 - Real-time status of input 0. Real-time status of input 1. Real-time status of input 2. Real-time status of input 3. Real-time status of input 4. Real-time status of input 5. Real-time status of input 6. Real-time status of input 7. Reserved. Input 0 state synchronized to the SCT clock. Input 1 state synchronized to the SCT clock. Input 2 state synchronized to the SCT clock. Input 3 state synchronized to the SCT clock. Input 4 state synchronized to the SCT clock. Input 5 state synchronized to the SCT clock. Input 6 state synchronized to the SCT clock. Input 7 state synchronized to the SCT clock. Reserved pin pin pin pin pin pin pin pin - FT D R A FT D R A FT D 24.6.10 SCT match/capture registers mode register If UNIFY = 1 in the CONFIG register, only the _L bits of this register are used, and they control whether each set of match/capture registers operate as unified 32-bit capture/match registers. If UNIFY = 0 in the CONFIG register, this register can be written to as two registers REGMODE_L (address 0x4000 404C) and REGMODE_H (address 0x4000 404E). Both the L and H registers can be read or written in a single 32-bit read or write operation, or they can be read or written individually. The _L bits/registers control the L match/capture registers, and the _H bits/registers control the H match/capture registers. The SCT contains 16 Match/Capture register pairs. The Register Mode register selects whether each register pair acts as a Match register (see Section 24.6.19) or as a Capture register (see Section 24.6.20). Each Match/Capture register has an accompanying register which serves as a Reload register when the register is used as a Match register (Section 24.6.21) or as a Capture-Control register when the register is used as a capture register (Section 24.6.22). REGMODE_H is used only when the UNIFY bit is 0. An alternate addressing mode is available for all of the Match/Capture and Reload/Capture-Control registers, for DMA access to halfword registers when UNIFY=0. It is described in Section 24.7.9. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 599 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 24: LPC18xx State Configurable Timer (SCT) FT D R R A Table 509. SCT match/capture registers mode register (REGMODE - address 0x4000 004C) bit description D R A R A FT D R FT D R A R A A FT D F FT D Bit Symbol Description Reset value R R A A FT D FT 15:0 REGMOD_L Each bit controls one pair of match/capture registers (register 0 = bit 0, register 1 = bit 1,..., register 15 = bit 15). 0 = registers operate as match registers. 1 = registers operate as capture registers. 0 D R A FT D R A 31:16 REGMOD_H Each bit controls one pair of match/capture registers (register 0 = bit 16, register 1 = bit 17,..., register 15 = bit 31). 0 = registers operate as match registers. 1 = registers operate as capture registers. 0 24.6.11 SCT output register The SCT supports 16 outputs, each of which has a corresponding bit in this register. Software can write to any of the output registers when both counters are halted to control the outputs directly. Writing to this register when either counter is stopped or running does not affect the outputs and results in an bus error. Software can read this register at any time to sense the state of the outputs. Table 510. SCT output register (OUTPUT - address 0x4000 0050) bit description Bit Symbol Description Reset value 15:0 OUT Writing a 1 to bit n makes the corresponding output HIGH. 0 makes 0 the corresponding output LOW (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15). Reserved 31:16 - 24.6.12 SCT bidirectional output control register This register specifies (for each output) the impact of the counting direction on the meaning of set and clear operations on the output (see Section 24.6.25 and Section 24.6.26). Table 511. SCT bidirectional output control register (OUTPUTDIRCTRL - address 0x4000 0054) bit description Bit Symbol Value Description Reset value 1:0 SETCLR0 0x0 0x1 0x2 Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value. Set and clear do not depend on any counter. Set and clear are reversed when counter L or the unified counter is counting down. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value. 0x0 0x1 0x2 Set and clear do not depend on any counter. Set and clear are reversed when counter L or the unified counter is counting down. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0 3:2 SETCLR1 0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 600 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 24: LPC18xx State Configurable Timer (SCT) FT D R R A Table 511. SCT bidirectional output control register (OUTPUTDIRCTRL - address 0x4000 0054) bit description D R A R A FT D R FT D R A R A A Bit Symbol Value Description Reset value FT D R A F FT D R A 5:4 SETCLR2 0x0 0x1 0x2 Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value. Set and clear do not depend on any counter. Set and clear are reversed when counter L or the unified counter is counting down. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value. 0x0 0x1 0x2 Set and clear do not depend on any counter. Set and clear are reversed when counter L or the unified counter is counting down. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value. 0x0 0x1 0x2 Set and clear do not depend on any counter. Set and clear are reversed when counter L or the unified counter is counting down. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value. 0x0 0x1 0x2 Set and clear do not depend on any counter. Set and clear are reversed when counter L or the unified counter is counting down. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value. 0x0 0x1 0x2 Set and clear do not depend on any counter. Set and clear are reversed when counter L or the unified counter is counting down. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value. 0x0 0x1 0x2 Set and clear do not depend on any counter. Set and clear are reversed when counter L or the unified counter is counting down. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value. 0x0 0x1 0x2 Set and clear do not depend on any counter. Set and clear are reversed when counter L or the unified counter is counting down. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value. 0x0 0x1 0x2 Set and clear do not depend on any counter. Set and clear are reversed when counter L or the unified counter is counting down. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value. 0x0 0x1 0x2 Set and clear do not depend on any counter. Set and clear are reversed when counter L or the unified counter is counting down. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value. 0x0 0x1 0x2 Set and clear do not depend on any counter. Set and clear are reversed when counter L or the unified counter is counting down. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. All information provided in this document is subject to legal disclaimers. 0 FT D R A FT D R A FT D 7:6 SETCLR3 0 9:8 SETCLR4 0 11: 10 SETCLR5 0 13: 12 SETCLR6 0 15: 14 SETCLR7 0 17: 16 SETCLR8 0 19: 18 SETCLR9 0 21: 20 SETCLR10 0 23: 22 SETCLR11 0 © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 601 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 24: LPC18xx State Configurable Timer (SCT) FT D R R A Table 511. SCT bidirectional output control register (OUTPUTDIRCTRL - address 0x4000 0054) bit description D R A R A FT D R FT D R A R A A Bit Symbol Value Description Reset value FT D R A F FT D R A 25: 24 SETCLR12 0x0 0x1 0x2 Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value. Set and clear do not depend on any counter. Set and clear are reversed when counter L or the unified counter is counting down. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value. 0x0 0x1 0x2 Set and clear do not depend on any counter. Set and clear are reversed when counter L or the unified counter is counting down. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value. 0x0 0x1 0x2 Set and clear do not depend on any counter. Set and clear are reversed when counter L or the unified counter is counting down. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value. 0x0 0x1 0x2 Set and clear do not depend on any counter. Set and clear are reversed when counter L or the unified counter is counting down. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0 FT D R A FT D R A FT D 27: 26 SETCLR13 0 29: 28 SETCLR14 0 31: 30 SETCLR15 0 24.6.13 SCT conflict resolution register The registers OUTPUTSETn (Section 24.6.25) and OUTPUTCLn (Section 24.6.26) allow both setting and clearing to be indicated for an output in the same clock cycle, even for the same event. This SCT conflict resolution register controls what happens when this occurs. To enable an event to toggle an output, set the OnRES value to 0x3 in this register, and set the event’s bits in both the Set and Clear registers. Table 512. SCT conflict resolution register (RES - address 0x4000 0058) bit description Bit Symbol Value Description Reset value 1:0 O0RES 0x0 0x1 0x2 0x3 Effect of simultaneous set and clear on output 0. No change. Set output (or clear based on the SETCLR0 field). Clear output (or set based on the SETCLR0 field). Toggle output. Effect of simultaneous set and clear on output 1. 0x0 0x1 0x2 0x3 No change. Set output (or clear based on the SETCLR1 field). Clear output (or set based on the SETCLR1 field). Toggle output. 0 3:2 O1RES 0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 602 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 24: LPC18xx State Configurable Timer (SCT) FT D R R A Table 512. SCT conflict resolution register (RES - address 0x4000 0058) bit description D R A R A FT D R FT D R A R A A Bit Symbol Value Description Reset value FT D R A F FT D R A 5:4 O2RES 0x0 0x1 0x2 0x3 Effect of simultaneous set and clear on output 2. No change. Set output (or clear based on the SETCLR2 field). Clear output n (or set based on the SETCLR2 field). Toggle output. Effect of simultaneous set and clear on output 3. 0x0 0x1 0x2 0x3 No change. Set output (or clear based on the SETCLR3 field). Clear output (or set based on the SETCLR3 field). Toggle output. Effect of simultaneous set and clear on output 4. 0x0 0x1 0x2 0x3 No change. Set output (or clear based on the SETCLR4 field). Clear output (or set based on the SETCLR4 field). Toggle output. Effect of simultaneous set and clear on output 5. 0x0 0x1 0x2 0x3 No change. Set output (or clear based on the SETCLR5 field). Clear output (or set based on the SETCLR5 field). Toggle output. Effect of simultaneous set and clear on output 6. 0x0 0x1 0x2 0x3 No change. Set output (or clear based on the SETCLR6 field). Clear output (or set based on the SETCLR6 field). Toggle output. Effect of simultaneous set and clear on output 7. 0x0 0x1 0x2 0x3 No change. Set output (or clear based on the SETCLR7 field). Clear output (or set based on the SETCLR7 field). Toggle output. Effect of simultaneous set and clear on output 8. 0x0 0x1 0x2 0x3 No change. Set output (or clear based on the SETCLR8 field). Clear output (or set based on the SETCLR8 field). Toggle output. Effect of simultaneous set and clear on output 9. 0x0 0x1 0x2 0x3 No change. Set output (or clear based on the SETCLR9 field). Clear output (or set based on the SETCLR9 field). Toggle output. 0 FT D R A FT D R A FT D 7:6 O3RES 0 9:8 O4RES 0 11: 10 O5RES 0 13: 12 O6RES 0 15: 14 O7RES 0 17: 16 O8RES 0 19: 18 O9RES 0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 603 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 24: LPC18xx State Configurable Timer (SCT) FT D R R A Table 512. SCT conflict resolution register (RES - address 0x4000 0058) bit description D R A R A FT D R FT D R A R A A Bit Symbol Value Description Reset value FT D R A F FT D R A 21: 20 O10RES 0x0 0x1 0x2 0x3 Effect of simultaneous set and clear on output 10. No change. Set output (or clear based on the SETCLR10 field). Clear output (or set based on the SETCLR10 field). Toggle output. Effect of simultaneous set and clear on output 11. 0x0 0x1 0x2 0x3 No change. Set output (or clear based on the SETCLR11 field). Clear output (or set based on the SETCLR11 field). Toggle output. Effect of simultaneous set and clear on output 12. 0x0 0x1 0x2 0x3 No change. Set output (or clear based on the SETCLR12 field). Clear output (or set based on the SETCLR12 field). Toggle output. Effect of simultaneous set and clear on output 13. 0x0 0x1 0x2 0x3 No change. Set output (or clear based on the SETCLR13 field). Clear output (or set based on the SETCLR13 field). Toggle output. Effect of simultaneous set and clear on output 14. 0x0 0x1 0x2 0x3 No change. Set output (or clear based on the SETCLR14 field). Clear output (or set based on the SETCLR14 field). Toggle output. Effect of simultaneous set and clear on output 15. 0x0 0x1 0x2 0x3 No change. Set output (or clear based on the SETCLR15 field). Clear output (or set based on the SETCLR15 field). Toggle output. 0 FT D R A FT D R A FT D 23: 22 O11RES 0 25: 24 O10RES 0 27: 26 O13RES 0 29: 28 O14RES 0 31: 30 O15RES 0 24.6.14 SCT DMA request 0 and 1 registers The SCT includes two DMA request outputs. These registers enable the DMA requests to be triggered when a particular event occurs or when a counter’s Match registers are loaded from its Reload registers. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 604 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 24: LPC18xx State Configurable Timer (SCT) FT D R R A Table 513. SCT DMA 0 request register (DMAREQ0 - address 0x4000 005C) bit description D R A R A FT D R FT D R A R A A FT FT F Bit Symbol Description Reset value D D R R A A 15:0 29:16 30 DEV_0 DRL0 If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 0 1 = bit 1,..., event 15 = bit 15). Reserved A 1 in this bit makes the SCT set DMA request 0 when it loads the Match_L/Unified registers from the Reload_L/Unified registers. This read-only bit indicates the state of DMA Request 0 - FT D R A FT D R A FT D 31 DRQ0 Table 514. SCT DMA 1 request register (DMAREQ1 - address 0x4000 0060) bit description Bit Symbol Description Reset value 15:0 29:16 30 DEV_1 DRL1 If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 0 1 = bit 1,..., event 15 = bit 15). Reserved A 1 in this bit makes the SCT set DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers. This read-only bit indicates the state of DMA Request 1. - 31 DRQ1 24.6.15 SCT flag enable register This register enables flags to request an interrupt if the FLAGn bit in the SCT event flag register (Section 24.6.16) is also set. Table 515. SCT flag enable register (EVEN - address 0x4000 00F0) bit description Bit Symbol Description Reset value 15:0 IEN The SCT requests interrupt when bit n of this register and the event 0 flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). Reserved 31:16 - 24.6.16 SCT event flag register This register records events. Writing ones to this register clears the corresponding flags and will negate the SCT interrupt request if all enabled Flag bits are zero. Table 516. SCT event flag register (EVFLAG - address 0x4000 00F4) bit description Bit Symbol Description Reset value 15:0 FLAG 31: 16 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). Reserved 0 - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 605 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 24: LPC18xx State Configurable Timer (SCT) FT D R A D R A R A FT D R FT 24.6.17 SCT conflict enable register D R This register enables the “no change conflict” events specified in the SCT conflict resolution register to request an IRQ. Table 517. SCT conflict enable register (CONEN - address 0x4000 00F8) bit description Bit Symbol Description R A FT D R R A F D R A FT A FT Reset value A FT D R A D FT D R A 15:0 NCEN The SCT requests interrupt when bit n of this register and the SCT 0 conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15). Reserved 31:16 - 24.6.18 SCT conflict flag register This register records interrupt-enabled no-change conflict events and provides details of a bus error. Writing ones to the NCFLAG bits clears the corresponding read bits and will negate the SCT’s interrupt request if all enabled Flag bits are then zero. Table 518. SCT conflict flag register (CONFLAG - address 0x4000 00FC) bit description Bit Symbol Description Reset value 15:0 NCFLAG Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15). Reserved. 0 29:16 30 BUSERRL - The most recent bus error from this SCT involved writing CTR 0 L/Unified, STATE L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. Note that a word write to certain L and H registers can be half successful and half unsuccessful. The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or the Output register when the H counter was not halted. 0 31 BUSERRH 24.6.19 SCT match registers 0 to 15 (REGMODEn bit = 0) Match registers are compared to the counter(s) to help create events. When the UNIFY bit is 0, the L and H registers are independently compared to the L and H counters. When UNIFY is 1, the L and H registers hold a 32-bit value that is compared to the unified counter. A Match can only occur in a clock in which the counter is running (STOP and HALT are both 0). Match registers can be read at any time. Writing to a Match register while the associated counter is running will not affect the Match register and will result in an bus error. Match events occur in the SCT clock in which the counter is (or would be) incremented to the next value. When a Match event limits its counter as described in Section 24.6.3, the value in the Match register is the last value of the counter before it is cleared to zero (or decremented if BIDIR is 1). All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 606 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 24: LPC18xx State Configurable Timer (SCT) FT D R R A There is no “write-through” from Reload registers to Match registers. Before starting a counter, software can write one value to the Match register that will be used in the first cycle of the counter, and a different value to the corresponding Match Reload register that will be used in the second cycle. R A Table 519. SCT match registers 0 to 15 (MATCH - address 0x4000 0100 (MATCH0) to 0x4000 4013C (MATCH15)) bit description (REGMODEn bit = 0) Bit Symbol Description Reset value D R A R A FT D R FT D R A A FT D R A R A FT F FT D R A FT D D R A FT D 15:0 MATCHn_L When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. MATCHn_H When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. 0 31:16 0 24.6.20 SCT capture registers 0 to 15 (REGMODEn bit = 1) These register(s) allow software to read the counter value(s) at which the event selected by the corresponding Capture Control register(s) occurred. Table 520. SCT capture registers 0 to 15 (CAP - address 0x4000 0100 (CAP0) to 0x4000 013C (CAP15)) bit description (REGMODEn bit = 1) Bit Symbol Description Reset value 15:0 CAPn_L When UNIFY = 0, read the 16-bit counter value at which this 0 register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. When UNIFY = 0, read the 16-bit counter value at which this 0 register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. 31:16 CAPn_H 24.6.21 SCT match reload registers 0 to 15 (REGMODEn bit = 0) A Match register (L, H, or unified 32-bit) is loaded from the corresponding Reload register when BIDIR is 0 and the counter reaches its limit condition, or when BIDIR is 1 and the counter reaches 0. Table 521. SCT match reload registers 0 to 15 (MATCHREL- address 0x4000 0200 (MATCHRELOAD0) to 0x4000 023C (MATCHRELOAD15) bit description (REGMODEn bit = 0) Bit Symbol Description Reset value 15:0 RELOADn_L When UNIFY = 0, read or write the 16-bit value to be loaded into the SCTMATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. 0 31:16 RELOADn_H When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. 0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 607 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 24: LPC18xx State Configurable Timer (SCT) FT D R A 24.6.22 SCT capture control registers 0 to 15 (REGMODEn bit = 1) If UNIFY = 1 in the CONFIG register, only the _L bits are used. If UNIFY = 0 in the CONFIG register, this register can be written to as two registers CAPCTRLn_L (address 0x4000 4100 to 0x4000 413C) and CAPCTRLn_H (address 0x4000 4102 to 0x4000 413E). Both the L and H registers can be read or written in a single 32-bit read or write operation, or they can be read or written individually. Each Capture Control register (L, H, or unified 32-bit) controls which events load the corresponding Capture register from the counter. Table 522. SCT capture control registers 0 to 15 (CAPCTRL- address 0x4000 0200 (CAPCTRL0) to 0x4000 023C (CAPCTRL15)) bit description (REGMODEn bit = 1) Bit Symbol Description Reset value D R A R A FT D R FT D R R A FT D R R A F D R A FT A FT A FT D R A D FT D R A 15:0 CAPCONn_L If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the 0 CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). If bit m is one, event m causes the CAPn_H (UNIFY = 0) 0 register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31). 31:16 CAPCONn_H 24.6.23 SCT event state mask registers 0 to 15 Each event has one associated SCT event state mask register that allow this event to happen in one or more states of the counter selected by the HEVENT bit in the corresponding EVCTRLn register. An event n is disabled when its EVSTATEMSKn register contains all zeros, since it is masked regardless of the current state. In simple applications that don’t use states, write 0x01 to this register to enable an event. Since the state will always remain at its reset value of 0, this effectively permanently state-enables this event. Table 523. SCT event state mask registers 0 to 15 (EVSTATEMSK - addresses 0x4000 0300 (EVSTATEMSK0) to 0x4000 0378 (EVSTATEMSK15)) bit description Bit Symbol Description Reset value 31:0 STATEMSKn If bit m is one, event n (n= 0 to 15) happens in state m of the 0 counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31). 24.6.24 SCT event control registers 0 to 15 This register defines the conditions for event n to occur, other than the state variable which is defined by the state mask register above. Most events are associated with a particular counter (high, low, or unified), in which case the event can depend on a match to that register. The other possible ingredient of an event is a selected input or output signal. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 608 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 24: LPC18xx State Configurable Timer (SCT) FT D R R A When the UNIFY bit is 0, each event is associated with a particular counter by the HEVENT bit in its event control register. An event can not occur when its related counter is halted nor when the current state is not enabled to cause the event as specified in its event mask register. Note that an event is permanently disabled when its event state mask register contains all 0s. R A An enabled event can be programmed to occur based on a selected input or output edge or level and/or based on its counter value matching a selected match register. Each event can modify its counter’s STATE value. If more than one event associated with the same counter occurs in a given clock cycle, only the state change specified for the highest-numbered event among them takes place. Other actions dictated by any simultaneously occurring events will all take place. Table 524. SCT event control register 0 to 15 (EVCTRL - address 0x4000 0304 (EVCTRL0) to 0x4000 037C (EVCTRL15)) bit description Bit Symbol Value Description Reset value D R A R A FT D R FT D R A A FT D R A R A FT F FT D R A FT D D R A FT D 3:0 4 MATCHSEL HEVENT - Selects the Match register associated with this event (if any). A match can occur only 0 when the counter selected by the HEVENT bit is running. Select L/H counter. Do not set this bit if UNIFY = 1. 0 Selects the L state and the L match register selected by MATCHSEL. Selects the H state and the H match register selected by MATCHSEL. Input/output select 0 Selects the output selected by IOSEL. Selects the input selected by IOSEL. Selects the input or output signal associated with this event (if any). If CKMODE is 1x, 0 the clock input is an implicit ingredient of every event, and should not be selected in this register. Selects the I/O condition for event n. (Note that the detection of edges on outputs will 0 lag the conditions that switch the outputs by one SCT clock). An input must have a minimum pulse width of at least one SCT clock period in order to guarantee proper edge/state detection. 0 1 5 OUTSEL 0 1 9:6 IOSEL - 11:10 IOCOND 0x0 0x1 0x2 0x3 13:12 COMBMODE 0x0 0x1 0x2 0x3 LOW Rise Fall HIGH Selects how the specified match and I/O condition are used and combined. OR. The event occurs when either the specified match or I/O condition occurs. MATCH. Uses the specified match only. IO. Uses the specified I/O condition only. AND. The event occurs when the specified match and I/O condition occur simultaneously. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 609 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 24: LPC18xx State Configurable Timer (SCT) FT D R R A Table 524. SCT event control register 0 to 15 (EVCTRL - address 0x4000 0304 (EVCTRL0) to 0x4000 037C (EVCTRL15)) bit description Bit Symbol Value Description D R A R A FT D R FT D R A R A FT Reset value A FT D R A F R A FT D FT 14 STATELD 0 1 This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state. STATEV value is added into STATE (the carry-out is ignored). STATEV value is loaded into STATE. This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value. Reserved D D R A FT D R A 19:15 STATEV 31:20 - 24.6.25 SCT output set registers 0 to 15 Each output n has one set register that controls how events effect each output. Whether outputs are set or cleared depends on the setting of the SETCLRn field in the SCTOUTPUTDIRCTRL register. Table 525. SCT output set register 0 to 15 (OUTPUTSET - address 0x4000 0500 (OUTPUTSET0) to 0x4000 0578 (OUTPUTSET15)) bit description Bit Symbol Description Reset value 15:0 31:16 SET - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15. Reserved 24.6.26 SCT output clear registers 0 to 15 Each output n has one clear register that controls how events effect each output. Whether outputs are set or cleared depends on the setting of the SETCLRn field in the OUTPUTDIRCTRL register. Table 526. SCT output set register 0 to 15 (OUTPUTCL - address 0x4000 0504 (OUTPUTCL0) to 0x4000 057C (OUTPUTCL15)) bit description Bit Symbol Description Reset value 15:0 31:16 CLR - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15. Reserved All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 610 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 24: LPC18xx State Configurable Timer (SCT) FT D R A D R A R A FT D R FT 24.7 Functional description 24.7.1 Match logic D R R A FT D R R A F D R A FT A FT A FT D R A D FT D R Match Reload iH Match Reload iL Counter L Fig 64. Match logic A Match Reg i H = UNIFY Match i H Match Reg i L = Match i L 24.7.2 Capture logic SCT clock Fig 65. Capture logic 24.7.3 Event selection State variable(s) allow control of the SCT across more than one cycle of the counter. Counter matches, input/output edges, and state values are combined into a set of general purpose events that can switch outputs, request interrupts, and change state values. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 611 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 24: LPC18xx State Configurable Timer (SCT) FT D R R A D R A R A FT D R FT D R A R A FT FT A F H matches L matches MATCHSELi inputs outputs IOSELi OUTSELi IOCONDi select D D R A FT D R A FT D A R select event i FT D R A COMBMODEi STATEMASKi H STATE L STATE HEVENTi select Fig 66. Event selection 24.7.4 Output generation Figure 67 shows one output slice of the SCT. Events Set register NoChangeConflict i SETCLRi OiRES Select OUT reg Output i i Clear register i Fig 67. Output slice i SCT clock 24.7.5 Interrupt generation The SCT generates one interrupt to the NVIC. Events Enable register Flags register Conflict Flags register UT interrupt Conflict Enable register No Change Conflict events Fig 68. SCT interrupt generation All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 612 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 24: LPC18xx State Configurable Timer (SCT) FT D R A D R A R A FT D R FT 24.7.6 Clearing the prescaler D R When enabled by a non-zero PRE field in the Control register, the prescaler acts as a clock divider for the counter, like a fractional part of the counter value. The prescaler is cleared whenever the counter is cleared or loaded for any of the following reasons: D R A R A FT R A F D R A FT D R A A FT FT D • • • • Hardware reset Software writing to the counter register Software writing a 1 to the CLRCTR bit in the control register an event selected by a 1 in the counter’s limit register when BIDIR = 0 FT D R A When BIDIR is 0, a limit event caused by an I/O signal can clear a non-zero prescaler, but a limit event caused by a Match will only clear a non-zero prescaler in one special case as described Section 24.7.7. A limit event when BIDIR is 1 does not clear the prescaler. Rather it clears the DOWN bit in the Control register, and decrements the counter on the same clock if the counter is enabled in that clock. 24.7.7 Match vs. I/O events Counter operation is complicated by the prescaler, and by clock mode 01 in which the SCT clock is the bus clock, but the prescaler and counter are enabled to count only when a selected edge is detected on a clock input. • The prescaler is enabled when the clock mode is not 01, or when the input edge selected by the CLKSEL field is detected. • The counter is enabled when the prescaler is enabled, and (PRELIM=0 or the prescaler is equal to the value in PRELIM). An I/O component of an event can occur in any SCT clock when its counter’s HALT bit is 0. In general a Match component of an event can only occur in a UT clock when its counter’s HALT and STOP bits are both 0 and the counter is enabled. Table 527 shows when the various kinds of events can occur. Table 527. Event conditions COMBMODE IOMODE Event can occur on clock: IO MATCH OR Any Any Any Event can occur whenever HALT = 0 (type A). Event can occur when HALT = 0 and STOP = 0 and the counter is enabled (type C). From the IO component: Event can occur whenever HALT = 0 (A). From the match component: Event can occur when HALT = 0 and STOP = 0 and the counter is enabled (C). Event can occur when HALT = 0 and STOP = 0 and the counter is enabled (C). Event can occur whenever HALT = 0 (A). AND AND LOW or HIGH RISE or FALL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 613 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 24: LPC18xx State Configurable Timer (SCT) FT D R A D R A R A FT D R FT 24.7.8 DMA operation D R A DMA controller can be used to write one or more Reload registers, or read one or more Capture registers, typically at the start of a counter cycle. DMA access to more than one Reload or Capture register requires that they be consecutive registers. (Nothing else in the SCT constrains how these registers are assigned and used.) D R A FT D A DMA request can be set by an event or when a counter’s Match registers are loaded from its Reload registers, as described in Section 24.6.14. The SCT’s two requests can be used to do the same kind of register access for both counters when UNIFY is 0, or one request can be used for writing Reload registers and the other for reading Capture registers. The SCT does not know how many transfers should be done for each request, so it cannot control its DMA requests accordingly. The two DMA requests are connected to DMABREQ7 and DMABREQ8. The number of registers to be transferred for each request should be written to the TransferSize field in the Channel Control Register of the DMA channel to which the request is connected. If the Linked List feature is used, there is a TransferSize value in each Linked List entry. The GPDMA asserts the DMACCLR signal when that number of transfers has been completed, which makes the SCT clear the request. R A FT R A F D R A FT D FT D R A R A A FT 24.7.9 Alternate addressing for match/capture registers The Match, Reload, Capture, and Capture Control registers are arranged as consecutive words, with the standard division of each word into two halfwords. When the UNIFY bit is zero, these two halfwords are related to the L and H counters. Software has the option of writing words initially to set up both halves of a SCT simultaneously, or writing halfwords to set up each half separately. Applications can use a DMA controller to write Reload registers or to read Capture registers. However, when UNIFY is 0, the addressing of the halfword registers is not compatible with many DMA controllers’ requirement to use consecutive addresses for sequential-address operation. Table 528 shows how the second half of the range occupied by each type of register contains an alternate address map for halfword accesses to the same registers, which is compatible with such DMA controllers. When UNIFY is 1, DMA word accesses should be done using standard offsets. Table 528. Alternate address map for DMA halfword access Match register Capture register Standard offset DMA halfword offset MATCH0_L MATCH0_H MATCH1_L MATCH1_H ... MATCHREL0_L MATCHREL0_H MATCHREL1_L MATCHREL1_H ... CAP0_L CAP0_H CAP1_L CAP1_H ... CAPCTRL0_L CAPCTRL0_H CAPCTRL1_L CAPCTRL1_H ... 0x100 0x102 0x104 0x106 ... 0x200 0x202 0x204 0x206 ... 0x180 0x1C0 0x182 0x1C2 ... 0x280 0x2C0 0x282 0x2C2 ... © NXP B.V. 2011. All rights reserved. All information provided in this document is subject to legal disclaimers. User manual Rev. 00.13 — 20 July 2011 614 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 24: LPC18xx State Configurable Timer (SCT) FT D R A D R A R A FT D R FT 24.7.10 SCT operation D R In its simplest, single-state configuration, the SCT operates as an event controlled uni- or bidirectional counter. Events can be configured to be counter match events, an input or output level, transitions on an input or output pin, or a combination of match and input/output behavior. In response to an event, the SCT’s output or outputs can transition or the SCT can perform other actions such as creating an interrupt or starting, stopping, or resetting the counter. Multiple simultaneous actions are allowed for each event. Furthermore, one specific action of the SCT can be triggered by any number of events. An event is defined uniquely by an action or multiple actions of the SCT. A state is defined by which events are enabled to trigger an SCT action or actions in any stage of the counter. Events not selected for this state are ignored. In a multi-state configuration, states change in response to events. A state change is an additional action that the SCT can perform when the event occurs. When an event is configured to change the state, the new state defines a new set of events resulting in different actions of the SCT. Through multiple cycles of the counter, events can change the state multiple times and thus create a large variety of event controlled transitions on the SCT’s outputs and/or interrupts. Once configured, the SCT can run continuously without software intervention and can generate multiple output patterns entirely under the control of events. D R A FT D • To configure the SCT, see Section 24.7.10.1. • To start, run, and stop the SCT, see Section 24.7.10.2. • To configure the SCT without in using multiple states as simple event controlled counter/timer, see Section 24.7.10.3. R A FT R A F D R A FT D FT D R A R A A FT 24.7.10.1 Configure the SCT To set up the SCT for multiple events and states perform the following configuration steps: 24.7.10.1.1 Configure the counter 1. Configure the L and H counters in the CONFIG register by selecting two independent 16-bit counters (L counter and H counter) or one combined 32-bit counter in the UNIFY field. 2. Select the SCT clock source in the CONFIG register (fields CLKMODE and CLKSEL) from any of the inputs or an internal clock. 24.7.10.1.2 Configure the match and capture registers 1. Select how many match and capture registers are needed by the application (total of up to 16): – In the REGMODE register, select for each of the 16 match/capture register pairs whether the register is used as a match register or capture register. 2. Define match conditions for each match register selected: – Each match register MATCH allows to set one match value if a 32-bit counter is used or two match values if the L and H 16-bit counters are used. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 615 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 24: LPC18xx State Configurable Timer (SCT) FT D R R A – Each match reload register MATCHRELOAD allows to set a reload value that is loaded into the match register when the counter reaches a limit condition or the value 0. R A FT D R A D R A R A FT D R FT D R A F D R A FT A FT FT 24.7.10.1.3 Configure events and event responses D 1. Define when each event can occur in the following way in the EVCTRL registers (up to 16, one register per event): – Select whether the event occurs on an input or output changing, on an input or output level, a match condition of the counter, or a combination of match and input/output conditions in field COMBMODE. – For a match condition: Select the match register that contains the match condition for the event to occur. Enter the number of the selected match register in field MATCHSEL. If using L and H counters, define whether the event occurs on matching the L or the H counter in field HEVENT. – For an SCT input or output level or transition: Select the input number or the output number that is associated with this event in fields IOSEL and OUTSEL. Define how the selected input or output triggers the event (edge or level sensitive) in field IOCOND. 2. Define what the effect of each event is on the SCT’s outputs in the OUTPUTSET or OUTPUTCLR registers (up to 16 outputs, one register per output): – For each SCT output, select which events set or clear this output. An output can be changed by more than one event, and each event can change multiple outputs. 3. Define how each event affects the counter: – Set the corresponding event bit in the LIMIT register for the event to set an upper limit for the counter. When a limit event occurs in unidirectional mode, the counter is cleared to zero and begins counting up on the next clock edge. When a limit event occurs in bidirectional mode, the counter begins to count down from the current value on the next clock edge. – Set the corresponding event bit in the HALT register for the event to halt the counter. If the counter is halted, it stops counting and no new events can occur. The counter operation can only be restored by clearing the HALT_L and/or the HALT_H bits in the CTRL register. – Set the corresponding event bit in the STOP register for the event to stop the counter. If the counter is stopped, it stops counting but can be restarted by an event that is configured as an transition on an input/output. – Set the corresponding event bit in the START register for the event to restart the counting. Only events that are defined by an input changing can be used to restart the counter. 4. Define which events contribute to the SCT interrupt: – Set the corresponding event bit in the EVEN and the EVFLAG registers to enable the event to contribute to the SCT interrupt. 5. Define whether an event triggers a DMA request. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. D R A FT D R A User manual Rev. 00.13 — 20 July 2011 616 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 24: LPC18xx State Configurable Timer (SCT) FT D R R A – Set the corresponding event bit in the DMAREQ0/1 registers for the event to trigger DMA requests 0 or 1. A FT D D R A R A FT D R FT D R A F R D R A FT R 24.7.10.1.4 Configure multiple states A 1. In the EVSTATEMASK register for each event (up to 16 events, one register per event), select the state or states (up to 31) this event is allowed to occur in. Each state can be selected for more than one event. 2. Determine how the event affects the system’s state: In the EVCTRL registers (up to 16 events, one register per event), set the new state value in the STATEV field for this event. If the event is the highest numbered in the current state, this value is either added to the existing state value or replaces the existing state value, depending on the field STATELD. Remark: If there are higher numbered events in the current state, the state cannot be changed by this event. If the STATEV and STATELD values are set to zero, the state does not change. 24.7.10.1.5 Miscellaneous options • There are a certain (selectable) number of capture registers. Each capture register can be programmed to capture the counter contents when one or more events occur. • If the counter is in bidirectional mode, the effect of set and clear of an output can be made to depend on whether the counter is counting up or down by writing to the OUTPUTDIRCTRL register. A FT D R A FT D FT D R A • 24.7.10.2 Operate the SCT 1. Configure the SCT (see Section 24.7.10.1 “Configure the SCT”). a. Configure the counter (see Section 24.7.10.1.1). b. Configure the match and capture registers (see Section 24.7.10.1.2). c. Configure the events and event responses (see Section 24.7.10.1.3). d. Configure multiple states (Section 24.7.10.1.4). 2. Write to the STATE register to define the initial state. By default this is state 0. 3. To start the SCT, write to the CTRL register: – Clear the counters. – Clear or set the STOP_L and/or STOP_H bits. Remark: The counter starts counting once the STOP bit is cleared as well. If the STOP bit is set, the SCT will wait instead for an event to occur that is configured to start the counter. – For each counter select unidirectional or bidirectional counting mode (field BIDIR_L and/or BIDIR_H). – Select the prescale factor for the counter clock (CTRL register). – Clear the HALT_L and/or HALT_H bit. By default, the counters are halted and no events can occur. 4. To stop the counters by software at any time, stop or halt the counter (write to STOP_L and/or STOP_H bits or HALT_L and/or HALT_H bits in the CTRL register). All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 617 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 24: LPC18xx State Configurable Timer (SCT) FT D R R A – When the counters are stopped, both an event configured to clear the STOP bit or software writing a zero to the STOP bit can start the counter again. R A – When the counter are halted, only a software write to clear the HALT bit can start the counter again. No events can occur. – When the counters are halted, software can set any SCT output HIGH or LOW directly by writing to the OUT register. The current state can be read at any time by reading the STATE register. R A FT D To change the current state by software (that is independently of any event occurring), set the HALT bit and write to the STATE register to change the state value. Writing to the STATE register is only allowed when the counter is halted (the HALT_L and/or HALT_H bits are set) and no events can occur. D R A R A FT D R FT D R A A FT D R A R A FT F FT D FT D D R A 24.7.10.3 Configure the SCT without using states The SCT can be used as standard counter/timer with external capture inputs and match outputs without using the state logic. To operate the SCT without states, configure the SCT as follows: • Write zero to the STATE register (this is the default). • Write zero to the STATELD and STATEV fields in the EVCTRL registers for each event. • Write 0x1 to the EVSTATEMASK register of each event. This enables the event. In effect, the event is allowed to occur in a single state which never changes while the counter is running. 24.7.10.4 Example Figure 69 shows a simple application of the SCT using two sets of match events (EV0/1 and EV3/4) to set/clear SCT output 0. A third match event (EV2) is used to reset the counter regardless of the current state. In the initial state 0, match event EV0 causes the output 0 to be set to HIGH and match event EV1 causes output 0 to be cleared. The SCT input 0 is monitored: If the input transitions from HIGH to LOW (EV2), the state is changed to state 1, and EV3/4 are enabled, which create the same output but triggered by different match values. If input 0 transitions from LOW to HIGH, the associated event (EV5) causes the state to change back to state 0. In state 0, the events EV0 and EV1 are enabled. The example uses the following SCT configuration: • • • • • 1 input 1 output 5 match registers 7 events 2 states All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 618 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 24: LPC18xx State Configurable Timer (SCT) FT D R R A D R A R A FT D R FT D R A R A A input transition events SC input 0 EV3 EV6 FT D R R A FT D R A FT A F FT D FT D D match events R A EV2 EV1 EV0 EV2 EV1 EV4 EV5 EV2 EV5 EV4 EV2 EV2 EV1 EV0 EV2 EV1 EV0 SCT counter EV0 SCT output 0 STATE 0 STATE 1 STATE 0 Fig 69. SCT configuration example This application of the SCT uses the following configuration (all register values not listed in Table 529 are set to their default values): Table 529. SCT configuration example Configuration Register(s) Setting Counter Clock base Match/Capture registers Define match values Define match reload values Define when event 0 occurs Define when event 1 occurs Define when event 2 occurs Define when event 3 occurs Define how event 3 changes the state CONFIG CTRL CONFIG REGMODE MATCH0/1/2/4/5 MATCHREL0/1/2/4/5 EVCTRL0 EVCTRL1 EVCTRL2 EVCTRL3 Uses one counter (UNIFY = 1). Uses unidirectional counter (BIDIR_L = 0). Uses default values for clock configuration. Configure one match register for each match event by setting REGMODE_L bits 0,1, 2, 4, 5 to 0. This is the default. Set a match value MATCH0/1/2/4/5_L in each register. Set a match reload value RELOAD0/1/2/4/5_L in each register (same as the match value in this example). • • • • • • • • • Set COMBMODE = 0x1. Event 0 uses match condition only. Set MATCHSEL = 0. Select match value of match register 0. Set COMBMODE = 0x1. Event 1 uses match condition only. Set MATCHSEL = 1. Select match value of match register 1. Set COMBMODE = 0x1. Event 2 uses match condition only. Set MATCHSEL = 2. Select match value of match register 2. Set COMBMODE = 0x2. Event 3 uses I/O condition only. Set IOSEL = 0. Select input 0. Set IOCOND = 0x2. Input 0 goes LOW. EVCTRL3 Set STATEV bits to 1 and the STATED bit to 1. Event 3 changes the state to state 1. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 619 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 24: LPC18xx State Configurable Timer (SCT) FT D R A D R A R A FT D R FT Table 529. SCT configuration example Configuration Register(s) Setting D R R A FT D R A F D A FT Define when event 4 occurs Define when event 5 occurs Define when event 6 occurs Define how event 6 changes the state Define by which events output 0 is set Define by which events output 0 is cleared Define which event resets the counter EVCTRL4 EVCTRL5 EVCTRL6 • • • • • • • Set COMBMODE = 0x1. Event 4 uses match condition only. Set MATCHSEL = 0x3. Select match value of match register 4. Set COMBMODE = 0x1. Event 5 uses match condition only. Set COMBMODE = 0x2. Event 6 uses I/O condition only. Set IOSEL = 0. Select input 0. Set IOCOND = 0x1. Input 0 goes HIGH. R Set MATCHSEL = 0x3. Select match value of match register 5. R A A FT D A FT D R A FT D R EVCTRL6 OUTPUTSET0 OUTPUTCLR0 LIMIT Set STATEV bits to 0 and the STATED bit to 1. Event 6 changes the state to state 0. Set SET0 bits 0 (for event 0) and 4 (for event 4) to one to set the output when these events 0 and 4 occur. Set CLR0 bits 1 (for events 1) and 5 (for event 5) to one to clear the output when events 1 and 5 occur. Set LIMMASK_L bit 2 to 1 (for event 2 to limit the counter). Set all other bits to zero. Set STATEMSK0 bit 0 to 1. Set all other bits to 0. Event 0 is enabled in state 0. Set STATEMSK1 bit 0 to 1. Set all other bits to 0. Event 1 is enabled in state 0. Set STATEMSK2 bit 0 to 1 and bit 1 to 1. Set all other bits to 0. Event 2 is enabled in state 0 and state 1. Set STATEMSK3 bit 0 to 1. Set all other bits to 0. Event 3 is enabled in state 0. Set STATEMSK4 bit 1 to 1. Set all other bits to 0. Event 4 is enabled in state 1. Set STATEMSK5 bit 1 to 1. Set all other bits to 0. Event 5 is enabled in state 1. Set STATEMSK6 bit 1 to 1. Set all other bits to 0. Event 6 is enabled in state 1. Configure states event 0 EVSTATEMSK0 is enabled Configure states event 1 EVSTATEMSK1 is enabled Configure states event 2 EVSTATEMSK2 is enabled Configure states event 3 EVSTATEMSK3 is enabled Configure states event 4 EVSTATEMSK4 is enabled Configure states event 5 EVSTATEMSK5 is enabled Configure states event 6 EVSTATEMSK6 is enabled All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 620 of 1164 D R A FT D R A FT D R A FT D R A FT D R A FT UM10430 Chapter 25: LPC18xx Timer0/1/2/3 Rev. 00.13 — 20 July 2011 D D D R A FT D D R A FT D R A FT D R A R A FT D R A R A FT D R A FT D R A F R A FT D R R D User manual FT D R A FT FT A FT 25.1 How to read this chapter The timers are available on all LPC18xx parts. The following configuration options apply to parts LPC1850_30_20_10 Rev ‘A’ only: D • The timer capture inputs and match outputs are configured through the GIMA (see Section 14.3). D R A FT D R A • All timer capture inputs are also connected to dedicated external pins (see Section 14.3 and Section 13.3.6). 25.2 Basic configuration The Timers are configured as follows: • See Table 530 for clocking and power control. • The Timer0/1/2/3 are reset by the TIMER0/1/2/3_RST (reset #32/33/34/35). • The Timer0/1/2/3 interrupts are connected to slot # 12/13/14/15 in the NVIC. Match channels 2 of Timer0/1/3 are connected to slots # 13, 14, 16 in the Event router. (These outputs are ORed with SCT outputs 2, 6, 14.) • For connecting the match channels 0 and 1 of Timer0/1/2/3 to the GPDMA, use the DMAMUX register in the CREG block (see Table 35) and enable the GPDMA channel in the DMA Channel Configuration registers (Section 16.6.20). • Inputs to Timer1/2/3 capture inputs are controlled by the CREG6 register in the CREG block (see Table 37). • The timer capture inputs and match outputs are configured through the GIMA (see Section 14.3). • All timer capture inputs are also connected to dedicated external pins (see Section 14.3 and Section 13.3.6). Table 530. Timer0/1/2/3 clocking and power control Base clock Branch clock Maximum frequency Clock to the timer0 register interface and timer0 peripheral clock PCLK. Clock to the timer1 register interface and timer1 peripheral clock PCLK. Clock to the timer2 register interface and timer2 peripheral clock PCLK. Clock to the timer3 register interface and timer3 peripheral clock PCLK. BASE_M3_CLK BASE_M3_CLK BASE_M3_CLK BASE_M3_CLK CLK_M3_TIMER0 150 MHz CLK_M3_TIMER1 150 MHz CLK_M3_TIMER2 150 MHz CLK_M3_TIMER3 150 MHz 25.3 Features • A 32 bit Timer/Counter with a programmable 32 bit Prescaler. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 621 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 25: LPC18xx Timer0/1/2/3 FT D R R A • Counter or Timer operation • Up to four 32 bit capture channels per timer, that can take a snapshot of the timer A FT D R A value when an input signal transitions. A capture event may also optionally generate an interrupt. FT D D R A R A FT D R FT D R A F R A FT D D R A FT • Four 32 bit match registers that allow: – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation. R A FT D R A • Up to four external outputs corresponding to match registers, with the following capabilities: – Set low on match. – Set high on match. – Toggle on match. – Do nothing on match. 25.4 General description The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an externally-supplied clock, and can optionally generate interrupts or perform other actions at specified timer values, based on four match registers. It also includes four capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. 25.5 Pin description Remark: The capture inputs are shared between four SCT inputs and the timer inputs. The timer match outputs are ORed with the SCT outputs (see Figure 24). Table 531. Timer0/1/2/3 pin description Function name Timer0 Direction Description CTIN_[2:0] CTOUT_[3:0] Timer1 I O CAP0_[2:0]; capture inputs 2 to 0 of timer 0. MAT0_[3:0]; match outputs 3:0 of timer 0 are ORed with SCT outputs 3 to 0. CAP1_0; capture input 0 of timer 1. CAP1_1; capture input 1 of timer 1. CAP1_2; capture input 2 of timer 1. MAT1_[3:0]; match outputs 3:0 of timer 1 are ORed with SCT outputs 7 to 4. CAP2_0; capture input 0 of timer 2. CAP2_1; capture input 1 of timer 2. CAP2_2; capture input 2 of timer 2. CTIN_0 CTIN_3 CTIN_4 CTOUT_[7:4] Timer2 I I I O CTIN_0 CTIN_1 CTIN_5 I I I All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 622 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 25: LPC18xx Timer0/1/2/3 FT D R A D R A R A FT D R FT Table 531. Timer0/1/2/3 pin description Function name Direction Description D R R A FT D R A F D A FT CTOUT_[11:8] Timer3 O MAT2_[3:0]; match outputs 3:0 of timer 2 are ORed with SCT outputs 11 to 8. R R A A FT D R A FT FT D CTIN_0 CTIN_6 CTIN_7 CTOUT_[15:12] I I I O CAP3_0; capture input 0 of timer 3. CAP3_1; capture input 1 of timer 3. CAP3_2; capture input 2 of timer 3. MAT3_[3:0]; match outputs 3:0 of timer 3 are ORed with SCT outputs 15 to 12. D R A Table 532 gives a brief summary of each of the Timer/Counter related pins. Table 532. Timer/Counter function description Pin Type Description CAP0_[3:0] CAP1_[3:0] CAP2_[3:0] CAP3_[3:0] Input Capture Signals- A transition on a capture pin can be configured to load one of the Capture Registers with the value in the Timer Counter and optionally generate an interrupt. Capture functionality can be selected from a number of pins. Timer/Counter block can select a capture signal as a clock source instead of the PCLK derived clock . For more details see Section 25.7.11. MAT0_[3:0] MAT1_[3:0] MAT2_[3:0] MAT3_[3:0] Output External Match Output - When a match register (MR3:0) equals the timer counter (TC) this output can either toggle, go LOW, go HIGH, or do nothing. The External Match Register (EMR) controls the functionality of this output. Match Output functionality can be selected on a number of pins in parallel. 25.6 DMA connections 25.7 Register description Each Timer/Counter contains the registers shown in Table 533. Table 533. Register overview: Timer0/1/2/3 (register base addresses 0x4008 4000 (TIMER0), 0x4008 5000 (TIMER1), 0x400C 3000 (TIMER2), 0x400C 4000 (TIMER3)) Name Access Address offset Description Reset value[1] IR TCR TC PR R/W R/W R/W R/W 0x000 0x004 0x008 0x00C Interrupt Register. The IR can be written to clear interrupts. The IR can be 0 read to identify which of eight possible interrupt sources are pending. Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. 0 Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. 0 The TC is controlled through the TCR. Prescale Register. The Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. 0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 623 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 25: LPC18xx Timer0/1/2/3 FT D R R A Table 533. Register overview: Timer0/1/2/3 (register base addresses 0x4008 4000 (TIMER0), 0x4008 5000 (TIMER1), 0x400C 3000 (TIMER2), 0x400C 4000 (TIMER3)) D R A R A FT D R FT D R A R A A FT F FT Name Access Address offset Description Reset value[1] D D R R A A FT FT PC R/W 0x010 Prescale Counter. The 32 bit PC is a counter which is incremented to the 0 value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. 0 D D R A FT D R A MCR MR0 R/W R/W 0x014 0x018 Match Register 0. MR0 can be enabled through the MCR to reset the TC, 0 stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. Match Register 1. See MR0 description. Match Register 2. See MR0 description. Match Register 3. See MR0 description. Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0(CAP0.0 or CAP1.0 respectively) input. Capture Register 1. See CR0 description. Capture Register 2. See CR0 description. Capture Register 3. See CR0 description. External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively). Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. 0 0 0 0 MR1 MR2 MR3 CCR R/W R/W R/W R/W 0x01C 0x020 0x024 0x028 CR0 CR1 CR2 CR3 EMR CTCR [1] RO RO RO RO R/W R/W 0x02C 0x030 0x034 0x038 0x03C 0x070 0 0 0 0 0 0 Reset value reflects the data stored in used bits only. It does not include reserved bits content. 25.7.1 Timer interrupt registers The Interrupt Register consists of four bits for the match interrupts and four bits for the capture interrupts. If an interrupt is generated then the corresponding bit in the IR will be high. Otherwise, the bit will be low. Writing a logic one to the corresponding IR bit will reset the interrupt. Writing a zero has no effect. The act of clearing an interrupt for a timer match also clears any corresponding DMA request. Table 534. Timer interrupt registers IR(IR - addresses 0x4008 4000 (TIMER0), 0x4008 5000 (TIMER1), 0x400C 3000 (TIMER3), 0x400C 4000 (TIMER4)) bit description Bit Symbol Description Reset value 0 1 2 3 4 5 MR0INT MR1INT MR2INT MR3INT CR0INT CR1INT Interrupt flag for match channel 0. Interrupt flag for match channel 1. Interrupt flag for match channel 2. Interrupt flag for match channel 3. Interrupt flag for capture channel 0 event. Interrupt flag for capture channel 1 event. 0 0 0 0 0 0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 624 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 25: LPC18xx Timer0/1/2/3 FT D R R A Table 534. Timer interrupt registers IR(IR - addresses 0x4008 4000 (TIMER0), 0x4008 5000 (TIMER1), 0x400C 3000 (TIMER3), 0x400C 4000 (TIMER4)) bit description D R A R A FT D R FT D R A R A A FT F FT Bit Symbol Description Reset value D D R R A A FT FT 6 7 31:8 CR2INT CR3INT - Interrupt flag for capture channel 2 event. Interrupt flag for capture channel 3 event. Reserved. 0 0 - D D R A FT D R A 25.7.2 Timer control registers The Timer Control Register (TCR) is used to control the operation of the Timer/Counter. Table 535. Timer control register TCR (TCR - addresses 0x4008 4004 (TIMER0), 0x4008 5004 (TIMER1), 0x400C 3003 (TIMER2), 0x400C 4004 (TIMER3)) bit description Bit Symbol Description Reset value 0 CEN When one, the Timer Counter and Prescale Counter are 0 enabled for counting. When zero, the counters are disabled. When one, the Timer Counter and the Prescale Counter 0 are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 1 CRST 31:2 - 25.7.3 Timer counter registers The 32-bit Timer Counter register is incremented when the prescale counter reaches its terminal count. Unless it is reset before reaching its upper limit, the Timer Counter will count up through the value 0xFFFF FFFF and then wrap back to the value 0x0000 0000. This event does not cause an interrupt, but a match register can be used to detect an overflow if needed. Table 536. Timer counter registers TC (TC - addresses 0x4008 4008 (TIMER0), 0x4008 5008 (TIMER1), 0x400C 3008 (TIMER2), 0x400C 4008 (TIMER3)) bit description Bit Symbol Description Reset value 31:0 TC Timer counter value. 0 25.7.4 Timer prescale registers The 32-bit Timer prescale register specifies the maximum value for the Prescale Counter. Table 537. Timer prescale registers PR (PR - addresses 0x4008 400C (TIMER0), 0x4008 500C (TIMER1), 0x400C 300C (TIMER2), 0x400C 400C (TIMER3)) bit description Bit Symbol Description Reset value 31:0 PM Prescale counter maximum value. 0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 625 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 25: LPC18xx Timer0/1/2/3 FT D R A D R A R A FT D R FT 25.7.5 Timer prescale counter registers D R The 32-bit Prescale Counter controls division of PCLK by some constant value before it is applied to the Timer Counter. This allows control of the relationship of the resolution of the timer versus the maximum time before the timer overflows. The Prescale Counter is incremented on every PCLK. When it reaches the value stored in the Prescale register, the Timer Counter is incremented and the Prescale Counter is reset on the next PCLK. This causes the Timer Counter to increment on every PCLK when PR = 0, every 2 PCLKs when PR = 1, etc. Table 538. Timer prescale counter registers PC(PC - addresses 0x4008 4010 (TIMER0), 0x4008 5010 (TIMER1), 0x400C 3010 (TIMER2), 0x400C 4010 (TIMER3)) bit description Bit Symbol Description Reset value R A FT D R R A F D R A FT D FT D R A A FT R A A FT D 31:0 PC Prescale counter value. 0 25.7.6 Timer match control registers The Match Control Register is used to control what operations are performed when one of the Match Registers matches the Timer Counter. The function of each of the bits is shown in Table 539. Table 539. Timer match control registers MCR (MCR - addresses 0x4008 4014 (TIMER0), 0x4008 5014 (TIMER1), 0x400C 3014 (TIMER2), 0x400C 4014 (TIMER3)) bit description Bit Symbol Value Description Reset value 0 MR0I 1 0 Interrupt on MR0 Interrupt is generated when MR0 matches the value in the TC. Interrupt is disabled Reset on MR0 1 0 TC will be reset if MR0 matches it. Feature disabled. Stop on MR0 TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. Feature disabled. Interrupt on MR1 1 0 Interrupt is generated when MR1 matches the value in the TC. Interrupt is disabled. Reset on MR1 1 0 TC will be reset if MR1 matches it. Feature disabled. Stop on MR1 1 0 TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. Feature disabled. 0 1 MR0R 0 2 MR0S 1 1 0 0 3 MR1I 0 4 MR1R 0 5 MR1S 0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 626 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 25: LPC18xx Timer0/1/2/3 FT D R R A Table 539. Timer match control registers MCR (MCR - addresses 0x4008 4014 (TIMER0), 0x4008 5014 (TIMER1), 0x400C 3014 (TIMER2), 0x400C 4014 (TIMER3)) bit description …continued D R A R A FT D R FT D R A R A FT D A F FT D R R A Bit Symbol Value Description Reset value A FT D FT D R 6 MR2I 1 0 Interrupt on MR2 Interrupt is generated when MR2 matches the value in the TC. Interrupt is disabled Reset on MR2 1 0 TC will be reset if MR2 matches it. Feature disabled. Stop on MR2. 1 0 TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC Feature disabled. Interrupt on MR3 1 0 Interrupt is generated when MR3 matches the value in the TC. This interrupt is disabled Reset on MR3 1 0 TC will be reset if MR3 matches it. Feature disabled. Stop on MR3 1 0 TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. Feature disabled. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0 A FT D R A 7 MR2R 0 8 MR2S 0 9 MR3I 0 10 MR3R 0 11 MR3S 0 31:12 - NA 25.7.7 Timer match registers (MR0 - MR3) The Match register values are continuously compared to the Timer Counter value. When the two values are equal, actions can be triggered automatically. The action possibilities are to generate an interrupt, reset the Timer Counter, or stop the timer. Actions are controlled by the settings in the MCR register. Table 540. Timer match registers MR0 to 3 (MR, addresses 0x4008 4018 (MR0) to 0x4008 4024 (M3) (TIMER0), 0x4008 5018 (MR0) to 0x4008 5024 (MR3)(TIMER1), 0x400C 3018 (MR0) to 0x400C 8024 (MR3) (TIMER2), 0x400C 4018 (MR0) to 0x400C 4024 (MR3)(TIMER3)) bit description Bit Symbol Description Reset value 31:0 MATCH Timer counter match value. 0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 627 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 25: LPC18xx Timer0/1/2/3 FT D R A D R A R A FT D R FT 25.7.8 Timer capture control registers D R The Capture Control Register is used to control whether one of the four Capture Registers is loaded with the value in the Timer Counter when the capture event occurs, and whether an interrupt is generated by the capture event. Setting both the rising and falling bits at the same time is a valid configuration, resulting in a capture event for both edges. In the description below, n represents the Timer number. D R A FT D Remark: If Counter mode is selected for a particular CAP input in the CTCR, the 3 bits for that input in this register should be programmed as 000, but capture and/or interrupt can be selected for the other 3 CAP inputs. Table 541. Timer capture control registers (CCR - addresses 0x4008 4028 (TIMER0), 0x4008 5020 (TIMER1), 0x400C 3028 (TIMER2), 0x400C 4028 (TIMER3)) bit description Bit Symbol Value Description Reset value R A FT R A F D R A FT D FT D R A R A A FT 0 CAP0RE 1 0 Capture on CAPn.0 rising edge A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC. This feature is disabled. Capture on CAPn.0 falling edge 1 0 A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC. This feature is disabled. Interrupt on CAPn.0 event 1 0 A CR0 load due to a CAPn.0 event will generate an interrupt. This feature is disabled. Capture on CAPn.1 rising edge 1 0 A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC. This feature is disabled. Capture on CAPn.1 falling edge 1 0 A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC. This feature is disabled. Interrupt on CAPn.1 event 1 0 A CR1 load due to a CAPn.1 event will generate an interrupt. This feature is disabled. Capture on CAPn.2 rising edge 1 0 A sequence of 0 then 1 on CAPn.2 will cause CR2 to be loaded with the contents of TC. This feature is disabled. Capture on CAPn.2 falling edge: 1 0 A sequence of 1 then 0 on CAPn.2 will cause CR2 to be loaded with the contents of TC. This feature is disabled. 0 1 CAP0FE 0 2 CAP0I 0 3 CAP1RE 0 4 CAP1FE 0 5 CAP1I 0 6 CAP2RE 0 7 CAP2FE 0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 628 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 25: LPC18xx Timer0/1/2/3 FT D R R A Table 541. Timer capture control registers (CCR - addresses 0x4008 4028 (TIMER0), 0x4008 5020 (TIMER1), 0x400C 3028 (TIMER2), 0x400C 4028 (TIMER3)) bit description …continued D R A R A FT D R FT D R A R A FT D R A F FT D R A Bit Symbol Value Description Reset value A FT D FT D R 8 CAP2I 1 0 Interrupt on CAPn.2 event A CR2 load due to a CAPn.2 event will generate an interrupt. This feature is disabled. Capture on CAPn.3 rising edge 1 0 A sequence of 0 then 1 on CAPn.3 will cause CR3 to be loaded with the contents of TC. This feature is disabled. Capture on CAPn.3 falling edge 1 0 A sequence of 1 then 0 on CAPn.3 will cause CR3 to be loaded with the contents of TC. This feature is disabled. Interrupt on CAPn.3 event: 1 0 A CR3 load due to a CAPn.3 event will generate an interrupt. This feature is disabled. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0 A FT D R A 9 CAP3RE 0 10 CAP3FE 0 11 CAP3I 0 31:12 - NA 25.7.9 Timer capture registers (CR0 - CR3) Each Capture register is associated with a device pin and may be loaded with the Timer Counter value when a specified event occurs on that pin. The settings in the Capture Control Register register determine whether the capture function is enabled, and whether a capture event happens on the rising edge of the associated pin, the falling edge, or on both edges. Table 542. Timer capture registers CR0 to 3 (CR, address 0x4008 402C (CR0) to 0x4008 4038 (CR3) (TIMER0), 0x4008 502C (CR0) to 0x4008 5038 (CR3) (TIMER1), 0x400C 302C (CR0) to 0x400C 3038 (CR3) (TIMER2), 0x400C 402C (CR0) to 0x400C 4038 (CR3) (TIMER3)) bit description Bit Symbol Description Reset value 31:0 CAP Timer counter capture value. 0 25.7.10 Timer external match registers The External Match Register provides both control and status of the external match pins. In the descriptions below, “n” represents the Timer number, 0 or 1, and “m” represent a Match number, 0 through 3. Match events for Match 0 and Match 1 in each timer can cause a DMA request, see Section 25.7.12. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 629 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 25: LPC18xx Timer0/1/2/3 FT D R R A Table 543. Timer external match registers (EMR - addresses 0x4008 403C (TIMER0), 0x4008 503C (TIMER1), 0x400C 303C (TIMER2), 0x400C 403C (TIMER3)) bit description D R A R A FT D R FT D R A R A FT D A A F FT D R R A Bit Symbol Value Description Reset value FT D A FT D R 0 EM0 External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high). External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). External Match Control 0. Determines the functionality of External Match 0. 0x0 0x1 0x2 0x3 Do Nothing. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). Toggle the corresponding External Match bit/output. External Match Control 1. Determines the functionality of External Match 1. 0x0 0x1 0x2 0x3 Do Nothing. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). Toggle the corresponding External Match bit/output. External Match Control 2. Determines the functionality of External Match 2. 0x0 0x1 0x2 0x3 Do Nothing. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). Toggle the corresponding External Match bit/output. 0 FT D R A 1 EM1 0 2 EM2 0 3 EM3 0 5:4 EMC0 00 7:6 EMC1 00 9:8 EMC2 00 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 630 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 25: LPC18xx Timer0/1/2/3 FT D R R A Table 543. Timer external match registers (EMR - addresses 0x4008 403C (TIMER0), 0x4008 503C (TIMER1), 0x400C 303C (TIMER2), 0x400C 403C (TIMER3)) bit description D R A R A FT D R FT D R A R A FT D A F FT D R R A Bit Symbol Value Description Reset value A FT D FT D R 11:10 EMC3 0x0 0x1 0x2 0x3 15:12 - External Match Control 3. Determines the functionality of External Match 3. Do Nothing. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). Toggle the corresponding External Match bit/output. 00 A FT D R A Reserved, user software should not write ones to reserved bits. NA The value read from a reserved bit is not defined. Table 544. External Match Control EMR[11:10], EMR[9:8], EMR[7:6], or EMR[5:4] Function 00 01 10 11 Do Nothing. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). Toggle the corresponding External Match bit/output. 25.7.11 Timer count control registers The Count Control Register (CTCR) is used to select between Timer and Counter mode, and in Counter mode to select the pin and edge(s) for counting. When Counter Mode is chosen as a mode of operation, the CAP input (selected by the CTCR bits 3:2) is sampled on every rising edge of the PCLK clock. After comparing two consecutive samples of this CAP input, one of the following four events is recognized: rising edge, falling edge, either of edges or no changes in the level of the selected CAP input. Only if the identified event corresponds to the one selected by bits 1:0 in the CTCR register, the Timer Counter register will be incremented. Effective processing of the externally supplied clock to the counter has some limitations. Since two successive rising edges of the PCLK clock are used to identify only one edge on the CAP selected input, the frequency of the CAP input can not exceed one quarter of the PCLK clock. Consequently, duration of the high/low levels on the same CAP input in this case can not be shorter than 1/(2 PCLK). All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 631 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 25: LPC18xx Timer0/1/2/3 FT D R R A Table 545. Timer count control register CTCR(CTCR - addresses 0x4008 4070 (TIMER0), 0x4008 5070 (TIMER1), 0x400C 3070 (TIMER2), 0x400C 4070 (TIMER3)) bit description D R A R A FT D R FT D R A R A FT D A F FT D R R A A Bit Symbol Value Description Reset value FT D R A FT D 1:0 CTMODE Counter/Timer Mode This field selects which rising PCLK edges can increment Timer’s Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register. 0x0 0x1 0x2 0x3 Timer Mode: every rising PCLK edge Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2. Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2. Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2. Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking: 0x0 0x1 0x2 0x3 CAPn.0 for TIMERn CAPn.1 for TIMERn CAPn.2 for TIMERn CAPn.3 for TIMERn Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer. 00 FT D R A 3:2 CINSEL 00 31:4 - - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 25.7.12 DMA operation DMA requests are generated by 0 to 1 transitions of the External Match 0 and 1 bits of each timer. In order to have an effect, the GPDMA must be configured and the relevant timer DMA request selected as a DMA source via the CREG block, see Table 35. When a timer is initially set up to generate a DMA request, the request may already be asserted before a match condition occurs. An initial DMA request may be avoided by having software by write a one to the interrupt flag location, as if clearing a timer interrupt. See Section 25.7.1. A DMA request will be cleared automatically when it is acted upon by the GPDMA controller. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 632 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 25: LPC18xx Timer0/1/2/3 FT D R A D R A R A FT D R FT 25.8 Example timer operation D R Figure 70 shows a timer configured to reset the count and generate an interrupt on match. The prescaler is set to 2 and the match register set to 6. At the end of the timer cycle where the match occurs, the timer count is reset. This gives a full length cycle to the match value. The interrupt indicating that a match occurred is generated in the next clock after the timer reached the match value. Figure 71 shows a timer configured to stop and generate an interrupt on match. The prescaler is again set to 2 and the match register set to 6. In the next clock after the timer reaches the match value, the timer enable bit in TCR is cleared, and the interrupt indicating that a match occurred is generated. R A FT D R A FT D R A F D R A FT D FT D R A R A A FT PCLK prescale counter timer counter timer counter reset interrupt 2 4 0 1 5 2 0 1 6 2 0 1 0 2 0 1 1 Fig 70. A timer cycle in which PR=2, MRx=6, and both interrupt and reset on match are enabled. PCLK prescale counter timer counter TCR[0] (counter enable) interrupt 2 4 0 1 5 1 2 0 6 0 Fig 71. A timer Cycle in Which PR=2, MRx=6, and both interrupt and stop on match are enabled 25.9 Architecture The block diagram for TIMER/COUNTER0 and TIMER/COUNTER1 is shown in Figure 72. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 633 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 25: LPC18xx Timer0/1/2/3 FT D R R A D R A R A FT D R FT D R A R A FT FT A F MATCH REGISTER 0 MATCH REGISTER 1 MATCH REGISTER 2 MATCH REGISTER 3 MATCH CONTROL REGISTER EXTERNAL MATCH REGISTER INTERRUPT REGISTER D D R A FT D R A FT D A FT D R A R CONTROL MAT[3:0] INTERRUPT CAP[3:0] STOP ON MATCH RESET ON MATCH LOAD[3:0] = = = = CAPTURE CONTROL REGISTER CAPTURE REGISTER 0 CAPTURE REGISTER 1 CAPTURE REGISTER 2 CAPTURE REGISTER 3 CSN TIMER COUNTER CE TCI PCLK PRESCALE COUNTER reset enable MAXVAL PRESCALE REGISTER TIMER CONTROL REGISTER Fig 72. Timer block diagram All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 634 of 1164 D R A FT D R A FT D R A FT D R A FT D R A FT UM10430 Rev. 00.13 — 20 July 2011 D D Chapter 26: LPC18xx Motor Control PWM (MOTOCONPWM) D R R A A FT FT D D R R A FT D R A FT D R A FT D FT D A D R A FT R A R A FT D R A FT D R A F R A FT D FT R User manual 26.1 How to read this chapter The Motor control PWM is available on all LPC18xx parts. D D R A FT D R A 26.2 Basic configuration The PWM is configured as follows: • See Table 546 for clocking and power control. • The PWM is reset by the MOTOCONPWM_RST (reset #38). • The PWM interrupt is connected to slot # 16 in the NVIC. Table 546. PWM clocking and power control Base clock Branch clock Maximum frequency Clock to the PWM Motor control block and BASE_APB1_ PWM Motocon peripheral clock. CLK CLK_APB1_ MOTOCON 150 MHz 26.3 Introduction The Motor Control PWM (MCPWM) is optimized for three-phase AC and DC motor control applications, but can be used in many other applications that need timing, counting, capture, and comparison. 26.4 Features The MCPWM contains three independent channels, each including: • • • • • • • a 32-bit Timer/Counter (TC) a 32-bit Limit register (LIM) a 32-bit Match register (MAT) a 10-bit dead-time register (DT) and an associated 10-bit dead-time counter a 32-bit capture register (CAP) two modulated outputs (MCOA and MCOB) with opposite polarities a period interrupt, a pulse-width interrupt, and a capture interrupt Input pins MCI0-2 can trigger TC capture or increment a channel’s TC. A global Abort input can force all of the channels into “A passive” state and cause an interrupt. 26.5 General description Section 26.8 includes detailed descriptions of the various modes of MCPWM operation, but a quick preview here will provide background for the register descriptions below. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 635 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 26: LPC18xx Motor Control PWM (MOTOCONPWM) FT D R R A The MCPWM includes 3 channels, each of which controls a pair of outputs that in turn can control something off-chip, like one set of coils in a motor. Each channel includes a Timer/Counter (TC) register that is incremented by a processor clock (timer mode) or by an input pin (counter mode). R A A FT D R A FT D Each channel has a Limit register that is compared to the TC value, and when a match occurs the TC is “recycled” in one of two ways. In “edge-aligned mode” the TC is reset to 0, while in “centered mode” a match switches the TC into a state in which it decrements on each processor clock or input pin transition until it reaches 0, at which time it starts counting up again. Each channel also includes a Match register that holds a smaller value than the Limit register. In edge-aligned mode the channel’s outputs are switched whenever the TC matches either the Match or Limit register, while in center-aligned mode they are switched only when it matches the Match register. So the Limit register controls the period of the outputs, while the Match register controls how much of each period the outputs spend in each state. Having a small value in the Limit register minimizes “ripple” if the output is integrated into a voltage, and allows the MCPWM to control devices that operate at high speed. The “downside” of small values in the Limit register is that they reduce the resolution of the duty cycle controlled by the Match register. If you have 8 in the Limit register, the Match register can only select the duty cycle among 0%, 12.5%, 25%, …, 87.5%, or 100%. In general, the resolution of each step in the Match value is 1 divided by the Limit value. This trade-off between resolution and period/frequency is inherent in the design of pulse width modulators. D R A R A FT D R FT D R A F R A FT D FT D R A D FT R A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 636 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 26: LPC18xx Motor Control PWM (MOTOCONPWM) FT D R A D R A R A FT D R FT 26.5.1 Block Diagram PCLK MCI0-2 D R R A FT D R R A F D R A FT A FT A FT D R A D FT D Clock selection TC0 Event selection Clock selection TC1 Event selection Clock selection TC2 Event selection R A MCCNTCON MCCAPCON RT0 cntl RT1 cntl RT2 cntl MAT0 (write) MAT0 (oper) LIM0 (write) LIM0 (oper) = CAP0 = MAT1 (write) MAT1 (oper) LIM1 (write) LIM1 (oper) = = mux ACMODE MAT2 (write) MAT2 (oper) LIM2 (write) LIM2 (oper) = = mux ACMODE CAP1 CAP2 interrupt logic MCABORT MCINTEN MCINTF ACMODE DT0 dead-time counter channel output control A0 MCCON MCCP MCABORT B0 MCCON DT1 dead-time counter mux ACMODE DT2 mux channel output control A1 B1 MCCON dead-time counter channel output control A2 B2 MCCON global output control MCOA0 MCOB0 MCOA1 MCOB1 MCOA2 MCOB2 Fig 73. MCPWM Block Diagram 26.6 Pin description Table 547 lists the MCPWM pins. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 637 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 26: LPC18xx Motor Control PWM (MOTOCONPWM) FT D R A D R A R A FT D R FT D Table 547. Pin summary Pin Type Description R R A FT D R A F D A FT MCOA0/1/2 MCOB0/1/2 MCABORT MCI0/1/2 O O I I Output A for channels 0, 1, 2 Output B for channels 0, 1, 2 Low-active Fast Abort Input for channels 0, 1, 2 R R A FT D R A FT D A FT D R A 26.7 Register description “Control” registers and “interrupt” registers have separate read, set, and clear addresses. Reading such a register’s read address (e.g. MCCON) yields the state of the register bits. Writing ones to the set address (e.g. MCCON_SET) sets register bit(s), and writing ones to the clear address (e.g. MCCON_CLR) clears register bit(s). The Capture registers (MCCAP) are read-only, and the write-only MCCAP_CLR address can be used to clear one or more of them. All the other MCPWM registers (MCTIM, MCPER, MCPW, MCDEADTIME, and MCCP) are normal read-write registers. Table 548. Register overview: Motor Control Pulse Width Modulator (MCPWM) (base address 0x400A 0000) Name Access Address offset Description Reset value CON CON_SET CON_CLR CAPCON CAPCON_SET CAPCON_CLR TC0 TC1 TC2 LIM0 LIM1 LIM2 MAT0 MAT1 MAT2 DT MCCP CAP0 CAP1 CAP2 INTEN INTEN_SET INTEN_CLR CNTCON RO WO WO RO WO WO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RO RO RO RO WO WO RO 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 0x024 0x028 0x02C 0x030 0x034 0x038 0x03C 0x040 0x044 0x048 0x04C 0x050 0x054 0x058 0x05C PWM Control read address PWM Control set address PWM Control clear address Capture Control read address Capture Control set address Event Control clear address Timer Counter register, channel 0 Timer Counter register, channel 1 Timer Counter register, channel 2 Limit register, channel 0 Limit register, channel 1 Limit register, channel 2 Match register, channel 0 Match register, channel 1 Match register, channel 2 Dead time register Communication Pattern register Capture register, channel 0 Capture register, channel 1 Capture register, channel 2 Interrupt Enable read address Interrupt Enable set address Interrupt Enable clear address Count Control read address 0 0 0 0 0 0xFFFF FFFF 0xFFFF FFFF 0xFFFF FFFF 0xFFFF FFFF 0xFFFF FFFF 0xFFFF FFFF 0x3FFF FFFF 0 0 0 0 0 0 © NXP B.V. 2011. All rights reserved. All information provided in this document is subject to legal disclaimers. User manual Rev. 00.13 — 20 July 2011 638 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 26: LPC18xx Motor Control PWM (MOTOCONPWM) FT D R R A Table 548. Register overview: Motor Control Pulse Width Modulator (MCPWM) (base address 0x400A 0000) D R A R A FT D R FT D R A R A A Name Access Address offset Description Reset value FT D R A F FT D R A CNTCON_SET CNTCON_CLR INTF INTF_SET INTF_CLR CAP_CLR WO WO RO WO WO WO 0x060 0x064 0x068 0x06C 0x070 0x074 Count Control set address Count Control clear address Interrupt flags read address Interrupt flags set address Interrupt flags clear address Capture clear address 0 - FT D R A FT D R A FT D 26.7.1 MCPWM Control register 26.7.1.1 MCPWM Control read address The CON register controls the operation of all channels of the PWM. This address is read-only, but the underlying register can be modified by writing to addresses CON_SET and CON_CLR. Table 549. MCPWM Control read address (CON - 0x400A 0000) bit description Bit Symbol Value Description Reset value 0 RUN0 0 1 Stops/starts timer channel 0. Stop. Run. Edge/center aligned operation for channel 0. 0 1 Edge-aligned. Center-aligned. Selects polarity of the MCOA0 and MCOB0 pins. 0 1 Passive state is LOW, active state is HIGH. Passive state is HIGH, active state is LOW. Controls the dead-time feature for channel 0. 0 1 Dead-time disabled. Dead-time enabled. Enable/disable updates of functional registers for channel 0 (see Section 26.8.2). 0 1 Functional registers are updated from the write registers at the end of each PWM cycle. Functional registers remain the same as long as the timer is running. Reserved. Stops/starts timer channel 1. 0 1 Stop. Run. Edge/center aligned operation for channel 1. 0 1 Edge-aligned. Center-aligned. 0 1 CENTER0 0 2 POLA0 0 3 DTE0 0 4 DISUP0 0 7:5 8 RUN1 - 0 9 CENTER1 0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 639 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 26: LPC18xx Motor Control PWM (MOTOCONPWM) FT D R A D R A R A FT D R FT Table 549. MCPWM Control read address (CON - 0x400A 0000) bit description Bit Symbol Value Description D R R A FT D R R A F D R A Reset value A FT A 10 POLA1 0 1 Selects polarity of the MCOA1 and MCOB1 pins. Passive state is LOW, active state is HIGH. Passive state is HIGH, active state is LOW. Controls the dead-time feature for channel 1. 0 1 Dead-time disabled. Dead-time enabled. Enable/disable updates of functional registers for channel 1 (see Section 26.8.2). 0 1 Functional registers are updated from the write registers at the end of each PWM cycle. Functional registers remain the same as long as the timer is running. Reserved. Stops/starts timer channel 2. 0 1 Stop. Run. Edge/center aligned operation for channel 2. 0 1 Edge-aligned. Center-aligned. Selects polarity of the MCOA2 and MCOB2 pins. 0 1 Passive state is LOW, active state is HIGH. Passive state is HIGH, active state is LOW. Controls the dead-time feature for channel 1. 0 1 Dead-time disabled. Dead-time enabled. Enable/disable updates of functional registers for channel 2 (see Section 26.8.2). 0 1 Functional registers are updated from the write registers at the end of each PWM cycle. Functional registers remain the same as long as the timer is running. Reserved. Controls the polarity of the MCOB outputs for all 3 channels. This bit is typically set to 1 only in 3-phase DC mode. 0 1 The MCOB outputs have opposite polarity from the MCOA outputs (aside from dead time). The MCOB outputs have the same basic polarity as the MCOA outputs. (see Section 26.8.6) 3-phase AC mode select (see Section 26.8.7). 0 1 3-phase AC-mode off: Each PWM channel uses its own timer-counter and period register. 3-phase AC-mode on: All PWM channels use the timer-counter and period register of channel 0. 0 FT D R A FT D R FT D 11 DTE1 0 A 12 DISUP1 0 15:13 16 RUN2 - 0 0 17 CENTER2 0 18 POLA2 0 19 DTE2 0 20 DISUP2 0 28:21 29 INVBDC - 30 ACMODE 0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 640 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 26: LPC18xx Motor Control PWM (MOTOCONPWM) FT D R A D R A R A FT D R FT Table 549. MCPWM Control read address (CON - 0x400A 0000) bit description Bit Symbol Value Description D R R A FT D R R A F D R A Reset value A FT A 31 DCMODE 0 1 3-phase DC mode select (see Section 26.8.6). 3-phase DC mode off: PWM channels are independent (unless bit ACMODE = 1) 3-phase DC mode on: The internal MCOA0 output is routed through the CP register (i.e. a mask) register to all six PWM outputs. 0 FT D R A FT D R A FT D 26.7.1.2 MCPWM Control set address Writing ones to this write-only address sets the corresponding bits in MCCON. Table 550. MCPWM Control set address (CON_SET - 0x400A 0004) bit description Bit Symbol Description Reset value 0 1 2 3 4 7:5 8 9 10 11 12 16 17 18 19 20 29 30 31 RUN0_SET CENTER0_SET POLA0_SET DTE0_SET DISUP0_SET RUN1_SET CENTER1_SET POLA1_SET DTE1_SET DISUP1_SET RUN2_SET CENTER2_SET POLA2_SET DTE2_SET DISUP2_SET INVBDC_SET ACMODE_SET DCMODE_SET Writing a one sets the corresponding bit in the CON register. Writing a one sets the corresponding bit in the CON register. Writing a one sets the corresponding bit in the CON register. Writing a one sets the corresponding bit in the CON register. Writing a one sets the corresponding bit in the CON register. Writing a one sets the corresponding bit in the CON register. Writing a one sets the corresponding bit in the CON register. Writing a one sets the corresponding bit in the CON register. Writing a one sets the corresponding bit in the CON register. Writing a one sets the corresponding bit in the CON register. Writing a one sets the corresponding bit in the CON register. Writing a one sets the corresponding bit in the CON register. Writing a one sets the corresponding bit in the CON register. Writing a one sets the corresponding bit in the CON register. Writing a one sets the corresponding bit in the CON register. Writing a one sets the corresponding bit in the CON register. Writing a one sets the corresponding bit in the CON register. Writing a one sets the corresponding bit in the CON register. Writing a one sets the corresponding bit in the CON register. Writing a one sets the corresponding bit in the CON register. Writing a one sets the corresponding bit in the CON register. - 15:13 - 28:21 - 26.7.1.3 MCPWM Control clear address Writing ones to this write-only address clears the corresponding bits in CON. Table 551. MCPWM Control clear address (CON_CLR - 0x400A 0008) bit description Bit Symbol Description Reset value 0 1 2 3 RUN0_CLR CENTER0_CLR POLA0_CLR DTE0_CLR Writing a one clears the corresponding bit in the CON register. Writing a one clears the corresponding bit in the CON register. Writing a one clears the corresponding bit in the CON register. Writing a one clears the corresponding bit in the CON register. © NXP B.V. 2011. All rights reserved. All information provided in this document is subject to legal disclaimers. User manual Rev. 00.13 — 20 July 2011 641 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 26: LPC18xx Motor Control PWM (MOTOCONPWM) FT D R R A Table 551. MCPWM Control clear address (CON_CLR - 0x400A 0008) bit description D R A R A FT D R FT D R A R A A Bit Symbol Description Reset value FT D R A F FT D R A 4 7:5 8 9 10 11 12 DISUP0_CLR RUN1_CLR CENTER1_CLR POLA1_CLR DTE1_CLR DISUP1_CLR Writing a one clears the corresponding bit in the CON register. Writing a one clears the corresponding bit in the CON register. Writing a one clears the corresponding bit in the CON register. Writing a one clears the corresponding bit in the CON register. Writing a one clears the corresponding bit in the CON register. Writing a one clears the corresponding bit in the CON register. Writing a one clears the corresponding bit in the CON register. Writing a one clears the corresponding bit in the CON register. Writing a one clears the corresponding bit in the CON register. Writing a one clears the corresponding bit in the CON register. Writing a one clears the corresponding bit in the CON register. Writing a one clears the corresponding bit in the CON register. Writing a one clears the corresponding bit in the CON register. Writing a one clears the corresponding bit in the CON register. Writing a one clears the corresponding bit in the CON register. Writing a one clears the corresponding bit in the CON register. Writing a one clears the corresponding bit in the CON register. FT D R A FT D R A FT D 15:1 3 16 17 18 19 20 RUN2_CLR CENTER2_CLR POLA2_CLR DTE2_CLR DISUP2_CLR 28:2 1 29 30 31 INVBDC_CLR ACMOD_CLR DCMODE_CLR 26.7.2 PWM Capture Control register 26.7.2.1 MCPWM Capture Control read address The MCCAPCON register controls detection of events on the MCI0-2 inputs for all MCPWM channels. Any of the three MCI inputs can be used to trigger a capture event on any or all of the three channels. This address is read-only, but the underlying register can be modified by writing to addresses CAPCON_SET and CAPCON_CLR. Table 552. MCPWM Capture Control read address (CAPCON - 0x400A 000C) bit description Bit Symbol Description Reset value 0 1 2 3 4 5 6 7 8 9 10 CAP0MCI0_RE CAP0MCI0_FE CAP0MCI1_RE CAP0MCI1_FE CAP0MCI2_RE CAP0MCI2_FE CAP1MCI0_RE CAP1MCI0_FE CAP1MCI1_RE CAP1MCI1_FE CAP1MCI2_RE A 1 in this bit enables a channel 0 capture event on a rising edge on MCI0. A 1 in this bit enables a channel 0 capture event on a falling edge on MCI0. A 1 in this bit enables a channel 0 capture event on a rising edge on MCI1. A 1 in this bit enables a channel 0 capture event on a falling edge on MCI1. A 1 in this bit enables a channel 0 capture event on a rising edge on MCI2. A 1 in this bit enables a channel 0 capture event on a falling edge on MCI2. A 1 in this bit enables a channel 1 capture event on a rising edge on MCI0. A 1 in this bit enables a channel 1 capture event on a falling edge on MCI0. A 1 in this bit enables a channel 1 capture event on a rising edge on MCI1. A 1 in this bit enables a channel 1 capture event on a falling edge on MCI1. A 1 in this bit enables a channel 1 capture event on a rising edge on MCI2. All information provided in this document is subject to legal disclaimers. 0 0 0 0 0 0 0 0 0 0 0 © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 642 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 26: LPC18xx Motor Control PWM (MOTOCONPWM) FT D R Table 552. MCPWM Capture Control read address (CAPCON - 0x400A 000C) bit description Bit Symbol Description D R A R A FT D R FT D A R R A FT D R R A F D R A Reset value A FT A 11 12 13 14 15 16 17 18 19 20 21 22 23 CAP1MCI2_FE CAP2MCI0_RE CAP2MCI0_FE CAP2MCI1_RE CAP2MCI1_FE CAP2MCI2_RE CAP2MCI2_FE RT0 RT1 RT2 HNFCAP0 HNFCAP1 HNFCAP2 A 1 in this bit enables a channel 1 capture event on a falling edge on MCI2. A 1 in this bit enables a channel 2 capture event on a rising edge on MCI0. A 1 in this bit enables a channel 2 capture event on a falling edge on MCI0. A 1 in this bit enables a channel 2 capture event on a rising edge on MCI1. A 1 in this bit enables a channel 2 capture event on a falling edge on MCI1. A 1 in this bit enables a channel 2 capture event on a rising edge on MCI2. A 1 in this bit enables a channel 2 capture event on a falling edge on MCI2. If this bit is 1, TC0 is reset by a channel 0 capture event. If this bit is 1, TC1 is reset by a channel 1 capture event. If this bit is 1, TC2 is reset by a channel 2 capture event. 0 0 FT D 0 0 0 0 0 0 0 0 Hardware noise filter: if this bit is 1, channel 0 capture events are delayed as described in 0 Section 26.8.4. Hardware noise filter: if this bit is 1, channel 1 capture events are delayed as described in 0 Section 26.8.4. Hardware noise filter: if this bit is 1, channel 2 capture events are delayed as described in 0 Section 26.8.4. Reserved. - FT D R A FT D R A 31:24 - 26.7.2.2 MCPWM Capture Control set address Writing ones to this write-only address sets the corresponding bits in CAPCON. Table 553. MCPWM Capture Control set address (CAPCON_SET - 0x400A 0010) bit description Bit Symbol Description Reset value 0 1 2 3 4 5 6 7 8 9 CAP0MCI0_RE_SET CAP0MCI0_FE_SET CAP0MCI1_RE_SET CAP0MCI1_FE_SET CAP0MCI2_RE_SET CAP0MCI2_FE_SET CAP1MCI0_RE_SET CAP1MCI0_FE_SET CAP1MCI1_RE_SET CAP1MCI1_FE_SET Writing a one sets the corresponding bits in the CAPCON register. Writing a one sets the corresponding bits in the CAPCON register. Writing a one sets the corresponding bits in the CAPCON register. Writing a one sets the corresponding bits in the CAPCON register. Writing a one sets the corresponding bits in the CAPCON register. Writing a one sets the corresponding bits in the CAPCON register. Writing a one sets the corresponding bits in the CAPCON register. Writing a one sets the corresponding bits in the CAPCON register. Writing a one sets the corresponding bits in the CAPCON register. Writing a one sets the corresponding bits in the CAPCON register. © NXP B.V. 2011. All rights reserved. All information provided in this document is subject to legal disclaimers. User manual Rev. 00.13 — 20 July 2011 643 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 26: LPC18xx Motor Control PWM (MOTOCONPWM) FT D R R A Table 553. MCPWM Capture Control set address (CAPCON_SET - 0x400A 0010) bit description D R A R A FT D R FT D R A R A FT A F FT Bit Symbol Description Reset value D D R R A A FT FT 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CAP1MCI2_RE_SET CAP1MCI2_FE_SET CAP2MCI0_RE_SET CAP2MCI0_FE_SET CAP2MCI1_RE_SET CAP2MCI1_FE_SET CAP2MCI2_RE_SET CAP2MCI2_FE_SET RT0_SET RT1_SET RT2_SET HNFCAP0_SET HNFCAP1_SET HNFCAP2_SET Writing a one sets the corresponding bits in the CAPCON register. Writing a one sets the corresponding bits in the CAPCON register. Writing a one sets the corresponding bits in the CAPCON register. Writing a one sets the corresponding bits in the CAPCON register. Writing a one sets the corresponding bits in the CAPCON register. Writing a one sets the corresponding bits in the CAPCON register. Writing a one sets the corresponding bits in the CAPCON register. Writing a one sets the corresponding bits in the CAPCON register. Writing a one sets the corresponding bits in the CAPCON register. Writing a one sets the corresponding bits in the CAPCON register. Writing a one sets the corresponding bits in the CAPCON register. Writing a one sets the corresponding bits in the CAPCON register. Writing a one sets the corresponding bits in the CAPCON register. Writing a one sets the corresponding bits in the CAPCON register. Reserved. - D D R A FT D R A 31:24 - 26.7.2.3 MCPWM Capture control clear address Writing ones to this write-only address clears the corresponding bits in MCCAPCON. Table 554. MCPWM Capture control clear register (CAPCON_CLR - address 0x400A 0014) bit description Bit Symbol Description Reset value 0 1 2 3 CAP0MCI0_RE_CLR CAP0MCI0_FE_CLR CAP0MCI1_RE_CLR CAP0MCI1_FE_CLR Writing a one clears the corresponding bits in the CAPCON register. Writing a one clears the corresponding bits in the CAPCON register. Writing a one clears the corresponding bits in the CAPCON register. Writing a one clears the corresponding bits in the CAPCON register. - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 644 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 26: LPC18xx Motor Control PWM (MOTOCONPWM) FT D R R A Table 554. MCPWM Capture control clear register (CAPCON_CLR - address 0x400A 0014) bit description D R A R A FT D R FT D R A R A A FT F FT Bit Symbol Description Reset value D D R R A A FT FT 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CAP0MCI2_RE_CLR CAP0MCI2_FE_CLR CAP1MCI0_RE_CLR CAP1MCI0_FE_CLR CAP1MCI1_RE_CLR CAP1MCI1_FE_CLR CAP1MCI2_RE_CLR CAP1MCI2_FE_CLR CAP2MCI0_RE_CLR CAP2MCI0_FE_CLR CAP2MCI1_RE_CLR CAP2MCI1_FE_CLR CAP2MCI2_RE_CLR CAP2MCI2_FE_CLR RT0_CLR RT1_CLR RT2_CLR HNFCAP0_CLR HNFCAP1_CLR HNFCAP2_CLR Writing a one clears the corresponding bits in the CAPCON register. Writing a one clears the corresponding bits in the CAPCON register. Writing a one clears the corresponding bits in the CAPCON register. Writing a one clears the corresponding bits in the CAPCON register. Writing a one clears the corresponding bits in the CAPCON register. Writing a one clears the corresponding bits in the CAPCON register. Writing a one clears the corresponding bits in the CAPCON register. Writing a one clears the corresponding bits in the CAPCON register. Writing a one clears the corresponding bits in the CAPCON register. Writing a one clears the corresponding bits in the CAPCON register. Writing a one clears the corresponding bits in the CAPCON register. Writing a one clears the corresponding bits in the CAPCON register. Writing a one clears the corresponding bits in the CAPCON register. Writing a one clears the corresponding bits in the CAPCON register. Writing a one clears the corresponding bits in the CAPCON register. Writing a one clears the corresponding bits in the CAPCON register. Writing a one clears the corresponding bits in the CAPCON register. Writing a one clears the corresponding bits in the CAPCON register. Writing a one clears the corresponding bits in the CAPCON register. Writing a one clears the corresponding bits in the CAPCON register. Reserved. - D D R A FT D R A 31:24 - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 645 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 26: LPC18xx Motor Control PWM (MOTOCONPWM) FT D R A D R A R A FT D R FT 26.7.3 MCPWM Timer/Counter 0-2 registers D R These registers hold the current values of the 32-bit counter/timers for channels 0-2. Each value is incremented on every PCLK, or by edges on the MCI0-2 pins, as selected by CNTCON. The timer/counter counts up from 0 until it reaches the value in its corresponding PER register (or is stopped by writing to CON_CLR). A TC register can be read at any time. In order to write to the TC register, its channel must be stopped. If not, the write will not take place, no exception is generated. Table 555. MCPWM Timer/Counter 0 to 2 registers (TC - 0x400A 0018 (TC0), 0x400A 001C (TC1), 0x400A 0020) (TC2)bit description Bit Symbol Description Reset value R A FT D R R A F D R A FT D FT D R A A FT R A A FT D 31:0 MCTC Timer/Counter value. 0 26.7.4 MCPWM Limit 0-2 registers These registers hold the limiting values for timer/counters 0-2. When a timer/counter reaches its corresponding limiting value: 1) in edge-aligned mode, it is reset and starts over at 0; 2) in center-aligned mode, it begins counting down until it reaches 0, at which time it begins counting up again. If the channel’s CENTER bit in CON is 0 selecting edge-aligned mode, the match between TC and LIM switches the channel’s A output from “active” to “passive” state. If the channel’s CENTER and DTE bits in CON are both 0, the match simultaneously switches the channel’s B output from “passive” to “active” state. If the channel’s CENTER bit is 0 but the DTE bit is 1, the match triggers the channel’s deadtime counter to begin counting -- when the deadtime counter expires, the channel’s B output switches from “passive” to “active” state. In center-aligned mode, matches between a channel’s TC and LIM registers have no effect on its A and B outputs. Writing to either a Limit or a Match (26.7.5) register loads a “write” register, and if the channel is stopped it also loads an “operating” register that is compared to the TC. If the channel is running and its “disable update” bit in CON is 0, the operating registers are loaded from the write registers: 1) in edge-aligned mode, when the TC matches the operating Limit register; 2) in center-aligned mode, when the TC counts back down to 0. If the channel is running and the “disable update” bit is 1, the operating registers are not loaded from the write registers until software stops the channel. Reading an LIM address always returns the operating value. Table 556. MCPWM Limit 0 to 2 registers (LIM - 0x400A 0024 (LIM0), 0x400A 0028 (LIM1), 0x400A 002C (LIM2)) bit description Bit Symbol Description Reset value 31:0 MCLIM Limit value. 0xFFFF FFFF Remark: In timer mode, the period of a channel’s modulated MCO outputs is determined by its Limit register, and the pulse width at the start of the period is determined by its Match register. If it suits your way of thinking, consider the Limit register to be the “Period register” and the Match register to be the “Pulse Width register”. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 646 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 26: LPC18xx Motor Control PWM (MOTOCONPWM) FT D R A D R A R A FT D R FT 26.7.5 MCPWM Match 0-2 registers D R These registers also have “write” and “operating” versions as described above for the Limit registers, and the operating registers are also compared to the channels’ TCs. See 26.7.4 above for details of reading and writing both Limit and Match registers. The Match and Limit registers control the MCO0-2 outputs. If a Match register is to have any effect on its channel’s operation, it must contain a smaller value than the corresponding Limit register. Table 557. MCPWM Match 0 to 2 registers (MAT - addresses 0x400A 0030 (MAT0), 0x400A 0034 (MAT1), 0x400A 0038 (MAT2)) bit description Bit Symbol Description Reset value R A FT D R R A F D R A FT D A FT D R A A FT R A FT D 31:0 MCMAT Match value. 0xFFFF FFFF 26.7.5.1 Match register in Edge-Aligned mode If the channel’s CENTER bit in CON is 0 selecting edge-aligned mode, a match between TC and MAT switches the channel’s B output from “active” to “passive” state. If the channel’s CENTER and DTE bits in CON are both 0, the match simultaneously switches the channel’s A output from “passive” to “active” state. If the channel’s CENTER bit is 0 but the DTE bit is 1, the match triggers the channel’s deadtime counter to begin counting -- when the deadtime counter expires, the channel’s A output switches from “passive” to “active” state. 26.7.5.2 Match register in Center-Aligned mode If the channel’s CENTER bit in CON is 1 selecting center-aligned mode, a match between TC and MAT while the TC is incrementing switches the channel’s B output from “active” to “passive” state, and a match while the TC is decrementing switches the A output from “active” to “passive”. If the channel’s CENTER bit in CON is 1 but the DTE bit is 0, a match simultaneously switches the channel’s other output in the opposite direction. If the channel’s CENTER and DTE bits are both 1, a match between TC and MAT triggers the channel’s deadtime counter to begin counting -- when the deadtime counter expires, the channel’s B output switches from “passive” to “active” if the TC was counting up at the time of the match, and the channel’s A output switches from “passive” to “active” if the TC was counting down at the time of the match. 26.7.5.3 0 and 100% duty cycle To lock a channel’s MCO outputs at the state “B active, A passive”, write its Match register with a higher value than you write to its Limit register. The match never occurs. To lock a channel’s MCO outputs at the opposite state, “A active, B passive”, simply write 0 to its Match register. 26.7.6 MCPWM Dead-time register This register holds the dead-time values for the three channels. If a channel’s DTE bit in CON is 1 to enable its dead-time counter, the counter counts down from this value whenever one its channel’s outputs changes from “active” to “passive” state. When the dead-time counter reaches 0, the channel changes its other output from “passive” to “active” state. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 647 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 26: LPC18xx Motor Control PWM (MOTOCONPWM) FT D R R A The motivation for the dead-time feature is that power transistors, like those driven by the A and B outputs in a motor-control application, take longer to fully turn off than they take to start to turn on. If the A and B transistors are ever turned on at the same time, a wasteful and damaging current will flow between the power rails through the transistors. In such applications, the dead-time register should be programmed with the number of PCLK periods that is greater than or equal to the transistors’ maximum turn-off time minus their minimum turn-on time. R A Table 558. MCPWM Dead-time register (DT - address 0x400A 003C) bit description Bit Symbol Description Reset value D R A R A FT D R FT D R A A FT D R A R A FT F FT D R A FT D D R A FT D 9:0 19:10 29:20 31:30 [1] [2] DT0 DT1 DT2 - Dead time for channel 0.[1] Dead time for channel Dead time for channel reserved 1.[2] 2.[2] 0x3FF 0x3FF 0x3FF If ACMODE is 1 selecting AC-mode, this field controls the dead time for all three channels. If ACMODE is 0. 26.7.7 MCPWM Communication Pattern register This register is used in DC mode only. The internal MCOA0 signal is routed to any or all of the six output pins under the control of the bits in this register. Like the Match and Limit registers, this register has “write” and “operational” versions. See 26.7.4 and 26.8.2 for more about this subject. Table 559. MCPWM Communication Pattern register (CP - address 0x400A 0040) bit description Bit Symbol Value Description Reset value 0 CCPA0 0 1 Communication pattern output A, channel 0. MCOA0 passive. internal MCOA0. Communication pattern output B, channel 0. 0 1 MCOB0 passive. MCOB0 tracks internal MCOA0. Communication pattern output A, channel 1. 0 1 MCOA1 passive. MCOA1 tracks internal MCOA0. Communication pattern output B, channel 1. 0 1 MCOB1 passive. MCOB1 tracks internal MCOA0. Communication pattern output A, channel 2. 0 1 MCOA2 passive. MCOA2 tracks internal MCOA0. Communication pattern output B, channel 2. 0 1 MCOB2 passive. MCOB2 tracks internal MCOA0. Reserved. All information provided in this document is subject to legal disclaimers. 0 1 CCPB0 0 2 CCPA1 0 3 CCPB1 0 4 CCPA2 0 5 CCPB2 0 31:6 - © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 648 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 26: LPC18xx Motor Control PWM (MOTOCONPWM) FT D R A D R A R A FT D R FT 26.7.8 MCPWM Capture read addresses D R The CAPCON register (Table 552) allows software to select any edge(s) on any of the MCI0-2 inputs as a capture event for each channel. When a channel’s capture event occurs, the current TC value for that channel is stored in its read-only Capture register. These addresses are read-only, but the underlying registers can be cleared by writing to the CAP_CLR address Table 560. MCPWM Capture read addresses (CAP - 0x400A 0044 (CAP0), 0x400A 0048 (CAP1), 0x400A 004C 9CAP2)) bit description Bit Symbol Description Reset value R A FT D R R A F D R A FT D A FT D R A A FT R A FT D 31:0 CAP Current TC value at a capture event. 0x0000 00 00 26.7.9 MCPWM Interrupt registers The Motor Control PWM module includes the following interrupt sources: Table 561. Motor Control PWM interrupts Symbol Description ILIM0/1/2 IMAT0/1/2 ICAP0/1/2 ABORT Limit interrupts for channels 0, 1, 2. Match interrupts for channels 0, 1, 2. Capture interrupts for channels 0, 1, 2. Fast abort interrupt 7.9.1 MCPWM Interrupt Enable read address The INTEN register controls which of the MCPWM interrupts are enabled. This address is read-only, but the underlying register can be modified by writing to addresses INTEN_SET and INTEN_CLR. Table 562. MCPWM Interrupt Enable read address (INTEN - 0x400A 0050) bit description Bit Symbol Value Description Reset value 0 ILIM0 0 1 Limit interrupt for channel 0. Interrupt disabled. Interrupt enabled. Match interrupt for channel 0. 0 1 Interrupt disabled. Interrupt enabled. Capture interrupt for channel 0. 0 1 Interrupt disabled. Interrupt enabled. Reserved. Limit interrupt for channel 1. 0 1 Interrupt disabled. Interrupt enabled. 0 1 IMAT0 0 2 ICAP0 0 3 4 ILIM1 0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 649 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 26: LPC18xx Motor Control PWM (MOTOCONPWM) FT D R R A Table 562. MCPWM Interrupt Enable read address (INTEN - 0x400A 0050) bit description D R A R A FT D R FT D R A R A A Bit Symbol Value Description Reset value FT D R A F FT D R A 5 IMAT1 0 1 Match interrupt for channel 1. Interrupt disabled. Interrupt enabled. Capture interrupt for channel 1. 0 1 Interrupt disabled. Interrupt enabled. Reserved. Limit interrupt for channel 2. 0 1 Interrupt disabled. Interrupt enabled. Match interrupt for channel 2. 0 1 Interrupt disabled. Interrupt enabled. Capture interrupt for channel 2. 0 1 Interrupt disabled. Interrupt enabled. Reserved. Fast abort interrupt. 0 1 Interrupt disabled. Interrupt enabled. Reserved. 0 FT D R A FT D R FT D 6 ICAP1 0 A 7 8 ILIM2 0 9 IMAT2 0 10 ICAP2 0 14:11 15 ABORT 0 31:16 - - 26.7.9.2 MCPWM Interrupt Enable set address Writing ones to this write-only address sets the corresponding bits in INTEN, thus enabling interrupts. Table 563. MCPWM interrupt enable set register (INTEN_SET - address 0x400A 0054) bit description Bit Symbol Description Reset value 0 1 2 3 4 5 6 ILIM0_SET IMAT0_SET ICAP0_SET ILIM1_SET IMAT1_SET ICAP1_SET Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. Reserved. Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 650 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 26: LPC18xx Motor Control PWM (MOTOCONPWM) FT D R R A Table 563. MCPWM interrupt enable set register (INTEN_SET - address 0x400A 0054) bit description D R A R A FT D R FT D R A R A FT A F FT Bit Symbol Description Reset value D D R R A A FT FT 7 9 10 11 ILIM2_SET IMAT2_SET ICAP2_SET Reserved. Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. Reserved. Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. Reserved. - D D R A FT D R A 14:12 15 ABORT_SET 31:16 - 26.7.9.3 MCPWM Interrupt Enable clear address Writing ones to this write-only address clears the corresponding bits in INTEN, thus disabling interrupts. Table 564. PWM interrupt enable clear register (INTEN_CLR - address 0x400A 0058) bit description Bit Symbol Description Reset value 0 1 2 3 4 5 6 7 8 9 10 ILIM0_CLR IMAT0_CLR ICAP0_CLR ILIM1_CLR IMAT1_CLR ICAP1_CLR ILIM2_CLR IMAT2_CLR ICAP2_CLR Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. Reserved. Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. Reserved. Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. Reserved. - 14:11 15 ABORT_CLR Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. Reserved. - 31:16 - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 651 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 26: LPC18xx Motor Control PWM (MOTOCONPWM) FT D R A D R A R A FT D R FT 26.7.9.4 MCPWM Interrupt Flags read address D R The INTF register includes all MCPWM interrupt flags, which are set when the corresponding hardware event occurs, or when ones are written to the INTF_SET address. When corresponding bits in this register and INTEN are both 1, the MCPWM asserts its interrupt request to the Interrupt Controller module. This address is read-only, but the bits in the underlying register can be modified by writing ones to addresses INTF_SET and INTF_CLR. Table 565. MCPWM Interrupt flags read address (INTF - 0x400A 0068) bit description Bit Symbol Value Description Reset value R A FT D R R A F D R A FT D A FT D R A A FT R A FT D 0 ILIM0_F 0 1 Limit interrupt flag for channel 0. This interrupt source is not contributing to the MCPWM interrupt request. If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. Match interrupt flag for channel 0. 0 1 This interrupt source is not contributing to the MCPWM interrupt request. If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. Capture interrupt flag for channel 0. 0 1 This interrupt source is not contributing to the MCPWM interrupt request. If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. Reserved. Limit interrupt flag for channel 1. 0 1 This interrupt source is not contributing to the MCPWM interrupt request. If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. Match interrupt flag for channel 1. 0 1 This interrupt source is not contributing to the MCPWM interrupt request. If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. Capture interrupt flag for channel 1. 0 1 This interrupt source is not contributing to the MCPWM interrupt request. If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. Reserved. 0 1 IMAT0_F 0 2 ICAP0_F 0 3 4 ILIM1_F 0 5 IMAT1_F 0 6 ICAP1_F 0 7 - - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 652 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 26: LPC18xx Motor Control PWM (MOTOCONPWM) FT D R R A Table 565. MCPWM Interrupt flags read address (INTF - 0x400A 0068) bit description D R A R A FT D R FT D R A R A A Bit Symbol Value Description Reset value FT D R A F FT D R A 8 ILIM2_F 0 1 Limit interrupt flag for channel 2. This interrupt source is not contributing to the MCPWM interrupt request. If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. Match interrupt flag for channel 2. 0 1 This interrupt source is not contributing to the MCPWM interrupt request. If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. Capture interrupt flag for channel 2. 0 1 This interrupt source is not contributing to the MCPWM interrupt request. If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. Reserved. Fast abort interrupt flag. 0 1 This interrupt source is not contributing to the MCPWM interrupt request. If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. Reserved. 0 FT D R A FT D R A FT D 9 IMAT2_F 0 10 ICAP2_F 0 14:11 15 ABORT_F 0 31:16 - - 26.7.9.5 MCPWM Interrupt Flags set address Writing one(s) to this write-only address sets the corresponding bit(s) in INTF, thus possibly simulating hardware interrupt(s). Table 566. MCPWM Interrupt Flags set address (INTF_SET - 0x400A 006C) bit description Bit Symbol Description Reset value 0 1 2 3 4 5 6 7 ILIM0_F_SET IMAT0_F_SET ICAP0_F_SET ILIM1_F_SET IMAT1_F_SET ICAP1_F_SET - Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. Reserved. Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. Reserved. - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 653 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 26: LPC18xx Motor Control PWM (MOTOCONPWM) FT D R R A Table 566. MCPWM Interrupt Flags set address (INTF_SET - 0x400A 006C) bit description D R A R A FT D R FT D R A R A A Bit Symbol Description Reset value FT D R A F FT D R A 8 9 10 ILIM2_F_SET IMAT2_F_SET ICAP2_F_SET Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. Reserved. - FT D R A FT D R A FT D 14:11 15 ABORT_F_SET Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. Reserved. 31:16 - 26.7.9.6 MCPWM Interrupt Flags clear address Writing one(s) to this write-only address sets the corresponding bit(s) in INTF, thus clearing the corresponding interrupt request(s). This is typically done in interrupt service routines. Table 567. MCPWM Interrupt Flags clear address (INTF_CLR - 0x400A 0070) bit description Bit Symbol Description Reset value 0 1 2 3 4 5 6 7 8 9 10 14:11 15 ILIM0_F_CLR IMAT0_F_CLR ICAP0_F_CLR ILIM1_F_CLR IMAT1_F_CLR ICAP1_F_CLR ILIM2_F_CLR IMAT2_F_CLR ICAP2_F_CLR ABORT_F_CLR Writing a one clears the corresponding bit in the INTF register, thus clearing the corresponding interrupt request. Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. Reserved. Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. Reserved. Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. Reserved. - 31:16 - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 654 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 26: LPC18xx Motor Control PWM (MOTOCONPWM) FT D R A D R A R A FT D R FT 26.7.10 MCPWM Count Control register 26.7.10.1 MCPWM Count Control read address D R The CNTCON register controls whether the MCPWM channels are in timer or counter mode, and in counter mode whether the counter advances on rising and/or falling edges on any or all of the three MCI inputs. If timer mode is selected, the counter advances based on the PCLK clock. FT R A FT D R R A F D R A FT D A FT A D R A FT D R A This address is read-only. To set or clear the register bits, write ones to the CNTCON_SET or CNTCON_CLR address. Table 568. MCPWM Count Control read address (CNTCON - 0x400A 005C) bit description Bit Symbol Value Description Reset value 0 TC0MCI0_RE 0 1 Counter 0 rising edge mode, channel 0. A rising edge on MCI0 does not affect counter 0. If MODE0 is 1, counter 0 advances on a rising edge on MCI0. Counter 0 falling edge mode, channel 0. 0 1 A falling edge on MCI0 does not affect counter 0. If MODE0 is 1, counter 0 advances on a falling edge on MCI0. Counter 0 rising edge mode, channel 1. 0 1 A rising edge on MCI1 does not affect counter 0. If MODE0 is 1, counter 0 advances on a rising edge on MCI1. Counter 0 falling edge mode, channel 1. 0 1 A falling edge on MCI1 does not affect counter 0. If MODE0 is 1, counter 0 advances on a falling edge on MCI1. Counter 0 rising edge mode, channel 2. 0 1 A rising edge on MCI0 does not affect counter 0. If MODE0 is 1, counter 0 advances on a rising edge on MCI2. Counter 0 falling edge mode, channel 2. 0 1 A falling edge on MCI0 does not affect counter 0. If MODE0 is 1, counter 0 advances on a falling edge on MCI2. Counter 1 rising edge mode, channel 0. 0 1 A rising edge on MCI0 does not affect counter 1. If MODE1 is 1, counter 1 advances on a rising edge on MCI0. Counter 1 falling edge mode, channel 0. 0 1 A falling edge on MCI0 does not affect counter 1. If MODE1 is 1, counter 1 advances on a falling edge on MCI0. Counter 1 rising edge mode, channel 1. 0 1 A rising edge on MCI1 does not affect counter 1. If MODE1 is 1, counter 1 advances on a rising edge on MCI1. Counter 1 falling edge mode, channel 1. 0 1 A falling edge on MCI0 does not affect counter 1. If MODE1 is 1, counter 1 advances on a falling edge on MCI1. 0 1 TC0MCI0_FE 0 2 TC0MCI1_RE 0 3 TC0MCI1_FE 0 4 TC0MCI2_RE 0 5 TC0MCI2_FE 0 6 TC1MCI0_RE 0 7 TC1MCI0_FE 0 8 TC1MCI1_RE 0 9 TC1MCI1_FE 0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 655 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 26: LPC18xx Motor Control PWM (MOTOCONPWM) FT D R Table 568. MCPWM Count Control read address (CNTCON - 0x400A 005C) bit description Bit Symbol Value Description D R A R A FT D R FT D A R R A FT D R R A F D R A Reset value A FT A 10 TC1MCI2_RE 0 1 Counter 1 rising edge mode, channel 2. A rising edge on MCI2 does not affect counter 1. If MODE1 is 1, counter 1 advances on a rising edge on MCI2. Counter 1 falling edge mode, channel 2. 0 1 A falling edge on MCI2 does not affect counter 1. If MODE1 is 1, counter 1 advances on a falling edge on MCI2. Counter 2 rising edge mode, channel 0. 0 1 A rising edge on MCI0 does not affect counter 2. If MODE2 is 1, counter 2 advances on a rising edge on MCI0. Counter 2 falling edge mode, channel 0. 0 1 A falling edge on MCI0 does not affect counter 2. If MODE2 is 1, counter 2 advances on a falling edge on MCI0. Counter 2 rising edge mode, channel 1. 0 1 A rising edge on MCI1 does not affect counter 2. If MODE2 is 1, counter 2 advances on a rising edge on MCI1. Counter 2 falling edge mode, channel 1. 0 1 A falling edge on MCI1 does not affect counter 2. If MODE2 is 1, counter 2 advances on a falling edge on MCI1. Counter 2 rising edge mode, channel 2. 0 1 A rising edge on MCI2 does not affect counter 2. If MODE2 is 1, counter 2 advances on a rising edge on MCI2. Counter 2 falling edge mode, channel 2. 0 1 A falling edge on MCI2 does not affect counter 2. If MODE2 is 1, counter 2 advances on a falling edge on MCI2. Reserved. Channel 0 counter/timer mode. 0 1 Channel 0 is in timer mode. Channel 0 is in counter mode. Channel 1 counter/timer mode. 0 1 Channel 1 is in timer mode. Channel 1 is in counter mode. Channel 2 counter/timer mode. 0 1 Channel 2 is in timer mode. Channel 2 is in counter mode. 0 FT D R A FT D R FT D 11 TC1MCI2_FE 0 A 12 TC2MCI0_RE 0 13 TC2MCI0_FE 0 14 TC2MCI1_RE 0 15 TC2MCI1_FE 0 16 TC2MCI2_RE 0 17 TC2MCI2_FE 0 28:18 29 CNTR0 - 0 30 CNTR1 0 31 CNTR2 0 26.7.10.2 MCPWM Count Control set address Writing one(s) to this write-only address sets the corresponding bit(s) in CNTCON. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 656 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 26: LPC18xx Motor Control PWM (MOTOCONPWM) FT D R R A Table 569. MCPWM Count Control set address (CNTCON_SET - 0x400A 0060) bit description D R A R A FT D R FT D R A R A A FT FT F Bit Symbol Description Reset value D D R R A A 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 TC0MCI0_RE_SET TC0MCI0_FE_SET TC0MCI1_RE_SET TC0MCI1_FE_SET TC0MCI2_RE_SET TC0MCI2_FE_SET TC1MCI0_RE_SET TC1MCI0_FE_SET TC1MCI1_RE_SET TC1MCI1_FE_SET TC1MCI2_RE_SET TC1MCI2_FE_SET TC2MCI0_RE_SET TC2MCI0_FE_SET TC2MCI1_RE_SET TC2MCI1_FE_SET TC2MCI2_RE_SET TC2MCI2_FE_SET Writing a one sets the corresponding bit in the CNTCON register. Writing a one sets the corresponding bit in the CNTCON register. Writing a one sets the corresponding bit in the CNTCON register. Writing a one sets the corresponding bit in the CNTCON register. Writing a one sets the corresponding bit in the CNTCON register. Writing a one sets the corresponding bit in the CNTCON register. Writing a one sets the corresponding bit in the CNTCON register. Writing a one sets the corresponding bit in the CNTCON register. Writing a one sets the corresponding bit in the CNTCON register. Writing a one sets the corresponding bit in the CNTCON register. Writing a one sets the corresponding bit in the CNTCON register. Writing a one sets the corresponding bit in the CNTCON register. Writing a one sets the corresponding bit in the CNTCON register. Writing a one sets the corresponding bit in the CNTCON register. Writing a one sets the corresponding bit in the CNTCON register. Writing a one sets the corresponding bit in the CNTCON register. Writing a one sets the corresponding bit in the CNTCON register. Writing a one sets the corresponding bit in the CNTCON register. Reserved. Writing a one sets the corresponding bit in the CNTCON register. Writing a one sets the corresponding bit in the CNTCON register. Writing a one sets the corresponding bit in the CNTCON register. - FT D R A FT D R A FT D 28:18 29 30 31 CNTR0_SET CNTR1_SET CNTR2_SET - 26.7.10.3 MCPWM Count Control clear address Writing one(s) to this write-only address clears the corresponding bit(s) in CNTCON. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 657 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 26: LPC18xx Motor Control PWM (MOTOCONPWM) FT D R R A Table 570. MCPWM Count Control clear address (CNTCON_CLR - 0x400A 0064) bit description D R A R A FT D R FT D R A R A FT D D A F FT Bit Symbol Description Reset value R R A A FT D FT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 TC0MCI0_RE_CLR Writing a one clears the corresponding bit in the CNTCON register. TC0MCI0_FE_CLR Writing a one clears the corresponding bit in the CNTCON register. D R A FT D R A TC0MCI1_RE_CLR Writing a one clears the corresponding bit in the CNTCON register. TC0MCI1_FE_CLR TC0MCI2_RE TC0MCI2_FE_CLR Writing a one clears the corresponding bit in the CNTCON register. Writing a one clears the corresponding bit in the CNTCON register. Writing a one clears the corresponding bit in the CNTCON register. TC1MCI0_RE_CLR Writing a one clears the corresponding bit in the CNTCON register. TC1MCI0_FE_CLR Writing a one clears the corresponding bit in the CNTCON register. TC1MCI1_RE_CLR Writing a one clears the corresponding bit in the CNTCON register. TC1MCI1_FE_CLR Writing a one clears the corresponding bit in the CNTCON register. TC1MCI2_RE_CLR Writing a one clears the corresponding bit in the CNTCON register. TC1MCI2_FE_CLR Writing a one clears the corresponding bit in the CNTCON register. TC2MCI0_RE_CLR Writing a one clears the corresponding bit in the CNTCON register. TC2MCI0_FE_CLR Writing a one clears the corresponding bit in the CNTCON register. TC2MCI1_RE_CLR Writing a one clears the corresponding bit in the CNTCON register. TC2MCI1_FE_CLR Writing a one clears the corresponding bit in the CNTCON register. TC2MCI2_RE_CLR Writing a one clears the corresponding bit in the CNTCON register. TC2MCI2_FE_CLR Writing a one clears the corresponding bit in the CNTCON register. Reserved. Writing a one clears the corresponding bit in the CNTCON register. Writing a one clears the corresponding bit in the CNTCON register. Writing a one clears the corresponding bit in the CNTCON register. 28:18 29 30 31 CNTR0_CLR CNTR1_CLR CNTR2_CLR All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 658 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 26: LPC18xx Motor Control PWM (MOTOCONPWM) FT D R A D R A R A FT D R FT 26.7.11 MCPWM Capture clear address Writing ones to this write-only address clears the selected CAP register(s). D R Table 571. MCPWM Capture clear address (CAP_CLR - 0x400A 0074) bit description Bit Symbol Description R A FT D R R A F D R A FT A FT A FT D R A D FT 0 1 2 31:3 CAP_CLR0 CAP_CLR1 CAP_CLR2 - Writing a 1 to this bit clears the CAP0 register. Writing a 1 to this bit clears the CAP1 register. Writing a 1 to this bit clears the CAP2 register. Reserved D R A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 659 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 26: LPC18xx Motor Control PWM (MOTOCONPWM) FT D R A D R A R A FT D R FT 26.8 Functional description 26.8.1 Pulse-width modulation D R Each channel of the MCPWM has two outputs, A and B, that can drive a pair of transistors to switch a controlled point between two power rails. Most of the time the two outputs have opposite polarity, but a dead-time feature can be enabled (on a per-channel basis) to delay both signals’ transitions from “passive” to “active” state so that the transistors are never both turned on simultaneously. In a more general view, the states of each output pair can be thought of “high”, “low”, and “floating” or “up”, “down”, and “center-off”. Each channel’s mapping from “active” and “passive” to “high” and “low” is programmable. After Reset, the three A outputs are passive/low, and the B outputs are active/high. The MCPWM can perform edge-aligned and center-aligned pulse-width modulation. Remark: In timer mode, the period of a channel’s modulated MCO outputs is determined by its Limit register, and the pulse width at the start of the period is determined by its Match register. If it suits your way of thinking, consider the Limit register to be the “Period register” and the Match register to be the “Pulse Width register”. Edge-aligned PWM without dead-time In this mode the timer TC counts up from 0 to the value in the LIM register. As shown in Figure 74, the MCO state is “A passive” until the TC matches the Match register, at which point it changes to “A active”. When the TC matches the Limit register, the MCO state changes back to “A passive”, and the TC is reset and starts counting up again. D R A FT D R R A F D R A FT A FT A FT R A D FT D R A active passive active passive MCOB passive active passive active MCOA POLA = 0 0 MAT LIM timer reset MAT LIM timer reset Fig 74. Edge-aligned PWM waveform without dead time, POLA = 0 Center-aligned PWM without dead-time In this mode the timer TC counts up from 0 to the value in the LIM register, then counts back down to 0 and repeats. As shown in Figure 75, while the timer counts up, the MCO state is “A passive” until the TC matches the Match register, at which point it changes to “A active”. When the TC matches the Limit register it starts counting down. When the TC matches the Match register on the way down, the MCO state changes back to “A passive”. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 660 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 26: LPC18xx Motor Control PWM (MOTOCONPWM) FT D R R A D R A active R A FT D R FT D R A R A FT FT A passive F active passive D D R A FT R A FT MCOB D D R A FT D R passive active passive active A MCOA POLA = 0 0 MAT LIM MAT 0 LIM Fig 75. Center-aligned PWM waveform without dead time, POLA = 0 Dead-time counter When the a channel’s DTE bit is set in CON, the dead-time counter delays the passive-to-active transitions of both MCO outputs. The dead-time counter starts counting down, from the channel’s DT value (in the DT register) to 0, whenever the channel’s A or B output changes from active to passive. The transition of the other output from passive to active is delayed until the dead-time counter reaches 0. During the dead time, the MCOA and MCOB output levels are both passive. Figure 76 shows operation in edge aligned mode with dead time, and Figure 77 shows center-aligned operation with dead time. active passive MCOB active passive DT DT active passive MCOA passive active POLA = 0 DT 0 MAT LIM timer reset MAT DT LIM timer reset Fig 76. Edge-aligned PWM waveform with dead time, POLA = 0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 661 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 26: LPC18xx Motor Control PWM (MOTOCONPWM) FT D R R A D R A R A FT D R FT D R A R A FT FT A F active passive active D passive D R A FT D R A FT D MCOB DT R A FT D R A active passive MCOA DT 0 MAT LIM MAT 0 LIM passive active POLA = 0 DT Fig 77. Center-aligned waveform with dead time, POLA = 0 26.8.2 Shadow registers and simultaneous updates The Limit, Match, and Communication Pattern registers (LIM, MAT, and CP) are implemented as register pairs, each consisting of a write register and an operational register. Software writes into the write registers. The operational registers control the actual operation of each channel and are loaded with the current value in the write registers when the TC starts counting up from 0. Updating of the functional registers can be disabled by setting a channel’s DISUP bit in the CON register. If the DISUP bits are set, the functional registers are not updated until software stops the channel. If a channel is not running when software writes to its LIM or MAT register, the functional register is updated immediately. Software can write to a TC register only when its channel is stopped. 26.8.3 Fast Abort (ABORT) The MCPWM has an external input MCABORT. When this input goes low, all six MCO outputs assume their “A passive” states, and the Abort interrupt is generated if enabled. The outputs remain locked in “A passive” state until the ABORT interrupt flag is cleared or the Abort interrupt is disabled. The ABORT flag may not be cleared before the MCABORT input goes high. In order to clear an ABORT flag, a 1 must be written to bit 15 of the INTF_CLR register. This will remove the interrupt request. The interrupt can also be disabled by writing a 1 to bit 15 of the INTEN_CLR register. 26.8.4 Capture events Each PWM channel can take a snapshot of its TC when an input signal transitions. Any channel may use any combination of rising and/or falling edges on any or all of the MCI0-2 inputs as a capture event, under control of the CAPCON register. Rising or falling edges on the inputs are detected synchronously with respect to PCLK. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 662 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 26: LPC18xx Motor Control PWM (MOTOCONPWM) FT D R R A If a channel’s HNF bit in the CAPCON register is set to enable “noise filtering”, a selected edge on an MCI pin starts the dead-time counter for that channel, and the capture event actions described below are delayed until the dead-time counter reaches 0. This function is targeted specifically for performing three-phase brushless DC motor control with Hall sensors. R A A capture event on a channel (possibly delayed by HNF) causes the following: • The current value of the TC is stored in the Capture register (CAP). • If the channel’s capture event interrupt is enabled (see Table 562), the capture event interrupt flag is set. • If the channel’s RT bit is set in the CAPCON register, enabling reset on a capture event, the input event has the same effect as matching the channel’s TC to its LIM register. This includes resetting the TC and switching the MCO pin(s) in edge-aligned mode as described in 26.7.4 and 26.8.1. D R A R A FT D R FT D R A A FT D R A R A FT F FT D R A FT D D R A FT D 26.8.5 External event counting (Counter mode) If a channel’s MODE bit is 1 in CNTCON, its TC is incremented by rising and/or falling edge(s) (synchronously detected) on the MCI0-2 input(s), rather than by PCLK. The PWM functions and capture functions are unaffected. 26.8.6 Three-phase DC mode The three-phase DC mode is selected by setting the DCMODE bit in the CON register. In this mode, the internal MCOA0 signal can be routed to any or all of the MCO outputs. Each MCO output is masked by a bit in the current commutation pattern register CP. If a bit in the CP register is 0, its output pin has the logic level for the passive state of output MCOA0. The polarity of the off state is determined by the POLA0 bit. All MCO outputs that have 1 bits in the CP register are controlled by the internal MCOA0 signal. The three MCOB output pins are inverted when the INVBDC bit is 1 in the CON register. This feature accommodates bridge-drivers that have active-low inputs for the low-side switches. The CP register is implemented as a shadow register pair, so that changes to the active communication pattern occur at the beginning of a new PWM cycle. See 26.7.4 and 26.8.2 for more about writing and reading such registers. Figure 78 shows sample waveforms of the MCO outputs in three-phase DC mode. Bits 1 and 3 in the CP register (corresponding to outputs MCOB1 and MCOB0) are set to 0 so that these outputs are masked and in the off state. Their logic level is determined by the POLA0 bit (here, POLA0 = 0 so the passive state is logic LOW). The INVBDC bit is set to 0 (logic level not inverted) so that the B output have the same polarity as the A outputs. Note that this mode differs from other modes in that the MCOB outputs are not the opposite of the MCOA outputs. In the situation shown in Figure 78, bits 0, 2, 4, and 5 in the CP register are set to 1. That means that MCOA1 and both MCO outputs for channel 2 follow the MCOA0 signal. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 663 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 26: LPC18xx Motor Control PWM (MOTOCONPWM) FT D R R A D R A R A FT D R FT D R A R A FT FT D R D A F R MCOB2 A CCPB2 = 1, on-state MCOA2 CCPA2 = 1, on-state A FT D R A FT D R A FT D MCOB1 CCPB1 = 0, off-state MCOA1 CCPA1 = 1, on-state MCOB0 CCPB0 = 0, off-state CCPA0 = 1, on-state MCOA0 POLA0 = 0, INVBDC = 0 Fig 78. Three-phase DC mode sample waveforms 26.8.7 Three phase AC mode The three-phase AC-mode is selected by setting the ACMODE bit in the CON register. In this mode, the value of channel 0’s TC is routed to all channels for comparison with their MAT registers. (The LIM1-2 registers are not used.) Each channel controls its MCO output by comparing its MAT value to TC0. Figure 79 shows sample waveforms for the six MCO outputs in three-phase AC mode. The POLA bits are set to 0 for all three channels, so that for all MCO outputs the active levels are high and the passive levels are low. Each channel has a different MAT value which is compared to the TC0 value. In this mode the period value is identical for all three channels and is determined by LIM0. The dead-time mode is disabled. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 664 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 26: LPC18xx Motor Control PWM (MOTOCONPWM) FT D R R A D R A R A FT D R FT D R A R A FT FT D R A FT D D A F R A FT D MCOB2 R A FT D R A POLA2 = 0 MCOA2 MAT2 MAT2 MCOB1 MCOA1 MAT1 MAT1 POLA1 = 0 MCOB0 MCOA0 POLA0 = 0 0 MAT0 LIM0 timer reset LIM0 timer reset Fig 79. Three-phase AC mode sample waveforms, edge aligned PWM mode 26.8.8 Interrupts The MCPWM includes 10 possible interrupt sources: • When any channel’s TC matches its Match register. • When any channel’s TC matches its Limit register. • When any channel captures the value of its TC into its Capture register, because a selected edge occurs on any of MCI0-2. • When all three channels’ outputs are forced to “A passive” state because the MCABORT pin goes low. Section 26.7.9 “MCPWM Interrupt registers” explains how to enable these interrupts, and Section 26.7.2 “PWM Capture Control register” describes how to map edges on the MCI0-2 inputs to “capture events” on the three channels. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 665 of 1164 D R A FT D R A FT D R A FT D R A FT D R A FT UM10430 Rev. 00.13 — 20 July 2011 D D Chapter 27: LPC18xx Quadrature Encoder Interface (QEI) D R R A A FT FT D D R A FT D R A FT D R A FT D FT D R A D R A FT R A R A FT D R A FT D R A F R A FT D FT R User manual 27.1 How to read this chapter The QEI is available on all LPC18xx parts. D D R A FT D R A 27.2 Basic configuration The QEI is configured as follows: • See Table 572 for clocking and power control. • The QEI is reset by the QEI_RST (reset #39). • The QEI interrupt is connected to slot # 15 in the Event router. Table 572. QEI clocking and power control Base clock Branch clock Maximum frequency Clock to the QEI register interface and QEI BASE_M3_CLK peripheral clock. CLK_M3_QEI 150 MHz 27.3 Features This Quadrature Encoder Interface (QEI) has the following features: • • • • • • • • • • tracks encoder position. increments/ decrements depending on direction. programmable for 2X or 4X position counting. velocity capture using built-in timer. velocity compare function with less than interrupt. uses 32-bit registers for position and velocity. three position compare registers with interrupts. index counter for revolution counting. index compare register with interrupts. can combine index and position interrupts to produce an interrupt for whole and partial revolution displacement. • digital filter with programmable delays for encoder input signals. • can accept decoded signal inputs (clock and direction). All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 666 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 27: LPC18xx Quadrature Encoder Interface (QEI) FT D R A D R A R A FT D R FT 27.4 Introduction D R A quadrature encoder, also known as a 2-channel incremental encoder, converts angular displacement into two pulse signals. By monitoring both the number of pulses and the relative phase of the two signals, you can track the position, direction of rotation, and velocity. In addition, a third channel, or index signal, can be used to reset the position counter. This quadrature encoder interface module decodes the digital pulses from a quadrature encoder wheel to integrate position over time and determine direction of rotation. In addition, it can capture the velocity of the encoder wheel. R A FT D R A FT D R A F D R A FT D FT D R A R A A FT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 667 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 27: LPC18xx Quadrature Encoder Interface (QEI) FT D R R A D R A R A FT D R FT D R A R A FT FT D R D A F R gating Fig 80. Encoder interface block diagram i dx Inx Inx_ pulse rst Velocity Timer A Phb PC LK Digital Filter Quad Decoder Windowing MaxPos Compare Pha dir A tim _int FT D R A FT D R FT D rst Velocity Reload A Velocity Compare velc _int rst Velocity Capture err _int Velocity Counter inx _int dir _int enclk _int max _pos _int clk _ pulse Position Counter Position Compare pos 0rev _int pos 1rev _int pos 2rev _int Index Counter pos 0rev _int pos 1rev _int pos 2rev _int Index Compare rev 0_ int rev 1_ int rev 2_ int All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 668 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 27: LPC18xx Quadrature Encoder Interface (QEI) FT D R A D R A R A FT D R FT 27.5 Pin description Table 573. QEI pin description Pin name I/O Description D R R A FT D R R A F D R A FT A FT A FT D R D QEI_A QEI_B QEI_IDX I I I Used as the Phase A (PhA) input to the Quadrature Encoder Interface. Used as the Phase B (PhB) input to the Quadrature Encoder Interface. Used as the Index (IDX) input to the Quadrature Encoder Interface. A FT D R A 27.6 Register description Table 574. Register overview: QEI (base address 0x400C 6000) Name Access Address offset Description Reset value Control registers CON STAT CONF POS MAXPOS CMPOS0 CMPOS1 CMPOS2 INXCNT INXCMP0 LOAD TIME VEL CAP VELCOMP FILTERPHA FILTERPHB FILTERINX WINDOW INXCMP1 INXCMP2 IEC IES INTSTAT WO RO R/W RO R/W R/W R/W R/W RO R/W R/W RO RO RO R/W R/W R/W R/W R/W R/W R/W WO WO RO 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 0x024 0x028 0x02C 0x030 0x034 0x038 0x03C 0x040 0x044 0x048 0x04C 0x050 0xFD8 0xFDC 0xFE0 Control register Encoder status register Configuration register Position register Maximum position register position compare register 0 position compare register 1 position compare register 2 Index count register Index compare register 0 Velocity timer reload register Velocity timer register Velocity counter register Velocity capture register Velocity compare register Digital filter register on input phase A (QEI_A) Digital filter register on input phase B (QEI_B) Digital filter register on input index (QEI_IDX) Index acceptance window register Index compare register 1 Index compare register 2 Interrupt enable clear register Interrupt enable set register Interrupt status register 0 0 0x000F 0000 0 0 0xFFFF FFFF 0xFFFF FFFF 0xFFFF FFFF 0 0xFFFF FFFF 0xFFFF FFFF 0xFFFF FFFF 0 0xFFFF FFFF 0 0 0 0 0x0000 0000 0xFFFF FFFF 0xFFFF FFFF 0 0 0 Position, index, and timer registers Interrupt registers All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 669 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 27: LPC18xx Quadrature Encoder Interface (QEI) FT D R A D R A R A FT D R FT Table 574. Register overview: QEI (base address 0x400C 6000) Name Access Address offset Description D R Reset value R A FT D R R A F D R A A FT A IE CLR SET RO WO WO 0xFE4 0xFE8 0xFEC Interrupt enable register Interrupt status clear register Interrupt status set register 0 0 0 FT D R A FT D R A FT D All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 670 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 27: LPC18xx Quadrature Encoder Interface (QEI) FT D R A D R A R A FT D R FT 27.6.1 Control registers 27.6.1.1 QEI Control register D R This register contains bits which control the operation of the position and velocity counters of the QEI module. FT D Table 575: QEI Control register (CON - address 0x400C 6000) bit description Bit Symbol Description Reset value R A FT D R R A F D R A FT D R A FT D R A A FT A 0 1 RESP RESPI Reset position counter. When set = 1, resets the position counter to all zeros. Autoclears when the position counter is cleared. Reset position counter on index. When set = 1, resets the position counter to all zeros when an index pulse occurs. Autoclears when the position counter is cleared. 0 0 2 RESV Reset velocity. When set = 1, resets the velocity counter to all zeros 0 and reloads the velocity timer. Autoclears when the velocity counter is cleared. Reset index counter. When set = 1, resets the index counter to all zeros. Autoclears when the index counter is cleared. reserved 0 0 3 31:4 RESI - 27.6.1.2 QEI Configuration register This register contains the configuration of the QEI module. Table 576: QEI Configuration register (CONF - address 0x400C 6008) bit description Bit Symbol Description Reset value 0 1 DIRINV SIGMODE Direction invert. When = 1, complements the DIR bit. Signal Mode. When = 0, PhA and PhB function as quadrature encoder inputs. When = 1, PhA functions as the direction signal and PhB functions as the clock signal. 0 0 2 CAPMODE Capture Mode. When = 0, only PhA edges are counted (2X). When = 1, BOTH PhA and PhB edges are counted (4X), increasing resolution but decreasing range. INVINX CRESPI Invert Index. When set, inverts the sense of the index input. Continuously reset position counter on index. When set = 1, resets the position counter to all zeros when an index pulse occurs at the next position increase (recalibration). Auto-clears when the position counter is cleared. Reserved Index gating configuration: when INXGATE(19)=1, pass the index when Pha=0 and Phb=0, else block. when INXGATE(18)=1, pass the index when Pha=0 and Phb=1, else block. when INXGATE(17)=1, pass the index when Pha=1 and Phb=1, else block. when INXGATE(16)=1, pass the index when Pha=1 and Phb=0, else block. reserved 0 3 4 0 0 15:5 19:16 INXGATE 0 1111 31:20 - 0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 671 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 27: LPC18xx Quadrature Encoder Interface (QEI) FT D R A D R A R A FT D R FT 27.6.1.3 QEI Status register This register provides the status of the encoder interface. D R Table 577: QEI Interrupt Status register (STAT - address 0x400C 6004) bit description Bit Symbol Description R A FT D R R A F D R A FT A FT Reset value A FT D R A D FT D 0 31:1 DIR - Direction bit. In combination with DIRINV bit indicates forward or reverse direction. See Table 604. reserved 0 R A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 672 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 27: LPC18xx Quadrature Encoder Interface (QEI) FT D R A D R A R A FT D R FT 27.6.2 Position, index and timer registers 27.6.2.1 QEI Position register D R This register contains the current value of the encoder position. Increments or decrements when encoder counts occur, depending on the direction of rotation. FT D Table 578. QEI Position register (POS - address 0x400C 600C) bit description Bit Symbol Description Reset value R A FT D R R A F D R A FT D R A FT D R A A FT A 31:0 POS Current position value. 0 27.6.2.2 QEI Maximum Position register This register contains the maximum value of the encoder position. In forward rotation the position register resets to zero when the position register exceeds this value. In reverse rotation the position register resets to this value when the position register decrements from zero. Table 579. QEI Maximum Position register (MAXPOS - address 0x400C 6010) bit description Bit Symbol Description Reset value 31:0 MAXPOS Maximum position value. 0 27.6.2.3 QEI Position Compare register 0 This register contains a position compare value. This value is compared against the current value of the position register. Interrupts can be enabled to interrupt when the compare value is less than, equal to, or greater than the current value of the position register. Table 580. QEI Position Compare register 0 (CMPOS0 - address 0x400C 6014) bit description Bit Symbol Description Reset value 31:0 PCMP0 Position compare value 0. 0xFFFF FFFF 27.6.2.4 QEI Position Compare register 1 This register contains a position compare value. This value is compared against the current value of the position register. Interrupts can be enabled to interrupt when the compare value is less than, equal to, or greater than the current value of the position register. Table 581. QEI Position Compare register 1 (CMPOS1 - address 0x400C 6018) bit description Bit Symbol Description Reset value 31:0 PCMP1 Position compare value 1. 0xFFFF FFFF 27.6.2.5 QEI Position Compare register 2 This register contains a position compare value. This value is compared against the current value of the position register. Interrupts can be enabled to interrupt when the compare value is less than, equal to, or greater than the current value of the position register. Table 582. QEI Position Compare register 2 (CMPOS2 - address 0x400C 601C) bit description Bit Symbol Description Reset value 31:0 PCMP2 Position compare value 2. All information provided in this document is subject to legal disclaimers. 0xFFFF FFFF © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 673 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 27: LPC18xx Quadrature Encoder Interface (QEI) FT D R A D R A R A FT D R FT 27.6.2.6 QEI Index Count register D R This register contains the current value of the encoder position. Increments or decrements when encoder counts occur, depending on the direction of rotation. Table 583. QEI Index Count register (INXCNT- address 0x400C 6020) bit description Bit Symbol Description Reset value R A FT D R R A F D R A FT D FT D A FT R A A FT D 31:0 ENCPOS Current encoder position value. 0 R A 27.6.2.7 QEI Index Compare register 0 This register contains an index compare value. This value is compared against the current value of the index count register. Interrupts can be enabled to interrupt when the compare value is less than, equal to, or greater than the current value of the index count register. Table 584. QEI Index Compare register 0(INXCMP0 - address 0x400C 6024) bit description Bit Symbol Description Reset value 31:0 ICMP0 Index compare value. 0xFFFF FFFF 27.6.2.8 QEI Timer Reload register This register contains the reload value of the velocity timer. When the timer (QEITIME) overflows or the RESV bit is asserted, this value is loaded into the timer (QEITIME). Table 585. QEI Timer Load register (LOAD - address 0x400C 6028) bit description Bit Symbol Description Reset value 31:0 VELLOAD Current velocity timer load value. 0xFFFF FFFF 27.6.2.9 QEI Timer register This register contains the current value of the velocity timer. When this timer overflows the value of velocity counter (QEIVEL) is stored in the velocity capture register (QEICAP), the velocity counter is reset to zero, the timer is reloaded with the value stored in the velocity reload register (QEILOAD), and the velocity interrupt (TIM_Int) is asserted. Table 586. QEI Timer register (TIME - address 0x400C 602C) bit description Bit Symbol Description Reset value 31:0 VELVAL Current velocity timer value. 0xFFFF FFFF 27.6.2.10 QEI Velocity register This register contains the running count of velocity pulses for the current time period. When the velocity timer (QEITIME) overflows the contents of this register is captured in the velocity capture register (QEICAP). After capture, this register is set to zero. This register is also reset when the velocity reset bit (RESV) is asserted. Table 587. QEI Velocity register (VEL - address 0x400C 6030) bit description Bit Symbol Description Reset value 31:0 VELPC Current velocity pulse count. 0x0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 674 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 27: LPC18xx Quadrature Encoder Interface (QEI) FT D R A D R A R A FT D R FT 27.6.2.11 QEI Velocity Capture register D R This register contains the most recently measured velocity of the encoder. This corresponds to the number of velocity pulses counted in the previous velocity timer period.The current velocity count is latched into this register when the velocity timer overflows. Table 588. QEI Velocity Capture register (CAP - address 0x400C 6034) bit description Bit Symbol Description Reset value R A FT D R R A F D R A FT A FT FT D R A A D FT D R A 31:0 VELCAP Velocity capture value. 0xFFFF FFFF 27.6.2.12 QEI Velocity Compare register This register contains a velocity compare value. This value is compared against the captured velocity in the velocity capture register. If the capture velocity is less than the value in this compare register, a velocity compare interrupt (VELC_Int) will be asserted, if enabled. Table 589. QEI Velocity Compare register (VELCOMP - address 0x400C 6038) bit description Bit Symbol Description Reset value 31:0 VELCMP Velocity compare value. 0x0 27.6.2.13 QEI Digital filter on phase A input register This register contains the sampling count for the digital filter. A sampling count of zero bypasses the filter. Table 590. QEI Digital filter on phase A input register (FILTERPHA - 0x400C 603C) bit description Bit Symbol Description Reset value 31:0 FILTA Digital filter sampling delay 0x0 27.6.2.14 QEI Digital filter on phase B input register This register contains the sampling count for the digital filter. A sampling count of zero bypasses the filter. Table 591. QEI Digital filter on phase B input register (FILTERPHB - 0x400C 6040) bit description Bit Symbol Description Reset value 31:0 FILTB Digital filter sampling delay 0x0 27.6.2.15 QEI Digital filter on index input register This register contains the sampling count for the digital filter. A sampling count of zero bypasses the filter. Table 592. QEI Digital filter on index input register (FILTERINX - 0x400C 6044) bit description Bit Symbol Description Reset value 31:0 FITLINX Digital filter sampling delay 0x0 © NXP B.V. 2011. All rights reserved. All information provided in this document is subject to legal disclaimers. User manual Rev. 00.13 — 20 July 2011 675 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 27: LPC18xx Quadrature Encoder Interface (QEI) FT D R A D R A R A FT D R FT 27.6.2.16 QEI Index acceptance window register D R This register contains the width of the index acceptance window, when the index and the phase / clock edges fall nearly together. If the activating phase / clock edge falls before the Index, but within the window, the (re)calibration will be activated on that clock/phase edge. FT D R A FT D Table 593. QEI Index acceptance window register (WINDOW - 0x400C 6048) bit description Bit Symbol Description Reset value R A R A F D R A FT D A FT D R A R A FT 31:0 WINDOW Index acceptance window width 0x0 27.6.2.17 QEI Index Compare register 1 This register contains an index compare value. This value is compared against the current value of the index count register. Interrupts can be enabled to interrupt when the compare value is less than, equal to, or greater than the current value of the index count register. Table 594. QEI Index Compare register 1 (INXCMP1 - address 0x400C 604C) bit description Bit Symbol Description Reset value 31:0 ICMP1 Index compare value 1. 0xFFFF FFFF 27.6.2.18 QEI Index Compare register 2 This register contains an index compare value. This value is compared against the current value of the index count register. Interrupts can be enabled to interrupt when the compare value is less than, equal to, or greater than the current value of the index count register. Table 595. QEI Index Compare register 0 (INXCMP2 - address 0x400C 6050) bit description Bit Symbol Description Reset value 31:0 ICMP2 Index compare value 2. 0xFFFF FFFF All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 676 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 27: LPC18xx Quadrature Encoder Interface (QEI) FT D R A D R A R A FT D R FT 27.6.3 Interrupt registers 27.6.3.1 QEI Interrupt Enable Clear register D R Writing a 1 to a bit in this register clears the corresponding bit in the QEI Interrupt Enable register (QEIIE). FT D Table 596: QEI Interrupt Enable Clear register (IEC - address 0x400C 6FD8) bit description Bit Symbol Description Reset value R A FT D R R A F D R A FT D R A FT D R A A FT A 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 31:16 INX_EN TIM_EN VELC_EN DIR_EN ERR_EN ENCLK_EN POS0_Int POS1_Int POS2_Int REV_Int Indicates that an index pulse was detected. Indicates that a velocity timer overflow occurred Indicates that captured velocity is less than compare velocity. Indicates that a change of direction was detected. Indicates that an encoder phase error was detected. Indicates that and encoder clock pulse was detected. Indicates that the position 0 compare value is equal to the current position. Indicates that the position 1compare value is equal to the current position. Indicates that the position 2 compare value is equal to the current position. Indicates that the index compare value is equal to the current index count. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 POS0REV_Int Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set. POS1REV_Int Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set. POS2REV_Int Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set. REV1_Int REV2_Int MAXPOS_Int Indicates that the index 1 compare value is equal to the current index count. Indicates that the index 2 compare value is equal to the current index count. Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction. Reserved 27.6.3.2 QEI Interrupt Enable Set register Writing a 1 to a bit in this register sets the corresponding bit in the QEI Interrupt Enable register (QEIIE). Table 597: QEI Interrupt Enable Set register (IES - address 0x400C 6FDC) bit description Bit Symbol Description Reset value 0 1 2 3 4 5 6 7 INX_EN TIM_EN VELC_EN DIR_EN ERR_EN ENCLK_EN POS0_Int POS1_Int Indicates that an index pulse was detected. Indicates that a velocity timer overflow occurred Indicates that captured velocity is less than compare velocity. Indicates that a change of direction was detected. Indicates that an encoder phase error was detected. Indicates that and encoder clock pulse was detected. Indicates that the position 0 compare value is equal to the current position. Indicates that the position 1compare value is equal to the current position. All information provided in this document is subject to legal disclaimers. 0 0 0 0 0 0 0 0 © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 677 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 27: LPC18xx Quadrature Encoder Interface (QEI) FT D R A D R A R A FT D R FT Table 597: QEI Interrupt Enable Set register (IES - address 0x400C 6FDC) bit description Bit Symbol Description D R R A FT D R R A F D R A Reset value A FT A 8 9 10 11 12 13 14 15 31:16 POS2_Int REV_Int Indicates that the position 2 compare value is equal to the current position. Indicates that the index compare value is equal to the current index count. 0 FT D 0 POS0REV_Int Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set 0 and the REV_Int is set. POS1REV_Int Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set 0 and the REV_Int is set. POS2REV_Int Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set 0 and the REV_Int is set. REV1_Int REV2_Int MAXPOS_Int Indicates that the index 1 compare value is equal to the current index count. Indicates that the index 2 compare value is equal to the current index count. Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction. Reserved 0 0 0 0 FT D R A FT D R A 27.6.3.3 QEI Interrupt Status register This register provides the status of the encoder interface and the current set of interrupt sources that are asserted to the controller. Bits set to 1 indicate the latched events that have occurred; a zero bit indicates that the event in question has not occurred. Writing a 0 to a bit position clears the corresponding interrupt. Table 598: QEI Interrupt Status register (INTSTAT - address 0x400C 6FE0) bit description Bit Symbol Description Reset value 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 31:16 INX_Int TIM_Int VELC_Int DIR_Int ERR_Int ENCLK_Int POS0_Int POS1_Int POS2_Int REV_Int POS0REV_Int POS1REV_Int POS2REV_Int REV1_Int REV2_Int MAXPOS_Int - Indicates that an index pulse was detected. Indicates that a velocity timer overflow occurred Indicates that captured velocity is less than compare velocity. Indicates that a change of direction was detected. Indicates that an encoder phase error was detected. Indicates that and encoder clock pulse was detected. Indicates that the position 0 compare value is equal to the current position. Indicates that the position 1compare value is equal to the current position. Indicates that the position 2 compare value is equal to the current position. Indicates that the index compare value is equal to the current index count. 0 0 0 0 0 0 0 0 0 0 Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set 0 and the REV_Int is set. Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set 0 and the REV_Int is set. Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set 0 and the REV_Int is set. Indicates that the index 1 compare value is equal to the current index count. Indicates that the index 2 compare value is equal to the current index count. Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction. Reserved All information provided in this document is subject to legal disclaimers. 0 0 0 0 © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 678 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 27: LPC18xx Quadrature Encoder Interface (QEI) FT D R A D R A R A FT D R FT 27.6.3.4 QEI Interrupt Enable register D R This register enables interrupt sources. Bits set to 1 enable the corresponding interrupt; a 0 bit disables the corresponding interrupt. FT D R A FT Table 599: QEI Interrupt Enable register (IE - address 0x400C 6FE4) bit description Bit Symbol Description R A R A F D R A FT D R A FT D R A Reset value A FT D 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 31:16 INX_Int TIM_Int VELC_Int DIR_Int ERR_Int ENCLK_Int POS0_Int POS1_Int POS2_Int REV_Int Indicates that an index pulse was detected. Indicates that a velocity timer overflow occurred Indicates that captured velocity is less than compare velocity. Indicates that a change of direction was detected. Indicates that an encoder phase error was detected. Indicates that and encoder clock pulse was detected. Indicates that the position 0 compare value is equal to the current position. Indicates that the position 1compare value is equal to the current position. Indicates that the position 2 compare value is equal to the current position. Indicates that the index compare value is equal to the current index count. 0 0 0 0 0 0 0 0 0 0 POS0REV_Int Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set 0 and the REV_Int is set. POS1REV_Int Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set 0 and the REV_Int is set. POS2REV_Int Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set 0 and the REV_Int is set. REV1_Int REV2_Int MAXPOS_Int Indicates that the index 1 compare value is equal to the current index count. Indicates that the index 2 compare value is equal to the current index count. Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction. Reserved 0 0 0 0 27.6.3.5 QEI Interrupt Clear register Writing a 1 to a bit in this register clears the corresponding bit in the QEI Interrupt Status register (QEISTAT). Table 600: QEI Interrupt Clear register (CLR - 0x400C 6FE8) bit description Bit Symbol Description Reset value 0 1 2 3 4 5 6 7 8 9 INX_Int TIM_Int VELC_Int DIR_Int ERR_Int ENCLK_Int POS0_Int POS1_Int POS2_Int REV_Int Indicates that an index pulse was detected. Indicates that a velocity timer overflow occurred Indicates that captured velocity is less than compare velocity. Indicates that a change of direction was detected. Indicates that an encoder phase error was detected. Indicates that and encoder clock pulse was detected. Indicates that the position 0 compare value is equal to the current position. Indicates that the position 1compare value is equal to the current position. Indicates that the position 2 compare value is equal to the current position. Indicates that the index compare value is equal to the current index count. All information provided in this document is subject to legal disclaimers. 0 0 0 0 0 0 0 0 0 0 © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 679 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 27: LPC18xx Quadrature Encoder Interface (QEI) FT D R A D R A R A FT D R FT Table 600: QEI Interrupt Clear register (CLR - 0x400C 6FE8) bit description Bit Symbol Description D R R A FT D R R A F D R A Reset value A FT A 10 11 13 14 15 31:16 POS0REV_Int Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set. POS1REV_Int Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set. REV1_Int REV2_Int MAXPOS_Int Indicates that the index 1 compare value is equal to the current index count. Indicates that the index 2 compare value is equal to the current index count. Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction. Reserved 0 0 FT D R A FT D R A 0 0 0 0 FT D 27.6.3.6 QEI Interrupt Set register Writing a one to a bit in this register sets the corresponding bit in the QEI Interrupt Status register (STAT). Table 601: QEI Interrupt Set register (SET - address 0x400C 6FEC) bit description Bit Symbol Description Reset value 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 31:16 INX_Int TIM_Int VELC_Int DIR_Int ERR_Int ENCLK_Int POS0_Int POS1_Int POS2_Int REV_Int POS0REV_Int POS1REV_Int POS2REV_Int REV1_Int REV2_Int MAXPOS_Int - Indicates that an index pulse was detected. Indicates that a velocity timer overflow occurred Indicates that captured velocity is less than compare velocity. Indicates that a change of direction was detected. Indicates that an encoder phase error was detected. Indicates that and encoder clock pulse was detected. Indicates that the position 0 compare value is equal to the current position. Indicates that the position 1compare value is equal to the current position. Indicates that the position 2 compare value is equal to the current position. Indicates that the index compare value is equal to the current index count. 0 0 0 0 0 0 0 0 0 Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set 0 and the REV_Int is set. Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set 0 and the REV_Int is set. Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set 0 and the REV_Int is set. Indicates that the index 1 compare value is equal to the current index count. Indicates that the index 2 compare value is equal to the current index count. Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction. Reserved 0 0 0 0 27.7 Functional description The QEI module interprets the two-bit gray code produced by a quadrature encoder wheel to integrate position over time and determine direction of rotation. In addition, it can capture the velocity of the encoder wheel. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 680 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 27: LPC18xx Quadrature Encoder Interface (QEI) FT D R A D R A R A FT D R FT 27.7.1 Input signals D R The QEI module supports two modes of signal operation: quadrature phase mode and clock/direction mode. In quadrature phase mode, the encoder produces two clocks that are 90 degrees out of phase; the edge relationship is used to determine the direction of rotation. In clock/direction mode, the encoder produces a clock signal to indicate steps and a direction signal to indicate the direction of rotation.). D R A FT This mode is determined by the SigMode bit of the QEI Control (CON) register (See Table 575). When the SigMode bit = 1, the quadrature decoder is bypassed and the PhA pin functions as the direction signal and PhB pin functions as the clock signal for the counters, etc. When the SigMode bit = 0, the PhA pin and PhB pins are decoded by the quadrature decoder. In this mode the quadrature decoder produces the direction and clock signals for the counters, etc. In both modes the direction signal is subject to the effects of the direction invert (DIRINV) bit. R A FT R A F D R A FT D R A FT D R A A FT D 27.7.1.1 Quadrature input signals When edges on PhA lead edges on PhB, the position counter is incremented. When edges on PhB lead edges on PhA, the position counter is decremented. When a rising and falling edge pair is seen on one of the phases without any edges on the other, the direction of rotation has changed. Table 602. Encoder states Phase A Phase B state 1 1 0 0 0 1 1 0 1 2 3 4 Table 603. Encoder state transitions[1] from state to state Direction 1 2 3 4 4 3 2 1 [1] 2 3 4 1 3 2 1 4 All other state transitions are illegal and should set the ERR bit. positive negative Interchanging of the PhA and PhB input signals are compensated by complementing the DIR bit. When set = 1, the direction inversion bit (DIRINV) complements the DIR bit. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 681 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 27: LPC18xx Quadrature Encoder Interface (QEI) FT D R A D R A R A FT D R FT D Table 604. Encoder direction DIR bit DIRINV bit direction R R A FT D R A F D A FT 0 1 0 1 0 0 1 1 forward reverse reverse forward R R A FT D R A FT D A FT D R A Figure 81 shows how quadrature encoder signals equate to direction and count. PhA PhB direction position -1 -1 -1 -1 -1 -1 -1 -1 -1 +1 +1 +1 +1 +1 +1 +1 +1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 Fig 81. Quadrature Encoder Basic Operation 27.7.1.2 Digital input filtering All three encoder inputs (PhA, PhB, and index) require digital filtering. The number of sample clocks is user programmable from 1 to 4,294,967,295 (0xFFFF FFFF). In order for a transition to be accepted, the input signal must remain in new state for the programmed number of sample clocks. 27.7.2 Position capture The capture mode for the position integrator can be set to update the position counter on every edge of the PhA signal or to update on every edge of both PhA and PhB. Updating the position counter on every PhA and PhB provides more positional resolution at the cost of less range in the positional counter. The position integrator and velocity capture can be independently enabled. Alternatively, the phase signals can be interpreted as a clock and direction signal as output by some encoders. The position counter is automatically reset on one of three conditions. Incrementing past the maximum position value (MAXPOS) will reset the position counter to zero. If the reset on index bit (RESPI) is set, sensing the index pulse for the first time will once reset the position counter to zero after the next positional increase (calibrate). If the continuously reset on index bit (CRESPI) is set, sensing the index pulse will continuously reset the position counter to zero after the next positional increase (recalibrate). 27.7.3 Velocity capture The velocity capture has a programmable timer and a capture register. It counts the number of phase edges (using the same configuration as for the position integrator) in a given time period. When the velocity timer (TIME) overflows the contents of the velocity counter (VEL) are transferred to the capture (CAP) register. The velocity counter is then All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 682 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 27: LPC18xx Quadrature Encoder Interface (QEI) FT D R A cleared. The velocity timer is loaded with the contents of the velocity reload register (LOAD). Finally, the velocity interrupt (TIM_Int) is asserted. The number of edges counted in a given time period is directly proportional to the velocity of the encoder. R Setting the reset velocity bit (RESV) will clear the velocity counter, reset the velocity capture register to 0xFFFF FFFF, and load the velocity timer with the contents of the velocity reload register (LOAD). The following equation converts the velocity counter value into an RPM value: RPM = (PCLK  Speed  60) / Load  PPR  Edges) where: • PCLK is the QEI controller clock. • PPR is the number of pulses per revolution of the physical encoder. • Edges is 2 or 4, based on the capture mode set in the CON register (2 for CapMode set to 0 and 4 for CapMode set to 1) For example, consider a motor running at 600 rpm. A 2048 pulse per revolution quadrature encoder is attached to the motor, producing 8192 phase edges per revolution. With clocking on both PhA and PhB edges, this results in 81,920 pulses per second (the motor turns 10 times per second). If the timer were clocked at 10,000 Hz, and the load value was 2,500 (¼ of a second), it would count 20,480 pulses per update. Using the above equation: RPM = (10000  20480  60) / (2500  2048  4) = 600 RPM Now, consider that the motor is sped up to 3000 RPM. This results in 409,600 pulses per second, or 102,400 every ¼ of a second. Again, the above equation gives: RPM = (10000  102400  60) / (2500  2048  4) = 3000 RPM D R A R A FT D R FT D R R A A A FT D R A R A FT F FT D R A FT D FT D D R A 27.7.4 Velocity compare In addition to velocity capture, the velocity measurement system includes a programmable velocity compare register. After every velocity capture event the contents of the velocity capture register (CAP) is compared with the contents of the velocity compare register (VELCOMP). If the captured velocity is less than the compare value an interrupt is asserted provided that the velocity compare interrupt enable bit is set. This can be used to determine if a motor shaft is either stalled or moving too slow. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 683 of 1164 D R A FT D R A FT D R A FT D R A FT D R A FT UM10430 Rev. 00.13 — 20 July 2011 D D Chapter 28: LPC18xx Repetitive Interrupt Timer (RIT) D R A FT D D R A FT D R A FT D R A FT D R A FT D R A R FT D A FT R A R A FT D R A FT D R A F R A FT D FT R User manual 28.1 How to read this chapter The RIT is available on all LPC18xx parts. D D R A FT D R A 28.2 Basic configuration The RIT is configured as follows: • See Table 605 for clocking and power control. • The RIT is reset by the RITIMER_RST (reset #36). • The RIT interrupt is connected to slot # 11 in the NVIC. Table 605. RIT clocking and power control Base clock Branch clock Maximum frequency Clock to the RI timer register interface and BASE_M3_CLK RI timer peripheral clock. CLK_M3_RITIMER 150 MHz 28.3 Features • 32-bit counter running from PCLK. Counter can be free-running, or be reset by a generated interrupt. • 32-bit compare value. • 32-bit compare mask. An interrupt is generated when the counter value equals the compare value, after masking. This allows for combinations not possible with a simple compare. 28.4 General description The Repetitive Interrupt Timer provides a versatile means of generating interrupts at specified time intervals, without using a standard timer. It is intended for repeating interrupts that aren’t related to Operating System interrupts. However, it could be used as an alternative to the Cortex-M3 System Tick Timer if there are different system requirements. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 684 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 28: LPC18xx Repetitive Interrupt Timer (RIT) FT D R A D R A R A FT D R FT 28.5 Register description Table 606. Register overview: Repetitive Interrupt Timer (RIT) (base address 0x400C 0000) Name Access Address Description D R Reset value[1] R A FT D R R A F D R A FT A FT A FT D R D COMPVAL MASK R/W R/W 0x000 0x004 Compare register 0xFFFF FFFF A FT Mask register. This register holds the 32-bit mask value. A ‘1’ 0 written to any bit will force a compare on the corresponding bit of the counter and compare register. Control register. 32-bit counter 0xC 0 D R A CTRL COUNTER [1] R/W R/W 0x008 0x00C Reset Value reflects the data stored in used bits only. It does not include content of reserved bits. 28.5.1 RI Compare Value register Table 607. RI Compare Value register (COMPVAL - address 0x400C 0000) bit description Bit Symbol Description Reset value 31:0 RICOMP Compare register. Holds the compare value which is compared to the counter. 0xFFFF FFFF 28.5.2 RI Mask register Table 608. RI Mask register (MASK - address 0x400C 0004) bit description Bit Symbol Description Reset value 31:0 RIMASK Mask register. This register holds the 32-bit mask value. A one written 0 to any bit overrides the result of the comparison for the corresponding bit of the counter and compare register (causes the comparison of the register bits to be always true). 28.5.3 RI Control register Table 609. RI Control register (CTRL - address 0x400C 0008) bit description Bit Symbol Value Description Reset value 0 RITINT 1 Interrupt flag This bit is set to 1 by hardware whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. Writing a 1 to this bit will clear it to 0. Writing a 0 has no effect. 0 The counter value does not equal the masked compare value. Timer enable clear 1 0 1 RITENCLR The timer will be cleared to 0 whenever the counter value 0 equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. This will occur on the same clock that sets the interrupt flag. The timer will not be cleared to 0. © NXP B.V. 2011. All rights reserved. 0 All information provided in this document is subject to legal disclaimers. User manual Rev. 00.13 — 20 July 2011 685 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 28: LPC18xx Repetitive Interrupt Timer (RIT) FT D Table 609. RI Control register (CTRL - address 0x400C 0008) bit description Bit Symbol Value Description D R A R A FT D R R R A FT D R A R A A FT Reset value FT D R A F D R A 2 RITENBR 1 0 Timer enable for debug The timer is halted when the processor is halted for debugging. Debug has no effect on the timer operation. Timer enable. 1 Timer enabled. Remark: This can be overruled by a debug halt if enabled in bit 2. 1 FT D R A FT D R A FT D 3 RITEN 1 0 31:4 - Timer disabled. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 28.5.4 RI Counter register Table 610. RI Counter register (COUNTER - address 0x400C 000C) bit description Bit Symbol Description Reset value 31:0 RICOUNTER 32-bit up counter. Counts continuously unless RITEN bit in RICTRL register is cleared or debug mode is entered (if enabled by the RITNEBR bit in RICTRL). Can be loaded to any value in software. 0 28.6 RI timer operation Following reset, the counter begins counting up from 0x00000000. Whenever the counter value equals the value programmed into the RICOMPVAL register the interrupt flag will be set. Any bit or combination of bits can be removed from this comparison (i.e. forced to compare) by writing a ‘1’ to the corresponding bit(s) in the RIMASK register. If the enable_clr bit is low (default state), a valid comparison ONLY causes the interrupt flag to be set. It has no effect on the count sequence. Counting continues as usual. When the counter reaches 0xFFFFFFFF it rolls-over to 0x00000000 on the next clock and continues counting. If the enable_clr bit is set to ‘1’ a valid comparison will also cause the counter to be reset to zero. Counting will resume from there on the next clock edge. Counting can be halted in software by writing a ‘0’ to the Enable_Timer bit - RICTRL(2). Counting will also be halted when the processor is halted for debugging provided the Enable_Break bit – RICTRL(1) is set. Both the Enable_Timer and Enable_Break bits are set on reset. The interrupt flag can be cleared in software by writing a ‘1’ to the Interrupt bit – RICTRL(0). Software can load the counter to any value at any time by writing to RICOUNTER. The counter (RICOUNTER), RICOMPVAL register, RIMASK register and RICTRL register can all be read by software at any time. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 686 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 28: LPC18xx Repetitive Interrupt Timer (RIT) FT D R R A D R A R A FT D R FT D R A R A FT FT A F RESET CNT_ENA D D R R A PBUS A FT D FT D ENA CLR 32-bit COUNTER RESET SET ENABLE_TIMER 3 PBUS ENABLE_BREAK BREAK ENABLE_CLK R A FT D R A 32 2 PBUS PBUS CLR RESET COMPARATOR EQ 32 SET_INT S 32 0 PBUS write '1' to clear RESET PBUS C CLR CTRL register INTR PBUS 32 RESET SET COMPARE REGISTER CLR PBUS MASK REGISTER PBUS PBUS Fig 82. RI timer block diagram All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 687 of 1164 D R A FT D R A FT D R A FT D R A FT D R A FT UM10430 Chapter 29: LPC18xx Alarm timer Rev. 00.13 — 20 July 2011 D D D R A FT D D R A FT D R A FT D R A R A FT D R A R A FT D R A FT D R A F R A FT D R R D User manual FT D R A FT FT A FT 29.1 How to read this chapter The Alarm timer is identical on all LPC18xx parts. D D R A FT D R A 29.2 Basic configuration The Alarm timer is configured as follows: • See Table 611 for clocking and power control. The 32 kHz output of the 32 kHz oscillator must be enabled in the CREG0 register in the CREG block (see Table 31). • • The Alarm timer interrupt is connected to slot # 4 in the Event router. Table 611. Alarm timer clocking and power control Base clock Branch clock Maximum frequency Clock to alarm timer register interface 32 kHz crystal oscillator output for the counter/timer clock BASE_M3_CLK - CLK_M3_BUS 150 MHz 1024 Hz (fixed frequency) 29.3 General description The alarm timer is a 16-bit timer and counts down from a preset value. The counter triggers a status bit when it reaches 0x00 and asserts an interrupt if enabled. The alarm timer operates in the RTC power domain. It consists of a 16-bit counter (DOWNCOUNTER) running at a 1024 Hz clock. The 1024 Hz clock is derived from the 32 kHz crystal clock. The alarm timer is inactive when this clock is not active. The alarm timer counts down from an initial value PRESET. When it reaches 0x0 and the interrupt is enabled (via SET_EN), bit STATUS is triggered. The counter continues counting down starting from PRESET. STATUS is propagated to the interrupt output. The interrupt is connected to the Event router and can be used to wake up the device from a low power mode. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 688 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 29: LPC18xx Alarm timer FT D R A D R A R A FT D R FT 29.4 Register description Table 612. Register overview: Alarm timer (base address 0x4004 0000) Name Access Address offset Description D R R A FT D R R A F D R A FT A FT A Reset Value FT D R A D FT DOWNCOUNTER PRESET CLR_EN SET_EN STATUS ENABLE CLR_STAT SET_STAT R/W R/W W W R R W W 0x000 0x004 0x008 0xFD4 0xFD8 0xFDC 0xFE0 0xFE4 0xFE8 0xFEC Downcounter register Preset value register Reserved Interrupt clear enable register Interrupt set enable register Status register Enable register Clear register Set register 0x000 0x000 0x0 0x0 0x0 0x0 0x0 0x0 D R A 29.4.1 Downcounter register Table 613. Downcounter register (DOWNCOUNTER - 0x4004 0000) bit description Bit Symbol Description Reset value 15:0 CVAL When equal to zero an interrupt is raised. When equal to zero PRESET is loaded and counting continues. 0x0 31:16 - Reserved. - 29.4.2 Preset value register Table 614. Preset value register (PRESET - 0x4004 0004) bit description Bit Symbol Description Reset value 15:0 31:16 PRESETVAL - Value loaded in DOWNCOUNTER when DOWNCOUNTER equals zero Reserved. - 29.4.3 Interrupt clear enable register Table 615. Interrupt clear enable register (CLR_EN - 0x4004 0FD8) bit description Bit Symbol Description Reset value 0 31:1 CLR_EN - Writing a 1 to this bit clears the interrupt enable bit in the ENABLE register. Reserved. - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 689 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 29: LPC18xx Alarm timer FT D R A D R A R A FT D R FT 29.4.4 Interrupt set enable register Bit Symbol Description D R Table 616. Interrupt set enable register (SET_EN - 0x4004 0FDC) bit description R A FT D R R A F D R A FT A FT A FT Reset value 0 31:1 SET_EN - Writing a 1 to this bit sets the interrupt enable bit in the ENABLE register. Reserved. 0 - D D R A FT D R A 29.4.5 Interrupt status register Table 617. Interrupt status register (STATUS - 0x4004 0FE0) bit description Bit Symbol Description Reset value 0 31:1 STAT - A 1 in this bit shows that the STATUS interrupt has been raised. Reserved. 0 - 29.4.6 Interrupt enable register Table 618. Interrupt enable register (ENABLE - 0x4004 0FE4) bit description Bit Symbol Description Reset value 0 EN A 1 in this bit shows that the STATUS interrupt has been enabled and that the STATUS interrupt request signal is asserted when STAT = 1 in the STATUS register. Reserved. 0 31:1 - - 29.4.7 Clear status register Table 619. Interrupt clear status register (CLR_STAT - 0x4004 0FE8) bit description Bit Symbol Description Reset value 0 31:1 CSTAT - Writing a 1 to this bit clears the STATUS interrupt bit in the STATUS register. Reserved. 0 - 29.4.8 Set status register Table 620. Interrupt set status register (SET_STAT - 0x4004 0FEC) bit description Bit Symbol Description Reset value 0 31:1 SSTAT - Writing a 1 to this bit sets the STATUS interrupt bit in the STATUS register. Reserved. 0 - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 690 of 1164 D R A FT D R A FT D R A FT D R A FT D R A FT UM10430 Rev. 00.13 — 20 July 2011 D D Chapter 30: LPC18xx Windowed Watchdog timer (WWDT) D R R A A FT FT D D R A FT D R A FT D R A FT D FT D R A D R A FT R A R A FT D R A FT D R A F R A FT D FT R User manual 30.1 How to read this chapter The WWDT is identical for all LPC18xx parts. D D R A FT D R A 30.2 Basic configuration The WWDT is configured as follows: • See Table 621 for clocking and power control. The only clock source for the WWDT clock (WDCLK) is the IRC. • The WWDT cannot be reset by software. • The WWDT interrupt is connected to slot # 7 in the Event router. Table 621. WWDT clocking and power control Base clock Branch clock Maximum frequency Clock to WWDT register interface (PCLK) Watchdog clock (WDCLK) BASE_M3_CLK BASE_SAFE_CLK CLK_M3_WWDT 150 MHz 12 MHz (fixed frequency) 30.3 Features • Internally resets chip if not reloaded during the programmable time-out period. • Optional windowed operation requires reload to occur between a minimum and maximum time-out period, both programmable. • Optional warning interrupt can be generated at a programmable time prior to watchdog time-out. • Programmable 24 bit timer with internal fixed pre-scaler. • Selectable time period from 1,024 watchdog clocks (TWDCLK  256  4) to over 67 million watchdog clocks (TWDCLK  224  4) in increments of 4 watchdog clocks. reset to be disabled. • Safe watchdog operation. Once enabled, requires a hardware reset or a Watchdog • Incorrect feed sequence causes immediate watchdog reset if enabled. • The watchdog reload value can optionally be protected such that it can only be changed after the “warning interrupt” time is reached. • Flag to indicate Watchdog reset. • The WWDT uses the IRC as a fixed clock source. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 691 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 30: LPC18xx Windowed Watchdog timer (WWDT) FT D R A D R A R A FT D R FT 30.4 Applications D R The purpose of the Watchdog Timer is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state. When enabled, a watchdog event will be generated if the user program fails to feed (or reload) the Watchdog within a predetermined amount of time. The Watchdog event will cause a chip reset if configured to do so. R A FT When a watchdog window is programmed, an early watchdog feed is also treated as a watchdog event. This allows preventing situations where a system failure may still feed the watchdog. For example, application code could be stuck in an interrupt service that contains a watchdog feed. Setting the window such that this would result in an early feed will generate a watchdog event, allowing for system recovery. R A FT D R A F D R A FT D A FT D R A R A FT D 30.5 Description The Watchdog consists of a fixed divide by 4 pre-scaler and a 24-bit counter which decrements on every clock cycle. The minimum value from which the counter decrements is 0xFF. Setting a value lower than 0xFF causes 0xFF to be loaded in the counter. Hence the minimum Watchdog interval is (TWDCLK  256  4) and the maximum Watchdog interval is (TWDCLK  224  4) in multiples of (TWDCLK  4). The Watchdog should be used in the following manner: • Set the Watchdog time-out value in TC register. • Setup the Watchdog timer operating mode in MOD register. • Set a value for the watchdog window time in WINDOW register if windowed operation is required. • Set a compare value for the watchdog warning interrupt in the WARNINT register if a warning interrupt is required. • Enable the Watchdog by writing 0xAA followed by 0x55 to the FEED register. • The Watchdog must be fed again before the Watchdog counter reaches zero in order to prevent a watchdog event. If a window value is programmed, the feed must also occur after the watchdog counter passes that value. When the Watchdog Timer is configured so that a watchdog event will cause a reset and the counter reaches zero, the CPU will be reset, loading the stack pointer and program counter from the vector table as in the case of external reset. The Watchdog time-out flag (WDTOF) can be examined to determine if the Watchdog has caused the reset condition. The WDTOF flag must be cleared by software. When the Watchdog Timer is configured to generate a warning interrupt, the interrupt will occur when the counter matches the compare value defined by the WARNINT register. 30.5.1 WWDT behavior in debug mode If code execution is halted in Debug mode, the WWDT stops counting until code execution resumes. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 692 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 30: LPC18xx Windowed Watchdog timer (WWDT) FT D R A D R A R A FT D R FT 30.6 Clocking D R The watchdog timer block uses two clocks: PCLK and WDCLK. PCLK is used for the APB accesses to the watchdog registers and is derived from the BASE_M3_CLK. The WDCLK is used for the watchdog timer counting and is derived from the IRC. The clock source (the IRC) is fixed to ensure that the WDT always has a valid clock. There is some synchronization logic between these two clock domains. When the MOD and TC registers are updated by APB operations, the new value will take effect in three WDCLK cycles on the logic in the WDCLK clock domain. When the watchdog timer is counting the WDCLK clock cycles, the synchronization logic will first lock the value of the counter on WDCLK and then synchronize it with the PCLK for reading as the TV register by the CPU. R A FT D R A FT D R A F D R A FT D FT D R A R A A FT 30.7 Register description The Watchdog contains six registers as shown in Table 622 below. Table 622. Register overview: Watchdog timer (base address 0x4008 0000) Name Access Address Description offset Reset value[1] MOD R/W 0x000 Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. 0 TC FEED R/W WO 0x004 0x008 Watchdog timer constant register. This register 0xFF determines the time-out value. Watchdog feed sequence register. Writing NA 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. Watchdog timer value register. This register reads out the current value of the Watchdog timer. Reserved Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value. Watchdog timer window register. This register contains the Watchdog window value. 0xFF TV RO 0x00C WARNINT R/W 0x010 0x014 0 WINDOW [1] R/W 0x018 0xFF FFFF Reset value reflects the data stored in used bits only. It does not include reserved bits content. 30.7.1 Watchdog mode register The WDMOD register controls the operation of the Watchdog as per the combination of WDEN and RESET bits. Note that a watchdog feed must be performed before any changes to the WDMOD register take effect. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 693 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 30: LPC18xx Windowed Watchdog timer (WWDT) FT D R Table 623. Watchdog Mode register (MOD - 0x4008 0000) bit description Bit Symbol Value Description D R A R A FT D R FT D A R Reset value R A FT D R A F D A FT 0 WDEN 0 1 Watchdog enable bit. This bit is Set Only. The watchdog timer is stopped. The watchdog timer is running. Watchdog reset enable bit. This bit is Set Only. 0 1 A watchdog time-out will not cause a chip reset. A watchdog time-out will cause a chip reset. Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT, cleared by software. Causes a chip reset if WDRESET = 1. This flag is cleared by software writing a 0 to this bit. Watchdog interrupt flag. Set when the timer reaches the value in the WARNINT register. Cleared by software by writing a 1 to this bit. Watchdog update mode. This bit is Set Only. 0 1 The watchdog time-out value (WDTC) can be changed at any time. The watchdog time-out value (WDTC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0 R R A FT D R A FT D A FT 1 WDRESET 0 D R A 2 WDTOF 0 (Only after external reset) 3 WDINT 0 4 WDPROTECT 0 7:5 - NA Once the WDEN, WDPROTECT, or WDRESET bits are set they can not be cleared by software. Both flags are cleared by an external reset or a Watchdog timer reset. WDTOF The Watchdog time-out flag is set when the Watchdog times out, when a feed error occurs, or when WDPROTECT =1 and an attempt is made to write to the TC register. This flag is cleared by software writing a 0 to this bit. WDINT The Watchdog interrupt flag is set when the Watchdog counter reaches the value specified by WDWARNINT. This flag is cleared when any reset occurs, and is cleared by software by writing a 1 to this bit. Watchdog reset or interrupt will occur any time the watchdog is running and has an operating clock source. Any clock source works in Sleep mode, and the IRC works in Deep-sleep mode. If a watchdog interrupt occurs in Sleep or Deep-sleep mode, it will wake up the device. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 694 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 30: LPC18xx Windowed Watchdog timer (WWDT) FT D R A D R A R A FT D R FT D Table 624. Watchdog operating modes selection WDEN WDRESET Mode of Operation R R A FT D R A F D A FT 0 1 X (0 or 1) 0 Debug/Operate without the Watchdog running. R R A FT D R A FT Watchdog interrupt mode: the watchdog warning interrupt will be generated but watchdog reset will not. D A FT D R A When this mode is selected, the watchdog counter reaching the value specified by WDWARNINT will set the WDINT flag and the Watchdog interrupt request will be generated. 1 1 Watchdog reset mode: Both the watchdog interrupt and watchdog reset are enabled. When this mode is selected, the watchdog counter reaching the value specified by WDWARNINT will set the WDINT flag and the Watchdog interrupt request will be generated. The watchdog counter reaching zero will reset the microcontroller. Remark: Other causes for a watchdog reset are: A watchdog feed or changing the WDTC value (if the WDPROTECT bit is set in the MOD register) before reaching the value of WDWINDOW. 30.7.2 Watchdog timer constant register The TC register determines the time-out value. Every time a feed sequence occurs, the TC register content is reloaded into the Watchdog timer. This is pre-loaded with the value 0x00 00FF upon reset. Writing values below 0xFF will cause 0x00 00FF to be loaded into the TC register. Thus the minimum time-out interval is TWDCLK  256  4. If the WDPROTECT bit in MOD register is set to one, an attempt to change the value of TC before the watchdog counter is below the values of WDWARNINT and WDWINDOW will cause a watchdog reset and set the WDTOF flag. Table 625. Watchdog Timer Constant register (TC - 0x4008 0004) bit description Bit Symbol Description Reset value 23:0 31:24 WDTC - Watchdog time-out value. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0x00 00FF NA 30.7.3 Watchdog feed register Writing 0xAA followed by 0x55 to this register will reload the Watchdog timer with the time-out value in the TC register. This operation will also start the Watchdog if it is enabled via the MOD register. Setting the WDEN bit in the WDMOD register is not sufficient to enable the Watchdog. A valid feed sequence must be completed after setting WDEN before the Watchdog is capable of generating a reset. Until then, the Watchdog will ignore feed errors. After writing 0xAA to FEED register, access to any Watchdog register other than writing 0x55 to FEED register causes an immediate reset/interrupt when the Watchdog is enabled, and sets the WDTOF flag. The reset will be generated during the second PCLK following an incorrect access to a Watchdog register during a feed sequence. Interrupts should be disabled during the feed sequence. An abort condition will occur if an interrupt happens during the feed sequence. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 695 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 30: LPC18xx Windowed Watchdog timer (WWDT) FT D R Table 626. Watchdog Feed register (FEED - 0x4008 0008) bit description Bit Symbol Description D R A R A FT D R FT D A R R A FT D R A F D Reset value A FT 7:0 Feed Feed value should be 0xAA followed by 0x55. NA R R A FT D R A FT D 30.7.4 Watchdog timer value register The WDTV register is used to read the current value of Watchdog timer counter. When reading the value of the 24 bit counter, the lock and synchronization procedure takes up to 6 WDCLK cycles plus 6 PCLK cycles, so the value of WDTV is older than the actual value of the timer when it's being read by the CPU. Table 627. Watchdog Timer Value register (TV - 0x4008 000C) bit description Bit Symbol Description Reset value A FT D R A 23:0 31:24 Count - Counter timer value. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0x00 00FF NA 30.7.5 Watchdog timer warning interrupt register The WDWARNINT register determines the watchdog timer counter value that will generate a watchdog interrupt. When the watchdog timer counter matches the value defined by WDWARNINT, an interrupt will be generated after the subsequent WDCLK. A match of the watchdog timer counter to WDWARNINT occurs when the bottom 10 bits of the counter have the same value as the 10 bits of WARNINT, and the remaining upper bits of the counter are all 0. This gives a maximum time of 1,023 watchdog timer counts (4,096 watchdog clocks) for the interrupt to occur prior to a watchdog event. If WDWARNINT is set to 0, the interrupt will occur at the same time as the watchdog event. Table 628. Watchdog Timer Warning Interrupt register (WARNINT - 0x4008 0014) bit description Bit Symbol Description Reset value 9:0 31:10 WDWARNINT - Watchdog warning interrupt compare value. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0 NA 30.7.6 Watchdog timer window register The WDWINDOW register determines the highest WDTV value allowed when a watchdog feed is performed. If a feed valid sequence completes prior to WDTV reaching the value in WDWINDOW, a watchdog event will occur. WDWINDOW resets to the maximum possible WDTV value, so windowing is not in effect. Values of WDWINDOW below 0x100 will make it impossible to ever feed the watchdog successfully. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 696 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 30: LPC18xx Windowed Watchdog timer (WWDT) FT D R R A Table 629. Watchdog Timer Window register (WINDOW - 0x4008 0018) bit description D R A R A FT D R FT D R A R A FT A FT F Bit Symbol Description Reset value D D 23:0 31:24 WDWINDOW Watchdog window value. - 0xFF FFFF R R A A FT FT D R A Reserved, user software should not write ones to reserved NA bits. The value read from a reserved bit is not defined. D FT D R 30.8 Block diagram The block diagram of the Watchdog is shown below in the Figure 83. The synchronization logic (PCLK - WDCLK) is not shown in the block diagram. A WDTC feed ok wd_clk WDFEED feed sequence detect and protection feed ok WDMOD register WDTC write in range WDCLKSEL clock select ÷4 24-bit down counter WDTV WDWIND compare 0 compare enable count WDINTVAL compare interrupt compare feed error underflow shadow bit feed ok WDPROTECT (WDMOD[4]) WDTOF (WDMOD[2]) WDINT (WDMOD[3]) WDRESET (WDMOD[1]) WDEN (WDMOD[0]) chip reset watchdog interrupt Fig 83. Watchdog block diagram 30.9 Watchdog timing examples The following figures illustrate several aspects of Watchdog Timer operation is shown below in Figure 84. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 697 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 30: LPC18xx Windowed Watchdog timer (WWDT) FT D R R A D R A R A FT D R FT D R A R A FT FT A F WDCLK / 4 Watchdog Counter Early Feed Event Watchdog Reset Conditions: WDWINDOW = 0x1200 WDWARNINT = 0x3FF WDTC = 0x2000 Fig 84. Early Watchdog Feed with Windowed Mode Enabled D D R A FT R A FT 125A 1259 1258 1257 D D R A FT D R A WDCLK / 4 Watchdog Counter Correct Feed Event Watchdog Reset Conditions: WDWINDOW = 0x1200 WDWARNINT = 0x3FF WDTC = 0x2000 Fig 85. Correct Watchdog Feed with Windowed Mode Enabled 1201 1200 11FF 11FE 11FD 11FC 2000 1FFF 1FFE 1FFD 1FFC WDCLK / 4 Watchdog Counter Watchdog Interrupt Conditions: WDWINDOW = 0x1200 WDWARNINT = 0x3FF WDTC = 0x2000 Fig 86. Watchdog Warning Interrupt 0403 0402 0401 0400 03FF 03FE 03FD 03FC 03FB 03FA 03F9 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 698 of 1164 D R A FT D R A FT D R A FT D R A FT D R A FT UM10430 Rev. 00.13 — 20 July 2011 D D Chapter 31: LPC18xx Real-Time Clock (RTC) D R A FT D D R A FT D R A FT D R A R A FT D R A R A FT D R A FT D R A F R A FT D R R D User manual FT D R A FT FT A FT 31.1 How to read this chapter D On parts LPC1850/30/20/10 Rev ‘A’, the function of the alarm pin RTC_ALARM must be configured in the CREG0 register (Table 31). D R A FT D R A 31.2 Basic configuration The RTC is configured as follows: • See Table 630 for clocking and power control. The 1 kHz output of the 32 kHz oscillator must be enabled in the CREG0 register in the CREG block (see Table 31). • The RTC interrupt is connected to slot # 5 in the Event router. • Remark: After initializing the 32 kHZ oscillator, wait for 2 sec before writing to the RTC registers. Table 630. RTC clocking and power control Base clock Branch clock Maximum frequency Clock to alarm timer register interface 32 kHz crystal oscillator output for the counter/timer clock BASE_M3_CLK - CLK_M3_BUS 150 MHz 1024 Hz (fixed frequency) 31.3 Features • Measures the passage of time to maintain a calendar and clock. Provides seconds, minutes, hours, day of month, month, year, day of week, and day of year. • Ultra-low power design to support battery powered systems. Uses power from the CPU power supply when it is present. • • • • Dedicated battery power supply pin. RTC power supply is isolated from the rest of the chip. Calibration counter allows adjustment to better than 1 sec/day with 1 sec resolution. Periodic interrupts can be generated from increments of any field of the time registers and selected fractional second values. • Alarm interrupt can be generated for a specific date/time. 31.4 General description The Real Time Clock (RTC) is a set of counters for measuring time when system power is on, and optionally when it is off. It uses very little power when its registers are not being accessed by the CPU, especially reduced power modes. On the LPC18xx, the RTC is clocked by a separate 32 kHz oscillator that produces a 1 Hz internal time reference. The RTC is powered by its own power supply pin, VBAT, . All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 699 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 31: LPC18xx Real-Time Clock (RTC) FT D R R A D R A R A FT D R FT D R A R A FT FT A F second Alarm Registers minute hour D D day month year R R A FT D R alarm compare 1 Hz Clock LSB out second LSB set minute hour day day of week day of year Calibration calibration compare register calibration compare counter reset calibration counter month year Alarm out and Alarm Interrupts Counter Increment Interrupts A FT D A FT D R A Time Registers sign bit match calibration control logic Fig 87. RTC functional block diagram 31.5 Pin description Table 631. RTC pin description Pin Direction Description RTC_ALARM O RTC controlled output. This is a 1.8 V pin. It goes HIGH when a RTC alarm is generated. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 700 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 31: LPC18xx Real-Time Clock (RTC) FT D R A D R A R A FT D R FT 31.6 Register description Table 632. Register overview: RTC (base address 0x4004 6000) Name ILR CCR CIIR AMR CTIME0 CTIME1 CTIME2 SEC MIN HRS DOM DOW DOY MONTH YEAR CALIBRATION ASEC AMIN AHRS ADOM ADOW ADOY AMON AYRS [1] D R R A FT D R R A F D R A FT A FT A FT Access W R/W R/W R/W R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Address offset 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 0x024 0x028 0x02C 0x030 0x034 0x038 0x03C 0x040 0x044 0x05C 0x060 0x064 0x068 0x6C 0x070 0x074 0x078 0x07C Description Interrupt Location Register Reserved Clock Control Register Counter Increment Interrupt Register Alarm Mask Register Consolidated Time Register 0 Consolidated Time Register 1 Consolidated Time Register 2 Seconds Register Minutes Register Hours Register Day of Month Register Day of Week Register Day of Year Register Months Register Years Register Calibration Value Register Reset Value 0x0 0x00 0x00 0x00 -[1] -[1] -[1] -[1] -[1] -[1] -[1] -[1] -[1] -[1] -[1] -[1] -[1] - D D R A FT D R A Alarm value for Seconds Alarm value for Minutes Alarm value for Hours Alarm value for Day of Month Alarm value for Day of Week Alarm value for Day of Year Alarm value for Months Alarm value for Year -[1] -[1] -[1] -[1] -[1] -[1] -[1] -[1] This register value is not changed by reset. In addition to the RTC registers, 64 general purpose registers are available to store data when the main power supply is switched off. The general purpose registers reside in the RTC power domain and can be battery powered. Table 633. Register overview: REGFILE (base address 0x4004 1000) Name REGFILE0 to REGFILE63 R/W 0x0FC General purpose storage register 0x0 Access R/W Address offset 0x000 Description General purpose storage register Reset Value 0x0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 701 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 31: LPC18xx Real-Time Clock (RTC) FT D R A D R A R A FT D R FT 31.6.1 Interrupt Location Register D R The Interrupt Location Register is a 2-bit register that specifies which blocks are generating an interrupt (see Table 634). Writing a one to the appropriate bit clears the corresponding interrupt. Writing a zero has no effect. This allows the programmer to read this register and write back the same value to clear only the interrupt that is detected by the read. D R A FT D Table 634. Interrupt Location Register (ILR - address 0x4004 6000) bit description Bit 0 Symbol RTCCIF Description Reset value 0 When one, the Counter Increment Interrupt block generated an interrupt. Writing a one to this bit location clears the counter increment interrupt. When one, the alarm registers generated an interrupt. Writing a one to 0 this bit location clears the alarm interrupt. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA R A FT R A F D R A FT D FT D R A R A A FT 1 31:2 RTCALF - 31.6.2 Clock Control Register The clock register is a 4-bit register that controls the operation of the clock divide circuit. Each bit of the clock register is described in Table 635. Bits 0, 1, and 4 in this register should be initialized when the RTC is first turned on. Table 635. Clock Control Register (CCR - address 0x4004 6008) bit description Bit 0 Symbol CLKEN 0 1 1 CTCRST 0 1 Value Description Clock Enable. The time counters are disabled so that they may be initialized. The time counters are enabled. CTC Reset. No effect. When one, the elements in the internal oscillator divider are reset, and remain reset until CCR[1] is changed to zero. This is the divider that generates the 1 Hz clock from the 32.768 kHz crystal. The state of the divider is not visible to software. Internal test mode controls. These bits must be 0 for normal RTC operation. Calibration counter enable. 0 The calibration counter is enabled and counting, using the 1 Hz clock. When the calibration counter is equal to the value of the CALIBRATION register, the counter resets and repeats counting up to the value of the CALIBRATION register. See Section 31.6.6.2 and Section 31.7.1. The calibration counter is disabled and reset to zero. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA -[1] -[1] 0 Reset value -[1] 3:2 4 CCALEN 1 31:5 [1] - This register value is not changed by reset. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 702 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 31: LPC18xx Real-Time Clock (RTC) FT D R A D R A R A FT D R FT 31.6.3 Counter Increment Interrupt Register D R The Counter Increment Interrupt Register (CIIR) gives the ability to generate an interrupt every time a counter is incremented. This interrupt remains valid until cleared by writing a 1 to bit 0 of the Interrupt Location Register (ILR[0]). D R A FT D Table 636. Counter Increment Interrupt Register (CIIR - address 0x4004 600C) bit description Bit 0 1 2 3 4 5 6 7 31:8 Symbol IMSEC IMMIN IMHOUR IMDOM IMDOW IMDOY IMMON IMYEAR Description When 1, an increment of the Second value generates an interrupt. When 1, an increment of the Minute value generates an interrupt. When 1, an increment of the Hour value generates an interrupt. When 1, an increment of the Day of Month value generates an interrupt. When 1, an increment of the Day of Week value generates an interrupt. When 1, an increment of the Month value generates an interrupt. When 1, an increment of the Year value generates an interrupt. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Reset value 0 0 0 0 0 When 1, an increment of the Day of Year value generates an interrupt. 0 0 0 NA R A FT R A F D R A FT D FT D R A R A A FT 31.6.4 Alarm Mask Register The Alarm Mask Register (AMR) allows the user to mask any of the alarm registers. Table 637 shows the relationship between the bits in the AMR and the alarms. For the alarm function, every non-masked alarm register must match the corresponding time counter for an interrupt to be generated. The interrupt is generated only when the counter comparison first changes from no match to match. The interrupt is removed when a one is written to the appropriate bit of the Interrupt Location Register (ILR). If all mask bits are set, then the alarm is disabled. Table 637. Alarm Mask Register (AMR - address 0x4004 6010) bit description Bit 0 1 2 3 4 5 6 7 31:8 Symbol AMRSEC AMRMIN AMRDOM AMRDOW AMRDOY AMRMON AMRYEAR Description When 1, the Second value is not compared for the alarm. When 1, the Minutes value is not compared for the alarm. When 1, the Day of Month value is not compared for the alarm. When 1, the Day of Week value is not compared for the alarm. When 1, the Day of Year value is not compared for the alarm. When 1, the Month value is not compared for the alarm. When 1, the Year value is not compared for the alarm. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Reset value 0 0 0 0 0 0 0 0 NA AMRHOUR When 1, the Hour value is not compared for the alarm. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 703 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 31: LPC18xx Real-Time Clock (RTC) FT D R A D R A R A FT D R FT 31.6.5 Consolidated time registers D R The values of the Time Counters can optionally be read in a consolidated format which allows the programmer to read all time counters with only three read operations. The various registers are packed into 32-bit values as shown in Table 638, Table 639, and Table 640. The least significant bit of each register is read back at bit 0, 8, 16, or 24. D R A The Consolidated Time Registers are read-only. To write new values to the Time Counters, the Time Counter addresses should be used. R A FT R A F D R A FT D R A FT D R A A FT FT D 31.6.5.1 Consolidated Time Register 0 The Consolidated Time Register 0 contains the low order time values: Seconds, Minutes, Hours, and Day of Week. Table 638. Consolidated Time register 0 (CTIME0 - address 0x4004 6014) bit description Bit 5:0 7:6 13:8 15:14 20:16 23:21 26:24 31:27 [1] Symbol SECONDS MINUTES HOURS DOW - Description Seconds value in the range of 0 to 59 Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Minutes value in the range of 0 to 59 Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Hours value in the range of 0 to 23 Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Day of week value in the range of 0 to 6 Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Reset value -[1] -[1] -[1] -[1] -[1] - This register value is not changed by reset. 31.6.5.2 Consolidated Time Register 1 The Consolidate Time Register 1 contains the Day of Month, Month, and Year values. Table 639. Consolidated Time register 1 (CTIME1 - address 0x4004 6018) bit description Bit 4:0 7:5 11:8 15:12 27:16 31:28 [1] Symbol DOM MONTH YEAR - Description Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year). Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Month value in the range of 1 to 12. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Year value in the range of 0 to 4095. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Reset value -[1] -[1] -[1] - This register value is not changed by reset. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 704 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 31: LPC18xx Real-Time Clock (RTC) FT D R A D R A R A FT D R FT 31.6.5.3 Consolidated Time Register 2 The Consolidate Time Register 2 contains just the Day of Year value. D R Table 640. Consolidated Time register 2 (CTIME2 - address 0x4004 601C) bit description Bit 11:0 31:12 [1] R A FT D R R A F D R A FT A FT A FT D D Symbol DOY - Description Day of year value in the range of 1 to 365 (366 for leap years). Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Reset value -[1] - R A FT D R A This register value is not changed by reset. 31.6.6 Time Counter Group The time value consists of the eight counters shown in Table 641 and Table 642. These counters can be read or written at the locations shown in Table 642. Table 641. Time Counter relationships and values Counter Second Minute Hour Day of Month Day of Week Day of Year Month Year Size 6 6 5 5 3 9 4 12 Enabled by 1 Hz Clock Second Minute Hour Hour Hour Day of Month Month or day of Year Minimum value 0 0 0 1 0 1 1 0 Maximum value 59 59 23 28, 29, 30 or 31 6 365 or 366 (for leap year) 12 4095 Table 642. Time Counter registers Name SEC MIN HRS DOM Size 6 6 5 5 Description Seconds value in the range of 0 to 59 Minutes value in the range of 0 to 59 Hours value in the range of 0 to 23 Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year).[1] Day of week value in the range of 0 to 6[1] Day of year value in the range of 1 to 365 (366 for leap years)[1] Month value in the range of 1 to 12 Year value in the range of 0 to 4095 Access R/W R/W R/W R/W Address 0x4004 6020 0x4004 6024 0x4004 6028 0x4004 602C DOW DOY MONTH YEAR [1] 3 9 4 12 R/W R/W R/W R/W 0x4004 6030 0x4004 6034 0x4004 6038 0x4004 603C These values are simply incremented at the appropriate intervals and reset at the defined overflow point. They are not calculated and must be correctly initialized in order to be meaningful. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 705 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 31: LPC18xx Real-Time Clock (RTC) FT D R Table 643. Second register (SEC - address 0x4004 6020) bit description Bit 5:0 31:6 [1] D R A R A FT D R FT D A R R A FT R A F A FT Symbol SECONDS - Description Seconds value in the range of 0 to 59 Reset value D D Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. R R - A -[1] A FT D R A FT D FT D R This register value is not changed by reset. A Table 644. Minute register (MIN - address 0x4004 6024) bit description Bit 5:0 31:6 [1] Symbol MINUTES - Description Minutes value in the range of 0 to 59 Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Reset value -[1] - This register value is not changed by reset. Table 645. Hour register (HRS - address 0x4004 6028) bit description Bit 4:0 31:5 [1] Symbol HOURS - Description Hours value in the range of 0 to 23 Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Reset value -[1] - This register value is not changed by reset. Table 646. Days of month register (DOM - address 0x4004 602C) bit description Bit 4:0 31:5 [1] Symbol DOM - Description Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year). Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Reset value -[1] - This register value is not changed by reset. Table 647. Days of week register (DOW - address 0x4004 6030) bit description Bit 2:0 31:3 [1] Symbol DOW - Description Day of week value in the range of 0 to 6. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Reset value -[1] - This register value is not changed by reset. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 706 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 31: LPC18xx Real-Time Clock (RTC) FT D Table 648. Days of year register (DOY - address 0x4004 6034) bit description Bit 8:0 31:9 [1] D R A R A FT D R R R A FT D R A R A FT A FT F Symbol DOY - Description Reset value D D Day of year value in the range of 1 to 365 (366 for leap years). Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. R R - A -[1] A FT D R A FT D FT D R This register value is not changed by reset. A Table 649. Month register (MONTH - address 0x4004 6038) bit description Bit 3:0 31:4 [1] Symbol MONTH - Description Month value in the range of 1 to 12. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Reset value -[1] - This register value is not changed by reset. Table 650. Year register (YEAR - address 0x4004 603C) bit description Bit 11:0 31:4 [1] Symbol YEAR - Description Year value in the range of 0 to 4095. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Reset value -[1] - This register value is not changed by reset. 31.6.6.1 Leap year calculation The RTC does a simple bit comparison to see if the two lowest order bits of the year counter are zero. If true, then the RTC considers that year a leap year. The RTC considers all years evenly divisible by 4 as leap years. This algorithm is accurate from the year 1901 through the year 2099, but fails for the year 2100, which is not a leap year. The only effect of leap year on the RTC is to alter the length of the month of February for the month, day of month, and year counters. 31.6.6.2 Calibration register The following register is used to calibrate the time counter. The bits in this register are not changed by reset. Table 651. Calibration register (CALIBRATION - address 0x4004 6040) bit description Bit 16:0 Symbol CALVAL Value Description Reset value If enabled, the calibration counter counts up to this value. -[1] The maximum value is 131072 corresponding to about 36.4 hours. Calibration is disabled if CALVAL = 0. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 707 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 31: LPC18xx Real-Time Clock (RTC) FT D R R A Table 651. Calibration register (CALIBRATION - address 0x4004 6040) bit description D R A R A FT D R FT D R A R A A Bit 17 Symbol CALDIR Value Description Calibration direction Reset value FT D R A F FT D R -[1] A FT D FT D 0 1 Forward calibration. When CALVAL is equal to the calibration counter, the RTC timers will jump by 2 seconds. Backward calibration. When CALVAL is equal to the calibration counter, the RTC timers will stop incrementing for 1 second. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - R A FT D R A 31:12 [1] This register value is not changed by reset. 31.6.7 Alarm register group The alarm registers are shown in Table 652. The values in these registers are compared with the time counters. If all the unmasked (See Section 31.6.4 “Alarm Mask Register” on page 703) alarm registers match their corresponding time counters then an interrupt is generated. The interrupt is cleared when a 1 is written to bit 1 of the Interrupt Location Register (ILR[1]). Table 652. Alarm registers Name ALSEC ALMIN ALHRS ALDOM ALDOW ALDOY ALMON ALYEAR Size 6 6 5 5 3 9 4 12 Description Alarm value for Seconds Alarm value for Minutes Alarm value for Hours Alarm value for Day of Month Alarm value for Day of Week Alarm value for Day of Year Alarm value for Months Alarm value for Years Access R/W R/W R/W R/W R/W R/W R/W R/W Address 0x4004 6060 0x4004 6064 0x4004 6068 0x4004 606C 0x4004 6070 0x4004 6074 0x4004 6078 0x4004 607C Table 653. Alarm Second register (ASEC - address 0x4004 6060) bit description Bit 5:0 31:6 [1] Symbol SECONDS - Description Seconds value in the range of 0 to 59 Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Reset value -[1] - This register value is not changed by reset. Table 654. Alarm Minute register (AMIN - address 0x4004 6064) bit description Bit 5:0 31:6 [1] Symbol MINUTES - Description Minutes value in the range of 0 to 59 Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Reset value -[1] - This register value is not changed by reset. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 708 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 31: LPC18xx Real-Time Clock (RTC) FT D Table 655. Alarm Hour register (AHRS - address 0x4004 6068) bit description Bit 4:0 31:5 [1] D R A R A FT D R R R A FT D R A R A FT A FT F Symbol HOURS - Description Hours value in the range of 0 to 23 Reset value D D Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. R R - A -[1] A FT D R A FT D FT D R This register value is not changed by reset. A Table 656. Alarm Days of month register (ADOM - address 0x4004 606C) bit description Bit 4:0 31:5 [1] Symbol DOM - Description Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year). Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Reset value -[1] - This register value is not changed by reset. Table 657. Alarm Days of week register (ADOW - address 0x4004 6070) bit description Bit 2:0 31:3 [1] Symbol DOW - Description Day of week value in the range of 0 to 6. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Reset value -[1] - This register value is not changed by reset. Table 658. Alarm Days of year register (ADOY - address 0x4004 6074) bit description Bit 8:0 31:9 [1] Symbol DOY - Description Day of year value in the range of 1 to 365 (366 for leap years). Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Reset value -[1] - This register value is not changed by reset. Table 659. Alarm Month register (AMON - address 0x4004 6078) bit description Bit 3:0 31:4 [1] Symbol MONTH - Description Month value in the range of 1 to 12. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Reset value -[1] - This register value is not changed by reset. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 709 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 31: LPC18xx Real-Time Clock (RTC) FT D Table 660. Alarm Year register (AYRS - address 0x4004 607C) bit description Bit 11:0 31:4 [1] D R A R A FT D R R R A FT D R A R A FT A FT F Symbol YEAR - Description Year value in the range of 0 to 4095. Reset value D D Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. R R - A -[1] A FT D R A FT D FT D R This register value is not changed by reset. A 31.7 Functional description 31.7.1 Calibration procedure The calibration logic can periodically adjust the time counter either by not incrementing the counter, or by incrementing the counter by 2 instead of 1. This allows calibrating the RTC oscillator under some typical voltage and temperature conditions without the need to externally trim the RTC oscillator. A recommended method for determining the calibration value is to use the CLKOUT feature to unintrusively observe the RTC oscillator frequency under the conditions it is to be trimmed for, and calculating the number of clocks that will be seen before the time is off by one second. That value is used to determine CALVAL. The exact method of calibration depends on whether CALVAL is even or odd. For even values, the hardware performs a two calibrations sequentially multiple times (one calibration at CALVAL+1 and one calibration at CALVAL - 1) and averages both calibration values. For odd values of CALVAL, the calibration time is accurate. If the RTC oscillator is trimmed externally, the same method of unintrusively observing the RTC oscillator frequency may be helpful in that process. Backward calibration Enable the RTC timer and calibration in the CCR register (set bits CLKEN = 1 and CCALEN = 0). In the CALIBRATION register, set the calibration value CALVAL  1 and select CALDIR = 1. • The SEC timer and the calibration counter count up for every 1 Hz clock cycle. • When the calibration counter reaches CALVAL, a calibration match occurs and all RTC timers will be stopped for one clock cycle so that the timers will not increment in the next cycle. • If an alarm match event occurs in the same cycle as the calibration match, the alarm interrupt will be delayed by one cycle to avoid a double alarm interrupt. Forward calibration Enable the RTC timer and calibration in the CCR register (set bits CLKEN = 1 and CCALEN = 0). In the CALIBRATION register, set the calibration value CALVAL  1 and select CALDIR = 0. • The SEC timer and the calibration counter count up for every 1 Hz clock cycle. • When the calibration counter reaches CALVAL, a calibration match occurs and the RTC timers are incremented by 2. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 710 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 31: LPC18xx Real-Time Clock (RTC) FT D R R A • When the calibration event occurs, the LSB of the ALSEC register is forced to be one R so that the alarm interrupt will not be missed when skipping a second. D R A R A FT D R FT D R A A A FT D R A FT D R A FT D R A FT F FT D D R A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 711 of 1164 D R A FT D R A FT D R A FT D R A FT D R A FT UM10430 Chapter 32: LPC18xx USART0_2_3 Rev. 00.13 — 20 July 2011 D D D R A FT D D R A FT D R A FT D R A R A FT D R A R A FT D R A FT D R A F R A FT D R R D User manual FT D R A FT FT A FT 32.1 How to read this chapter The USART0/2/3 controllers are available on all LPC18xx parts. D D R A FT D R A 32.2 Basic configuration The USART0/2/3 are configured as follows: • • • • See Table 661 for clocking and power control. The USART0/2/3 are reset by the UART0/2/3_RST (reset #44/46/47). The USART0/2/3 interrupts are connected to slots # 24/26/27 in the NVIC. For connecting the USART0/2/3 receive and transmit lines to the GPDMA, use the DMAMUX register in the CREG block (see Table 35) and enable the GPDMA channel in the DMA Channel Configuration registers (Section 16.6.20). Table 661. USART0/2/3 clocking and power control Base clock USART0 clock to register interface USART0 peripheral clock (PCLK) USART2 clock to register interface USART2 peripheral clock (PCLK) USART3 clock to register interface USART3 peripheral clock (PCLK) BASE_M3_CLK BASE_UART0_CLK BASE_M3_CLK BASE_UART2_CLK BASE_M3_CLK BASE_UART3_CLK Branch clock CLK_M3_UART0 CLK_M3_UART2 CLK_M3_UART3 Maximum frequency 150 MHz 150 MHz 150 MHz CLK_APB0_UART0 150 MHz CLK_APB2_UART2 150 MHz CLK_APB2_UART3 150 MHz 32.3 Features • • • • • • • • • • 16-byte receive and transmit FIFOs. Register locations conform to ‘550 industry standard. Receiver FIFO trigger points at 1, 4, 8, and 14 bytes. Built-in baud rate generator. UART allows for implementation of either software or hardware flow control. RS-485/EIA-485 9-bit mode support with output enable. Support for synchronous mode UART (USART). IrDA interface (USART3 only). DMA support. Smart Card interface. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 712 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 32: LPC18xx USART0_2_3 FT D R A D R A R A FT D R FT 32.4 Pin description Table 662. USART0/2/3 pin description Function name USART0 U0_RXD U0_TXD U0_DIR U0_UCLK USART2 U2_RXD U2_TXD U2_DIR U2_UCLK USART3 U3_RXD U3_TXD U3_DIR U3_UCLK U3_BAUD I O I/O I/O Serial Input. Serial receive data. Serial Output. Serial transmit data. RS-485/EIA-485 output enable/direction control. I O I/O I/O Serial Input. Serial receive data. Serial Output. Serial transmit data. RS-485/EIA-485 output enable/direction control. I O I/O I/O Serial Input. Serial receive data. Serial Output. Serial transmit data. RS-485/EIA-485 output enable/direction control. Direction Description D R Serial clock input/output for USART0 in synchronous mode. Serial clock input/output for USART2 in synchronous mode. Serial clock input/output for USART3 in synchronous mode. R A FT D R R A F D R A FT A FT A FT D R A D FT D R A 32.5 Register description The UART contains registers organized as shown in Table 663. The Divisor Latch Access Bit (DLAB) is contained in LCR[7] and enables access to the Divisor Latches. Reset value reflects the data stored in used bits only. It does not include the content of reserved bits. Table 663. Register overview: UART0/2/3 (base address: 0x4008 1000, 0x400C 1000, 0x400C 2000) Name RBR THR DLL Access Address Description offset RO WO R/W 0x000 0x000 0x000 Receiver Buffer Register. Contains the next received character to be read (DLAB = 0). Reset value NA Transmit Holding Register. The next character to be NA transmitted is written here (DLAB = 0). Divisor Latch LSB. Least significant byte of the baud 0x01 rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). Divisor Latch MSB. Most significant byte of the baud 0x00 rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB = 0). 0x00 DLM R/W 0x004 IER R/W 0x004 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 713 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 32: LPC18xx USART0_2_3 FT D R R A Table 663. Register overview: UART0/2/3 (base address: 0x4008 1000, 0x400C 1000, 0x400C 2000) D R A R A FT D R FT D R A R A A FT F FT Name IIR FCR LCR LSR SCR ACR ICR FDR HDEN SCICTRL RS485CTRL Access Address Description offset RO WO R/W RO R/W R/W R/W R/W R/W R/W R/W 0x008 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 0x024 0x028 0x02C 0x03C 0x040 0x044 0x048 0x04C Reset value D Interrupt ID Register. Identifies which interrupt(s) are 0x01 pending. FIFO Control Register. Controls UART FIFO usage and modes. Line Control Register. Contains controls for frame formatting and break generation. Reserved 0x00 0x00 - Line Status Register. Contains flags for transmit and 0x60 receive status, including line errors. Reserved Scratch Pad Register. Eight-bit temporary storage for software. Auto-baud Control Register. Contains controls for the auto-baud feature. IrDA control register (UART3 only) 0x00 0x00 0x00 Fractional Divider Register. Generates a clock input 0x10 for the baud rate divider. Reserved Half-duplex enable Register Reserved Smart card interface control register RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. RS-485/EIA-485 direction control delay. Synchronous mode control register. Transmit Enable Register. Turns off UART transmitter for use with software flow control. 0x00 - D R R A A FT D A FT D R A FT D R RS485ADRMA R/W TCH RS485DLY SYNCCTRL TER R/W R/W R/W 0x050 0x054 0x058 0x05C 0x00 0x00 0x00 0x01 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 714 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 32: LPC18xx USART0_2_3 FT D R A D R A R A FT D R FT 32.5.1 UART Receiver Buffer Register D R The RBR is the top byte of the UART RX FIFO. The top byte of the RX FIFO contains the oldest character received and can be read via the bus interface. The LSB (bit 0) represents the “oldest” received data bit. If the character received is less than 8 bits, the unused MSBs are padded with zeroes. The Divisor Latch Access Bit (DLAB) in LCR must be zero in order to access the RBR. The RBR is always Read Only. D R A FT D Since PE, FE and BI bits (see Table 673) correspond to the byte sitting on the top of the RBR FIFO (i.e. the one that will be read in the next read from the RBR), the right approach for fetching the valid pair of received byte and its status bits is first to read the content of the LSR register, and then to read a byte from the RBR. Table 664. UART Receiver Buffer Registers when DLAB = 0, Read Only (RBR - addresses 0x4008 1000 (UART0), 0x400C 1000 (UART2), 0x400C 2000 (UART3)) bit description Bit 7:0 Symbol RBR Description Reset value undefined Receiver buffer. The UART Receiver Buffer Register contains the oldest received byte in the UART RX FIFO. Reserved - R A FT R A F D R A FT D FT D R A R A A FT 31:8 - 32.5.2 UART Transmitter Holding Register The THR is the top byte of the UART TX FIFO. The top byte is the newest character in the TX FIFO and can be written via the bus interface. The LSB represents the first bit to transmit. The Divisor Latch Access Bit (DLAB) in LCR must be zero in order to access the THR. The THR is always Write Only. Table 665. UART Transmitter Holding Register when DLAB = 0, Write Only(THR - addresses 0x4008 1000 (UART0), 0x400C 1000 (UART2), 0x400C 2000 (UART3)) bit description Bit 7:0 Symbol THR Description Transmit Holding Register. Writing to the UART Transmit Holding Register causes the data to be stored in the UART transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available. Reserved Reset value NA 31:8 - - 32.5.3 UART Divisor Latch LSB and MSB Registers The UART Divisor Latch is part of the UART Baud Rate Generator and holds the value used, along with the Fractional Divider, to divide the UART_PCLK clock in order to produce the baud rate clock, which must be 16x the desired baud rate. The DLL and DLM registers together form a 16-bit divisor where DLL contains the lower 8 bits of the divisor and DLM contains the higher 8 bits of the divisor. A 0x0000 value is treated like a 0x0001 value as division by zero is not allowed.The Divisor Latch Access Bit (DLAB) in LCR must be one in order to access the UART Divisor Latches. Details on how to select the right value for DLL and DLM can be found in Section 32.5.12. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 715 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 32: LPC18xx USART0_2_3 FT D R R A Table 666. UART Divisor Latch LSB Register when DLAB = 1 (DLL - addresses 0x4008 1000 (UART0), 0x400C 1000 (UART2), 0x400C 2000 (UART3)) bit description D R A R A FT D R FT D R A R A A FT D F FT D Bit 7:0 Symbol DLLSB Description Divisor latch LSB. The UART Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the UART. Reserved Reset value R R A A FT D R A 0x01 FT D FT 31:8 - - D R A Table 667. UART Divisor Latch MSB Register when DLAB = 1 (DLM - addresses 0x4008 1004 (UART0), 0x400C 1004 (UART2), 0x400C 2004 (UART3)) bit description Bit 7:0 Symbol DLMSB Description Divisor latch MSB. The UART Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the UART. Reserved Reset value 0x00 31:8 - - 32.5.4 UART Interrupt Enable Register The IER is used to enable the four UART interrupt sources. Table 668. UART Interrupt Enable Register when DLAB = 0 (IER - addresses 0x4008 1004 (UART0), 0x400C 1004 (UART2), 0x400C 2004 (UART3) ) bit description Bit 0 Symbol RBRIE Value Description RBR Interrupt Enable. Enables the Receive Data Available interrupt for UART. It also controls the Character Receive Time-out interrupt. 0 1 1 THREIE Disable the RDA interrupt. Enable the RDA interrupt. THRE Interrupt Enable. Enables the THRE interrupt for UART. The status of this interrupt can be read from LSR[5]. 0 1 2 RXIE Disable the THRE interrupt. Enable the THRE interrupt. RX Line Interrupt Enable. Enables the UART RX line status interrupts. The status of this interrupt can be read from LSR[4:1]. 0 1 3 6:4 7 8 ABEOINTEN 0 1 Disable the RX line status interrupts. Enable the RX line status interrupts. Reserved Reserved, user software should not write ones to reserved NA bits. The value read from a reserved bit is not defined. Reserved Enables the end of auto-baud interrupt. Disable end of auto-baud Interrupt. Enable end of auto-baud Interrupt. 0 0 0 0 Reset value 0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 716 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 32: LPC18xx USART0_2_3 FT D R R A Table 668. UART Interrupt Enable Register when DLAB = 0 (IER - addresses 0x4008 1004 (UART0), 0x400C 1004 (UART2), 0x400C 2004 (UART3) ) bit description …continued D R A R A FT D R FT D R A R A A FT F FT Bit 9 Symbol ABTOINTEN Value Description Enables the auto-baud time-out interrupt. Reset value D D R R 0 A A FT D A FT D R 0 1 31:10 - Disable auto-baud time-out Interrupt. Enable auto-baud time-out Interrupt. Reserved, user software should not write ones to reserved NA bits. The value read from a reserved bit is not defined. FT D R A 32.5.5 UART Interrupt Identification Register IIR provides a status code that denotes the priority and source of a pending interrupt. The interrupts are frozen during a IIR access. If an interrupt occurs during a IIR access, the interrupt is recorded for the next IIR access. Table 669. UART Interrupt Identification Register, read only (IIR - addresses 0x4008 1008 (UART0), 0x400C 1008 (UART2), 0x400C 2008 (UART3)) bit description Bit 0 Symbol INTSTATUS Value Description Reset value Interrupt status. 1 Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1]. 0 1 At least one interrupt is pending. No interrupt is pending. Interrupt identification. IER[3:1] identifies an interrupt corresponding to the UART Rx FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111). 0x3 0x2 0x6 0x1 0x0 Priority 1 (highest) - Receive Line Status (RLS). Priority 2 - Receive Data Available (RDA). Priority 2 - Character Time-out Indicator (CTI). Priority 3 - THRE Interrupt. Priority 4 (lowest) - Reserved. Reserved, user software should not write ones to reserved NA bits. The value read from a reserved bit is not defined. Copies of FCR[0]. 0 End of auto-baud interrupt. 0 True if auto-baud has finished successfully and interrupt is enabled. Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled. 0 0 3:1 INTID 5:4 7:6 8 FIFOENABLE ABEOINT 9 ABTOINT 31:10 - Reserved, user software should not write ones to reserved NA bits. The value read from a reserved bit is not defined. Bits IIR[9:8] are set by the auto-baud function and signal a time-out or end of auto-baud condition. The auto-baud interrupt conditions are cleared by setting the corresponding Clear bits in the Auto-baud Control Register. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 717 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 32: LPC18xx USART0_2_3 FT D R R A If the IntStatus bit is one and no interrupt is pending and the IntId bits will be zero. If the IntStatus is 0, a non auto-baud interrupt is pending in which case the IntId bits identify the type of interrupt and handling as described in Table 670. Given the status of IIR[3:0], an interrupt handler routine can determine the cause of the interrupt and how to clear the active interrupt. The IIR must be read in order to clear the interrupt prior to exiting the Interrupt Service Routine. R A A FT D R A FT D The UART RLS interrupt (IIR[3:1] = 011) is the highest priority interrupt and is set whenever any one of four error conditions occur on the UART RX input: overrun error (OE), parity error (PE), framing error (FE) and break interrupt (BI). The UART Rx error condition that set the interrupt can be observed via LSR[4:1]. The interrupt is cleared upon a LSR read. The UART RDA interrupt (IIR[3:1] = 010) shares the second level priority with the CTI interrupt (IIR[3:1] = 110). The RDA is activated when the UART Rx FIFO reaches the trigger level defined in FCR7:6 and is reset when the UART Rx FIFO depth falls below the trigger level. When the RDA interrupt goes active, the CPU can read a block of data defined by the trigger level. The CTI interrupt (IIR[3:1] = 110) is a second level interrupt and is set when the UART Rx FIFO contains at least one character and no UART Rx FIFO activity has occurred in 3.5 to 4.5 character times. Any UART Rx FIFO activity (read or write of UART RSR) will clear the interrupt. This interrupt is intended to flush the UART RBR after a message has been received that is not a multiple of the trigger level size. For example, if a peripheral wished to send a 105 character message and the trigger level was 10 characters, the CPU would receive 10 RDA interrupts resulting in the transfer of 100 characters and 1 to 5 CTI interrupts (depending on the service routine) resulting in the transfer of the remaining 5 characters. Table 670. UART Interrupt Handling IIR[3:0] value[1] 0001 0110 Priority Interrupt type None Highest RX Line Status / Error Second RX Data Available Interrupt source None OE[2] or PE[2] or FE[2] or BI[2] Interrupt reset LSR Read[2] D R A R A FT D R FT D R A F R A FT D FT D R A D FT R A 0100 Rx data available or trigger level reached in FIFO (FCR0=1) RBR Read[3] or UART FIFO drops below trigger level 1100 Second Character Minimum of one character in the RX FIFO and RBR Time-out no character input or removed during a time Read[3] indication period depending on how many characters are in FIFO and what the trigger level is set at (3.5 to 4.5 character times). The exact time will be: [(word length)  7 - 2]  8 + [(trigger level number of characters)  8 + 1] RCLKs 0010 Third THRE THRE[2] IIR Read[4] (if source of interrupt) or THR write © NXP B.V. 2011. All rights reserved. All information provided in this document is subject to legal disclaimers. User manual Rev. 00.13 — 20 July 2011 718 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 32: LPC18xx USART0_2_3 FT D R A D R A R A FT D R FT [1] [2] [3] [4] Values 0000, 0011, 010, 0111, 1000, 1001, 1010, 1011,1101, 1110,1111 are reserved. For details see Section 32.5.8 “UART Line Status Register” For details see Section 32.5.1 “UART Receiver Buffer Register” D R For details see Section 32.5.5 “UART Interrupt Identification Register” and Section 32.5.2 “UART Transmitter Holding Register” The UART THRE interrupt (IIR[3:1] = 001) is a third level interrupt and is activated when the UART THR FIFO is empty provided certain initialization conditions have been met. These initialization conditions are intended to give the UART THR FIFO a chance to fill up with data to eliminate many THRE interrupts from occurring at system start-up. The initialization conditions implement a one character delay minus the stop bit whenever THRE = 1 and there have not been at least two characters in the THR at one time since the last THRE = 1 event. This delay is provided to give the CPU time to write data to THR without a THRE interrupt to decode and service. A THRE interrupt is set immediately if the UART THR FIFO has held two or more characters at one time and currently, the THR is empty. The THRE interrupt is reset when a THR write occurs or a read of the IIR occurs and the THRE is the highest interrupt (IIR[3:1] = 001). R A FT D R R A F D R A FT A FT A FT D R A D FT D R A 32.5.6 UART FIFO Control Register The FCR controls the operation of the UART RX and TX FIFOs. Table 671. UART FIFO Control Register Write Only (FCR - addresses 0x4008 1008 (UART0), 0x400C 1008 (UART2), 0x400C 2008 (UART3)) bit description Bit 0 Symbol FIFOEN 0 1 Value Description FIFO Enable. UART FIFOs are disabled. Must not be used in the application. Active high enable for both UART Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the UART FIFOs. RX FIFO Reset. 0 1 2 TXFIFO RES No impact on either of UART FIFOs. Writing a logic 1 to FCR[1] will clear all bytes in UART Rx FIFO, reset the pointer logic. This bit is self-clearing. TX FIFO Reset. 0 1 3 5:4 DMAMO DE No impact on either of UART FIFOs. Writing a logic 1 to FCR[2] will clear all bytes in UART TX FIFO, reset the pointer logic. This bit is self-clearing. DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0 NA 0 0 Reset value 0 1 RXFIFO RES All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 719 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 32: LPC18xx USART0_2_3 FT D R R A Table 671. UART FIFO Control Register Write Only (FCR - addresses 0x4008 1008 (UART0), 0x400C 1008 (UART2), 0x400C 2008 (UART3)) bit description D R A R A FT D R FT D R A R A A FT F FT Bit 7:6 Symbol RXTRIG LVL Value Description RX Trigger Level. These two bits determine how many receiver UART FIFO characters must be written before an interrupt is activated. 0x0 0x1 0x2 0x3 Trigger level 0 (1 character or 0x01). Trigger level 1 (4 characters or 0x04). Trigger level 2 (8 characters or 0x08). Trigger level 3 (14 characters or 0x0E). Reserved Reset value D D R R A A 0 FT D A FT D R A FT D R 31:8 - - - 32.5.6.1 DMA Operation The user can optionally operate the UART transmit and/or receive using DMA. The DMA mode is determined by the DMA Mode Select bit in the FCR register. Note that for DMA operation as for any operation of the UART, the FIFOs must be enabled via the FIFO Enable bit in the FCR register. UART receiver DMA In DMA mode, the receiver DMA request is asserted when the receiver FIFO level becomes equal to or greater than trigger level, or if a character time-out occurs. See the description of the RX Trigger Level above. The receiver DMA request is cleared by the DMA controller. UART transmitter DMA In DMA mode, the transmitter DMA request is asserted when the transmitter FIFO transitions to not full. The transmitter DMA request is cleared by the DMA controller. 32.5.7 UART Line Control Register The LCR determines the format of the data character that is to be transmitted or received. Table 672. UART Line Control Register (LCR - addresses 0x4008 100C (UART0), 0x400C 100C (UART2), 0x400C 200C (UART3)) bit description Bit 1:0 Symbol Value Description WLS 0x0 0x1 0x2 0x3 2 SBS 0 1 Word Length Select. 5-bit character length. 6-bit character length. 7-bit character length. 8-bit character length. Stop Bit Select. 1 stop bit. 2 stop bits (1.5 if LCR[1:0]=00). 0 Reset Value 0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 720 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 32: LPC18xx USART0_2_3 FT D R R A Table 672. UART Line Control Register (LCR - addresses 0x4008 100C (UART0), 0x400C 100C (UART2), 0x400C 200C (UART3)) bit description …continued D R A R A FT D R FT D R A R A FT A F FT Bit 3 Symbol Value Description PE 0 1 Parity Enable Disable parity generation and checking. Enable parity generation and checking. Parity Select. 0x0 0x1 0x2 0x3 Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd. Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even. Forced "1" stick parity. Forced "0" stick parity. Break Control. 0 1 Disable break transmission. Reset Value D D R R A A 0 FT D A FT D R A FT D R 5:4 PS 0 6 BC 0 Enable break transmission. Output pin UART TXD is forced to logic 0 when LCR[6] is active high. Divisor Latch Access Bit. 0 Disable access to Divisor Latches. Enable access to Divisor Latches. Reserved - 7 DLAB 0 1 31: 8 - - 32.5.8 UART Line Status Register The LSR is a Read Only register that provides status information on the UART TX and RX blocks. Table 673. UART Line Status Register Read Only (LSR - addresses 0x4008 1014 (UART0), 0x400C 1014 (UART2), 0x400C 2014 (UART3) ) bit description Bit Symbol 0 RDR Value Description Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is cleared when the UART RBR FIFO is empty. 0 1 1 OE RBR is empty. RBR contains valid data. Overrun Error. The overrun error condition is set as soon as it occurs. A LSR read clears LSR[1]. LSR[1] is set when UART RSR has a new character assembled and the UART RBR FIFO is full. In this case, the UART RBR FIFO will not be overwritten and the character in the UART RSR will be lost. 0 1 Overrun error status is inactive. Overrun error status is active. 0 Reset Value 0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 721 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 32: LPC18xx USART0_2_3 FT D R R A Table 673. UART Line Status Register Read Only (LSR - addresses 0x4008 1014 (UART0), 0x400C 1014 (UART2), 0x400C 2014 (UART3) ) bit description …continued D R A R A FT D R FT D R A R A A FT F FT Bit Symbol 2 PE Value Description Reset Value D 0 Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the UART RBR FIFO. 0 1 Parity error status is inactive. Parity error status is active. 0 Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. A LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART RBR FIFO. 0 1 Framing error status is inactive. Framing error status is active. 0 Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the UART RBR FIFO. 0 1 Break interrupt status is inactive. Break interrupt status is active. 1 Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UART THR and is cleared on a THR write. 0 1 THR contains valid data. THR is empty. Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data. 0 1 THR and/or the TSR contains valid data. THR and the TSR are empty. 1 D R R A A FT D A FT D R A FT D R 3 FE 4 BI 5 THRE 6 TEMT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 722 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 32: LPC18xx USART0_2_3 FT D R R A Table 673. UART Line Status Register Read Only (LSR - addresses 0x4008 1014 (UART0), 0x400C 1014 (UART2), 0x400C 2014 (UART3) ) bit description …continued D R A R A FT D R FT D R A R A A FT F FT Bit Symbol 7 RXFE Value Description Reset Value D Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the UART FIFO. 0 1 RBR contains no UART RX errors or FCR[0]=0. UART RBR contains at least one UART RX error. Error in transmitted character. A NACK response is given by the receiver in Smart card T=0 mode. This bit is cleared when the LSR register is read. 0 1 No error (normal default condition). A NACK response is received during Smart card T=0 operation. Reserved D R R A A 0 FT D A FT D R A FT D R 8 TXERR 0 31: 9 - - 32.5.9 UART Scratch Pad Register The SCR has no effect on the UART operation. This register can be written and/or read at user’s discretion. There is no provision in the interrupt interface that would indicate to the host that a read or write of the SCR has occurred. Table 674. UART Scratch Pad Register (SCR - addresses 0x4008 101C (UART0), 0x400C 101C (UART2), 0x400C 201C (UART3)) bit description Bit 7:0 31:8 Symbol Description PAD Scratch pad. A readable, writable byte. Reserved Reset Value 0x00 - 32.5.10 UART Auto-baud Control Register The UART Auto-baud Control Register (ACR) controls the process of measuring the incoming clock/data rate for the baud rate generation and can be read and written at user’s discretion. Table 675. Autobaud Control Register (ACR - addresses 0x4008 1020 (UART0), 0x400C 1020 (UART2), 0x400C 2020 (UART3)) bit description Bit 0 Symbol START Value Description Start bit. This bit is automatically cleared after auto-baud completion. 0 1 Auto-baud stop (auto-baud is not running). Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion. Auto-baud mode select bit. 0 1 Reset value 0 1 MODE 0 Mode 0. Mode 1. © NXP B.V. 2011. All rights reserved. All information provided in this document is subject to legal disclaimers. User manual Rev. 00.13 — 20 July 2011 723 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 32: LPC18xx USART0_2_3 FT D R R A Table 675. Autobaud Control Register (ACR - addresses 0x4008 1020 (UART0), 0x400C 1020 (UART2), 0x400C 2020 (UART3)) bit description D R A R A FT D R FT D R A R A A FT F FT Bit 2 Symbol AUTORESTART Value Description Restart bit. 0 1 No restart Restart in case of time-out (counter restarts at next UART Rx falling edge) Reset value 0 D D R R A A FT D R A FT D R A FT D 7:3 - Reserved, user software should not write ones to 0 reserved bits. The value read from a reserved bit is not defined. End of auto-baud interrupt clear bit (write-only). 0 1 Writing a 0 has no impact. Writing a 1 will clear the corresponding interrupt in the IIR. Auto-baud time-out interrupt clear bit (write-only). 0 1 Writing a 0 has no impact. Writing a 1 will clear the corresponding interrupt in the IIR. Reserved, user software should not write ones to 0 reserved bits. The value read from a reserved bit is not defined. 0 0 8 ABEOINTCLR 9 ABTOINTCLR 31:10 - 32.5.10.1 Auto-baud The UART auto-baud function can be used to measure the incoming baud rate based on the ”AT" protocol (Hayes command). If enabled the auto-baud feature will measure the bit time of the receive data stream and set the divisor latch registers DLM and DLL accordingly. Auto-baud is started by setting the ACR Start bit. Auto-baud can be stopped by clearing the ACR Start bit. The Start bit will clear once auto-baud has finished and reading the bit will return the status of auto-baud (pending/finished). Two auto-baud measuring modes are available which can be selected by the ACR Mode bit. In Mode 0 the baud rate is measured on two subsequent falling edges of the UART Rx pin (the falling edge of the start bit and the falling edge of the least significant bit). In Mode 1 the baud rate is measured between the falling edge and the subsequent rising edge of the UART Rx pin (the length of the start bit). The ACR AutoRestart bit can be used to automatically restart baud rate measurement if a time-out occurs (the rate measurement counter overflows). If this bit is set, the rate measurement will restart at the next falling edge of the UART Rx pin. The auto-baud function can generate two interrupts. • The IIR ABTOInt interrupt will get set if the interrupt is enabled (IER ABToIntEn is set and the auto-baud rate measurement counter overflows). • The IIR ABEOInt interrupt will get set if the interrupt is enabled (IER ABEOIntEn is set and the auto-baud has completed successfully). All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 724 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 32: LPC18xx USART0_2_3 FT D R 16   2 + databits + paritybits + stopbits  The auto-baud interrupts have to be cleared by setting the corresponding ACR ABTOIntClr and ABEOIntEn bits. R The fractional baud rate generator must be disabled (DIVADDVAL = 0) during auto-baud. Also, when auto-baud is used, any write to DLM and DLL registers should be done before ACR register write. The minimum and the maximum baud rates supported by UART are function of UART_PCLK, number of data bits, stop bits and parity bits. A FT D 2  P CLK PCLK ratemin = ------------------------  UART baudrate  ----------------------------------------------------------------------------------------------------------- = ratemax 16  2 15 D R A R A FT D R FT D R A A R A FT D A FT D R F R A FT D FT D R A (6) R A 32.5.10.2 Auto-baud modes When the software is expecting an ”AT" command, it configures the UART with the expected character format and sets the ACR Start bit. The initial values in the divisor latches DLM and DLM don‘t care. Because of the ”A" or ”a" ASCII coding (”A" = 0x41, ”a" = 0x61), the UART Rx pin sensed start bit and the LSB of the expected character are delimited by two falling edges. When the ACR Start bit is set, the auto-baud protocol will execute the following phases: 1. On ACR Start bit setting, the baud rate measurement counter is reset and the UART RSR is reset. The RSR baud rate is switched to the highest rate. 2. A falling edge on UART Rx pin triggers the beginning of the start bit. The rate measuring counter will start counting UART_PCLK cycles. 3. During the receipt of the start bit, 16 pulses are generated on the RSR baud input with the frequency of the UART input clock, guaranteeing the start bit is stored in the RSR. 4. During the receipt of the start bit (and the character LSB for Mode = 0), the rate counter will continue incrementing with the pre-scaled UART input clock (UART_PCLK). 5. If Mode = 0, the rate counter will stop on next falling edge of the UART Rx pin. If Mode = 1, the rate counter will stop on the next rising edge of the UART Rx pin. 6. The rate counter is loaded into DLM/DLL and the baud rate will be switched to normal operation. After setting the DLM/DLL, the end of auto-baud interrupt IIR ABEOInt will be set, if enabled. The RSR will now continue receiving the remaining bits of the ”A/a" character. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 725 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 32: LPC18xx USART0_2_3 FT D R R A D R A R A FT D R FT D R A R A FT FT A F 'A' (0x41) or 'a' (0x61) start UARTn RX start bit LSB of 'A' or 'a' bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop D D R A FT D R A FT D A FT D R A R U0ACR start rate counter 16xbaud_rate 16 cycles 16 cycles a. Mode 0 (start bit and LSB are used for auto-baud) 'A' (0x41) or 'a' (0x61) start UARTn RX start bit LSB of 'A' or 'a' bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop U1ACR start rate counter 16xbaud_rate 16 cycles b. Mode 1 (only start bit is used for auto-baud) Fig 88. Auto-baud a) mode 0 and b) mode 1 waveform 32.5.11 IrDA Control Register (UART3) The IrDA Control Register enables and configures the IrDA mode for UART3 only. The value of U3ICR should not be changed while transmitting or receiving data, or data loss or corruption may occur. Remark: IrDA is available on UART3 only. Table 676. IrDA Control Register (ICR - address 0x4000 8024) bit description Bit 0 Symbol IRDAEN 0 1 Value Description IrDA mode enable. IrDA mode on UART3 is disabled, UART3 acts as a standard UART. IrDA mode on UART3 is enabled. Reset value 0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 726 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 32: LPC18xx USART0_2_3 FT D Table 676. IrDA Control Register (ICR - address 0x4000 8024) bit description Bit 1 Symbol IRDAINV 0 1 2 FIXPULSEEN 0 1 5:3 PULSEDIV NA Value Description Serial input direction. The serial input is not inverted. The serial input is inverted. This has no effect on the serial output. IrDA fixed pulse width mode. IrDA fixed pulse width mode disabled. IrDA fixed pulse width mode enabled. Configures the pulse when FixPulseEn = 1. See Table 677 for details. 0 0 D R A R A FT D R R R A FT D R A R A A Reset value FT D R A D R A FT F FT 0 D R A FT FT D D R A 31:6 - Reserved, user software should not write ones to 0 reserved bits. The value read from a reserved bit is not defined. The PulseDiv bits in U3ICR are used to select the pulse width when the fixed pulse width mode is used in IrDA mode (IrDAEn = 1 and FixPulseEn = 1). The value of these bits should be set so that the resulting pulse width is at least 1.63 µs. Table 677 shows the possible pulse widths. Table 677. IrDA Pulse Width FixPulseEn 0 1 1 1 1 1 1 1 1 PulseDiv x 0 1 2 3 4 5 6 7 IrDA Transmitter Pulse width (µs) 3 / (16  baud rate) 2  TPCLK 4  TPCLK 8  TPCLK 16  TPCLK 32  TPCLK 64  TPCLK 128  TPCLK 256  TPCLK 32.5.12 UART Fractional Divider Register (U0FDR - 0x4000 8028) The UART Fractional Divider Register (FDR) controls the clock pre-scaler for the baud rate generation and can be read and written at the user’s discretion. This pre-scaler takes the APB clock and generates an output clock according to the specified fractional requirements. Important: If the fractional divider is active (DIVADDVAL > 0) and DLM = 0, the value of the DLL register must be 3 or greater. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 727 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 32: LPC18xx USART0_2_3 FT D R R A Table 678. UART Fractional Divider Register (FDR - addresses 0x4008 1028 (UART0), 0x400C 1028 (UART2), 0x400C 2028 (UART3)) bit description D R A R A FT D R FT D R A R A A FT D F FT D Bit 3:0 Function DIVADDVAL Description Reset value R R A A FT D FT D R A Baud rate generation pre-scaler divisor value. 0 If this field is 0, fractional baud rate generator will not impact the UART baud rate. Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for UART to operate properly, regardless of whether the fractional baud rate generator is used or not. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 1 FT D R A 7:4 MULVAL 31:8 - 0 This register controls the clock pre-scaler for the baud rate generation. The reset value of the register keeps the fractional capabilities of UART disabled making sure that UART is fully software and hardware compatible with UARTs not equipped with this feature. The UART baud rate can be calculated as: (7) PCLK UART baudrate = -----------------------------------------------------------------------------------------------------------------DivAddVal 16   256  DLM + DLL    1 + ----------------------------   MulVal  Where UART_PCLK is the peripheral clock, DLM and DLL are the standard UART baud rate divider registers, and DIVADDVAL and MULVAL are UART fractional baud rate generator specific parameters. The value of MULVAL and DIVADDVAL should comply to the following conditions: 1. 1 MULVAL  15 2. 0  DIVADDVAL  14 3. DIVADDVAL< MULVAL The value of the FDR should not be modified while transmitting/receiving data or data may be lost or corrupted. If the FDR register value does not comply to these two requests, then the fractional divider output is undefined. If DIVADDVAL is zero then the fractional divider is disabled, and the clock will not be divided. 32.5.12.1 Baud rate calculation UART can operate with or without using the Fractional Divider. In real-life applications it is likely that the desired baud rate can be achieved using several different Fractional Divider settings. The following algorithm illustrates one way of finding a set of DLM, DLL, MULVAL, and DIVADDVAL values. Such set of parameters yields a baud rate with a relative error of less than 1.1% from the desired one. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 728 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 32: LPC18xx USART0_2_3 FT D R R A D R A R A FT D R FT D R A R A FT FT A F Calculating UART baudrate (BR) D D R A FT D R A FT D A R PCLK, BR FT D R A DL est = PCLK/(16 x BR) DL est is an integer? True False FR est = 1.5 DIVADDVAL = 0 MULVAL = 1 Pick another FR est from the range [1.1, 1.9] DL est = Int(PCLK/(16 x BR x FR est)) FR est = PCLK/(16 x BR x DL est) False 1.1 < FR est < 1.9? True DIVADDVAL = table(FR est ) MULVAL = table(FR est ) DLM = DL est [15:8] DLL = DLest [7:0] End Fig 89. Algorithm for setting UART dividers All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 729 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 32: LPC18xx USART0_2_3 FT D R A D R A R A FT D R FT D Table 679. Fractional Divider setting look-up table FR 1.000 1.067 1.071 1.077 1.083 1.091 1.100 1.111 1.125 1.133 1.143 1.154 1.167 1.182 1.200 1.214 1.222 1.231 DivAddVal/ MulVal 0/1 1/15 1/14 1/13 1/12 1/11 1/10 1/9 1/8 2/15 1/7 2/13 1/6 2/11 1/5 3/14 2/9 3/13 FR 1.250 1.267 1.273 1.286 1.300 1.308 1.333 1.357 1.364 1.375 1.385 1.400 1.417 1.429 1.444 1.455 1.462 1.467 DivAddVal/ MulVal 1/4 4/15 3/11 2/7 3/10 4/13 1/3 5/14 4/11 3/8 5/13 2/5 5/12 3/7 4/9 5/11 6/13 7/15 FR 1.500 1.533 1.538 1.545 1.556 1.571 1.583 1.600 1.615 1.625 1.636 1.643 1.667 1.692 1.700 1.714 1.727 1.733 DivAddVal/ MulVal 1/2 8/15 7/13 6/11 5/9 4/7 7/12 3/5 8/13 5/8 7/11 9/14 2/3 9/13 7/10 5/7 8/11 11/15 FR 1.750 1.769 1.778 1.786 1.800 1.818 1.833 1.846 1.857 1.867 1.875 1.889 1.900 1.909 1.917 1.923 1.929 1.933 R R 3/4 10/13 7/9 11/14 4/5 9/11 5/6 11/13 6/7 13/15 7/8 8/9 9/10 10/11 11/12 12/13 13/14 14/15 R A A DivAddVal/ MulVal A FT D R A FT D R A R A FT F FT D D R A FT D 32.5.12.1.1 Example 1: UART_PCLK = 14.7456 MHz, BR = 9600 According to the provided algorithm DLest = PCLK/(16 x BR) = 14.7456 MHz / (16 x 9600) = 96. Since this DLest is an integer number, DIVADDVAL = 0, MULVAL = 1, DLM = 0, and DLL = 96. 32.5.12.1.2 Example 2: UART_PCLK = 12 MHz, BR = 115200 According to the provided algorithm DLest = PCLK/(16 x BR) = 12 MHz / (16 x 115200) = 6.51. This DLest is not an integer number and the next step is to estimate the FR parameter. Using an initial estimate of FRest = 1.5 a new DLest = 4 is calculated and FRest is recalculated as FRest = 1.628. Since FRest = 1.628 is within the specified range of 1.1 and 1.9, DIVADDVAL and MULVAL values can be obtained from the attached look-up table. The closest value for FRest = 1.628 in the look-up Table 679 is FR = 1.625. It is equivalent to DIVADDVAL = 5 and MULVAL = 8. Based on these findings, the suggested UART setup would be: DLM = 0, DLL = 4, DIVADDVAL = 5, and MULVAL = 8. According to Equation 7, the UART’s baud rate is 115384. This rate has a relative error of 0.16% from the originally specified 115200. 32.5.13 UART Half-duplex enable register Remark: The HDEN register should be disabled when in smart card mode (smart card by default runs in half-duplex mode). All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 730 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 32: LPC18xx USART0_2_3 FT D R R A After reset the USART will be in full-duplex mode, meaning that both TX and RX work independently. After setting the HDEN bit, the USART will be in half-duplex mode. In this mode, the USART ensures that the receiver is locked when idle, or will enter a locked state after having received a complete ongoing character reception. Line conflicts must be handled in software. The behavior of the USART is unpredictactable when data is presented for reception while data is being transmitted. R A For this reason, the value of the HDEN register should not be modified while sending or receiving data, or data may be lost or corrupted. Table 680. UART Half duplex enable register (HDEN - addresses 0x4008 1040 (UART0), 0x400C 1040 (UART2), 0x400C 2040 (UART3)) bit description Bit 0 Symbol HDEN 0 1 31:1 Value Description Half-duplex mode enable Disable half-duplex mode. Enable half-duplex mode. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Reset value 0 D R A R A FT D R FT D R A A FT D R A R A FT F FT D R A FT D D R A FT D 32.5.14 UART Smart card interface control register Table 681. UART Smart card interface control register (SCICTRL - addresses 0x4008 1048 (UART0), 0x400C 1048 (UART2), 0x400C 2048 (UART3)) bit description Bit 0 Symbol SCIEN 0 1 1 NACKDIS 0 1 2 PROTSEL 0 1 7:5 TXRETRY Value Description Smart Card Interface Enable. Smart card interface disabled. Asynchronous half duplex smart card interface is enabled. NACK response disable. Only applicable in T=0. A NACK response is enabled. A NACK response is inhibited. Protocol selection as defined in the ISO7816-3 standard. 0 T=0 T=1 Maximum number of retransmissions in case of a negative acknowledge (protocol T=0). When the retry counter is exceeded, the USART will be locked until the FIFO is cleared. A TX error interrupt is generated when enabled. Extra guard time. No extra guard time (0x0) results in a standard guard time as defined in ISO 7816-3, depending on the protocol type. A guard time of 0xFF indicates a minimal guard time as defined for the selected protocol. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 0 Reset value 0 15:8 GUARDTIME 31:16 - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 731 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 32: LPC18xx USART0_2_3 FT D R R A After reset the USART smart card interface will be disabled. After setting the SCIEN bit the USART will be in ISO 7816-3 compliant asynchronous smart card mode T=0. R A FT D R A The NACKDIS bit is used to inhibit a nack response during T=0 (the I/O line is not pulled low during the guard time to indicate an erroneous reception). The received character will be stored in the RX FIFO but a parity error will be generated. It is up to the software to handle the incorrect received character. The PROTSEL bit is used to selected between the two supported smart card protocols T=0 and T=1. More information on these protocols can be found in the ISO 7816-3 standard. FT D The retry bit field indicates the number of retransmission when receiving a NACK response, which can be up to 7 trails. When the number is exceeded, an interrupt is generated and the USART is locked until the FIFO is empty. This can be done by flushing the FIFO. When no FIFO is available, or the FIFO is already empty, the interrupt can be used by the software to determine the next action. The guard time bit file is used to program the extra number of guard time cycles to allow the smart card to process the information before sending a response. The extra guard time can be programmed from 0 to 255, where 255 indicates the minimum possible character length. This value is depending on the selected protocol and can be either 11 etu for protocol T=1 or 12 etu for protocol T=0. Waiting times as defined in the standard cannot be programmed directly, but are implemented using the CAP1 and CAP2 inputs of the timers. Use the CREG6 register in the CREG block (see Table 37) to set up the timers for polling the tx_active and rx_active polling signals. Remark: The SCICTRL register should not be modified while sending or receiving data, or data may be lost or corrupted. Remark: The SCICTRL register should not be enabled in combination with the SYNCCTRL register, as only asynchronous smart card is supported. D R A R A FT D R FT D R A F D R A FT D FT D R A A FT R A 32.5.15 UART RS485 Control register The RS485CTRL register controls the configuration of the UART in RS-485/EIA-485 mode. Table 682. UART RS485 Control register (RS485CTRL - addresses 0x4008 104C (UART0), 0x400C 104C (UART2), 0x400C 204C (UART3)) bit description Bit 0 Symbol NMMEN 0 1 Value Description NMM enable. RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the UART to set the parity error and generate an interrupt. Reset value 0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 732 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 32: LPC18xx USART0_2_3 FT D R R A Table 682. UART RS485 Control register (RS485CTRL - addresses 0x4008 104C (UART0), 0x400C 104C (UART2), 0x400C 204C (UART3)) bit description …continued D R A R A FT D R FT D R A R A FT A F FT Bit 1 Symbol RXDIS Value Description Receiver enable. Reset value D D R R A FT D R A FT 0 D A 0 1 2 AADEN 0 1 3 4 DCTRL 0 1 5 OINV - The receiver is enabled. The receiver is disabled. AAD enable Auto Address Detect (AAD) is disabled. Auto Address Detect (AAD) is enabled. Reserved. Direction control for DIR pin. Disable Auto Direction Control. Enable Auto Direction Control. Direction control pin polarity. This bit reverses the polarity of the direction control signal on the DIR pin. 0 0 0 FT D R A 0 The direction control pin will be driven to logic ‘0’ when the transmitter has data to be sent. It will be driven to logic ‘1’ after the last bit of data has been transmitted. The direction control pin will be driven to logic ‘1’ when the transmitter has data to be sent. It will be driven to logic ‘0’ after the last bit of data has been transmitted. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 1 31:6 - - After reset RS485 mode will be disabled. The RS485 feature allows the USART to be configured as one of multiple addressable slave receivers controlled by a single USART. In RS485 mode the USART differentiates between an address character and a data character by means of a ninth bit. The parity bit is used to implement this bit, and when set to ‘1’ indicates an address and when set to ‘0’ indicates data. RS485 mode is enabled by setting the NMMEN bit. The USART slave receiver can be assigned a unique address and, manually or automatically, reject or accept data based on a received address. See section Section 32.6.3 for details. 32.5.16 UART RS485 Address Match register The RS485ADRMATCH register contains the address match value for RS-485/EIA-485 mode. Table 683. UART RS485 Address Match register (RS485ADRMATCH - addresses 0x4008 1050 (UART0), 0x400C 1050 (UART2), 0x400C 2050 (UART3)) bit description Bit 7:0 31:8 Symbol ADRMATCH Description Contains the address match value. Reserved Reset value 0x00 - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 733 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 32: LPC18xx USART0_2_3 FT D R R A The ADRMATCH bit field contains the slave address match value that is used to compare a received address value to. During automatic address detection, this value is used to accept or reject serial input data. R A A FT D R A FT D R A R A FT D R FT D R A F R A FT D D FT 32.5.17 UART1 RS485 Delay value register The user may program the 8-bit RS485DLY register with a delay between the last stop bit leaving the TXFIFO and the de-assertion of the DIR pin. This delay time is in periods of the baud clock. Any delay time from 0 to 255 bit times may be programmed. Table 684. UART RS485 Delay value register (RS485DLY - addresses 0x4008 1054 (UART0), 0x400C 1054 (UART2), 0x400C 2054 (UART3)) bit description Bit 7:0 31:8 Symbol DLY Description Contains the direction control delay value. This register works in conjunction with an 8-bit counter. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Reset value 0x00 NA D R A FT D R A 32.5.18 UART Synchronous mode control register SYNCCTRL register is a Read/write register that controls the synchronous mode. The synchronous mode control module generates or receives the synchronous clock with the serial input/ output data and distributes the edge detect samples to the transmit and receive shift registers. Table 685. UART Synchronous mode control registers (SYNCCTRL - address addresses 0x4008 1058 (UART0), 0x400C 1058 (UART2), 0x400C 2058 (UART3)) bit description Bit 0 Symbol SYNC 0 1 1 CSRC 0 1 2 FES 0 1 3 TSBYPASS 0 1 4 CSCEN 0 1 Value Description Enables synchronous mode. Disabled Enabled Clock source select. Synchronous slave mode (SCLK in) Synchronous master mode (SCLK out) Falling edge sampling. RxD is sampled on the rising edge of SCLK RxD is sampled on the falling edge of SCLK Transmit synchronization register bypass. Continuous master clock enable (used only when CSRC is 1) SCLK cycles only when characters are being sent on TxD SCLK runs continuously (characters can be received on RxD independently from transmission on TxD) 0 0 0 0 Reset value 0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 734 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 32: LPC18xx USART0_2_3 FT D R R A Table 685. UART Synchronous mode control registers (SYNCCTRL - address addresses 0x4008 1058 (UART0), 0x400C 1058 (UART2), 0x400C 2058 (UART3)) bit description D R A R A FT D R FT D R A R A FT D A F FT D R R A Bit 5 Symbol SSSDIS Value Description Start/stop bits Reset value 0 A FT D A FT FT D R 0 1 6 CCCLR 0 1 31:7 - Send start and stop bits as in other modes. Do not send start/stop bits. Continuous clock clear CSCEN is under software control. Hardware clears CSCEN after each character is received. Reserved. The value read from a reserved bit is not defined. NA 0 D R A After reset, synchronous mode is disabled. Synchronous mode allows the user to send (synchronous master mode) or receive (synchronous slave mode) a clock with the serial input and output data. Synchronous mode is enabled by setting the SYNC bit. The CSRC bit can be used to switch between synchronous slave mode (logic 0) and synchronous master mode (logic 1). The serial data can either be sampled on the rising edge (default) or the falling edge of the serial clock. When the STARTSTOPDISABLE bit is set, the FES bit is hardware overwritten to sample on the falling edge. A master clock is only required to generate a clock when transmitting data. In this case, data can only be received when data is transmitted. When the CSCEN bit is set, the clock will always be running (during synchronous master mode only), allowing data to be received continuously. Note that this option should not be used in combination with STARTSTOPDISABLE (during full-duplex communication). The continuous clock can be automatically stopped by hardware after having received a complete character. This can be done by asserting the CCCLR bit. This is useful in half-duplex mode, where the clock cannot be generated by sending a character. After the reception of one character, the CSCEN bit is automatically cleared by hardware. When another character needs to be received, the CSCEN should be enabled again. By default data transmission and reception performs the same in asynchronous mode and synchronous mode. When the STARTSTOPDISABLE bit is set, no start and stop bits are transmitted (nor are they received). This means that all bits that are send or received (a clock is running) are data bits. Remark: The value of the SYNCCTRL register should not be modified while transmitting/receiving, data or data might get lost or corrupted. Remark: The SYNCCTRL register should not be enabled in combination with the SCICTRL register, as only asynchronous smart card is supported. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 735 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 32: LPC18xx USART0_2_3 FT D R A D R A R A FT D R FT 32.5.19 UART Transmit Enable Register D R In addition to being equipped with full hardware flow control (auto-cts and auto-rts mechanisms described above), TER enables implementation of software flow control. When TxEn = 1, UART transmitter will keep sending data as long as they are available. As soon as TxEn becomes 0, UART transmission will stop. Table 686 describes how to use TXEn bit in order to achieve software flow control. Table 686. UART Transmit Enable Register (TER - addresses 0x4008 1030 (UART0), 0x400C 1030 (UART2), 0x400C 205C (UART3)) bit description Bit 0 Symbol TXEN Description Transmit enable. After reset transmission is enabled. When the txen bit is de-asserted, no data will be transmitted although data may be pending in the TSR or THR. Reset value 1 R A FT D R R A F D R A FT D FT D R A A FT R A A FT D 31:1 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 32.6 Functional description 32.6.1 Asynchronous mode 32.6.2 Synchronous mode When the synchronous receiver/ transmitter feature is configured (USART), the serial interface is extended with a serial input and output clock and an output enable for controlling the clock pad. Fig 90. USART serial interface protocol By default transmission and reception in synchronous mode operates uses the same protocol as in asynchronous mode. Synchronous mode can be configured using the Synchronous Mode Control Register. This register allows to control: • • • • The direction of the serial clock, i.e. synchronous slave or master mode The sampling edge of the serial clock Two-stage or one stage synchronization of the input serial clock during transmission During synchronous master mode, the clock can be continuous or disabled when in idle or break mode running clock. Sampling is always done on the falling edge of the serial clock • The transmission of start and stop bits can be omitted. Valid data is identified by a Data is shifted in the receive shift register at the sampling edge of the serial clock. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 736 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 32: LPC18xx USART0_2_3 FT D R A D R A R A FT D R FT 32.6.2.1 Synchronous slave mode D R This mode is enabled by setting the CSRC bit of the control register to ‘0’. During synchronous slave mode, an external clock is required that clocks the serial input and output data. Note that internally, the serial clock is treated as a data signal. Edge detection on the serial clock is performed to synchronize the serial clock with the UART clock domain, hence no registers are clocked with the serial clock. FT D R A FT D R A R A F D R A FT D FT D R A R A A FT Reception By default the received character is similar to the character in asynchronous mode. The serial data stream is kept HIGH when no data is available. During this time it is not required for the external serial clock to be running. The first bit that will be received is the start bit. During this time, the external serial clock must be running. The beginning of the start bit can either be aligned with the rising edge of the serial clock (sampling on the falling edge) or the falling edge (sampling on the rising edge), see the FES bit in Table 685. When sampling on the rising edge, it is not required that the beginning of the start bit is aligned with a clock edge (the clock may not have been running before). In this case, the edge on the serial input data due to the start bit (logic 1 to 0) is used to determine the start of the character (see figure 11). Fig 91. Transmission of data in synchronous slave mode The NOSTARTSTOPBITS bit of the Synchronous Mode Control register allows the user to disable the transmission/ reception of the start and stop bits, improving the efficiency of the USART. As a character is no longer identified by the start and stop bits, the serial clock is used to determine the data bits. When the serial clock is running, all data that is sampled is regarded as valid data. In order to be able to identify the start of a character, the beginning of the character must be aligned with the rising edge of the serial clock. For this reason, the FES bit of the Synchronous Mode Control register is forced in hardware to ‘1’. Directly after sampling the last bit, the character is stored in the receive FIFO. Transmission During synchronous slave mode, data can only be transmitted when the external serial clock is running. Hence, when no start and stop bits are sent, transmission can only take place when data is received from the master. When the start and stop bits are transmitted, the external clock may only be detected after the first half of the received start bit (sampling at the rising edge of the external serial clock). By using the edge created by the received start bit (logic 1 to 0), it is made sure that the start bit of the character that is to be transmitted by the slave is stable before this rising edge the external slave clock. In this way it is ensured, that the master receives as many bits as it has transmitted. When the first sample edge of the incoming serial clock samples a ‘1’ on the serial input data (and start-stop bits are transmitted, thus the master has not initiated a transaction yet), it is assumed that the master is running a continuous clock (instead of only running the clock when sending data characters). The USART will not wait for a start bit from the master, but will immediately start transmitting data when available. Note that in this All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 737 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 32: LPC18xx USART0_2_3 FT D R R A situation, the number of bits transmitted by the master and the number of bits transmitted by the slave (received by the master) may not be aligned. It is assumed that a higher level protocol ensures that complete characters are received when the master stops the clock. R A Transmission of data during synchronous slave mode is most time-critical. First the external serial input clock must be detected using edge detection logic. Then, data needs to be shifted out and be stable before the sampling edge of the external serial clock. D Remark: In this mode the u_clk period is allowed to be 4x the serial clock period. D R A R A FT D R FT D R A A FT D R A R A FT F FT D R A FT FT D D R A 32.6.2.2 Synchronous master mode Synchronous master mode is enabled by setting the CSRC register bit to ‘1’. In this mode, the external clock is generated internally by the baud-rate generation logic and is used to clock the input and output serial data. The functionality of the baud-rate generation is described in Section 32.5.12.1. Auto-baud is not supported during synchronous mode. The 1x baud rate clock is used to shift out the serial output data and to sample the serial input data. Synchronous master mode behaves similar to the slave mode, except that the serial input data is not registered at the interface but is clocked in the UART clock domain at the sampling edge of the serial clock. During synchronous master mode, when start and stop bits are transmitted, the user can enable the external clock continuously using cscen bit of the Synchronous Mode Control register. This allows the connected slave to transmit data even when no data is transmitted by the master itself. 32.6.3 RS-485/EIA-485 modes of operation The RS-485/EIA-485 feature allows the UART to be configured as an addressable slave. The addressable slave is one of multiple slaves controlled by a single master. The UART master transmitter will identify an address character by setting the parity (9th) bit to ‘1’. For data characters, the parity bit is set to ‘0’. Each UART slave receiver can be assigned a unique address. The slave can be programmed to either manually or automatically reject data following an address which is not theirs. RS-485/EIA-485 Normal Multidrop Mode (NMM) Setting the RS485CTRL bit 0 enables this mode. In this mode, an address is detected when a received byte causes the UART to set the parity error and generate an interrupt. If the receiver is disabled (RS485CTRL bit 1 = ‘1’), any received data bytes will be ignored and will not be stored in the RXFIFO. When an address byte is detected (parity bit = ‘1’) it will be placed into the RXFIFO and an Rx Data Ready Interrupt will be generated. The processor can then read the address byte and decide whether or not to enable the receiver to accept the following data. While the receiver is enabled (RS485CTRL bit 1 =’0’), all received bytes will be accepted and stored in the RXFIFO regardless of whether they are data or address. When an address character is received a parity error interrupt will be generated and the processor can decide whether or not to disable the receiver. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 738 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 32: LPC18xx USART0_2_3 FT D R A D R A R A FT D R FT RS-485/EIA-485 Auto Address Detection (AAD) mode D R When both RS485CTRL register bits 0 (9-bit mode enable) and 2 (AAD mode enable) are set, the UART is in auto address detect mode. FT D R A FT D In this mode, the receiver will compare any address byte received (parity = ‘1’) to the 8-bit value programmed into the RS485ADRMATCH register. If the receiver is disabled (RS485CTRL bit 1 = ‘1’), any received byte will be discarded if it is either a data byte OR an address byte which fails to match the RS485ADRMATCH value. When a matching address character is detected it will be pushed onto the RXFIFO along with the parity bit, and the receiver will be automatically enabled (RS485CTRL bit 1 will be cleared by hardware). The receiver will also generate an Rx Data Ready Interrupt. While the receiver is enabled (RS485CTRL bit 1 = ‘0’), all bytes received will be accepted and stored in the RXFIFO until an address byte which does not match the RS485ADRMATCH value is received. When this occurs, the receiver will be automatically disabled in hardware (RS485CTRL bit 1 will be set), The received non-matching address character will not be stored in the RXFIFO. RS-485/EIA-485 Auto Direction Control RS485/EIA-485 mode includes the option of allowing the transmitter to automatically control the state of the DIR pin as a direction control output signal. Setting RS485CTRL bit 4 = ‘1’ enables this feature. When Auto Direction Control is enabled, the selected pin will be asserted (driven LOW) when the CPU writes data into the TXFIFO. The pin will be de-asserted (driven HIGH) once the last bit of data has been transmitted. See bits 4 and 5 in the RS485CTRL register. The RS485CTRL bit 4 takes precedence over all other mechanisms controlling the direction control pin. RS485/EIA-485 driver delay time The driver delay time is the delay between the last stop bit leaving the TXFIFO and the de-assertion of the DIR pin. This delay time can be programmed in the 8-bit RS485DLY register. The delay time is in periods of the baud clock. Any delay time from 0 to 255 bit times may be used. RS485/EIA-485 output inversion The polarity of the direction control signal on the DIR pin can be reversed by programming bit 5 in the RS485CTRL register. When this bit is set, the direction control pin will be driven to logic 1 when the transmitter has data waiting to be sent. The direction control pin will be driven to logic 0 after the last bit of data has been transmitted. R A R A F D R A FT D FT D R A R A A FT 32.6.4 Smart card mode Figure 92 shows a typical asynchronous smart card application. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 739 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 32: LPC18xx USART0_2_3 FT D R R A D R A R A FT D R FT D R A R A FT FT A F selectable power rail pull-up resistor GPIO pull-up resistor pull-up resistor VCC D D R A FT D R A FT D A FT D R A R LPCxxxx MATx/ PWMx TXD GPIO GPIO Optional Logic Level Translation CLK ISO 7816 Smart Card I/O RST Insertion Switch Fig 92. Typical smart card application When the SCIEN bit in the SCICTRL register (Table 681) is set as described above, the UART provides bidirectional serial data on the open-drain TXD pin. No RXD pin is used when SCIEN is 1. If a clock source is needed as an oscillator source into the Smart Card, a timer match or PWM output can be used in cases when a higher frequency clock is needed that is not synchronous with the data bit rate. The UART SCLK pin will output synchronously with the data and at the data bit rate and may not be adequate for most asynchronous cards. Software must use timers to implement character and block waiting times (no hardware support via trigger signals is provided on the LPCxxxx). GPIO pins can be used to control the smart card reset and power pins. Any power supplied to the card must be externally switched as card power supply requirements often exceed source currents possible on the LPCxxxx. As the specific application may accommodate any of the available ISO 7816 class A, B, or C power requirements, be aware of the logic level tolerances and requirements when communicating or powering cards that use different power rails than the LPCxxxx. 32.6.4.1 Smart card set-up procedure A T = 0 protocol transfer consists of 8-bits of data, an even parity bit, and two guard bits that allow for the receiver of the particular transfer to flag parity errors through the NACK response (see Figure 93). Extra guard bits may be added according to card requirements. If no NACK is sent (provided the interface accepts them in SCICTRL), the next byte may be transmitted immediately after the last guard bit. If the NACK is sent, the transmitter will retry sending the byte until successfully received or until the SCICTRL retry limit has been met. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 740 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 32: LPC18xx USART0_2_3 FT D R R A D R A R A FT D R FT D R A R A FT FT D D A F Clock Asynchronous transfer TXD start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity NACK extra extra guard1 guard2 guard1 guard2 extra guardn R Next transfer or First retry start bit0 R A FT D R A FT D A FT D R A Fig 93. Smart card T = 0 waveform The smart card must be set up with the following considerations: 1. If necessary, bring the UART out of reset and enable clocking to the peripheral. 2. Setup an available UART TXD pin for the bidirectional transfers. 3. Setup the match output or PWM clock source. The default clock requirement for most asynchronous cards is 372 times the bit rate. 4. Configure DLL and DLM for baud rate. It may not be necessary to target a specific standard baud rate but rather to maintain a fraction of the previously mentioned clock rate. For example if the clock rate is set to 4 MHz the baud rate would be 10753. A clock rate of 3.5712 MHz would need a baud rate of 9600. An ISO 7816 PPS exchange may require the baud rate to be changed later. 5. Configure LCR for character size and parity (typically 8-bit and even parity). 6. Configure SCICTRL with the desired NACK response, extra guard bits, and protocol type. 7. Place the GPIO output signals into an inactive state where card power is off, RST is low, and CLK is low and unchanging. Thereafter, software should monitor card insertion, handle activation, wait for answer to reset as described in ISO7816-3. 32.7 Architecture The architecture of the UART is shown below in the block diagram. The APB interface provides a communications link between the CPU or host and the UART. The UART receiver block, RX, monitors the serial input line, RXD, for valid input. The UART RX Shift Register (RSR) accepts valid characters via RXD. After a valid character is assembled in the RSR, it is passed to the UART RX Buffer Register FIFO to await access by the CPU or host via the generic host interface. The UART transmitter block, TX, accepts data written by the CPU or host and buffers the data in the UART TX Holding Register FIFO (THR). The UART TX Shift Register (TSR) reads the data stored in the THR and assembles the data to transmit via the serial output pin, TXD1. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 741 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 32: LPC18xx USART0_2_3 FT D R R A The UART Baud Rate Generator block, BRG, generates the timing enables used by the UART TX block. The BRG clock input source is UART_PCLK. The main clock is divided down per the divisor specified in the DLL and DLM registers. This divided down clock is a 16x oversample clock, NBAUDOUT. R A The interrupt interface contains registers IER and IIR. The interrupt interface receives several one clock wide enables from the TX and RX blocks. Status information from the TX and RX is stored in the LSR. Control information for the TX and RX is stored in the LCR. D R A R A FT D R FT D R A A FT D R A R A FT F FT D R A FT D D R A FT D Fig 94. UART block diagram All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 742 of 1164 D R A FT D R A FT D R A FT D R A FT D R A FT UM10430 Chapter 33: LPC18xx UART1 Rev. 00.13 — 20 July 2011 D D D R A FT D D R A FT D R A FT D R A R A FT D R A R A FT D R A FT D R A F R A FT D R R D User manual FT D R A FT FT A FT 33.1 How to read this chapter The UART1 controller is available on all LPC18xx parts. D D R A FT D R A 33.2 Basic configuration The UART1 is configured as follows: • • • • See Table 687 for clocking and power control. The UART1 is reset by the UART1_RST (reset #45). The UART1 interrupt is connected to slot # 25 in the NVIC. For connecting the UART1 receive and transmit lines to the GPDMA, use the DMAMUX register in the CREG block (see Table 35) and enable the GPDMA channel in the DMA Channel Configuration registers (Section 16.6.20). Table 687. UART1 clocking and power control Base clock UART1 clock to register interface UART1 peripheral clock (PCLK) BASE_M3_CLK BASE_UART1_CLK Branch clock CLK_M3_UART0 Maximum frequency 150 MHz CLK_APB0_UART1 150 MHz 33.3 Features • • • • • • • • • • • Full modem control handshaking available. Data sizes of 5, 6, 7, and 8 bits. Parity generation and checking: odd, even mark, space or none. One or two stop bits. 16 byte Receive and Transmit FIFOs. Built-in baud rate generator, including a fractional rate divider for great versatility. Supports DMA for both transmit and receive. Auto-baud capability. Break generation and detection. Multiprocessor addressing mode. RS-485 support. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 743 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 33: LPC18xx UART1 FT D R A D R A R A FT D R FT 33.4 Pin description Table 688: UART1 Pin description Pin Direction Description Serial Input. Serial receive data. Serial Output. Serial transmit data. RXD1 Input TXD1 Output CTS1 Input D R Clear To Send. Active low signal indicates if the external modem is ready to accept transmitted data via TXD1 from the UART1. In normal operation of the modem interface (U1MCR[4] = 0), the complement value of this signal is stored in U1MSR[4]. State change information is stored in U1MSR[0] and is a source for a priority level 4 interrupt, if enabled (U1IER[3] = 1). Clear to send. CTS1 is an asynchronous, active low modem status signal. Its condition can be checked by reading bit 4 (CTS) of the modem status register. Bit 0 (DCTS) of the Modem Status Register (MSR) indicates that CTS1 has changed states since the last read from the MSR. If the modem status interrupt is enabled when CTS1 changes levels and the auto-cts mode is not enabled, an interrupt is generated. CTS1 is also used in the auto-cts mode to control the transmitter. R A FT D R R A F D R A FT A FT A FT D R A D FT D R A DCD1 Input Data Carrier Detect. Active low signal indicates if the external modem has established a communication link with the UART1 and data may be exchanged. In normal operation of the modem interface (U1MCR[4]=0), the complement value of this signal is stored in U1MSR[7]. State change information is stored in U1MSR3 and is a source for a priority level 4 interrupt, if enabled (U1IER[3] = 1). Data Set Ready. Active low signal indicates if the external modem is ready to establish a communications link with the UART1. In normal operation of the modem interface (U1MCR[4] = 0), the complement value of this signal is stored in U1MSR[5]. State change information is stored in U1MSR[1] and is a source for a priority level 4 interrupt, if enabled (U1IER[3] = 1). Data Terminal Ready. Active low signal indicates that the UART1 is ready to establish connection with external modem. The complement value of this signal is stored in U1MCR[0]. The DTR pin can also be used as an RS-485/EIA-485 output enable signal. Ring Indicator. Active low signal indicates that a telephone ringing signal has been detected by the modem. In normal operation of the modem interface (U1MCR[4] = 0), the complement value of this signal is stored in U1MSR[6]. State change information is stored in U1MSR[2] and is a source for a priority level 4 interrupt, if enabled (U1IER[3] = 1). Request To Send. Active low signal indicates that the UART1 would like to transmit data to the external modem. The complement value of this signal is stored in U1MCR[1]. In auto-rts mode, RTS1 is used to control the transmitter FIFO threshold logic. Request to send. RTS1 is an active low signal informing the modem or data set that the UART is ready to receive data. RTS1 is set to the active (low) level by setting the RTS modem control register bit and is set to the inactive (high) level either as a result of a system reset or during loop-back mode operations or by clearing bit 1 (RTS) of the MCR. In the auto-rts mode, RTS1 is controlled by the transmitter FIFO threshold logic. The RTS pin can also be used as an RS-485/EIA-485 output enable signal. DSR1 Input DTR1 Output RI1 Input RTS1 Output All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 744 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 33: LPC18xx UART1 FT D R A D R A R A FT D R FT 33.5 Register description D R UART1 contains registers organized as shown in Table 689. The Divisor Latch Access Bit (DLAB) is contained in U1LCR[7] and enables access to the Divisor Latches. Reset value reflects the data stored in used bits only. It does not include the content of reserved bits. Table 689: Register overview: UART1 (base address 0x4008 2000) Name RBR THR DLL Access Address Description offset RO WO R/W 0x000 0x000 0x000 Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) Reset value NA Transmit Holding Register. The next character to NA be transmitted is written here. (DLAB=0) 0x01 Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) 0x00 Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider.(DLAB=1) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART1 interrupts. (DLAB=0) 0x00 R A FT D R R A F D R A FT D FT D R A A FT A FT D R A DLM R/W 0x004 IER R/W 0x004 IIR FCR LCR MCR LSR MSR SCR ACR FDR TER RS485CTRL RO WO R/W R/W RO RO R/W R/W R/W R/W R/W 0x008 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 0x028 0x030 0x04C Interrupt ID Register. Identifies which interrupt(s) 0x01 are pending. FIFO Control Register. Controls UART1 FIFO usage and modes. Line Control Register. Contains controls for frame formatting and break generation. Modem Control Register. Contains controls for flow control handshaking and loopback mode. Line Status Register. Contains flags for transmit and receive status, including line errors. Modem Status Register. Contains handshake signal status flags. 0x00 0x00 0x00 0x60 0x00 Scratch Pad Register. 8-bit temporary storage for 0x00 software. Auto-baud Control Register. Contains controls for the auto-baud feature. Fractional Divider Register. Generates a clock input for the baud rate divider. Transmit Enable Register. Turns off UART transmitter for use with software flow control. RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. 0x00 0x10 0x80 0x00 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 745 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 33: LPC18xx UART1 FT D Table 689: Register overview: UART1 (base address 0x4008 2000) …continued Name RS485ADRMA TCH RS485DLY FIFOLVL Access Address Description offset R/W R/W RO 0x050 0x054 0x058 RS-485/EIA-485 direction control delay. FIFO Level register. Provides the current fill levels of the transmit and receive FIFOs. RS-485/EIA-485 address match. Contains the 0x00 address match value for RS-485/EIA-485 mode. 0x00 0x00 D R A R A FT D R R R A FT D R A R A A Reset value FT D R A D R A FT F FT D R A FT D D R A FT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 746 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 33: LPC18xx UART1 FT D R A 33.5.1 UART1 Receiver Buffer Register (when DLAB = 0) The U1RBR is the top byte of the UART1 RX FIFO. The top byte of the RX FIFO contains the oldest character received and can be read via the bus interface. The LSB (bit 0) represents the “oldest” received data bit. If the character received is less than 8 bits, the unused MSBs are padded with zeroes. The Divisor Latch Access Bit (DLAB) in U1LCR must be zero in order to access the U1RBR. The U1RBR is always read-only. D R A FT D Since PE, FE and BI bits correspond to the byte sitting on the top of the RBR FIFO (i.e. the one that will be read in the next read from the RBR), the right approach for fetching the valid pair of received byte and its status bits is first to read the content of the U1LSR register, and then to read a byte from the U1RBR. Table 690: UART1 Receiver Buffer Register when DLAB = 0 (RBR - address 0x4008 2000 ) bit description Bit 7:0 31:8 Symbol Description RBR Receiver Buffer. Contains the oldest received byte in the UART1 RX FIFO. Reserved, the value read from a reserved bit is not defined. Reset value undefined NA 33.5.2 UART1 Transmitter Holding Register (when DLAB = 0) The write-only U1THR is the top byte of the UART1 TX FIFO. The top byte is the newest character in the TX FIFO and can be written via the bus interface. The LSB represents the first bit to transmit. The Divisor Latch Access Bit (DLAB) in U1LCR must be zero in order to access the U1THR. The U1THR is write-only. Table 691: UART1 Transmitter Holding Register when DLAB = 0 (THR - address 0x4008 2000 ) bit description Bit 7:0 Symbol Description THR Reset value NA Transmit Holding Register. Writing to the UART1 Transmit Holding Register causes the data to be stored in the UART1 transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available. Reserved, user software should not write ones to reserved bits. NA D R A R A FT D R FT D R R A FT R A F D R A FT D FT D R A R A A FT 31:8 - 33.5.3 UART1 Divisor Latch LSB and MSB Registers (when DLAB = 1) The UART1 Divisor Latch is part of the UART1 Baud Rate Generator and holds the value used, along with the Fractional Divider, to divide the APB clock (PCLK) in order to produce the baud rate clock, which must be 16x the desired baud rate. The U1DLL and U1DLM registers together form a 16-bit divisor where U1DLL contains the lower 8 bits of the divisor and U1DLM contains the higher 8 bits of the divisor. A 0x0000 value is treated like a 0x0001 value as division by zero is not allowed.The Divisor Latch Access Bit (DLAB) in U1LCR must be one in order to access the UART1 Divisor Latches. Details on how to select the right value for U1DLL and U1DLM can be found later in this chapter, see Section 33.5.16. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 747 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 33: LPC18xx UART1 FT D R R A Table 692: UART1 Divisor Latch LSB Register when DLAB = 1 (DLL - address 0x4008 2000 ) bit description D R A R A FT D R FT D R A R A FT A FT F Bit 7:0 Symbol Description DLLSB Divisor Latch LSB. The UART1 Divisor Latch LSB Register, along with the U1DLM register, determines the baud rate of the UART1. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Reset value 0x01 D D R A FT D R A FT D A R 31:8 - NA FT D R A Table 693: UART1 Divisor Latch MSB Register when DLAB = 1 (DLM - address 0x4008 2004 ) bit description Bit 7:0 Symbol Description DLMSB Divisor Latch MSB. The UART1 Divisor Latch MSB Register, along with the U1DLL register, determines the baud rate of the UART1. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Reset value 0x00 31:8 - NA 33.5.4 UART1 Interrupt Enable Register (when DLAB = 0) The U1IER is used to enable the four UART1 interrupt sources. Table 694: UART1 Interrupt Enable Register when DLAB = 0 (IER - address 0x4008 2004 ) bit description Bit 0 Symbol RBRIE 0 1 1 THREIE 0 1 2 RXIE 0 1 3 MSIE 0 1 6:4 Value Description RBR Interrupt Enable. Enables the Receive Data Available interrupt for UART1. It also controls the Character Receive Time-out interrupt. Disable the RDA interrupts. Enable the RDA interrupts. THRE Interrupt Enable. Enables the THRE interrupt for UART1. The status of this interrupt can be read from U1LSR[5]. Disable the THRE interrupts. Enable the THRE interrupts. RX Line Interrupt Enable. Enables the UART1 RX line status interrupts. The status of this interrupt can be read from U1LSR[4:1]. Disable the RX line status interrupts. Enable the RX line status interrupts. Modem Status Interrupt Enable. Enables the modem interrupt. The status of this interrupt can be read from U1MSR[3:0]. Disable the modem interrupt. Enable the modem interrupt. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 0 0 0 Reset value 0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 748 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 33: LPC18xx UART1 FT D R Table 694: UART1 Interrupt Enable Register when DLAB = 0 (IER - address 0x4008 2004 ) bit description D R A R A FT D R FT D A R R R A A A Bit 7 Symbol CTSIE Value Description Reset value FT D R A R A FT F CTS Interrupt Enable. If auto-cts mode is enabled this bit enables/disables the modem status interrupt generation on a CTS1 signal transition. If auto-cts mode is disabled a CTS1 transition will generate an interrupt if Modem Status Interrupt Enable (U1IER[3]) is set. In normal operation a CTS1 signal transition will generate a Modem Status Interrupt unless the interrupt has been disabled by clearing the U1IER[3] bit in the U1IER register. In auto-cts mode a transition on the CTS1 bit will trigger an interrupt only if both the U1IER[3] and U1IER[7] bits are set. 0 1 Disable the CTS interrupt. Enable the CTS interrupt. Enables the end of auto-baud interrupt. 0 1 Disable end of auto-baud Interrupt. Enable end of auto-baud Interrupt. Enables the auto-baud time-out interrupt. 0 1 Disable auto-baud time-out Interrupt. Enable auto-baud time-out Interrupt. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. FT D R A 0 FT D D R A FT D 8 ABEOIE 0 9 ABTOIE 0 31:10 - NA 33.5.5 UART1 Interrupt Identification Register The U1IIR provides a status code that denotes the priority and source of a pending interrupt. The interrupts are frozen during an U1IIR access. If an interrupt occurs during an U1IIR access, the interrupt is recorded for the next U1IIR access. Table 695: UART1 Interrupt Identification Register (IIR - address 0x4008 2008) bit description Bit 0 Symbol INTSTATUS 0 1 3:1 INTID Value Description Interrupt status. Note that U1IIR[0] is active low. The pending interrupt can be determined by evaluating U1IIR[3:1]. At least one interrupt is pending. No interrupt is pending. Interrupt identification. U1IER[3:1] identifies an interrupt corresponding to the UART1 Rx or TX FIFO. All other combinations of U1IER[3:1] not listed below are reserved (100,101,111). 0x3 0x2 0x6 0x1 0x0 5:4 7:6 FIFOENABL E 1 - Receive Line Status (RLS). 2a - Receive Data Available (RDA). 2b - Character Time-out Indicator (CTI). 3 - THRE Interrupt. 4 - Modem Interrupt. Reserved, user software should not write ones to reserved bits. The value read NA from a reserved bit is not defined. Copies of U1FCR[0]. 0 0 Reset value 1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 749 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 33: LPC18xx UART1 FT D R Table 695: UART1 Interrupt Identification Register (IIR - address 0x4008 2008) bit description Bit 8 9 Symbol ABEOINT ABTOINT Value Description End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled. Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled. Reserved, the value read from a reserved bit is not defined. D R A R A FT D R FT D A R R A 0 0 NA Reset value R A F A FT D R A FT D R A FT D R A FT D FT D R A 31:10 - Bit U1IIR[9:8] are set by the auto-baud function and signal a time-out or end of auto-baud condition. The auto-baud interrupt conditions are cleared by setting the corresponding Clear bits in the Auto-baud Control Register. If the IntStatus bit is 1 no interrupt is pending and the IntId bits will be zero. If the IntStatus is 0, a non auto-baud interrupt is pending in which case the IntId bits identify the type of interrupt and handling as described in Table 696. Given the status of U1IIR[3:0], an interrupt handler routine can determine the cause of the interrupt and how to clear the active interrupt. The U1IIR must be read in order to clear the interrupt prior to exiting the Interrupt Service Routine. The UART1 RLS interrupt (U1IIR[3:1] = 011) is the highest priority interrupt and is set whenever any one of four error conditions occur on the UART1RX input: overrun error (OE), parity error (PE), framing error (FE) and break interrupt (BI). The UART1 Rx error condition that set the interrupt can be observed via U1LSR[4:1]. The interrupt is cleared upon an U1LSR read. The UART1 RDA interrupt (U1IIR[3:1] = 010) shares the second level priority with the CTI interrupt (U1IIR[3:1] = 110). The RDA is activated when the UART1 Rx FIFO reaches the trigger level defined in U1FCR7:6 and is reset when the UART1 Rx FIFO depth falls below the trigger level. When the RDA interrupt goes active, the CPU can read a block of data defined by the trigger level. The CTI interrupt (U1IIR[3:1] = 110) is a second level interrupt and is set when the UART1 Rx FIFO contains at least one character and no UART1 Rx FIFO activity has occurred in 3.5 to 4.5 character times. Any UART1 Rx FIFO activity (read or write of UART1 RSR) will clear the interrupt. This interrupt is intended to flush the UART1 RBR after a message has been received that is not a multiple of the trigger level size. For example, if a peripheral wished to send a 105 character message and the trigger level was 10 characters, the CPU would receive 10 RDA interrupts resulting in the transfer of 100 characters and 1 to 5 CTI interrupts (depending on the service routine) resulting in the transfer of the remaining 5 characters. Table 696: UART1 Interrupt Handling U1IIR[3:0] Priority Interrupt value[1] Type 0001 0110 None Highest RX Line Status / Error Second RX Data Available Interrupt Source None OE[2] or PE[2] or FE[2] or BI[2] Interrupt Reset U1LSR Read[2] 0100 Rx data available or trigger level reached in FIFO (U1FCR0=1) U1RBR Read[3] or UART1 FIFO drops below trigger level All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 750 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 33: LPC18xx UART1 FT D R A D R A R A FT D R FT Table 696: UART1 Interrupt Handling U1IIR[3:0] Priority Interrupt value[1] Type 1100 Interrupt Source D R Interrupt Reset R A FT D R R A F D R A A FT A Second Character Minimum of one character in the RX FIFO and no U1RBR Read[3] Time-out character input or removed during a time period depending indication on how many characters are in FIFO and what the trigger level is set at (3.5 to 4.5 character times). The exact time will be: [(word length)  7 - 2]  8 + [(trigger level - number of characters)  8 + 1] RCLKs FT D R A FT D R A FT D 0010 0000 Third Fourth THRE Modem Status [1] [2] [3] [4] THRE[2] CTS or DSR or RI or DCD U1IIR Read[4] (if source of interrupt) or THR write MSR Read Values "0000", “0011”, “0101”, “0111”, “1000”, “1001”, “1010”, “1011”,”1101”,”1110”,”1111” are reserved. For details see Section 33.5.10 “UART1 Line Status Register” For details see Section 33.5.1 “UART1 Receiver Buffer Register (when DLAB = 0)” For details see Section 33.5.5 “UART1 Interrupt Identification Register” and Section 33.5.2 “UART1 Transmitter Holding Register (when DLAB = 0)” The UART1 THRE interrupt (U1IIR[3:1] = 001) is a third level interrupt and is activated when the UART1 THR FIFO is empty provided certain initialization conditions have been met. These initialization conditions are intended to give the UART1 THR FIFO a chance to fill up with data to eliminate many THRE interrupts from occurring at system start-up. The initialization conditions implement a one character delay minus the stop bit whenever THRE = 1 and there have not been at least two characters in the U1THR at one time since the last THRE = 1 event. This delay is provided to give the CPU time to write data to U1THR without a THRE interrupt to decode and service. A THRE interrupt is set immediately if the UART1 THR FIFO has held two or more characters at one time and currently, the U1THR is empty. The THRE interrupt is reset when a U1THR write occurs or a read of the U1IIR occurs and the THRE is the highest interrupt (U1IIR[3:1] = 001). It is the lowest priority interrupt and is activated whenever there is any state change on modem inputs pins, DCD, DSR or CTS. In addition, a low to high transition on modem input RI will generate a modem interrupt. The source of the modem interrupt can be determined by examining U1MSR[3:0]. A U1MSR read will clear the modem interrupt. 33.5.6 UART1 FIFO Control Register The write-only U1FCR controls the operation of the UART1 RX and TX FIFOs. Table 697: UART1 FIFO Control Register (FCR - address 0x4008 2008) bit description Bit 0 Symbol FIFOEN 0 1 Value Description FIFO enable. Must not be used in the application. Active high enable for both UART1 Rx and TX FIFOs and U1FCR[7:1] access. This bit must be set for proper UART1 operation. Any transition on this bit will automatically clear the UART1 FIFOs. Reset value 0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 751 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 33: LPC18xx UART1 FT D R A D R A R A FT D R FT Table 697: UART1 FIFO Control Register (FCR - address 0x4008 2008) bit description Bit 1 Symbol RXFIFORES 0 1 2 TXFIFORES 0 1 3 5:4 7:6 DMAMODE RXTRIGLVL 0x0 0x1 0x2 0x3 31:8 Value Description RX FIFO Reset. No impact on either of UART1 FIFOs. Writing a logic 1 to U1FCR[1] will clear all bytes in UART1 Rx FIFO, reset the pointer logic. This bit is self-clearing. TX FIFO Reset. No impact on either of UART1 FIFOs. Writing a logic 1 to U1FCR[2] will clear all bytes in UART1 TX FIFO, reset the pointer logic. This bit is self-clearing. DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode. See Section 33.5.6.1. D R Reserved, user software should not write ones to reserved bits. The value read NA from a reserved bit is not defined. RX Trigger Level. These two bits determine how many receiver UART1 FIFO characters must be written before an interrupt is activated. Trigger level 0 (1 character or 0x01). Trigger level 1 (4 characters or 0x04). Trigger level 2 (8 characters or 0x08). Trigger level 3 (14 characters or 0x0E). Reserved, user software should not write ones to reserved bits. NA 0 R A 0 0 0 R A F Reset value A FT D R A R A FT FT D R A FT D FT D D R A 33.5.6.1 DMA Operation The user can optionally operate the UART transmit and/or receive using DMA. The DMA mode is determined by the DMA Mode Select bit in the FCR register. Note that for DMA operation as for any operation of the UART, the FIFOs must be enabled via the FIFO Enable bit in the FCR register. UART receiver DMA In DMA mode, the receiver DMA request is asserted on the event of the receiver FIFO level becoming equal to or greater than trigger level, or if a character time-out occurs. See the description of the RX Trigger Level above. The receiver DMA request is cleared by the DMA controller. UART transmitter DMA In DMA mode, the transmitter DMA request is asserted on the event of the transmitter FIFO transitioning to not full. The transmitter DMA request is cleared by the DMA controller. 33.5.7 UART1 Line Control Register The U1LCR determines the format of the data character that is to be transmitted or received. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 752 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 33: LPC18xx UART1 FT D R A D R A R A FT D R FT D Table 698: UART1 Line Control Register (LCR - address 0x4008 200C) bit description Bit 1:0 Symbol WLS 0x0 0x1 0x2 0x3 2 SBS 0 1 3 PE 0 1 5:4 PS 00 01 10 11 6 BC 0 1 7 DLAB 0 1 31:8 Value Description Word Length Select. 5-bit character length. 6-bit character length. 7-bit character length. 8-bit character length. Stop Bit Select. 1 stop bit. 2 stop bits (1.5 if U1LCR[1:0]=00). Parity Enable. Disable parity generation and checking. Enable parity generation and checking. Parity Select. Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd. Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even. Forced "1" stick parity. Forced "0" stick parity. Break Control. Disable break transmission. Enable break transmission. Output pin UART1 TXD is forced to logic 0 when U1LCR[6] is active high. Divisor Latch Access Bit (DLAB) Disable access to Divisor Latches. Enable access to Divisor Latches. R Reserved, user software should not write ones to reserved bits. The value NA read from a reserved bit is not defined. R A 0 0 0 0 0 0 R A F A FT D R D R A FT D R A Reset value FT A FT D FT D R A 33.5.8 UART1 Modem Control Register The U1MCR enables the modem loopback mode and controls the modem output signals. Table 699: UART1 Modem Control Register (MCR - address 0x4008 2010) bit description Bit 0 Symbol DTRCTRL Value Description Reset value DTR Control. 0 Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode is active. RTSControl. 0 Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active. Reserved, user software should not write ones to reserved bits. The value read from a 0 reserved bit is not defined. 1 RTSCTRL - 3:2 - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 753 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 33: LPC18xx UART1 FT D R A D R A R A FT D R FT Table 699: UART1 Modem Control Register (MCR - address 0x4008 2010) bit description Bit 4 Symbol LMS Value Description D R 0 Loopback Mode Select. The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD1, has no effect on loopback and output pin, TXD1 is held in marking state. The 4 modem inputs (CTS, DSR, RI and DCD) are disconnected externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the 4 modem outputs are connected to the 4 modem inputs. As a result of these connections, the upper 4 bits of the U1MSR will be driven by the lower 4 bits of the U1MCR rather than the 4 modem inputs in normal mode. This permits modem status interrupts to be generated in loopback mode by writing the lower 4 bits of U1MCR. 0 1 Disable modem loopback mode. Enable modem loopback mode. Reserved, user software should not write ones to reserved bits. The value read from a 0 reserved bit is not defined. RTS enable. 0 1 Disable auto-rts flow control. Enable auto-rts flow control. CTS enable. 0 1 Disable auto-cts flow control. Enable auto-cts flow control. 0 0 R A FT D R R A F D R A FT D FT D R A Reset value A FT R A A FT D 5 6 RTSEN 7 CTSEN 31:8 - Reserved, user software should not write ones to reserved bits. The value read from a NA reserved bit is not defined. 33.5.9 Auto-flow control If auto-RTS mode is enabled the UART1‘s receiver FIFO hardware controls the RTS1 output of the UART1. If the auto-CTS mode is enabled the UART1‘s U1TSR hardware will only start transmitting if the CTS1 input signal is asserted. 33.5.9.1 Auto-RTS The auto-RTS function is enabled by setting the RTSen bit. Auto-RTS data flow control originates in the U1RBR module and is linked to the programmed receiver FIFO trigger level. If auto-RTS is enabled, the data-flow is controlled as follows: When the receiver FIFO level reaches the programmed trigger level, RTS1 is de-asserted (to a high value). It is possible that the sending UART sends an additional byte after the trigger level is reached (assuming the sending UART has another byte to send) because it might not recognize the de-assertion of RTS1 until after it has begun sending the additional byte. RTS1 is automatically reasserted (to a low value) once the receiver FIFO has reached the previous trigger level. The re-assertion of RTS1 signals to the sending UART to continue transmitting data. If Auto-RTS mode is disabled, the RTSen bit controls the RTS1 output of the UART1. If Auto-RTS mode is enabled, hardware controls the RTS1 output, and the actual value of RTS1 will be copied in the RTS Control bit of the UART1. As long as Auto-RTS is enabled, the value of the RTS Control bit is read-only for software. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 754 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 33: LPC18xx UART1 FT D R R A Example: Suppose the UART1 operating in ‘550 mode has trigger level in U1FCR set to 0x2 then if Auto-RTS is enabled the UART1 will de-assert the RTS1 output as soon as the receive FIFO contains 8 bytes (Table 697 on page 751). The RTS1 output will be reasserted as soon as the receive FIFO hits the previous trigger level: 4 bytes. R A A FT D R A FT D D R A R A FT D R FT D R A F R A FT D FT D FT R A ~ ~ UART1 Rx start byte N stop start bits0..7 stop D R start bits0..7 stop A RTS1 pin UART1 Rx FIFO read UART1 Rx FIFO level N-1 N N-1 N-2 N-1 N-2 ~~ ~~ M+2 ~ ~ M+1 M M-1 Fig 95. Auto-RTS Functional Timing 33.5.9.2 Auto-CTS The Auto-CTS function is enabled by setting the CTSen bit. If Auto-CTS is enabled the transmitter circuitry in the U1TSR module checks CTS1 input before sending the next data byte. When CTS1 is active (low), the transmitter sends the next byte. To stop the transmitter from sending the following byte, CTS1 must be released before the middle of the last stop bit that is currently being sent. In Auto-CTS mode a change of the CTS1 signal does not trigger a modem status interrupt unless the CTS Interrupt Enable bit is set, Delta CTS bit in the U1MSR will be set though. Table 700 lists the conditions for generating a Modem Status interrupt. Table 700: Modem status interrupt generation Enable Modem Status Interrupt (U1ER[3]) 0 1 1 1 1 1 1 1 1 CTSen CTS Interrupt Delta CTS Delta DCD or Trailing Edge RI Modem Status (U1MCR[7]) Enable (U1IER[7]) (U1MSR[0]) or Delta DSR (U1MSR[3] or Interrupt U1MSR[2] or U1MSR[1]) x 0 0 0 1 1 1 1 1 x x x x 0 0 1 1 1 x 0 1 x x x 0 1 x x 0 x 1 0 1 0 x 1 No No Yes Yes No Yes No Yes Yes The auto-CTS function reduces interrupts to the host system. When flow control is enabled, a CTS1 state change does not trigger host interrupts because the device automatically controls its own transmitter. Without Auto-CTS, the transmitter sends any data present in the transmit FIFO and a receiver overrun error can result. Figure 96 illustrates the Auto-CTS functional timing. All information provided in this document is subject to legal disclaimers. ~ ~ © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 755 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 33: LPC18xx UART1 FT D R R A D R A R A FT D R FT D R A R A FT FT A F ~ ~ ~ ~ UART1 TX start bits0..7 stop D D start bits0..7 stop start bits0..7 stop R R A A FT FT ~ ~ D D R A ~ ~ CTS1 pin FT D R Fig 96. Auto-CTS Functional Timing A While starting transmission of the initial character the CTS1 signal is asserted. Transmission will stall as soon as the pending transmission has completed. The UART will continue transmitting a 1 bit as long as CTS1 is de-asserted (high). As soon as CTS1 gets de-asserted transmission resumes and a start bit is sent followed by the data bits of the next character. 33.5.10 UART1 Line Status Register The U1LSR is a read-only register that provides status information on the UART1 TX and RX blocks. Table 701: UART1 Line Status Register (LSR - address 0x4008 2014) bit description Bit 0 Symbol RDR Value Description Reset value Receiver Data Ready. 0 U1LSR[0] is set when the U1RBR holds an unread character and is cleared when the UART1 RBR FIFO is empty. 0 1 The UART1 receiver FIFO is empty. The UART1 receiver FIFO is not empty. Overrun Error. The overrun error condition is set as soon as it occurs. An U1LSR read clears U1LSR[1]. U1LSR[1] is set when UART1 RSR has a new character assembled and the UART1 RBR FIFO is full. In this case, the UART1 RBR FIFO will not be overwritten and the character in the UART1 RSR will be lost. 0 1 Overrun error status is inactive. Overrun error status is active. Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An U1LSR read clears U1LSR[2]. Time of parity error detection is dependent on U1FCR[0]. Note: A parity error is associated with the character at the top of the UART1 RBR FIFO. 0 1 Parity error status is inactive. Parity error status is active. 0 0 1 OE 2 PE All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 756 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 33: LPC18xx UART1 FT D R A D R A R A FT D R FT Table 701: UART1 Line Status Register (LSR - address 0x4008 2014) bit description Bit 3 Symbol FE Value Description D R 0 Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An U1LSR read clears U1LSR[3]. The time of the framing error detection is dependent on U1FCR0. Upon detection of a framing error, the RX will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART1 RBR FIFO. 0 1 Framing error status is inactive. Framing error status is active. Break Interrupt. When RXD1 is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). An U1LSR read clears this status bit. The time of break detection is dependent on U1FCR[0]. Note: The break interrupt is associated with the character at the top of the UART1 RBR FIFO. 0 1 Break interrupt status is inactive. Break interrupt status is active. Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UART1 THR and is cleared on a U1THR write. 0 1 U1THR contains valid data. U1THR is empty. Transmitter Empty. TEMT is set when both U1THR and U1TSR are empty; TEMT is cleared when either the U1TSR or the U1THR contain valid data. 0 1 U1THR and/or the U1TSR contains valid data. U1THR and the U1TSR are empty. Error in RX FIFO. U1LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the U1RBR. This bit is cleared when the U1LSR register is read and there are no subsequent errors in the UART1 FIFO. 0 1 U1RBR contains no UART1 RX errors or U1FCR[0]=0. UART1 RBR contains at least one UART1 RX error. Reserved, the value read from a reserved bit is not defined. R A FT D R R A F D R A FT D FT D R A Reset value A FT R A A 0 FT D 4 BI 5 THRE 1 6 TEMT 1 7 RXFE 0 31:8 - NA 33.5.11 UART1 Modem Status Register The U1MSR is a read-only register that provides status information on the modem input signals. U1MSR[3:0] is cleared on U1MSR read. Note that modem signals have no direct effect on UART1 operation, they facilitate software implementation of modem signal operations. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 757 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 33: LPC18xx UART1 FT D R A D R A R A FT D R FT D Table 702: UART1 Modem Status Register (MSR - address 0x4008 2018) bit description Bit 0 Symbol DCTS 0 1 1 DDSR 0 1 2 TERI 0 1 3 DDCD 0 1 4 5 6 7 31:8 CTS DSR RI DCD Value Description Delta CTS. Set upon state change of input CTS. Cleared on an U1MSR read. No change detected on modem input, CTS. State change detected on modem input, CTS. Delta DSR. Set upon state change of input DSR. Cleared on an U1MSR read. No change detected on modem input, DSR. State change detected on modem input, DSR. Trailing Edge RI. Set upon low to high transition of input RI. Cleared on an U1MSR read. No change detected on modem input, RI. Low-to-high transition detected on RI. Delta DCD. Set upon state change of input DCD. Cleared on an U1MSR read. No change detected on modem input, DCD. State change detected on modem input, DCD. Clear To Send State. Complement of input signal CTS. This bit is connected to U1MCR[1] in modem loopback mode. Data Set Ready State. Complement of input signal DSR. This bit is connected to U1MCR[0] in modem loopback mode. Ring Indicator State. Complement of input RI. This bit is connected to U1MCR[2] in modem loopback mode. R Data Carrier Detect State. Complement of input DCD. This bit is connected 0 to U1MCR[3] in modem loopback mode. Reserved, the value read from a reserved bit is not defined. NA R A 0 0 0 0 0 0 0 R A F A FT D R D R A FT D R A Reset value FT A FT D FT D R A 33.5.12 UART1 Scratch Pad Register The U1SCR has no effect on the UART1 operation. This register can be written and/or read at user’s discretion. There is no provision in the interrupt interface that would indicate to the host that a read or write of the U1SCR has occurred. Table 703: UART1 Scratch Pad Register (SCR - address 0x4008 2014) bit description Bit 7:0 31:8 Symbol Description Pad Scratch pad. A readable, writable byte. Reserved, the value read from a reserved bit is not defined. Reset value 0x00 NA 33.5.13 UART1 Auto-baud Control Register The UART1 Auto-baud Control Register (U1ACR) controls the process of measuring the incoming clock/data rate for the baud rate generation and can be read and written at user’s discretion. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 758 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 33: LPC18xx UART1 FT D R A D R A R A FT D R FT D Table 704: Autobaud Control Register (ACR - address 0x4008 2020) bit description Bit 0 Symbol START 0 1 1 MODE 0 1 2 AUTORESTA RT 0 1 7:3 8 ABEOINTCL R Value Description Auto-baud start bit. This bit is automatically cleared after auto-baud completion. Auto-baud stop (auto-baud is not running). Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion. Auto-baud mode select bit. Mode 0. Mode 1. Auto-baud restart bit. No restart Restart in case of time-out (counter restarts at next UART1 Rx falling edge) R Reserved, user software should not write ones to reserved bits. The value read 0 from a reserved bit is not defined. End of auto-baud interrupt clear bit (write-only). 0 Writing a 0 has no impact. Writing a 1 will clear the corresponding interrupt in the U1IIR. Auto-baud time-out interrupt clear bit (write-only). 0 Writing a 0 has no impact. Writing a 1 will clear the corresponding interrupt in the U1IIR. Reserved, user software should not write ones to reserved bits. The value read 0 from a reserved bit is not defined. R A 0 0 0 R A F A FT D R D R A FT D R A Reset value FT A FT D FT D R A 0 1 9 ABTOINTCLR 0 1 31:10 - - 33.5.14 Auto-baud The UART1 auto-baud function can be used to measure the incoming baud-rate based on the “AT” protocol (Hayes command). If enabled the auto-baud feature will measure the bit time of the receive data stream and set the divisor latch registers U1DLM and U1DLL accordingly. Remark: the fractional rate divider is not connected during auto-baud operations, and therefore should not be used when the auto-baud feature is needed. Auto-baud is started by setting the U1ACR Start bit. Auto-baud can be stopped by clearing the U1ACR Start bit. The Start bit will clear once auto-baud has finished and reading the bit will return the status of auto-baud (pending/finished). Two auto-baud measuring modes are available which can be selected by the U1ACR Mode bit. In mode 0 the baud-rate is measured on two subsequent falling edges of the UART1 Rx pin (the falling edge of the start bit and the falling edge of the least significant bit). In mode 1 the baud-rate is measured between the falling edge and the subsequent rising edge of the UART1 Rx pin (the length of the start bit). The U1ACR AutoRestart bit can be used to automatically restart baud-rate measurement if a time-out occurs (the rate measurement counter overflows). If this bit is set the rate measurement will restart at the next falling edge of the UART1 Rx pin. The auto-baud function can generate two interrupts. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 759 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 33: LPC18xx UART1 FT D R R A • The U1IIR ABTOInt interrupt will get set if the interrupt is enabled (U1IER ABToIntEn R is set and the auto-baud rate measurement counter overflows). is set and the auto-baud has completed successfully). • The U1IIR ABEOInt interrupt will get set if the interrupt is enabled (U1IER ABEOIntEn R A FT D The auto-baud interrupts have to be cleared by setting the corresponding U1ACR ABTOIntClr and ABEOIntEn bits. Typically the fractional baud-rate generator is disabled (DIVADDVAL = 0) during auto-baud. However, if the fractional baud-rate generator is enabled (DIVADDVAL > 0), it is going to impact the measuring of UART1 Rx pin baud-rate, but the value of the U1FDR register is not going to be modified after rate measurement. Also, when auto-baud is used, any write to U1DLM and U1DLL registers should be done before U1ACR register write. The minimum and the maximum baud rates supported by UART1 are function of pclk, number of data bits, stop bits and parity bits. (8) 2  P CLK PCLK ratemin = ------------------------  UART 1 baudrate  ----------------------------------------------------------------------------------------------------------- = ratemax 16  2 15 16   2 + databits + paritybits + stopbits  D R A R A FT D R FT D R A A A FT D FT D R A R A FT F FT D D R A 33.5.15 Auto-baud modes When the software is expecting an “AT” command, it configures the UART1 with the expected character format and sets the U1ACR Start bit. The initial values in the divisor latches U1DLM and U1DLM don‘t care. Because of the “A” or “a” ASCII coding (”A" = 0x41, “a” = 0x61), the UART1 Rx pin sensed start bit and the LSB of the expected character are delimited by two falling edges. When the U1ACR Start bit is set, the auto-baud protocol will execute the following phases: 1. On U1ACR Start bit setting, the baud-rate measurement counter is reset and the UART1 U1RSR is reset. The U1RSR baud rate is switch to the highest rate. 2. A falling edge on UART1 Rx pin triggers the beginning of the start bit. The rate measuring counter will start counting pclk cycles optionally pre-scaled by the fractional baud-rate generator. 3. During the receipt of the start bit, 16 pulses are generated on the RSR baud input with the frequency of the (fractional baud-rate pre-scaled) UART1 input clock, guaranteeing the start bit is stored in the U1RSR. 4. During the receipt of the start bit (and the character LSB for mode = 0) the rate counter will continue incrementing with the pre-scaled UART1 input clock (pclk). 5. If Mode = 0 then the rate counter will stop on next falling edge of the UART1 Rx pin. If Mode = 1 then the rate counter will stop on the next rising edge of the UART1 Rx pin. 6. The rate counter is loaded into U1DLM/U1DLL and the baud-rate will be switched to normal operation. After setting the U1DLM/U1DLL the end of auto-baud interrupt U1IIR ABEOInt will be set, if enabled. The U1RSR will now continue receiving the remaining bits of the “A/a” character. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 760 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 33: LPC18xx UART1 FT D R R A D R A R A FT D R FT D R A R A FT FT A F 'A' (0x41) or 'a' (0x61) start UARTn RX start bit LSB of 'A' or 'a' bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop D D R A FT D R A FT D A FT D R A R U0ACR start rate counter 16xbaud_rate 16 cycles 16 cycles a. Mode 0 (start bit and LSB are used for auto-baud) 'A' (0x41) or 'a' (0x61) start UARTn RX start bit LSB of 'A' or 'a' bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop U1ACR start rate counter 16xbaud_rate 16 cycles b. Mode 1 (only start bit is used for auto-baud) Fig 97. Auto-baud a) mode 0 and b) mode 1 waveform 33.5.16 UART1 Fractional Divider Register The UART1 Fractional Divider Register (U1FDR) controls the clock pre-scaler for the baud rate generation and can be read and written at the user’s discretion. This pre-scaler takes the APB clock and generates an output clock according to the specified fractional requirements. Important: If the fractional divider is active (DIVADDVAL > 0) and DLM = 0, the value of the DLL register must be greater than 2. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 761 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 33: LPC18xx UART1 FT D R R A Table 705: UART1 Fractional Divider Register (FDR - address 0x4008 2028) bit description D R A R A FT D R FT D R A R A A FT FT F Bit 3:0 Function DIVADDVAL Description Reset value D D R A FT D Baud-rate generation pre-scaler divisor value. If this field is 0, 0 fractional baud-rate generator will not impact the UARTn baudrate. Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 1 R A FT D A R 7:4 MULVAL FT D R A 31:8 - 0 This register controls the clock pre-scaler for the baud rate generation. The reset value of the register keeps the fractional capabilities of UART1 disabled making sure that UART1 is fully software and hardware compatible with UARTs not equipped with this feature. UART1 baud rate can be calculated as (n = 1): (9) PCLK UART1 baudrate = ---------------------------------------------------------------------------------------------------------------------------------DivAddVal 16   256  U1DLM + U1DLL    1 + ----------------------------   MulVal  Where PCLK is the peripheral clock, U1DLM and U1DLL are the standard UART1 baud rate divider registers, and DIVADDVAL and MULVAL are UART1 fractional baud rate generator specific parameters. The value of MULVAL and DIVADDVAL should comply to the following conditions: 1. 1  MULVAL  15 2. 0  DIVADDVAL  14 3. DIVADDVAL < MULVAL The value of the U1FDR should not be modified while transmitting/receiving data or data may be lost or corrupted. If the U1FDR register value does not comply to these two requests, then the fractional divider output is undefined. If DIVADDVAL is zero then the fractional divider is disabled, and the clock will not be divided. 33.5.16.1 Baud rate calculation UART1 can operate with or without using the Fractional Divider. In real-life applications it is likely that the desired baud rate can be achieved using several different Fractional Divider settings. The following algorithm illustrates one way of finding a set of DLM, DLL, MULVAL, and DIVADDVAL values. Such set of parameters yields a baud rate with a relative error of less than 1.1% from the desired one. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 762 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 33: LPC18xx UART1 FT D R R A D R A R A FT D R FT D R A R A FT FT A F Calculating UART baudrate (BR) D D R A FT D R A FT D A R PCLK, BR FT D R A DL est = PCLK/(16 x BR) DL est is an integer? True False FR est = 1.5 DIVADDVAL = 0 MULVAL = 1 Pick another FR est from the range [1.1, 1.9] DL est = Int(PCLK/(16 x BR x FR est)) FR est = PCLK/(16 x BR x DL est) False 1.1 < FR est < 1.9? True DIVADDVAL = table(FR est ) MULVAL = table(FR est ) DLM = DL est [15:8] DLL = DLest [7:0] End Fig 98. Algorithm for setting UART dividers All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 763 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 33: LPC18xx UART1 FT D R A D R A R A FT D R FT D Table 706. Fractional Divider setting look-up table FR 1.000 1.067 1.071 1.077 1.083 1.091 1.100 1.111 1.125 1.133 1.143 1.154 1.167 1.182 1.200 1.214 1.222 1.231 DivAddVal/ MulVal 0/1 1/15 1/14 1/13 1/12 1/11 1/10 1/9 1/8 2/15 1/7 2/13 1/6 2/11 1/5 3/14 2/9 3/13 FR 1.250 1.267 1.273 1.286 1.300 1.308 1.333 1.357 1.364 1.375 1.385 1.400 1.417 1.429 1.444 1.455 1.462 1.467 DivAddVal/ MulVal 1/4 4/15 3/11 2/7 3/10 4/13 1/3 5/14 4/11 3/8 5/13 2/5 5/12 3/7 4/9 5/11 6/13 7/15 FR 1.500 1.533 1.538 1.545 1.556 1.571 1.583 1.600 1.615 1.625 1.636 1.643 1.667 1.692 1.700 1.714 1.727 1.733 DivAddVal/ MulVal 1/2 8/15 7/13 6/11 5/9 4/7 7/12 3/5 8/13 5/8 7/11 9/14 2/3 9/13 7/10 5/7 8/11 11/15 FR 1.750 1.769 1.778 1.786 1.800 1.818 1.833 1.846 1.857 1.867 1.875 1.889 1.900 1.909 1.917 1.923 1.929 1.933 R R 3/4 10/13 7/9 11/14 4/5 9/11 5/6 11/13 6/7 13/15 7/8 8/9 9/10 10/11 11/12 12/13 13/14 14/15 R A A DivAddVal/ MulVal A FT D R A FT D R A R A FT F FT D D R A FT D 33.5.16.1.1 Example 1: PCLK = 14.7456 MHz, BR = 9600 According to the provided algorithm DLest = PCLK/(16 x BR) = 14.7456 MHz / (16 x 9600) = 96. Since this DLest is an integer number, DIVADDVAL = 0, MULVAL = 1, DLM = 0, and DLL = 96. 33.5.16.1.2 Example 2: PCLK = 12 MHz, BR = 115200 According to the provided algorithm DLest = PCLK/(16 x BR) = 12 MHz / (16 x 115200) = 6.51. This DLest is not an integer number and the next step is to estimate the FR parameter. Using an initial estimate of FRest = 1.5 a new DLest = 4 is calculated and FRest is recalculated as FRest = 1.628. Since FRest = 1.628 is within the specified range of 1.1 and 1.9, DIVADDVAL and MULVAL values can be obtained from the attached look-up table. The closest value for FRest = 1.628 in the look-up Table 706 is FR = 1.625. It is equivalent to DIVADDVAL = 5 and MULVAL = 8. Based on these findings, the suggested UART setup would be: DLM = 0, DLL = 4, DIVADDVAL = 5, and MULVAL = 8. According to Equation 9 the UART rate is 115384. This rate has a relative error of 0.16% from the originally specified 115200. 33.5.17 UART1 Transmit Enable Register In addition to being equipped with full hardware flow control (auto-cts and auto-rts mechanisms described above), U1TER enables implementation of software flow control, too. When TxEn=1, UART1 transmitter will keep sending data as long as they are available. As soon as TxEn becomes 0, UART1 transmission will stop. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 764 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 33: LPC18xx UART1 FT D R R A Although Table 707 describes how to use TxEn bit in order to achieve hardware flow control, it is strongly suggested to let UART1 hardware implemented auto flow control features take care of this, and limit the scope of TxEn to software flow control. A FT D R A U1TER enables implementation of software and hardware flow control. When TXEn=1, UART1 transmitter will keep sending data as long as they are available. As soon as TXEn becomes 0, UART1 transmission will stop. D Table 707 describes how to use TXEn bit in order to achieve software flow control. Table 707: UART1 Transmit Enable Register (TER - address 0x4008 2030) bit description Bit 6:0 7 Symbol Description TXEN Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Reset value NA 1 Transmit enable bit. When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA D R A R A FT D R FT D R A F R A FT D FT D R A D R A FT R A FT 31:8 - 33.5.18 UART1 RS485 Control register The U1RS485CTRL register controls the configuration of the UART in RS-485/EIA-485 mode. Table 708: UART1 RS485 Control register (RS485CTRL - address 0x4008 204C) bit description Bit 0 Symbol NMMEN 0 1 Value Description Multidrop mode select. RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the UART to set the parity error and generate an interrupt. Receive enable. 0 1 2 AADEN 0 1 3 SEL 0 1 The receiver is enabled. The receiver is disabled. Auto Address Detect enable. Auto Address Detect (AAD) is disabled. Auto Address Detect (AAD) is enabled. Direction control. If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control. If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control. 0 0 0 Reset value 0 1 RXDIS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 765 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 33: LPC18xx UART1 FT D R Table 708: UART1 RS485 Control register (RS485CTRL - address 0x4008 204C) bit description Bit 4 Symbol DCTRL 0 1 5 OINV 0 1 31:6 Value Description Direction control enable. Disable Auto Direction Control. Enable Auto Direction Control. Polarity. 0 This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin. The direction control pin will be driven to logic ‘0’ when the transmitter has data to be sent. It will be driven to logic ‘1’ after the last bit of data has been transmitted. The direction control pin will be driven to logic ‘1’ when the transmitter has data to be sent. It will be driven to logic ‘0’ after the last bit of data has been transmitted. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA D R A R A FT D R FT D A R R A 0 R A F Reset value A FT D R A R A FT FT D R A FT D FT D D R A 33.5.19 UART1 RS-485 Address Match register The U1RS485ADRMATCH register contains the address match value for RS-485/EIA-485 mode. Table 709. UART1 RS485 Address Match register (RS485ADRMATCH - address 0x4008 2050) bit description Bit 7:0 31:8 Symbol ADRMATCH Description Contains the address match value. Reset value 0x00 Reserved, user software should not write ones to reserved bits. The value read from a NA reserved bit is not defined. 33.5.20 UART1 RS-485 Delay value register The user may program the 8-bit RS485DLY register with a delay between the last stop bit leaving the TXFIFO and the de-assertion of RTS (or DTR). This delay time is in periods of the baud clock. Any delay time from 0 to 255 bit times may be programmed. Table 710. UART1 RS485 Delay value register (RS485DLY - address 0x4008 2054) bit description Bit 7:0 31:8 Symbol DLY Description Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter. Reset value 0x00 Reserved, user software should not write ones to reserved bits. The value read from a NA reserved bit is not defined. 33.5.21 RS-485/EIA-485 modes of operation The RS-485/EIA-485 feature allows the UART to be configured as an addressable slave. The addressable slave is one of multiple slaves controlled by a single master. The UART master transmitter will identify an address character by setting the parity (9th) bit to ‘1’. For data characters, the parity bit is set to ‘0’. Each UART slave receiver can be assigned a unique address. The slave can be programmed to either manually or automatically reject data following an address which is not theirs. RS-485/EIA-485 Normal Multidrop Mode (NMM) All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 766 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 33: LPC18xx UART1 FT D R R A Setting the RS485CTRL bit 0 enables this mode. In this mode, an address is detected when a received byte causes the UART to set the parity error and generate an interrupt. R A A FT D R A FT If the receiver is DISABLED (RS485CTRL bit 1 = ‘1’) any received data bytes will be ignored and will not be stored in the RXFIFO. When an address byte is detected (parity bit = ‘1’) it will be placed into the RXFIFO and an Rx Data Ready Interrupt will be generated. The processor can then read the address byte and decide whether or not to enable the receiver to accept the following data. D While the receiver is ENABLED (RS485CTRL bit 1 =’0’) all received bytes will be accepted and stored in the RXFIFO regardless of whether they are data or address. When an address character is received a parity error interrupt will be generated and the processor can decide whether or not to disable the receiver. RS-485/EIA-485 Auto Address Detection (AAD) mode When both RS485CTRL register bits 0 (9-bit mode enable) and 2 (AAD mode enable) are set, the UART is in auto address detect mode. In this mode, the receiver will compare any address byte received (parity = ‘1’) to the 8-bit value programmed into the RS485ADRMATCH register. If the receiver is DISABLED (RS485CTRL bit 1 = ‘1’) any received byte will be discarded if it is either a data byte OR an address byte which fails to match the RS485ADRMATCH value. When a matching address character is detected it will be pushed onto the RXFIFO along with the parity bit, and the receiver will be automatically enabled (RS485CTRL bit 1 will be cleared by hardware). The receiver will also generate n Rx Data Ready Interrupt. While the receiver is ENABLED (RS485CTRL bit 1 = ‘0’) all bytes received will be accepted and stored in the RXFIFO until an address byte which does not match the RS485ADRMATCH value is received. When this occurs, the receiver will be automatically disabled in hardware (RS485CTRL bit 1 will be set), The received non-matching address character will not be stored in the RXFIFO. RS-485/EIA-485 Auto Direction Control RS485/EIA-485 Mode includes the option of allowing the transmitter to automatically control the state of either the RTS pin or the DTR pin as a direction control output signal. Setting RS485CTRL bit 4 = ‘1’ enables this feature. Direction control, if enabled, will use the RTS pin when RS485CTRL bit 3 = ‘0’. It will use the DTR pin when RS485CTRL bit 3 = ‘1’. When Auto Direction Control is enabled, the selected pin will be asserted (driven low) when the CPU writes data into the TXFIFO. The pin will be de-asserted (driven high) once the last bit of data has been transmitted. See bits 4 and 5 in the RS485CTRL register. The RS485CTRL bit 4 takes precedence over all other mechanisms controlling RTS (or DTR) with the exception of loopback mode. RS485/EIA-485 driver delay time D R A R A FT D R FT D R A F R A FT D FT D R A D FT R A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 767 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 33: LPC18xx UART1 FT D R R A The driver delay time is the delay between the last stop bit leaving the TXFIFO and the de-assertion of RTS (or DTR). This delay time can be programmed in the 8-bit RS485DLY register. The delay time is in periods of the baud clock. Any delay time from 0 to 255 bit times may be programmed. R A A FT D R A FT D D R A R A FT D R FT D R A F R A FT D D FT R RS485/EIA-485 output inversion The polarity of the direction control signal on the RTS (or DTR) pins can be reversed by programming bit 5 in the U1RS485CTRL register. When this bit is set, the direction control pin will be driven to logic 1 when the transmitter has data waiting to be sent. The direction control pin will be driven to logic 0 after the last bit of data has been transmitted. A FT D R A 33.5.22 UART1 FIFO Level register U1FIFOLVL register is a read-only register that allows software to read the current FIFO level status. Both the transmit and receive FIFO levels are present in this register. Table 711. UART1 FIFO Level register (FIFOLVL - address 0x4008 2058) bit description Bit 3:0 7:4 11:8 Symbol RXFIFILVL TXFIFOLVL Description Reflects the current level of the UART1 receiver FIFO. 0 = empty, 0xF = FIFO full. Reserved. The value read from a reserved bit is not defined. Reflects the current level of the UART1 transmitter FIFO. 0 = empty, 0xF = FIFO full. 31:12 Reserved, the value read from a reserved bit is not defined. NA NA 0x00 Reset value 0x00 33.6 Architecture The architecture of the UART1 is shown below in the block diagram. The APB interface provides a communications link between the CPU or host and the UART1. The UART1 receiver block, U1RX, monitors the serial input line, RXD1, for valid input. The UART1 RX Shift Register (U1RSR) accepts valid characters via RXD1. After a valid character is assembled in the U1RSR, it is passed to the UART1 RX Buffer Register FIFO to await access by the CPU or host via the generic host interface. The UART1 transmitter block, U1TX, accepts data written by the CPU or host and buffers the data in the UART1 TX Holding Register FIFO (U1THR). The UART1 TX Shift Register (U1TSR) reads the data stored in the U1THR and assembles the data to transmit via the serial output pin, TXD1. The UART1 Baud Rate Generator block, U1BRG, generates the timing enables used by the UART1 TX block. The U1BRG clock input source is the APB clock (PCLK). The main clock is divided down per the divisor specified in the U1DLL and U1DLM registers. This divided down clock is a 16x oversample clock, NBAUDOUT. The modem interface contains registers U1MCR and U1MSR. This interface is responsible for handshaking between a modem peripheral and the UART1. The interrupt interface contains registers U1IER and U1IIR. The interrupt interface receives several one clock wide enables from the U1TX and U1RX blocks. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 768 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 33: LPC18xx UART1 FT D R R A Status information from the U1TX and U1RX is stored in the U1LSR. Control information for the U1TX and U1RX is stored in the U1LCR. R A A FT D R A FT D R A Transmitter Transmitter Holding Register Transmitter FIFO Transmitter DMA Interface TX_DMA_REQ TX_DMA_CLR Baud Rate Generator Fractional Main Rate Divider Divider (DLM, DLL) FIFO Control & Status Interrupt Control & Status U1_OE Line Control & Status RS485, IrDA, & Auto-baud Receiver Receiver Buffer Register Receiver FIFO Receiver DMA Interface RX_DMA_REQ RX_DMA_CLR R A FT D R FT D R A F R A FT D FT D FT R A D Transmitter Shift Register U1_TXD D R A PCLK UART1 interrupt U1_CTS U1_RTS U1_DSR U1_DTR U1_DCD U1_RI Modem Control & Status Receiver Shift Register U1_RXD Fig 99. UART1 block diagram All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 769 of 1164 D R A FT D R A FT D R A FT D R A FT D R A FT UM10430 Chapter 34: LPC18xx SSP0/1 Rev. 00.13 — 20 July 2011 D D D R A FT D D R A FT D R A FT D R A R A FT D R A R A FT D R A FT D R A F R A FT D R R D User manual FT D R A FT FT A FT 34.1 How to read this chapter The SSP0/1 controllers are available on all LPC18xx parts. D D R A FT D R A 34.2 Basic configuration The SSP0/1 are configured as follows: • • • • See Table 712 for clocking and power control. The SSP0/1 are reset by the SSP0/1_RST (reset #50/51). The SSP0/1 interrupts are connected to slots # 22/23 in the NVIC. For connecting the SSP0/1 receive and transmit lines to the GPDMA, use the DMAMUX register in the CREG block (see Table 35) and enable the GPDMA channel in the DMA Channel Configuration registers (Section 16.6.20). Table 712. SSP0/1 clocking and power control Base clock Branch clock Maximum frequency Clock to SSP0 register interface SSP0 peripheral clock (PCLK) Clock to SSP1 register interface SSP1 peripheral clock (PCLK) BASE_M3_CLK BASE_SSP0_CLK BASE_M3_CLK BASE_SSP1_CLK CLK_M3_SSP0 CLK_APB0_SSP0 CLK_M3_SSP1 CLK_APB2_SSP1 150 MHz 150 MHz 150 MHz 150 MHz 34.3 Features • Compatible with Motorola SPI, 4-wire TI SSI, and National Semiconductor Microwire buses. • • • • Synchronous Serial Communication. Supports master or slave operation. Eight-frame FIFOs for both transmit and receive. 4-bit to 16-bit frame. 34.4 General description The SSP is a Synchronous Serial Port (SSP) controller capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given data transfer. Data transfers are in principle full duplex, with frames of 4 to 16 bits of data flowing from the master to the slave and from the slave to the master. In practice it is often the case that only one of these data flows carries meaningful data. The LPC18xx has two Synchronous Serial Port controllers -- SSP0 and SSP1. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 770 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 34: LPC18xx SSP0/1 FT D R A D R A R A FT D R FT 34.5 Pin description Table 713. SSP pin description Pin Name Direction Interface pin name/function SPI SSI Microwire Pin description D R R A FT D R R A F D R A FT A FT A FT D R A D FT D R SCK0/1 I/O SCK CLK SK Serial Clock. SCK/CLK/SK is a clock signal used to synchronize the transfer of data. It is driven by the master and received by the slave. When the SPI interface is used, the clock is programmable to be active-high or active-low, otherwise it is always active-high. SCK1 only switches during a data transfer. Any other time, the SSPn interface either holds it in its inactive state, or does not drive it (leaves it in high-impedance state). Frame Sync/Slave Select. When the SSPn interface is a bus master, it drives this signal to an active state before the start of serial data, and then releases it to an inactive state after the serial data has been sent. The active state of this signal can be high or low depending upon the selected bus and mode. When the SSPn is a bus slave, this signal qualifies the presence of data from the Master, according to the protocol in use. A SSEL0/1 I/O SSEL FS CS When there is just one bus master and one bus slave, the Frame Sync or Slave Select signal from the Master can be connected directly to the slave's corresponding input. When there is more than one slave on the bus, further qualification of their Frame Select/Slave Select inputs will typically be necessary to prevent more than one slave from responding to a transfer. MISO0/1 I/O MISO DR(M) SI(M) DX(S) SO(S) Master In Slave Out. The MISO signal transfers serial data from the slave to the master. When the SSPn is a slave, serial data is output on this signal. When the SSPn is a master, it clocks in serial data from this signal. When the SSPn is a slave and is not selected by FS/SSEL, it does not drive this signal (leaves it in high-impedance state). Master Out Slave In. The MOSI signal transfers serial data from the master to the slave. When the SSPn is a master, it outputs serial data on this signal. When the SSPn is a slave, it clocks in serial data from this signal. MOSI0/1 I/O MOSI DX(M) SO(M) DR(S) SI(S) 34.6 Register description The register addresses of the SSP controllers are shown in Table 714 and Table 715. Table 714. Register overview: SSP0 (base address 0x4008 3000) Name Access Address offset Description Reset value[1] CR0 CR1 DR SR CPSR IMSC R/W R/W R/W RO R/W R/W 0x000 0x004 0x008 0x00C 0x010 0x014 Control Register 0. Selects the serial clock rate, bus type, and data size. Control Register 1. Selects master/slave and other modes. Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. Status Register Clock Prescale Register Interrupt Mask Set and Clear Register All information provided in this document is subject to legal disclaimers. 0 0 0 0x0000 0003 0 0 © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 771 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 34: LPC18xx SSP0/1 FT D R A D R A R A FT D R FT Table 714. Register overview: SSP0 (base address 0x4008 3000) Name Access Address offset Description D R R A FT D R R A F D R A Reset value[1] A FT A RIS MIS ICR DMACR [1] RO RO WO R/W 0x018 0x01C 0x020 0x024 Raw Interrupt Status Register Masked Interrupt Status Register SSPICR Interrupt Clear Register SSP0 DMA control register 0x0000 0008 FT D R A FT D FT D 0 0 R A Reset value reflects the data stored in used bits only. It does not include reserved bits content. Table 715. Register overview: SSP1 (base address 0x400C 5000) Name Access Address offset Description Reset value[1] CR0 CR1 DR SR CPSR IMSC RIS MIS ICR DMACR [1] R/W R/W R/W RO R/W R/W RO RO R/W R/W 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 0x024 Control Register 0. Selects the serial clock rate, bus type, and data size. Control Register 1. Selects master/slave and other modes. Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. Status Register Clock Prescale Register Interrupt Mask Set and Clear Register Raw Interrupt Status Register Masked Interrupt Status Register SSPICR Interrupt Clear Register SSP1 DMA control register 0 0 0 0x0000 0003 0 0 0x0000 0008 0 0 Reset value reflects the data stored in used bits only. It does not include reserved bits content. 34.6.1 SSPControl Register 0 This register controls the basic operation of the SSP controller. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 772 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 34: LPC18xx SSP0/1 FT D R R A Table 716: SSP Control Register 0 (CR0 - address 0x4008 3000 (SSP0), 0x400C 5000 (SSP1)) bit description D R A R A FT D R FT D R A R A A FT D F FT D Bit Symbol Value Description Reset value R R A A FT D FT 3:0 DSS Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used. 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF 4-bit transfer 5-bit transfer 6-bit transfer 7-bit transfer 8-bit transfer 9-bit transfer 10-bit transfer 11-bit transfer 12-bit transfer 13-bit transfer 14-bit transfer 15-bit transfer 16-bit transfer Frame Format. 0x0 0x1 0x2 0x3 SPI TI Microwire This combination is not supported and should not be used. Clock Out Polarity. This bit is only used in SPI mode. 0 1 SSP controller maintains the bus clock low between frames. SSP controller maintains the bus clock high between frames. Clock Out Phase. This bit is only used in SPI mode. 0 SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line. SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line. 0000 D R A FT D R A 5:4 FRF 00 6 CPOL 0 7 CPHA 0 1 15:8 SCR Serial Clock Rate. The number of prescaler-output clocks per bit 0x00 on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR  [SCR+1]). Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 31:16 - 34.6.2 SSP Control Register 1 This register controls certain aspects of the operation of the SSP controller. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 773 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 34: LPC18xx SSP0/1 FT D R R A Table 717: SSP Control Register 1 (CR1 - address 0x4008 3004 (SSP0), 0x400C 5004 (SSP1)) bit description D R A R A FT D R FT D R A R A A FT D F FT D Bit Symbol Value Description Reset value R R A A FT D FT 0 LBM 0 1 Loop Back Mode. During normal operation. Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively). SSP Enable. 0 1 The SSP controller is disabled. The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit. 0 D R A FT D R A 1 SSE 0 2 MS 0 1 Master/Slave Mode.This bit can only be written when the SSE bit 0 is 0. The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line. The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines. Slave Output Disable. This bit is relevant only in slave mode 0 (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO). Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 3 SOD 31:4 - 34.6.3 SSP Data Register Software can write data to be transmitted to this register, and read data that has been received. Table 718: SSP Data Register (DR - address 0x4008 3008 (SSP0), 0x400C 5008 (SSP1)) bit description Bit Symbol Description Reset value 15:0 DATA 0x0000 Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s. 31:16 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 774 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 34: LPC18xx SSP0/1 FT D R A D R A R A FT D R FT 34.6.4 SSP Status Register This read-only register reflects the current status of the SSP controller. D R Table 719: SSP Status Register (SR - address 0x4008 300C (SSP0), 0x400C 500C (SSP1)) bit description R A FT D R R A F D R A FT A FT A FT D R A D Bit Symbol Description Reset value FT D R A 0 1 2 3 4 31:5 TFE TNF RNE RFF BSY - Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not. 1 Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not. Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not. Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not. Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 1 0 0 0 NA 34.6.5 SSP Clock Prescale Register This register controls the factor by which the Prescaler divides the SSP peripheral clock PCLK to yield the prescaler clock that is, in turn, divided by the SCR factor in SSPnCR0, to determine the bit clock. Table 720: SSP Clock Prescale Register (CPSR - address 0x4008 3010 (SSP0), 0x400C 5010 (SSP1)) bit description Bit Symbol Description Reset value 7:0 31:8 CPSDVSR - This even value between 2 and 254, by which PCLK is divided to yield 0 the prescaler output clock. Bit 0 always reads as 0. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA Important: the SSPnCPSR value must be properly initialized or the SSP controller will not be able to transmit data correctly. In Slave mode, the SSP clock rate provided by the master must not exceed 1/12 of the SSP peripheral clock. The content of the SSPnCPSR register is not relevant. In master mode, CPSDVSRmin = 2 or larger (even numbers only). 34.6.6 SSP Interrupt Mask Set/Clear Register This register controls whether each of the four possible interrupt conditions in the SSP controller are enabled. Note that ARM uses the word “masked” in the opposite sense from classic computer terminology, in which “masked” meant “disabled”. ARM uses the word “masked” to mean “enabled”. To avoid confusion we will not use the word “masked”. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 775 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 34: LPC18xx SSP0/1 FT D R R A Table 721: SSP Interrupt Mask Set/Clear register (IMSC - address 0x4008 3014 (SSP0), 0x400C 5014 (SSP1)) bit description D R A R A FT D R FT D R A R A FT D A F FT D Bit Symbol Description Reset value R R A A FT D FT 0 RORIM Software should set this bit to enable interrupt when a Receive Overrun 0 occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs. Software should set this bit to enable interrupt when a Receive Time-out 0 condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR  [SCR+1]). Software should set this bit to enable interrupt when the Rx FIFO is at least half full. Software should set this bit to enable interrupt when the Tx FIFO is at least half empty. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0 0 NA D R A FT D R A 1 RTIM 2 3 31:4 RXIM TXIM - 34.6.7 SSP Raw Interrupt Status Register This read-only register contains a 1 for each interrupt condition that is asserted, regardless of whether or not the interrupt is enabled in the SSPnIMSC. Table 722: SSP Raw Interrupt Status register (RIS - address 0x4008 3018 (SSP0), RIS 0x400C 5018 (SSP1)) bit description Bit Symbol Description Reset value 0 RORRIS This bit is 1 if another frame was completely received while the RxFIFO 0 was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs. This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR  [SCR+1]). This bit is 1 if the Rx FIFO is at least half full. This bit is 1 if the Tx FIFO is at least half empty. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0 1 RTRIS 2 3 31:4 RXRIS TXRIS - 0 1 NA 34.6.8 SSP Masked Interrupt Status Register This read-only register contains a 1 for each interrupt condition that is asserted and enabled in the SSPnIMSC. When an SSP interrupt occurs, the interrupt service routine should read this register to determine the cause(s) of the interrupt. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 776 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 34: LPC18xx SSP0/1 FT D R R A Table 723: SSP Masked Interrupt Status register (MIS -address 0x4008 301C (SSP0), 0x400C 501C (SSP1)) bit description D R A R A FT D R FT D R A R A FT D A F FT D Bit Symbol Description Reset value R R A A FT D FT 0 1 RORMIS RTMIS This bit is 1 if another frame was completely received while the RxFIFO 0 was full, and this interrupt is enabled. 0 This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR  [SCR+1]). This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled. This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0 0 NA D R A FT D R A 2 3 31:4 RXMIS TXMIS - 34.6.9 SSP Interrupt Clear Register Software can write one or more one(s) to this write-only register, to clear the corresponding interrupt condition(s) in the SSP controller. Note that the other two interrupt conditions can be cleared by writing or reading the appropriate FIFO, or disabled by clearing the corresponding bit in SSPnIMSC. Table 724: SSP interrupt Clear Register (ICR - address 0x4008 3020 (SSP0), ICR 0x400C 5020 (SSP1)) bit description Bit Symbol Description Reset value 0 1 RORIC RTIC Writing a 1 to this bit clears the “frame was received when RxFIFO was full” interrupt. NA NA Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR  [SCR+1]). Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 31:2 - 34.6.10 SSP DMA Control Register The SSPnDMACR register is the DMA control register. It is a read/write register. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 777 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 34: LPC18xx SSP0/1 FT D R R A Table 725: SSP DMA Control Register (DMACR - address 0x4008 3024 (SSP0), 0x400C 5024 (SSP1)) bit description D R A R A FT D R FT D R A R A A FT D F FT D Bit Symbol Description Reset value R R A A FT D FT 0 RXDMAE Receive DMA Enable. When this bit is set to one 1, DMA 0 for the receive FIFO is enabled, otherwise receive DMA is disabled. Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled 0 D R A FT D R A 1 TXDMAE 31:2 - Reserved, user software should not write ones to reserved NA bits. The value read from a reserved bit is not defined. 34.7 Functional description 34.7.1 Texas Instruments synchronous serial frame format Figure 100 shows the 4-wire Texas Instruments synchronous serial frame format supported by the SSP module. CLK FS DX/DR MSB 4 to 16 bits LSB a. Single frame transfer CLK FS DX/DR MSB 4 to 16 bits LSB MSB 4 to 16 bits LSB b. Continuous/back-to-back frames transfer Fig 100. Texas Instruments Synchronous Serial Frame Format: a) Single and b) Continuous/back-to-back Two Frames Transfer For device configured as a master in this mode, CLK and FS are forced LOW, and the transmit data line DX is tri-stated whenever the SSP is idle. Once the bottom entry of the transmit FIFO contains data, FS is pulsed HIGH for one CLK period. The value to be transmitted is also transferred from the transmit FIFO to the serial shift register of the transmit logic. On the next rising edge of CLK, the MSB of the 4-bit to 16-bit data frame is shifted out on the DX pin. Likewise, the MSB of the received data is shifted onto the DR pin by the off-chip serial slave device. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 778 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 34: LPC18xx SSP0/1 FT D R R A Both the SSP and the off-chip serial slave device then clock each data bit into their serial shifter on the falling edge of each CLK. The received data is transferred from the serial shifter to the receive FIFO on the first rising edge of CLK after the LSB has been latched. R A A FT D R A FT D R A R A FT D R FT D R A F R A FT D D FT 34.7.2 SPI frame format The SPI interface is a four-wire interface where the SSEL signal behaves as a slave select. The main feature of the SPI format is that the inactive state and phase of the SCK signal are programmable through the CPOL and CPHA bits within the SSPCR0 control register. D R A FT D R A 34.7.2.1 Clock Polarity (CPOL) and Phase (CPHA) control When the CPOL clock polarity control bit is 0, it produces a steady state low value on the SCK pin. If the CPOL clock polarity control bit is 1, a steady state high value is placed on the CLK pin when data is not being transferred. The CPHA control bit selects the clock edge that captures data and allows it to change state. It has the most impact on the first bit transmitted by either allowing or not allowing a clock transition before the first data capture edge. When the CPHA phase control bit is 0, data is captured on the first clock edge transition. If the CPHA clock phase control bit is 1, data is captured on the second clock edge transition. 34.7.2.2 SPI format with CPOL=0,CPHA=0 Single and continuous transmission signal sequences for SPI format with CPOL = 0, CPHA = 0 are shown in Figure 101. SCK SSEL MOSI MISO MSB MSB 4 to 16 bits LSB LSB Q a. Single transfer with CPOL=0 and CPHA=0 SCK SSEL MOSI MISO MSB MSB 4 to 16 bits LSB LSB Q MSB MSB 4 to 16 bits LSB LSB Q b. Continuous transfer with CPOL=0 and CPHA=0 Fig 101. SPI frame format with CPOL=0 and CPHA=0 (a) Single and b) Continuous Transfer) All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 779 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 34: LPC18xx SSP0/1 FT D R A D R A R A FT D R FT In this configuration, during idle periods: D R R A FT R A F A FT • The CLK signal is forced LOW. • SSEL is forced HIGH. • The transmit MOSI/MISO pad is in high impedance. D If the SSP is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSEL master signal being driven LOW. This causes slave data to be enabled onto the MISO input line of the master. Master’s MOSI is enabled. One half SCK period later, valid master data is transferred to the MOSI pin. Now that both the master and slave data have been set, the SCK master clock pin goes HIGH after one further half SCK period. The data is now captured on the rising and propagated on the falling edges of the SCK signal. In the case of a single word transmission, after all bits of the data word have been transferred, the SSEL line is returned to its idle HIGH state one SCK period after the last bit has been captured. However, in the case of continuous back-to-back transmissions, the SSEL signal must be pulsed HIGH between each data word transfer. This is because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the CPHA bit is logic zero. Therefore the master device must raise the SSEL pin of the slave device between each data transfer to enable the serial peripheral data write. On completion of the continuous transfer, the SSEL pin is returned to its idle state one SCK period after the last bit has been captured. D R A FT D R A FT D A FT D R A R 34.7.2.3 SPI format with CPOL=0,CPHA=1 The transfer signal sequence for SPI format with CPOL = 0, CPHA = 1 is shown in Figure 102, which covers both single and continuous transfers. SCK SSEL MOSI MISO Q MSB MSB 4 to 16 bits LSB LSB Q Fig 102. SPI frame format with CPOL=0 and CPHA=1 In this configuration, during idle periods: • The CLK signal is forced LOW. • SSEL is forced HIGH. • The transmit MOSI/MISO pad is in high impedance. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 780 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 34: LPC18xx SSP0/1 FT D R R A If the SSP is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSEL master signal being driven LOW. Master’s MOSI pin is enabled. After a further one half SCK period, both master and slave valid data is enabled onto their respective transmission lines. At the same time, the SCK is enabled with a rising edge transition. R A Data is then captured on the falling edges and propagated on the rising edges of the SCK signal. In the case of a single word transfer, after all bits have been transferred, the SSEL line is returned to its idle HIGH state one SCK period after the last bit has been captured. For continuous back-to-back transfers, the SSEL pin is held LOW between successive data words and termination is the same as that of the single word transfer. D R A R A FT D R FT D R A A FT D R A R A FT F FT D R A FT D D R A FT D 34.7.2.4 SPI format with CPOL = 1,CPHA = 0 Single and continuous transmission signal sequences for SPI format with CPOL=1, CPHA=0 are shown in Figure 103. SCK SSEL MOSI MISO MSB MSB 4 to 16 bits LSB LSB Q a. Single transfer with CPOL=1 and CPHA=0 SCK SSEL MOSI MISO MSB MSB 4 to 16 bits LSB LSB Q MSB MSB 4 to 16 bits LSB LSB Q b. Continuous transfer with CPOL=1 and CPHA=0 Fig 103. SPI frame format with CPOL = 1 and CPHA = 0 (a) Single and b) Continuous Transfer) In this configuration, during idle periods: • The CLK signal is forced HIGH. • SSEL is forced HIGH. • The transmit MOSI/MISO pad is in high impedance. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 781 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 34: LPC18xx SSP0/1 FT D R R A If the SSP is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSEL master signal being driven LOW, which causes slave data to be immediately transferred onto the MISO line of the master. Master’s MOSI pin is enabled. R A One half period later, valid master data is transferred to the MOSI line. Now that both the master and slave data have been set, the SCK master clock pin becomes LOW after one further half SCK period. This means that data is captured on the falling edges and be propagated on the rising edges of the SCK signal. In the case of a single word transmission, after all bits of the data word are transferred, the SSEL line is returned to its idle HIGH state one SCK period after the last bit has been captured. However, in the case of continuous back-to-back transmissions, the SSEL signal must be pulsed HIGH between each data word transfer. This is because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the CPHA bit is logic zero. Therefore the master device must raise the SSEL pin of the slave device between each data transfer to enable the serial peripheral data write. On completion of the continuous transfer, the SSEL pin is returned to its idle state one SCK period after the last bit has been captured. D R A R A FT D R FT D R A A FT D R A R A FT F FT D R A FT D D R A FT D 34.7.2.5 SPI format with CPOL = 1,CPHA = 1 The transfer signal sequence for SPI format with CPOL = 1, CPHA = 1 is shown in Figure 104, which covers both single and continuous transfers. SCK SSEL MOSI MISO Q MSB MSB 4 to 16 bits LSB LSB Q Fig 104. SPI Frame Format with CPOL = 1 and CPHA = 1 In this configuration, during idle periods: • The CLK signal is forced HIGH. • SSEL is forced HIGH. • The transmit MOSI/MISO pad is in high impedance. If the SSP is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSEL master signal being driven LOW. Master’s MOSI is enabled. After a further one half SCK period, both master and slave data are enabled onto their respective transmission lines. At the same time, the SCK is enabled with a falling edge transition. Data is then captured on the rising edges and propagated on the falling edges of the SCK signal. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 782 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 34: LPC18xx SSP0/1 FT D R R A After all bits have been transferred, in the case of a single word transmission, the SSEL line is returned to its idle HIGH state one SCK period after the last bit has been captured. For continuous back-to-back transmissions, the SSEL pins remains in its active LOW state, until the final bit of the last word has been captured, and then returns to its idle state as described above. In general, for continuous back-to-back transfers the SSEL pin is held LOW between successive data words and termination is the same as that of the single word transfer. R A A FT D R A FT D D R A R A FT D R FT D R A F R A FT D FT D R A D FT R A 34.7.3 National Semiconductor Microwire frame format Figure 105 shows the Microwire frame format for a single frame. Figure 106 shows the same format when back-to-back frames are transmitted. SK CS SO SI MSB LSB 8-bit control 0 MSB LSB 4 to 16 bits output data Fig 105. Microwire frame format (single transfer) Microwire format is very similar to SPI format, except that transmission is half-duplex instead of full-duplex, using a master-slave message passing technique. Each serial transmission begins with an 8-bit control word that is transmitted from the SSP to the off-chip slave device. During this transmission, no incoming data is received by the SSP. After the message has been sent, the off-chip slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent, responds with the required data. The returned data is 4 to 16 bits in length, making the total frame length anywhere from 13 to 25 bits. In this configuration, during idle periods: • The SK signal is forced LOW. • CS is forced HIGH. • The transmit data line SO is arbitrarily forced LOW. A transmission is triggered by writing a control byte to the transmit FIFO.The falling edge of CS causes the value contained in the bottom entry of the transmit FIFO to be transferred to the serial shift register of the transmit logic, and the MSB of the 8-bit control frame to be shifted out onto the SO pin. CS remains LOW for the duration of the frame transmission. The SI pin remains tristated during this transmission. The off-chip serial slave device latches each control bit into its serial shifter on the rising edge of each SK. After the last bit is latched by the slave device, the control byte is decoded during a one clock wait-state, and the slave responds by transmitting data back to the SSP. Each bit is driven onto SI line on the falling edge of SK. The SSP in turn All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 783 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 34: LPC18xx SSP0/1 FT D R R A latches each bit on the rising edge of SK. At the end of the frame, for single transfers, the CS signal is pulled HIGH one clock period after the last bit has been latched in the receive serial shifter, that causes the data to be transferred to the receive FIFO. R A A FT D R A FT D Note: The off-chip slave device can tristate the receive line either on the falling edge of SK after the LSB has been latched by the receive shiftier, or when the CS pin goes HIGH. For continuous transfers, data transmission begins and ends in the same manner as a single transfer. However, the CS line is continuously asserted (held LOW) and transmission of data occurs back to back. The control byte of the next frame follows directly after the LSB of the received data from the current frame. Each of the received values is transferred from the receive shifter on the falling edge SK, after the LSB of the frame has been latched into the SSP. D R A R A FT D R FT D R A F R A FT D FT D R A D FT R A SK CS SO SI LSB MSB LSB 8-bit control 0 MSB LSB MSB LSB 4 to 16 bits output data 4 to 16 bits output data Fig 106. Microwire frame format (continuous transfers) 34.7.3.1 Setup and hold time requirements on CS with respect to SK in Microwire mode In the Microwire mode, the SSP slave samples the first bit of receive data on the rising edge of SK after CS has gone LOW. Masters that drive a free-running SK must ensure that the CS signal has sufficient setup and hold margins with respect to the rising edge of SK. Figure 107 illustrates these setup and hold time requirements. With respect to the SK rising edge on which the first bit of receive data is to be sampled by the SSP slave, CS must have a setup of at least two times the period of SK on which the SSP operates. With respect to the SK rising edge previous to this edge, CS must have a hold of at least one SK period. t HOLD= tSK tSETUP=2*tSK SK CS SI Fig 107. Microwire frame format setup and hold details All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 784 of 1164 D R A FT D R A FT D R A FT D R A FT D R A FT UM10430 Chapter 35: LPC18xx I2S interface Rev. 00.13 — 20 July 2011 D D D R A FT D D R A FT D R A FT D R A R A FT D R A R A FT D R A FT D R A F R A FT D R R D User manual FT D R A FT FT A FT 35.1 How to read this chapter This chapter applies to parts LPC1850/30/20/10 Rev ‘A’. The I2S interface is available on all LPC18xx parts. D D R A FT D R A 35.2 Basic configuration The I2S interface is configured as follows: • • • • • • See Table 726 for clocking and power control. The I2S0 is reset by the I2S0_RST (reset # 52). The I2S1 is reset by the I2S1_RST (reset # 53). The I2S0 interrupt is connected to slot # 28 in the NVIC. The I2S1 interrupt is connected to slot # 29 in the NVIC. For connecting the I2S receive and transmit lines to the GPDMA, use the DMAMUX register in the CREG block (see Table 35) and enable the GPDMA channel in the DMA Channel Configuration registers (Section 16.6.20). timer and SCT inputs. • See Table 37 for interconnections between the I2S transmit/receive lines and the Table 726. I2S clocking and power control Base clock Branch clock Maximum frequency Clock to the I2S0 and I2S1 register interface and I2S0/1 peripheral clock. BASE_APB1_CLK CLK_APB1_I2S 150 MHz 35.3 Features The I2S bus provides a standard communication interface for digital audio applications. The I2S bus specification defines a 3-wire serial bus, having one data, one clock, and one word select signal. The basic I2S connection has one master, which is always the master, and one slave. The I2S interface provides a separate transmit and receive channel, each of which can operate as either a master or a slave. • The I2S input can operate in both master and slave mode. The I2S output can operate in both master and slave mode, independent of the I2S input. • Capable of handling 8-bit, 16-bit, and 32-bit word sizes. • Mono and stereo audio data supported. • Versatile clocking includes independent transmit and receive fractional rate generators, and an ability to use a single clock input or output for a 4-wire mode. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 785 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 35: LPC18xx I2S interface FT D R R A • The sampling frequency (fs) can range (in practice) from 16 to 192 kHz (16, 22.05, 32, R D R A R A FT D R FT D R 44.1, 48, 96, or 192 kHz) for audio applications. up to 512 times the I2S sampling frequency. output). A A • Separate Master Clock outputs for both transmit and receive channels support a clock • Word Select period in master mode is configurable (separately for I2S input and I2S • Two 8 word (32 byte) FIFO data buffers are provided, one for transmit and one for receive. R A FT D • Generates interrupt requests when buffer levels cross a programmable boundary. • Two DMA requests, controlled by programmable buffer levels. These are connected to the General Purpose DMA block. • Controls include reset, stop and mute options separately for I2S input and I2S output. A FT D FT D R A R A FT F FT D D R A 35.4 General description The I2S performs serial data out via the transmit channel and serial data in via the receive channel. These support the NXP Inter IC Audio format for 8-bit, 16-bit and 32-bit audio data, both for stereo and mono modes. Configuration, data access and control is performed by a APB register set. Data streams are buffered by FIFOs with a depth of 8 words. The I2S receive and transmit stage can operate independently in either slave or master mode. Within the I2S module the difference between these modes lies in the word select (WS) signal which determines the timing of data transmissions. Data words start on the next falling edge of the transmitting clock after a WS change. In stereo mode when WS is low left data is transmitted and right data when WS is high. In mono mode the same data is transmitted twice, once when WS is low and again when WS is high. • In master mode, word select is generated internally with a 9-bit counter. The half period count value of this counter can be set in the control register. • In slave mode, word select is input from the relevant bus pin. • When an I2S bus is active, the word select, receive clock and transmit clock signals are sent continuously by the bus master, while data is sent continuously by the transmitter. • Disabling the I2S can be done with the stop or mute control bits separately for the transmit and receive. • The stop bit will disable accesses by the transmit channel or the receive channel to the FIFOs and will place the transmit channel in mute mode. • The mute control bit will place the transmit channel in mute mode. In mute mode, the transmit channel FIFO operates normally, but the output is discarded and replaced by zeroes. This bit does not affect the receive channel, data reception can occur normally. 35.4.1 I2S connection schemes I2S1 is automatically a slave to I2S0 if no external pins are selected for the I2S1 clock and data lines. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 786 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 35: LPC18xx I2S interface FT D R R A The MCLK can be provided by a master or used by the master to create the I2S CLK. MCLK can also be generated internally by the audio PLL through the CREG block (see Table 37). R A FT D R A D R A R A FT D R FT D R A F D R A FT D FT D R A A FT R A D FT Fig 108. I2S connections All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 787 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 35: LPC18xx I2S interface FT D R A D R A R A FT D R FT 35.5 Pin description D R R A FT D R R A F D R A FT A FT A FT Table 727. Pin description Pin name Direction Description D D R A FT D I2S0/1_RX_SCK Input/ Output Input/ Output Receive Clock. A clock signal used to synchronize the transfer of data on the receive channel. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S bus specification. Receive Word Select. Selects the channel from which data is to be received. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S bus specification. WS = 0 indicates that data is being received by channel 1 (left channel). WS = 1 indicates that data is being received by channel 2 (right channel). R A I2S0/1_RX_WS I2S0/1_RX_SDA I2S0/1_RX_MCLK I2S0/1_TX_SCK Input/ Output Output Input/ Output Input/ Output Receive Data. Serial data, received MSB first. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S bus specification. Optional master clock output for the I2S receive function. Transmit Clock. A clock signal used to synchronize the transfer of data on the transmit channel. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S bus specification. Transmit Word Select. Selects the channel to which data is being sent. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S bus specification. WS = 0 indicates that data is being sent to channel 1 (left channel). WS = 1 indicates that data is being sent to channel 2 (right channel). I2S0/1_TX_WS I2S0/1_TX_SDA IS0/1_TX_MCLK Input/ Output Output Transmit Data. Serial data, sent MSB first. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S bus specification. Optional master clock output for the I2S transmit function. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 788 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 35: LPC18xx I2S interface FT D R R A D R A R A FT D R FT D R A R A A SCK: serial clock TRANSMITTER (MASTER) WS: word select SD: serial data RECEIVER (SLAVE) TRANSMITTER (SLAVE) SCK: serial clock WS: word select SD: serial data FT D R R A FT D R A FT A F RECEIVER (MASTER) FT D FT D CONTROLLER (MASTER) SCK TRANSMITTER (SLAVE) WS SD RECEIVER (SLAVE) D R A SCK WS SD word n-1 right channel MSB word n left channel LSB MSB word n+1 right channel Fig 109. Simple I2S configurations and bus timing All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 789 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 35: LPC18xx I2S interface FT D R A D R A R A FT D R FT 35.6 Register description D R Table 728 shows the registers associated with the I2S interface and a summary of their functions. Following the table are details for each register. Reset value reflects the data stored in used bits only. It does not include reserved bits content. Table 728. Register overview: I2S0 (base address 0x400A 2000) Name Access Address offset Description Reset value R A FT D R R A F D R A FT D R A FT D R A A FT A FT D DAO DAI TXFIFO RXFIFO STATE DMA1 DMA2 IRQ TXRATE R/W R/W WO RO RO R/W R/W R/W R/W 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel. I2S Digital Audio Input Register. Contains control bits for the I2S receive channel. I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO. I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO. I2S Status Feedback Register. Contains status information about the I2S interface. I2S DMA Configuration Register 1. Contains control information for DMA request 1. I2S DMA Configuration Register 2. Contains control information for DMA request 2. I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated. 0x87E1 0x07E1 0 0 0x7 0 0 0 I2S Transmit MCLK divider. This register determines the I2S TX MCLK 0 rate by specifying the value to divide PCLK by in order to produce MCLK. I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK. I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock. 0 RXRATE R/W 0x024 TXBITRATE R/W 0x028 0 RXBITRATE R/W 0x02C I2S Receive bit rate divider. This register determines the I2S receive bit 0 rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock. I2S Transmit mode control. I2S Receive mode control. 0 0 TXMODE RXMODE R/W R/W 0x030 0x034 Table 729. Register overview: I2S1 (base address 0x400A 3000) Name Access Address offset Description Reset value DAO DAI TXFIFO RXFIFO R/W R/W WO RO 0x000 0x004 0x008 0x00C I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel. I2S Digital Audio Input Register. Contains control bits for the I2S receive channel. I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO. I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO. All information provided in this document is subject to legal disclaimers. 0x87E1 0x07E1 0 0 © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 790 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 35: LPC18xx I2S interface FT D R A D R A R A FT D R FT Table 729. Register overview: I2S1 (base address 0x400A 3000) Name Access Address offset Description D R R A FT D R R A F D R A Reset value A FT A STATE DMA1 DMA2 IRQ TXRATE RO R/W R/W R/W R/W 0x010 0x014 0x018 0x01C 0x020 I2S Status Feedback Register. Contains status information about the I2S interface. I2S DMA Configuration Register 1. Contains control information for DMA request 1. I2S DMA Configuration Register 2. Contains control information for DMA request 2. I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated. 0x7 0 0 0 FT D R A FT D R A FT D I2S Transmit MCLK divider. This register determines the I2S TX MCLK 0 rate by specifying the value to divide PCLK by in order to produce MCLK. I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK. I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock. 0 RXRATE R/W 0x024 TXBITRATE R/W 0x028 0 RXBITRATE R/W 0x02C I2S Receive bit rate divider. This register determines the I2S receive bit 0 rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock. I2S Transmit mode control. I2S Receive mode control. 0 0 TXMODE RXMODE R/W R/W 0x030 0x034 35.6.1 I2S Digital Audio Output register The DAO register controls the operation of the I2S transmit channel. The function of bits in DAO are shown in Table 730. Table 730. I2S Digital Audio Output register (DAO - address 0x400A 2000 (I2S0) and 0x400A 3000 (I2S1)) bit description Bit Symbol Value Description Reset value 1:0 WORDWIDTH 0x0 0x1 0x2 0x3 Selects the number of bytes in data as follows: 8-bit data 16-bit data Reserved, do not use this setting 32-bit data When 1, data is of monaural format. When 0, the data is in stereo format. When 1, disables accesses on FIFOs, places the transmit channel in mute mode. When 1, asynchronously resets the transmit channel and FIFO. When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 35.7.2 for a summary of useful combinations for this bit with TXMODE. 01 2 3 4 5 MONO STOP RESET WS_SEL 0 0 0 1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 791 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 35: LPC18xx I2S interface FT D R R A Table 730. I2S Digital Audio Output register (DAO - address 0x400A 2000 (I2S0) and 0x400A 3000 (I2S1)) bit description D R A R A FT D R FT D R A R A FT A F FT Bit Symbol Value Description Reset value D D R R A A FT FT 14:6 15 WS_HALFPERIOD MUTE Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31. When 1, the transmit channel sends only zeroes. 0x1F 1 D D R A FT D 31:16 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. R A 35.6.2 I2S Digital Audio Input register The DAI register controls the operation of the I2S receive channel. The function of bits in DAI are shown in Table 731. Table 731. I2S Digital Audio Input register (DAI - address 0x400A 2004 (I2S0) and 0x400A 3004 (I2S1)) bit description Bit Symbol Value Description Reset value 1:0 WORDWIDTH 0x0 0x1 0x2 0x3 Selects the number of bytes in data as follows: 8-bit data 16-bit data Reserved, do not use this setting 32-bit data When 1, data is of monaural format. When 0, the data is in stereo format. When 1, disables accesses on FIFOs, places the transmit channel in mute mode. When 1, asynchronously reset the transmit channel and FIFO. When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 35.7.2 for a summary of useful combinations for this bit with RXMODE. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 01 2 3 4 5 MONO STOP RESET WS_SEL 0 0 0 1 14:6 31:15 WS_HALFPERIOD - Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31. 0x1F - 35.6.3 I2S Transmit FIFO register The TXFIFO register provides access to the transmit FIFO. The function of bits in TXFIFO are shown in Table 732. Table 732. Transmit FIFO register (TXFIFO - address 0x400A 2008 (I2S0) and 0x400A 3008 (I2S1)) bit description Bit Symbol Description Reset value 31:0 I2STXFIFO 8 x 32-bit transmit FIFO. 0 35.6.4 Receive FIFO register The I2SRXFIFO register provides access to the receive FIFO. The function of bits in I2SRXFIFO are shown in Table 733. Table 733. I2S Receive FIFO register (RXFIFO - address 0x400A 200C (I2S0) and 0x400A 300C (I2S1)) bit description Bit Symbol Description Reset value 31:0 I2SRXFIFO 8 x 32-bit transmit FIFO. All information provided in this document is subject to legal disclaimers. 0 © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 792 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 35: LPC18xx I2S interface FT D R A D R A R A FT D R FT 35.6.5 I2S Status Feedback register D R The STATE register provides status information about the I2S interface. The meaning of bits in STATE are shown in Table 734. D R A FT Table 734. I2S Status Feedback register (STATE - address 0x400A 2010 (I2S0) and 0x400A 3010 (I2S1)) bit description Bit Symbol Description R A FT R A F D R A FT D R A FT D R A Reset value A FT D 0 IRQ This bit reflects the presence of Receive Interrupt or Transmit Interrupt. This is determined 1 by comparing the current FIFO levels to the rx_depth_irq and tx_depth_irq fields in the IRQ register. This bit reflects the presence of Receive or Transmit DMA Request 1. This is determined by 1 comparing the current FIFO levels to the rx_depth_dma1 and tx_depth_dma1 fields in the DMA1 register. This bit reflects the presence of Receive or Transmit DMA Request 2. This is determined by 1 comparing the current FIFO levels to the rx_depth_dma2 and tx_depth_dma2 fields in the DMA2 register. Reserved. Reflects the current level of the Receive FIFO. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Reflects the current level of the Transmit FIFO. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0 0 0 - 1 DMAREQ1 2 DMAREQ2 7:3 11:8 15:12 19:16 31:20 RX_LEVEL TX_LEVEL - 35.6.6 I2S DMA Configuration Register 1 The DMA1 register controls the operation of DMA request 1. The function of bits in DMA1 are shown in Table 735. Refer to Chapter 16 “LPC18xx General Purpose DMA (GPDMA) controller” for details of DMA operation. This register enables the DMA for the I2S receive and transmit channels and sets the FIFO level. Remark: The FIFOs contain eight 16-bit words. Therefore, if the I2S controller is configured for 32-bit mode (see Table 730 and Table 731), the maximum allowed FIFO level is 4. Table 735. I2S DMA Configuration register 1 (DMA1 - address 0x400A 2014 (I2S0) and 0x400A 3014 (I2S1)) bit description Bit Symbol Description Reset value 0 1 7:2 11:8 RX_DMA1_ENABLE TX_DMA1_ENABLE RX_DEPTH_DMA1 When 1, enables DMA1 for I2S receive. When 1, enables DMA1 for I2S transmit. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Set the FIFO level that triggers a receive DMA request on DMA1. 0 0 0 0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 793 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 35: LPC18xx I2S interface FT D R R A Table 735. I2S DMA Configuration register 1 (DMA1 - address 0x400A 2014 (I2S0) and 0x400A 3014 (I2S1)) bit description D R A R A FT D R FT D R A R A FT A F FT Bit Symbol Description Reset value D D R R A A FT FT 15:12 19:16 31:20 TX_DEPTH_DMA1 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Set the FIFO level that triggers a transmit DMA request on DMA1. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0 - D D R A FT D R A 35.6.7 I2S DMA Configuration Register 2 The DMA2 register controls the operation of DMA request 2. The function of bits in DMA2 are shown in Table 730. This register enables the DMA for the I2S receive and transmit channels and sets the FIFO level. Remark: The FIFOs contain eight 16-bit words. Therefore, if the I2S controller is configured for 32-bit mode (see Table 730 and Table 731), the maximum allowed FIFO level is 4. Table 736. I2S DMA Configuration register 2 (DMA2 - address 0x400A 2018 (I2S0) and 0x400A 3018 (I2S1)) bit description Bit Symbol Description Reset value 0 1 7:2 11:8 15:12 19:16 31:20 RX_DMA2_ENABLE TX_DMA2_ENABLE RX_DEPTH_DMA2 TX_DEPTH_DMA2 - When 1, enables DMA1 for I2S receive. When 1, enables DMA1 for I2S transmit. Reserved. Set the FIFO level that triggers a receive DMA request on DMA2. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Set the FIFO level that triggers a transmit DMA request on DMA2. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0 0 0 0 0 - 35.6.8 I2S Interrupt Request Control register The IRQ register controls the operation of the I2S interrupt request. The function of bits in IRQ are shown in Table 730. Table 737. I2S Interrupt Request Control register (IRQ - address 0x400A 201C (I2S0) and 0x400A 301C (I2S1)) bit description Bit Symbol Description Reset value 0 1 7:2 11:8 RX_IRQ_ENABLE TX_IRQ_ENABLE RX_DEPTH_IRQ When 1, enables I2S receive interrupt. When 1, enables I2S transmit interrupt. Reserved. Set the FIFO level on which to create an irq request. 0 0 0 0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 794 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 35: LPC18xx I2S interface FT D R R A Table 737. I2S Interrupt Request Control register (IRQ - address 0x400A 201C (I2S0) and 0x400A 301C (I2S1)) bit description D R A R A FT D R FT D R A R A FT A F FT Bit Symbol Description Reset value D D R R A A FT FT 15:12 19:16 31:20 TX_DEPTH_IRQ - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Set the FIFO level on which to create an irq request. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. D D R A FT D 0 R A 35.6.9 I2S Transmit Clock Rate register The MCLK rate for the I2S transmitter is determined by the values in the TXRATE register. The required TXRATE setting depends on the desired audio sample rate desired, the format (stereo/mono) used, and the data size. The transmitter MCLK rate is generated using a fractional rate generator, dividing down the frequency of PCLK_I2S ( = CLK_APB1_I2S). Values of the numerator (X) and the denominator (Y) must be chosen to produce a frequency twice that desired for the transmitter MCLK, which must be an integer multiple of the transmitter bit clock rate. Fractional rate generators have some aspects that the user should be aware of when choosing settings. These are discussed in Section 35.6.9.1. The equation for the fractional rate generator is: I2STXMCLK = PCLK_I2S * (X/Y) /2 Note: If the value of X or Y is 0, then no clock is generated. Also, the value of Y must be greater than or equal to X. Table 738. I2S Transmit Clock Rate register (TXRATE - address 0x400A 2020 (I2S0) and 0x400A 3020 (I2S1)) bit description Bit Symbol Description Reset value 7:0 Y_DIVIDER I2S transmit MCLK rate denominator. This value is used to divide PCLK to produce the 0 transmit MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock. I2S transmit MCLK rate numerator. This value is used to multiply PCLK by to produce the transmit MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0 15:8 X_DIVIDER 31:16 - - 35.6.9.1 Notes on fractional rate generators The nature of a fractional rate generator is that there will be some output jitter with some divide settings. This is because the fractional rate generator is a fully digital function, so output clock transitions are synchronous with the source clock, whereas a theoretical perfect fractional rate may have edges that are not related to the source clock. So, output jitter will not be greater than plus or minus one source clock between consecutive clock edges. For example, if X = 0x07 and Y = 0x11, the fractional rate generator will output 7 clocks for every 17 (11 hex) input clocks, distributed as evenly as it can. In this example, there is no way to distribute the output clocks in a perfectly even fashion, so some clocks will be All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 795 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 35: LPC18xx I2S interface FT D R R A longer than others. The output is divided by 2 in order to square it up, which also helps with the jitter. The frequency averages out to exactly (7/17) / 2, but some clocks will be a slightly different length than their neighbors. It is possible to avoid jitter entirely by choosing fractions such that X divides evenly into Y, such as 2/4, 2/6, 3/9, 1/N, etc. R A A FT D R A FT D R A R A FT D R FT D R A F R A FT D D FT R A D 35.6.10 I2S Receive Clock Rate register The MCLK rate for the I2S receiver is determined by the values in the RXRATE register. The required RXRATE setting depends on the peripheral clock rate (PCLK_I2S = CLK_APB1_I2S) and the desired MCLK rate (such as 256 fs). FT D R A The receiver MCLK rate is generated using a fractional rate generator, dividing down the frequency of PCLK_I2S. Values of the numerator (X) and the denominator (Y) must be chosen to produce a frequency twice that desired for the receiver MCLK, which must be an integer multiple of the receiver bit clock rate. Fractional rate generators have some aspects that the user should be aware of when choosing settings. These are discussed in Section 35.6.9.1. The equation for the fractional rate generator is: I2SRXMCLK = PCLK_I2S * (X/Y) /2 Note: If the value of X or Y is 0, then no clock is generated. Also, the value of Y must be greater than or equal to X. Table 739. I2S Receive Clock Rate register (RXRATE - address 0x400A 2024 (I2S0) and 0x400A 3024 (I2S1)) bit description Bit Symbol Description Reset value 7:0 Y_DIVIDER I2S receive MCLK rate denominator. This value is used to divide PCLK to produce the 0 receive MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock. I2S receive MCLK rate numerator. This value is used to multiply PCLK by to produce the receive MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0 15:8 X_DIVIDER 31:16 - - 35.6.11 I2S Transmit Clock Bit Rate register The bit rate for the I2S transmitter is determined by the value of the TXBITRATE register. The value depends on the audio sample rate desired, and the data size and format (stereo/mono) used. For example, a 48 kHz sample rate for 16-bit stereo data requires a bit rate of 48,000´16´2 = 1.536 MHz. Table 740. I2S Transmit Clock Rate register (TXBITRATE - address 0x400A 2028 (I2S0) and 0x400A 3028 (I2S1)) bit description Bit Symbol Description Reset value 5:0 31:6 TX_BITRATE - I2S transmit bit rate. This value plus one is used to divide TX_MCLK to produce the transmit bit clock. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0 - All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 796 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 35: LPC18xx I2S interface FT D R A D R A R A FT D R FT 35.6.12 I2S Receive Clock Bit Rate register D R The bit rate for the I2S receiver is determined by the value of the RXBITRATE register. The value depends on the audio sample rate, as well as the data size and format used. The calculation is the same as for RXBITRATE. D R A FT Table 741. I2S Receive Clock Rate register (RXBITRATE - address 0x400A 202C (I2S0) and 0x400A 302C (I2S1)) bit description Bit Symbol Description Reset value R A FT R A F D R A FT D R A FT D R A A FT D 5:0 31:6 RX_BITR ATE - I2S receive bit rate. This value plus one is used to divide RX_MCLK to produce the receive bit 0 clock. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - 35.6.13 I2S Transmit Mode Control register The Transmit Mode Control register contains additional controls for transmit clock source, enabling the 4-pin mode, and how MCLK is used. See Section 35.7.2 for a summary of useful mode combinations. Table 742. I2S Transmit Mode Control register (TXMODE - address 0x400A 2030 (I2S0) and 0x400A 3030 (I2S1)) bit description Bit Symbol Value Description Reset value 1:0 TXCLKSEL 0x0 0x1 0x2 0x3 Clock source selection for the transmit bit clock divider. Select the TX fractional rate divider clock output as the source Reserved Select the RX_MCLK signal as the TX_MCLK clock source Reserved Transmit 4-pin mode selection. When 1, enables 4-pin mode. 0 2 3 31:4 TX4PIN TXMCENA - 0 Enable for the TX_MCLK output. When 0, output of TX_MCLK is not enabled. When 1, 0 output of TX_MCLK is enabled. Reserved, user software should not write ones to reserved bits. The value read from a NA reserved bit is not defined. 35.6.14 I2S Receive Mode Control register The Receive Mode Control register contains additional controls for receive clock source, enabling the 4-pin mode, and how MCLK is used. See Section 35.7.2 for a summary of useful mode combinations. Table 743. I2S Receive Mode Control register (RXMODE - address 0x400A 2034 (I2S0) and 0x400A 3034 (I2S1)) bit description Bit Symbol Value Description Reset value 1:0 RXCLKSEL 0x0 0x1 0x2 0x3 Clock source selection for the receive bit clock divider. Select the RX fractional rate divider clock output as the source Reserved Select the TX_MCLK signal as the RX_MCLK clock source Reserved All information provided in this document is subject to legal disclaimers. 0 © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 797 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 35: LPC18xx I2S interface FT D R R A Table 743. I2S Receive Mode Control register (RXMODE - address 0x400A 2034 (I2S0) and 0x400A 3034 (I2S1)) bit description D R A R A FT D R FT D R A R A A FT F FT Bit Symbol Value Description Reset value D D R R A A FT FT 2 3 31:4 RX4PIN RXMCENA - Receive 4-pin mode selection. When 1, enables 4-pin mode. 0 D D R A FT D Enable for the RX_MCLK output. When 0, output of RX_MCLK is not enabled. When 1, 0 output of RX_MCLK is enabled. Reserved, user software should not write ones to reserved bits. The value read from a NA reserved bit is not defined. R A 35.7 Functional description 35.7.1 I2S transmit and receive interfaces The I2S interface can transmit and receive 8-bit, 16-bit or 32-bit stereo or mono audio information. Some details of I2S implementation are: • When the FIFO is empty, the transmit channel will repeat transmitting the same data until new data is written to the FIFO. • When mute is true, the data value 0 is transmitted. • When mono is false, two successive data words are respectively left and right data. • Data word length is determined by the wordwidth value in the configuration register. There is a separate wordwidth value for the receive channel and the transmit channel. – 0: word is considered to contain four 8-bit data words. – 1: word is considered to contain two 16-bit data words. – 3: word is considered to contain one 32-bit data word. • When the transmit FIFO contains insufficient data the transmit channel will repeat transmitting the last data until new data is available. This can occur when the microprocessor or the DMA at some time is unable to provide new data fast enough. Because of this delay in new data there is a need to fill the gap, which is accomplished by continuing to transmit the last sample. The data is not muted as this would produce an noticeable and undesirable effect in the sound. • The transmit channel and the receive channel only handle 32-bit aligned words, data chunks must be clipped or extended to a multiple of 32 bits. When switching between data width or modes the I2S must be reset via the reset bit in the control register in order to ensure correct synchronization. It is advisable to set the stop bit also until sufficient data has been written in the transmit FIFO. Note that when stopped data output is muted. All data accesses to FIFOs are 32 bits. Figure 122 shows the possible data sequences. A data sample in the FIFO consists of: • 1´32 bits in 8-bit or 16-bit stereo modes. • 1´32 bits in mono modes. • 2´32 bits, first left data, second right data, in 32-bit stereo modes. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 798 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 35: LPC18xx I2S interface FT D R R A Data is read from the transmit FIFO after the falling edge of WS, it will be transferred to the transmit clock domain after the rising edge of WS. On the next falling edge of WS the left data will be loaded in the shift register and transmitted and on the following rising edge of WS the right data is loaded and transmitted. R A A FT D R A FT D The receive channel will start receiving data after a change of WS. When word select becomes low it expects this data to be left data, when WS is high received data is expected to be right data. Reception will stop when the bit counter has reached the limit set by wordwidth. On the next change of WS the received data will be stored in the appropriate hold register. When complete data is available it will be written into the receive FIFO. D R A R A FT D R FT D R A F R A FT D FT D R A D FT R A 35.7.2 I2S operating modes The clocking and WS usage of the I2S interface is configurable. In addition to master and slave modes, which are independently configurable for the transmitter and the receiver, several different clock sources are possible, including variations that share the clock and/or WS between the transmitter and receiver. This last option allows using I2S with fewer pins, typically four. Many configurations are possible that are not considered useful, the following tables and figures give details of the configurations that are most likely to be useful. Table 744. I2S transmit modes DAO bit TXMODE 5 bits [3:0] Description 0 0000 Typical transmitter master mode. See Figure 110. The I2S transmit function operates as a master. The transmit clock source is the fractional rate divider. The WS used is the internally generated TX_WS. The TX_MCLK pin is not enabled for output. 0 0010 Transmitter master mode sharing the receiver reference clock. See Figure 111. The I2S transmit function operates as a master. The transmit clock source is RX_REF. The WS used is the internally generated TX_WS. The TX_MCLK pin is not enabled for output. 0 0100 4-wire transmitter master mode sharing the receiver bit clock and WS. See Figure 112. The I2S transmit function operates as a master. The transmit clock source is the RX bit clock. The WS used is the internally generated RX_WS. The TX_MCLK pin is not enabled for output. 0 1000 Transmitter master mode with TX_MCLK output. See Figure 110. The I2S transmit function operates as a master. The transmit clock source is the fractional rate divider. The WS used is the internally generated TX_WS. The TX_MCLK pin is enabled for output. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 799 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 35: LPC18xx I2S interface FT D R A D R A R A FT D R FT Table 744. I2S transmit modes DAO bit TXMODE 5 bits [3:0] Description D R R A FT D R R A F D R A A FT A 1 0000 Typical transmitter slave mode. See Figure 113. The I2S transmit function operates as a slave. The transmit clock source is the TX_SCK pin. The WS used is the TX_WS pin. FT D R A FT D R A FT D 1 0010 Transmitter slave mode sharing the receiver reference clock. See Figure 114. The I2S transmit function operates as a slave. The transmit clock source is RX_REF. The WS used is the TX_WS pin. 1 0100 4-wire transmitter slave mode sharing the receiver bit clock and WS. See Figure 115. The I2S transmit function operates as a slave. The transmit clock source is the RX bit clock. The WS used is RX_WS ref. I2STXMODE[3] (Pin OE) I2STX_RATE[15:8] I2STX_RATE[7:0] X CCLK Y I2STXBITRATE[5:0] TX_REF I2S_TX_SCK I2 S peripheral block (transmit ) I2S_TX_SDA I2S_TX_WS 8-bit Fractional Rate Divider ÷2 ÷N (1 to 64) TX bit clock TX_WS ref Fig 110. Typical transmitter master mode, with or without MCLK output I2S_TX_SCK I2STXBITRATE[5:0] RX_REF ÷N (1 to 64) TX bit clock I2S peripheral block (transmit ) I2S_TX_SDA I2S_TX_WS TX_WS ref Fig 111. Transmitter master mode sharing the receiver reference clock All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 800 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 35: LPC18xx I2S interface FT D R R A D R A I2S_TX_SCK I2S peripheral block (transmit ) RX_WS ref R A FT D R FT D R A R A FT FT D R A FT D A F R A FT RX bit clock I2S_TX_SDA D D R A FT D R A Fig 112. 4-wire transmitter master mode sharing the receiver bit clock and WS I2S_TX_SCK I2STXBITRATE[5:0] TX_REF ÷N (1 to 64) TX bit clock I2S peripheral block (transmit ) I2S_TX_SDA I2S_TX_WS Fig 113. Typical transmitter slave mode I2STXBITRATE[5:0] RX_REF ÷N (1 to 64) TX bit clock I2S peripheral block (transmit ) I2S_TX_SDA I2S_TX_WS Fig 114. Transmitter slave mode sharing the receiver reference clock RX bit clock I2S peripheral block (transmit ) RX_WS ref I2S_TX_SDA Fig 115. 4-wire transmitter slave mode sharing the receiver bit clock and WS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 801 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 35: LPC18xx I2S interface FT D R A D R A R A FT D R FT D Table 745. I2S receive modes DAI bit 5 RXMODE bit Description [3:0] R R A FT D R R A F D R A A FT A 0 0000 Typical receiver master mode. See Figure 116. The I2S receive function operates as a master. The receive clock source is the fractional rate divider. The WS used is the internally generated RX_WS. The RX_MCLK pin is not enabled for output. FT D R A FT D R A FT D 0 0010 Receiver master mode sharing the transmitter reference clock. See Figure 117. The I2S receive function operates as a master. The receive clock source is TX_REF. The WS used is the internally generated RX_WS. The RX_MCLK pin is not enabled for output. 0 0100 4-wire receiver master mode sharing the transmitter bit clock and WS. See Figure 118. The I2S receive function operates as a master. The receive clock source is the TX bit clock. The WS used is the internally generated TX_WS. The RX_MCLK pin is not enabled for output. 0 1000 Receiver master mode with RX_MCLK output. See Figure 116. The I2S receive function operates as a master. The receive clock source is the fractional rate divider. The WS used is the internally generated RX_WS. The RX_MCLK pin is enabled for output. 1 0000 Typical receiver slave mode. See Figure 119. The I2S receive function operates as a slave. The receive clock source is the RX_SCK pin. The WS used is the RX_WS pin. 1 0010 Receiver slave mode sharing the transmitter reference clock. See Figure 120. The I2S receive function operates as a slave. The receive clock source is TX_REF. The WS used is the RX_WS pin. 1 0100 This is a 4-wire receiver slave mode sharing the transmitter bit clock and WS. See Figure 121. The I2S receive function operates as a slave. The receive clock source is the TX bit clock. The WS used is TX_WS ref. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 802 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 35: LPC18xx I2S interface FT D R R A D R A I2SRXMODE[3] R A FT D R FT D R A R A FT FT D R A A (Pin OE) F R D A FT FT D I2S_RX_MCLK I2SRX_RATE[15:8] I2SRX_RATE[7:0] X CCLK Y I2SRXBITRATE[5:0] RX_REF D R A I2S_RX_SCK I2 S peripheral block (receive ) RX_WS ref FT D R A 8-bit Fractional Rate Divider ÷2 ÷N (1 to 64) RX bit clock I2S_RX_SDA I2S_RX_WS Fig 116. Typical receiver master mode, with or without MCLK output I2S_RX_SCK I2SRXBITRATE[5:0] TX_REF ÷N (1 to 64) RX bit clock I2S peripheral block (receive) I2S_RX_SDA I2S_RX_WS RX_WS ref Fig 117. Receiver master mode sharing the transmitter reference clock I2S_RX_SCK I2S peripheral block (receive) TX_WS ref TX bit clock I2S_RX_SDA Fig 118. 4-wire receiver master mode sharing the transmitter bit clock and WS I2S_RX_SCK I2SRXBITRATE[5:0] RX_REF ÷N (1 to 64) RX bit clock I2S peripheral block (receive) I2S_RX_SDA I2S_RX_WS Fig 119. Typical receiver slave mode All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. User manual Rev. 00.13 — 20 July 2011 803 of 1164 D R A FT D R A FT NXP Semiconductors UM10430 FT FT D D R R A A FT FT D D R R A A FT FT D D D R A D R A D D R A FT Chapter 35: LPC18xx I2S interface FT D R R A D R A R A FT D R FT D R A R A FT A I2SRXBITRATE[5:0] TX_REF F FT D D ÷N (1 to 64) RX bit clock I2S peripheral block (receive) R R I2S_RX_SDA I2S_RX_WS A A FT D R A FT D FT D R A Fig 120. Receiver slave mode sharing the transmitter reference clock TX bit clock I2S peripheral block (receive) TX_WS ref I2S_RX_SDA Fig 121. 4-wire receiver slave mode sharing the transmitter bit clock and WS 35.7.3 FIFO controller Handling of data for transmission and reception is performed via the FIFO controller which can generate two DMA requests and an interrupt request. The controller consists of a set of comparators which compare FIFO levels with depth settings contained in registers. The current status of the level comparators can be seen in the APB status register. Table 746. Conditions for FIFO level comparison Level Comparison Condition dmareq_tx_1 dmareq_rx_1 dmareq_tx_2 dmareq_rx_2 irq_tx irq_rx tx_depth_dma1 >= tx_level rx_depth_dma1 = tx_level rx_depth_dma2 = tx_level rx_depth_irq