PAS302BCW-22S

PAS302BCW-22S CMOS Image Sensor IC PAS302BCW-22S CMOS VGA DIGITAL IMAGE SENSOR General Description The PAS302BCW-22S is a highly integrated CMOS active-pixel image sensor that has a VGA resolution of 644H x 484V. The PAS302BCW-22S outputs 8-bit RGB raw data through a parallel data bus and is available in 22-pin CSP package. The PAS302BCW-22S can be programmed to set the exposure time for different luminance condition via I 2 CTM serial control bus. By programming the internal register sets, it can perform on-chip frame rate adjustment, offset correction DAC and programmable gain control. Features VGA(644 x 484 pixels) resolution, ~1/4” Lens Bayer-RGB color filter array Output format: 8-bit parallel RGB raw data On-chip 10-bit pipelined A/D converter On-chip programmable gain amplifier 4-bit color gain amplifier (x1~x2) 4-bit global gain amplifier (x1~x2) Digital gain stage Continuous variable frame time(1/2sec~1/30sec) Continuous variable exposure time IC 2 TM Key Specification Supply Voltage Resolution Array diagonal Pixel Size Chief Ray Angle Frame rate System clock Pixel clock Sensitivity Color filter Exposure Time Scan Mode S/N Ratio 2.5V ~ 3.3V 644(H) x 484(V) 4.5mm (~1/4”Optic) 5.6µmx5.6µm 20∘ ~ 22∘ ~30 fps Up to 48 MHz Up to 12MHz 1.56 V/Lux-Sec RGB Bayer Pattern ~ Frame time to Line time Progressive > 45 dB Interface Support flash light timing Single 2.5V / 3.3V supply voltage < 15mA(~30 fps) power dissipation 2µA power dissipation when power down mode Window-Of-Interest (WOI) Sub-sampling Defect compensation Pin-to-pin compatible to OV7648 Note1: Only two decoupling capacitors needed Note2: Good sensitivity compared to competitors Package 22-pin lead-free CSP Version 2.4, 20 Sep. 2005 E-mail: fae_service@pixart.com.tw PixArt Imaging Inc. 1 PAS302BCW-22S CMOS Image Sensor IC 1. Pin Assignment PX7 PX9 RESET VDDQ HSYNC 15 PX8 13 VSSD 11 SYSCLK 9 PXCLK 7 VSYNC 14 PX6 12 10 -- Top View -- 8 6 VDDD 16 PX5 PAS302BCW-22S PX3 SCL VDDA 5 VREF 17 PX4 19 PX2 21 SDA 2 VSSA 4 PWDN 18 20 22 1 3 Figure 1.1. PAS302BCW-22S pin assignment Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Name VSSA VDDA PWDN VREF VDDD VSYNC HSYNC PXCLK VDDQ SYSCLK RESET VSSD PX9 PX8 PX7 PX6 PX5 PX4 PX3 PX2 SCL SDA Type GND PWR IN IN PWR OUT OUT OUT PWR IN IN GND OUT OUT OUT OUT OUT OUT OUT OUT IN I/O Description Analog ground Analog VDD. Power Down (chip power down when high) Internal voltage reference Digital VDD. Vertical synchronization signal Horizontal synchronization signal Pixel clock output Sensor VDD, 2.5V ~ 3.3V Master clock input Resets all registers to their default values (chip reset when high) Digital ground Digital data out Digital data out Digital data out Digital data out Digital data out Digital data out Digital data out Digital data out I 2 CTM clock. I 2 CTM data. Internal pull high resister is 10KΩ. Version 2.4, 20 Sep. 2005 E-mail: fae_service@pixart.com.tw PixArt Imaging Inc. 2 PAS302BCW-22S CMOS Image Sensor IC 2. Block Diagram Front Gain Color Gain CG Global Gain GG The PAS302BCW-22S is a 1/4” CMOS imaging sensor with 644x488 physical pixels. The active region of sensor array is 644x484 as shown in Fig. 2.1. The sensor array is covered with Bayer pattern color filters and micro-lens. The first pixel location is programmable in 2 direction (X and Y) and the default value is at the left-down side of sensor array. After a programmable exposure time, the signals of image are sampled first with CDS (Correlated Double Sampling) block to improve S/N ratio and reduce fixed pattern noise. Three analog gain stages are implemented before signals are transferred to 10-Bit ADC. The front gain stage (FG) can be programmed to fit the saturation level of sensor to the full-range input of ADC. The programmable color gain stage (CG) is used to balance the luminance response difference between B, G and R color. The global gain stage (GG) is programmed to adapt the gain to the image luminance. After three gain stages, the signals will be digitized by the on-chip 10-Bit ADC. After the image data have been digitized, further adjustment to the signal can be applied before the data is output to next stage. Version 2.4, 20 Sep. 2005 E-mail: fae_service@pixart.com.tw Row Decoder SCL Sensor Array 644x484 FG 10-Bit A/D DAC2 3-Bit x2 ~ x4 DAC1 4-Bit x1 ~ x2 4-Bit x1 ~ x2 CDS Column Decoder Timing Generator & Control Logic Companding Digital Gain Stage Defect Compensation PX(9 : 2) SDA SYSCLK Figure 2.1. PAS302BCW-22S sensor block diagram VSYNC HSYNC PXCLK PixArt Imaging Inc. 3 PAS302BCW-22S CMOS Image Sensor IC 3. Function Description 3.1 Defect Compensation The Defect Compensation block can detect the possible defect pixel and replace it with average output of like-colored pixels from near side of defect pixel. There is no limitation capability of defect pixel number. This function can be programmed to enable/disable by user. 3.2 Companding Curves The companding function which means compressing and expanding is used to simulate the gamma curve and do non-linear transformation before the data is output. There are 4 curves selected by setting Register Compand_Sel as shown in Fig. 3.1. This function can be programmed to enable/disable by user. O/P ( 10-Bit) 11,1111,1111 3 2 1 0 without companding 00,0xxx,xxxx 00,1xxx,xxxx 010 011 10,xxxx,xxxx 11,xxxx,xxxx I/P ( 10-Bit) Figure 3.1 Companding curves programmed by Compand_EnH and Compand_Sel. 3.3 Power Down Mode The PAS302BCW-22S can be powered down by setting register “Sw_PwrDn” = 1 or by enable Pwdn pin. The register value will sustain in the power down mode. PAS302BCW-22S supports 2 power down modes: Software power down：Set register “Sw_PwrDn” = 1 to power down all the internal block except I 2 CTM . Hardware power down：Pull Pwdn pin to high to power down the chip. The chip will go into standby mode. 3.4 Reset Mode The PAS302BCW-22S can be reseted by setting register “Sw_Reset” = 1 or by enable Reset pin. PAS302BCW-22S supports 2 reset modes: Software reset：Set register “Sw_Reset” = 1 to reset all the I 2 CTM registers. Hardware reset：Pull Reset pin to high to reset the full chip. Version 2.4, 20 Sep. 2005 E-mail: fae_service@pixart.com.tw PixArt Imaging Inc. 4 PAS302BCW-22S CMOS Image Sensor IC 4. Output Format 4.1 Physical Sensor Array 644 - Column Dark Line Dark Line Dark Line Dark Line GRGRGRGR BGBGBGBG GRGRGRGR GRGRGRGR BGBGBGBG GRGRGRGR 488 - Row 644 X 484 Active Pixels BGBGBGBG GRGRGRGR BGBGBGBG BGBGBGBG GRGRGRGR BGBGBGBG Figure 4.1 Physical Sensor Array Version 2.4, 20 Sep. 2005 E-mail: fae_service@pixart.com.tw PixArt Imaging Inc. 5 PAS302BCW-22S CMOS Image Sensor IC 4.2 Output Timing VGA mode ( 644 x 488 ) pixel readout: H_Start[9:0] = 0, V_Start[8:0] = 0, Nov_By2[7:0] = 87, H_Size[9:0] = 643, V_Size[8:0]= 487, NovSize = Nov_By2 *2 +1 = 175 Pixclks( default ) Line-time = NovSize + 644 = 819 Pixclks( default ) Hsync GRGR NovSize Pixclk B GB G Valid pixel = 644 Pixclks B GBG GRGR Figure 4.2 Inter-line timing ( default ) If Mask_Dark[3] = 0, Frame Time = LPF + 1 = 488 Line ( default ) Vsync Hsync Dark Dark Dark Dark Dark Dark Line = 4 Line Valid Line = 484 Line Figure 4.3 Inter-frame timing (LPF default setting = 487, Mask_Dark[3] =0) If Mask_Dark[3] = 1, Frame Time = LPF + 1 = 488 Line ( default ) Vsync Hsync Dark Line = 4 Line Valid Line = 484 Line Figure 4.4 Inter-frame timing (LPF default setting = 487, Mask_Dark[3] =1) 4.3 Hardware Windowing Users are allowed to define window size as well as window location in PAS302BCW-22S, Window size can range from 20x14 to 644x484. The location of window can be anywhere in the sensor array. Window location and size is defined by register H_Start, V_Start, H_Size and V_Size; the H_Start defines the starting column while V_Start defines the starting row of the window; the H_Size define the column width of the window and V_Start define the row depth of the window. 4.4 Sub-sampling PAS302BCW-22S can be programmed to output image in QVGA and QQVGA size by setting Registers Skip_Digital or Skip_Analog. In QVGA sub-sampling mode, both vertical and horizontal pixels are sub-sampling at 1/2, while in QQVGA sub-sampling mode, both vertical and horizontal pixels are sub-sampling at 1/4. The maximum sub-sampling rate is 1/16. Version 2.4, 20 Sep. 2005 E-mail: fae_service@pixart.com.tw PixArt Imaging Inc. 6 PAS302BCW-22S CMOS Image Sensor IC 5. I 2 CTM Bus PAS302BCW-22S supports I 2 CTM bus transfer protocol and acts as slave device. The 7 bits unique slave address is 1000000 and the bus supports receiving / transmitting speed up to 400kHz. 5.1 I 2 CTM Bus Overview There are only two lines SDA (serial data) and SCL (serial clock) carry information between the devices which are connected by I 2 CTM bus. Normally both SDA and SCL lines are open collector structure and pulled high by external pull-up resistors. Only the master can initiate a transfer (start), generate clock signals, and terminate a transfer (stop). Start Condition : A high to low transition of the SDA line while SCL is high defines a start condition. Stop Condition : A low to high transition of the SDA line while SCL is high defines a stop condition. Valid Data: The data on the SDA line must be stable during the high period of the SCL clock. Within each byte, MSB is always transferred first. Read/write control bit is the LSB of the first byte. Both the master and slave can transmit and receive data from the bus. Acknowledge : The receiving device should pull down the SDA line during high period of the SCL clock line when a byte was transferred completely by transmitter. When in the case of that a master received data from a slave, the master does not generate an acknowledgment on the last byte to indicate the end of a master read cycle. SDA SCL S Start Condition P Stop Condition Figure 5-1: Start and Stop Conditions SDA DATA STABLE DATA CHANGE ALLOWED SCL Figure 5-2: Valid Data Version 2.4, 20 Sep. 2005 E-mail: fae_service@pixart.com.tw PixArt Imaging Inc. 7 PAS302BCW-22S CMOS Image Sensor IC 5.2 Data Transfer Format 5.2.1 Master transmits data to slave (write cycle) S : Start A : Acknowledge by slave P : Stop RW : The LSB of 1st byte to decide whether current cycle is read or write cycle. If RW=1 that means read cycle, if RW=0 that means write cycle. SUBADDRESS : The address values of PAS302BCW-22S internal control registers (Please refer to PAS302BCW-22S register description) 1ST BYTE 2ND BYTE n BYTEs + A S SLAVE ID (7 BIT) RW A SUBADDRESS (8 BIT) A DATA A DATA A P MSB LSB=0 During the write cycle, the master generates start condition and then places the 1st byte data that combined slave address (7 bits) with a read/write control bit on SDA line. After slave(PAS302BCW-22S) issues acknowledgment, the master places 2nd byte (sub-address) data on SDA line. And then following the slave’s( PAS302BCW-22S) acknowledgment, the master places the 8 bits data on SDA line and transmit to PAS302BCW-22S control register (address was assigned by 2nd byte). After PAS302BCW-22S issue acknowledgment, the master can generate a stop condition to end this write cycle. In the condition of multi-byte write, the PAS302BCW-22S sub-address will be increased automatically after each DATA byte has been transferred. The Data and A cycles are repeated until last byte write. Every control registers value inside PAS302BCW-22S can be programming via this way. (Please refer to Figure 5.3.) 5.2.2 Slave transmits data to master (read cycle) The sub-address was assigned by previous write cycle The sub-address is automatically increased after each byte read Am : Acknowledged by master Note: there is no acknowledgment from master after last byte read 1ST BYTE SLAVE ADDRESS (7 BITS) 2ND BYTE n BYTE S RW A DATA (8 BIT) Am DATA Am DATA 1 P NO ACK IN LAST BYTE During read cycle, the master generates start condition and then place the 1st byte data that combine slave address (7 bits) with a read/write control bit to SDA line. After slave issue acknowledgment, 8 bits DATA was placed on SDA line by PAS302BCW-22S. The 8 bit data was read from PAS302BCW-22S internal control register that address was assigned by previous write cycle. Following the master acknowledgment, the PAS302BCW-22S place the next 8 bits data (address is increased automatically) on SDA line and then transfer to master serially. The Version 2.4, 20 Sep. 2005 E-mail: fae_service@pixart.com.tw PixArt Imaging Inc. 8 PAS302BCW-22S CMOS Image Sensor IC DATA and Am cycles are repeated until the last byte read. After last byte read, Am is no longer generated by master but instead of keeping SDA line as high. The slave (PAS302BCW-22S) must releases SDA line back to master to generate STOP condition. (Please refer to Figure 5.3.) SDA SCL 1-7 S Start Condition Address R/W ACK from Receiver Data ACK from Receiver Data 8 9 1-7 8 9 1-7 8 9 P Stop ACK from Condition Receiver Figure 5.3 Data Transfer Format 5.3 I 2 CTM Bus Timing SDA tf tLOW SCL S tHD;STA tHD;DAT tSU;STA Sr tSU;STO P S tr tSU;DAT tf tHD;STA tSP tr tBUF tHIGH Figure 5.4 I 2 CTM Bus Timing 5.4 I 2 CTM Bus Timing Specification PARAMETER SCL clock frequency Hold time (repeated) START condition. After this period, the first clock pulse is generated. Low period of the SCL clock HIGH period of the SCL clock Set-up time for a repeated START condition Data hold time. For I 2 CTM bus device Data set-up time Rise time of both SDA and SCL signals(note) Fall time of both SDA and SCL signals(note) Set-up time for STOP condition Bus free time between a STOP and START Capacitive load for each bus line Version 2.4, 20 Sep. 2005 E-mail: fae_service@pixart.com.tw STANDARD-MODE SYMBOL UNIT kHz µs µs µs µs µs ns ns ns µs µs pF 9 fscl tHD:STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tr tf tSU;STO tBUF Cb MIN. 10 4.0 4.7 0.75 4.7 0 250 30 30 4.0 4.7 1 MAX. 400 3.45 N.D. N.D. 15 PixArt Imaging Inc. PAS302BCW-22S Noise margin at LOW level for each VnL connected device (including hysteresis) Noise margin at HIGH level for each VnH connected device (including hysteresis) Note: It depends on the "high" period time of SCL. 0.1 VDD 0.2 VDD CMOS Image Sensor IC - V V Version 2.4, 20 Sep. 2005 E-mail: fae_service@pixart.com.tw PixArt Imaging Inc. 10 PAS302BCW-22S CMOS Image Sensor IC 6. Electrical Characteristics Absolute Maximum Ratings Ambient Storage Temperature VDDD Supply Voltages ( with respect to Ground ) VDDA VDDMA VDDQ All Input / Output Voltages ( with respect to Ground ) Lead Temperature, Surface-mount process ESD Rating, Human Body model DC Electrical Characteristics ( VDD = 2.5V ± 4% , Ta = 0℃ ~ 70℃ ) Symbol Parameter Min. Typ. Type :PWR VDDA VDDD VDDQ IDD DC Supply voltage – Analog DC Supply voltage – Digital DC Supply voltage – I/O Operating Current 2.4 2.4 2.4 2.5 2.5 15 2 0.7 x VDDQ 0.3 x VDDQ 10 0.9 x VDDQ 0.1 x VDDQ Min. Typ. Max. 48 12 2.6 2.6 3.3 V V V mA µA V V pF V V -40℃ ~ +125℃ 3V 3V 4V 4V -0.3V to VDDQ + 1V +230℃ 2000V Max. Unit IPWDN Power Down current Type :IN & I/O Reset and SYSCLK VIH VIL CIN VOH VOL Input voltage HIGH Input voltage LOW Input capacitor Output voltage HIGH Output voltage LOW Type : OUT & I/O for PXD0:7, PXCK, H/VSYNC & SDA, load 10pf, 1.2kΩ,2.5volts AC Operating Condition Symbol Parameter SYSCLK PXCK Master clock frequency Pixel clock output frequency Unit MHz MHz Sensor Characteristics Parameter Sensitivity Signal to Noise Ratio Dynamic Range Temperature Range Operation Stable Image Typ. 1.56 > 45 60 -10 ~ 70 Unit V/Lux-Sec dB dB ℃ Note 0 ~ 50 Version 2.4, 20 Sep. 2005 E-mail: fae_service@pixart.com.tw PixArt Imaging Inc. 11 PAS302BCW-22S VDDQ PXCLK HSYNC VSYNC VREF Version 2.4, 20 Sep. 2005 C2 JP1 9 8 7 6 5 4 VREF VDDQ PXCLK SY SCLK PWDN VDDA VSSA SDA SCL PX5 PX4 PX3 PX2 21 SCL 22 SDA 1 2 0.1U PWDN 3 C1 HSYNC VSYNC VDDD PX7 15 16 PX6 17 18 19 20 PX7 PX6 PX5 PX4 PX3 PX2 E-mail: fae_service@pixart.com.tw 0.1U PX8 PX6 PX4 PX2 PX9 PX7 PX5 VDDQ PX3 PXCLK HSY NC SCL RESET 7. Reference Circuit Schematic U1 VSY NC SY SCLK SDA 10 SY SCLK PWDN RESET 11 RESET 1 3 5 7 9 11 13 15 17 19 21 2 4 6 8 10 12 14 16 18 20 22 SENSOR BOARD INTERFACE 12 VSSD PX9 13 PAS302BCW PX9 PixArt Imaging Inc. PX8 14 PX8 Notes: VDDQ is 2.5V to 3.3V sensor power. C1 should close to sensor VDDA and AGND. C2 should close to sensor VREF and AGND. CMOS Image Sensor IC 12 PAS302BCW-22S CMOS Image Sensor IC 8. Package Specification Dimensions Package Body Dimension X Package Body Dimension Y Package Height Ball Height Package Body Thickness Thickness of Glass surface to wafer Ball Diameter Pin Pitch X axis Pin Pitch Y axis Edge to Pin Center Distance along X Edge to Pin Center Distance along Y Symbol A B C C1 C2 C3 D J1 J2 S1 S2 Min. 4310 4130 740 130 605 395 270 537.5 447.5 Typ. 4335 4155 800 160 640 415 300 800 800 567.5 477.5 Max. 4360 4180 860 190 675 435 330 597.5 507.5 Unit µm µm µm µm µm µm µm µm µm µm µm Version 2.4, 20 Sep. 2005 E-mail: fae_service@pixart.com.tw PixArt Imaging Inc. 13 PAS302BCW-22S CMOS Image Sensor IC 9. Recommended Lens and Holder Version 2.4, 20 Sep. 2005 E-mail: fae_service@pixart.com.tw PixArt Imaging Inc. 14 PAS302BCW-22S CMOS Image Sensor IC Version 2.4, 20 Sep. 2005 E-mail: fae_service@pixart.com.tw PixArt Imaging Inc. 15