P500-15DC

( Preliminary) PLL500-15/16 L ow Phase Noise VCXO (1MHz to 18MHz) F EATURES • • • • • • • • • • • V CXO with Divider Selection (DIVSEL) input pin • P LL500-15: ÷8, ÷16 • P LL500-16: ÷2, ÷4 V CXO output for the 1MHz to 18MHz range 1 6MHz to 36MHz fundamental crystal input. L ow phase noise (-130 dBc @ 10kHz offset using a 35.328MHz crystal). C MOS output with OE tri-state control. I ntegrated high linearity variable capacitors. 1 2mA drive capability at TTL output. ± 1 50 ppm pull range, max 5% linearity. L ow jitter (RMS): 2.5ps period jitter. 2 .5V to 3.3V operation. A vailable in 8-Pin SOIC, 6-pin SOT23 G REEN / RoHS compliant packages, or DIE. P IN CONFIGURATION XIN VCON DIVSEL^ GND 1 2 3 4 8 7 6 5 XOUT OE^ VDD CLK SOIC-8 PLL500-15/16 P500-15/16 1 2 3 6 5 4 XOUT VDD CLK XIN VCON GND D ESCRIPTION T he PLL500-15/16 is a low cost, high performance and low phase noise VCXO for the 1.0MHz to 18MHz range, providing less than -130dBc at 10kHz offset when using a 35.328MHz crystal. The very low jitter (2.5 ps RMS period jitter) makes this chip ideal for applications requiring voltage controlled frequency sources. Input crystal can range from 16MHz to 36MHz (fundamental resonant mode). SOT23-6* ^: Denotes internal Pull-up *: SOT package offers single divider option only D IVIDER SELECTION LOGIC LEVELS P art # P LL500-15 P LL500-16 DivSel State 1 ( Default) 0 1 ( Default) 0 O peration ÷16 ÷8 ÷4 ÷2 B LOCK DIAGRAM DIVSEL XIN VCXO XOUT VCON Varicap Selectable Divider CLK 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 10/12/06 Page 1 ( Preliminary) PLL500-15/16 L ow Phase Noise VCXO (1MHz to 18MHz) D IE PAD LAYOUT DIE SPECIFICATIONS N ame Value 32 mil (812,986) 8 1 XIN XOUT OE^ 7 39 mil 2 VCON VDD 6 S ize R everse side P ad dimensions T hickness 39 x 32 mil GND 80 micron x 80 micron 10 mil 3 DIVSEL^ 4 GND CLK 5 DIE ID: PLL500-15: C500A A1111-12 PLL500-16: C500A A1111-11 Y X (0,0) Note: ^ denotes internal pull up P ACKAGE PIN and DIE PAD ASSIGNMENT P in# N ame X IN V CON D IVSEL G ND C LK V DD OE X OUT Die Pad Position X ( µ m) 94.183 94.157 94.183 94.193 715.472 715.307 715.472 476.906 SOP-8 1 2 3 4 5 6 7 8 SOT23-6 6 5 4 3 2 1 Y ( µ m) 768.599 605.029 331.756 140.379 203.866 455.726 626.716 888.881 Type I P I P O P I I Crystal input pin. Description Frequency Control Voltage input pin. Divider Selection input pin. Default Logic 1 for SOT23 package. See Divider Selection Logic Levels table on Page 1. Ground pin. Output clock pin. VDD power supply pin. Output Enable input pin. Disables the output when low. Internal pull-up enables output by default if pin is not connected to low. Default “Enabled” (Logic 1) for SOT23 package. Crystal output pin. 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 10/12/06 Page 2 ( Preliminary) PLL500-15/16 L ow Phase Noise VCXO (1MHz to 18MHz) E LECTRICAL SPECIFICATIONS 1 . Absolute Maximum Ratings P ARAMETERS S upply Voltage I nput Voltage, dc O utput Voltage, dc S torage Temperature A mbient Operating Temperature* J unction Temperature L ead Temperature (soldering, 10s) E SD Protection, Human Body Model SYMBOL V DD VI VO TS TA TJ MIN. - 0.5 - 0.5 - 65 - 40 MAX. 4 .6 V DD +0.5 V DD +0.5 150 85 1 25 260 2 UNITS V V V °C °C °C °C kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only. 2 . AC Electrical Specifications P ARAMETERS I nput Crystal Frequency O utput Clock Rise/Fall Time O utput Clock Duty Cycle 0 .8V ~ 2.0V with 10 pF load 0 .3V ~ 3.0V with 15 pF load M easured @ 1.4V 45 SYMBOL CONDITIONS MIN. 16 TYP. 1.15 3.7 50 MAX. 36 UNITS MHz ns 55 % 3 . Voltage Control Crystal Oscillator P ARAMETERS V CXO Stabilization Time * V CXO Tuning Range C LK output pullability V CXO Tuning Characteristic P ull range linearity P ower Supply Rejection V CON pin input impedance V CON modulation BW PWSRR SYMBOL T VCXOSTB CONDITIONS F rom power valid X TAL C 0 /C 1 < 2 50 0V ≤ V CON ≤ 3 .3V VCON=1.65V, ± 1.65V MIN. TYP. 300 MAX. 10 UNITS ms ppm ppm ppm/V % ppm kΩ kHz ± 150 1 00 5 F requency change with VDD varied +/- 10% 0 V ≤ V CON ≤ 3 .3V, -3dB -1 2 000 45 +1 N ote: P arameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 10/12/06 Page 3 ( Preliminary) PLL500-15/16 L ow Phase Noise VCXO (1MHz to 18MHz) 4 . Jitter and Phase Noise Specifications P ARAMETERS R MS Period Jitter (1 sigma – 1000 samples) P hase Noise relative to carrier P hase Noise relative to carrier P hase Noise relative to carrier P hase Noise relative to carrier P hase Noise relative to carrier CONDITIONS With capacitive decoupling between VDD and GND. 18MHz @100Hz offset 18MHz @1kHz offset 18MHz @10kHz offset 18MHz @100kHz offset 18MHz @1MHz offset MIN. TYP. 2.5 -75 -105 -125 -133 -140 MAX. UNITS ps dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz 5 . DC Specifications P ARAMETERS S upply Current, Dynamic, with Loaded Outputs O perating Voltage O utput Low Voltage at CMOS level O utput High Voltage at CMOS level O utput drive current V CXO Control Voltage SYMBOL I DD V DD V OLC V OHC VCON CONDITIONS F XIN = 3 6MHz Output load of 15pF MIN. TYP. 5 MAX. 6 3.63 0.4 UNITS mA V V V 2 .25 I OL = + 4mA I OH = - 4mA For V OL 2.4V V DD – 0 .4 8 0 9.5 V DD mA V 6 . Crystal Specifications P ARAMETERS C rystal Resonator Frequency C rystal Loading Rating (VCON = 1.65V) M aximum Sustainable Drive Level O perating Drive Level C0 C 0/C1 E SR SYMBOL F XIN C L (xtal) MIN. 16 TYP. 8 .5 MAX. 36 200 UNITS MHz pF µW µW pF Ω 50 5 250 30 RS N ote : The crystal must be such that it oscillates (parallel resonant) at nominal frequency when presented a C Load as specified above. If the crystal requires more load to be at nominal frequency, the additional load must be added externally. This however may reduce the pull range. 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 10/12/06 Page 4 ( Preliminary) PLL500-15/16 L ow Phase Noise VCXO (1MHz to 18MHz) P ACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT) S OIC 8L Symbol A A1 A2 B C D E H L e S OT-23 6L Symbol A A1 A2 B C D E H L e D imension in MM Min. Max. 1 .05 1.35 0.05 0.15 1.00 1.20 0 .30 0.50 0 .08 0.20 2 .80 3.00 1 .50 1.70 2 .60 3.00 0 .35 0.55 0 .95 BSC D imension in MM Min. Max. 1 .35 1.75 0.10 0.25 1.25 1.50 0 .33 0.53 0 .19 0.27 4 .80 5.00 3 .80 4.00 5 .80 6.20 0 .40 0.89 1 .27 BSC E H D A2 A A1 e b C L E H D A2 A A1 e b C L 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 10/12/06 Page 5 ( Preliminary) PLL500-15/16 L ow Phase Noise VCXO (1MHz to 18MHz) O RDERING INFORMATION (GREEN PACKAGE COMPLIANT) F or part ordering, please contact our Sales Department: 4 7745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 P ART NUMBER T he order number for this device is a combination of the following: Part number, Package type and Operating temperature range P LL500-XX X X X X P ART NUMBER N ONE= TUBE R=TAPE AND REEL N ONE=NORMAL PACK A GE L=GREEN PACKAGE P ACKAGE TYPE D=Die S= SOIC-8L T= SOT23-6L P art / Order Number P LL500-15DC P LL500-15SC P LL500-15SC-R P LL500-15SCL P LL500-15SCL-R P LL500-15TC P LL500-15TC-R P LL500-15TCL P LL500-15TCL-R P LL500-16DC P LL500-16SC P LL500-16SC-R P LL500-16SCL P LL500-16SCL-R P LL500-16TC P LL500-16TC-R P LL500-16TCL P LL500-16TCL-R Marking P500-15DC P500-15SC P500-15SC P500-15SCL P500-15SCL P500-15TC P500-15TC P500-15TCL P500-15TCL P500-16DC P500-16SC P500-16SC P500-16SCL P500-16SCL P500-16TC P500-16TC P500-16TCL P500-16TCL T EMPERATURE C=COMMERCIAL I=INDUSTRIAL Package Option Die (Waffle Pack) 8-Pin SOIC (Tube) 8-Pin SOIC (Tape and Reel) 8-Pin SOIC G REEN ( Tube) 8-Pin SOIC G REEN ( Tape and Reel) 6-Pin SOT23 (Tube) 6-Pin SOT23 (Tape and Reel) 6-Pin SOT23 G REEN ( Tube) 6-Pin SOT23 G REEN ( Tape and Reel) Die (Waffle Pack) 8-Pin SOIC (Tube) 8-Pin SOIC (Tape and Reel) 8-Pin SOIC G REEN ( Tube) 8-Pin SOIC G REEN ( Tape and Reel) 6-Pin SOT23 (Tube) 6-Pin SOT23 (Tape and Reel) 6-Pin SOT23 G REEN ( Tube) 6-Pin SOT23 G REEN ( Tape and Reel) P haseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. L IFE SUPPORT POLICY : PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 10/12/06 Page 6