P520-08OC

P LL520-05/-06/-07/-08/-09 L ow Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal) F EATURES • • 1 00MHz to 200MHz Fundamental Mode Crystal. O utput range: 100 – 200MHz (no multiplication), 200 – 400MHz (2x multiplier), 400 – 800MHz (4x multiplier), or 800MHz – 1GHz (PLL520-09 TSSOP only, 8x multiplier). H igh yield design supports up to 2pF stray capacitance at 200MHz. C MOS (Standard drive PLL520-07 or Selectable Drive PLL520-06), PECL (Enable low PLL520-08 or Enable high PLL520-05) or LVDS output (PLL520-09). I ntegrated variable capacitors. S upports 3.3V-Power Supply. A vailable in 16-Pin (TSSOP or 3x3mm QFN) Note: PLL520-06 only available in 3x3mm. Note: PLL520-07 only available in TSSOP. PIN CONFIGURATION ( Top View) VDD XIN XOUT SEL3^ SEL2^ OE VCON GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 SEL0^ SEL1^ GND CLKC VDD CLKT GND GND PLL 520-0x • • • • • GND/DRIVSEL* SEL0^ 10 GND GND B LOCK DIAGRAM SEL OE VCON Oscillator XIN XOUT Amplifier w/ integrated varicaps PLL (Phase Locked Loop) ^ : Internal pull-up *: PLL520-06 pin 12 is output drive select (DRIVSEL) (0 for High Drive CMOS, 1 for Standard Drive CMOS) O UTPUT ENABLE LOGICAL LEVELS P art # P LL520-08 P LL520-05 PLL520-06 PLL520-07 PLL520-09 OE S tate Q Q 0 ( Default) 1 0 1 (Default) VCON Output enabled Tri-state T ri-state Output enabled PLL by-pass O E input: Logical states defined by PECL levels for PLL520-08 Logical states defined by CMOS levels for PLL520-05/-06/07/-09 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 09/20/04 Page 1 GND T he PLL520-05/-06/-07/-08/-09 is a family of VCXO ICs specifically designed to pull high frequency fundamental crystals. Their design was optimized to tolerate higher limits of interelectrode capacitance and bonding capacitance to improve yield. They achieve very low current into the crystal resulting in better overall stability. Their internal varicaps allow an on chip frequency pulling, controlled by the VCON input. XIN XOUT SEL2^ OE 12 13 14 15 16 1 VDD D ESCRIPTION 11 SEL1^ 9 8 7 6 5 GND CLKC VDD CLKT P520-0x 2 3 4 P LL520-05/-06/-07/-08/-09 L ow Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal) P IN DESCRIPTIONS N ame X IN X OUT OE V CON G ND D RIVSEL** TSSOP* Pin number 2 3 6 7 8,9, 10, 14 - 3x3mm QFN* Pin number 13 14 16 1 2,3,4,8,12 12 Type I I I I P I Description Crystal in connector. Crystal out connector. Output enable pin. Frequency control input (0.3V to 3.0V) Ground (except pin 12 on PLL520-06: DRIVSEL see below). PLL520-06 only: Drive Select Input. This pin has an internal pull-up that will default DRIVSEL to ‘1’ when not connect to GND. CMOS output of PLL520-06 will be high drive CMOS when DRIVSEL is set to ‘0’, and will be standard CMOS otherwise. True output PECL (PLL520-08) or LVDS (PLL520-09) (N/C for PLL520-07) Complementary output PECL (PLL520-08) or LVDS (PLL520-09) (CMOS out for PLL520-07). Multiplier selector pins. These pins have an internal pull-up that will default SEL to ‘1’ when not connected to GND. +3.3V power supply. C LKT C LKC S EL0 S EL1 S EL2 S EL3 V DD 11 13 16 15 5 4 1, 12 5 7 10 9 15 Not available 6,11 O O I I I I P * N ote: PLL520-06 only available in 3x3mm QFN, PLL520-07 only available in TSSOP. ** Note: DRIVSEL on pin 12 on PLL520-06 only. F REQUENCY SELECTION TABLE S EL3* SEL2 SEL1 SEL0 Selected Multiplier 0* 1* 1* 1* 0 0 1 1 1 1 1 1 1 1 0 1 Fin x 8 (PLL520-09 in TSSOP only) Fin x 4 Fin x 2 No multiplication N ote *: S EL3 is not available (always “1”) in 3x3mm package All pins have internal pull-ups (default value is 1). Connect to GND to set to 0. 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 09/20/04 Page 2 P LL520-05/-06/-07/-08/-09 L ow Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal) E LECTRICAL SPECIFICATIONS 1 . Absolute Maximum Ratings P ARAMETERS S upply Voltage I nput Voltage, dc O utput Voltage, dc S torage Temperature A mbient Operating Temperature* J unction Temperature L ead Temperature (soldering, 10s) E SD Protection, Human Body Model SYMBOL V DD VI VO TS TA TJ MIN. - 0.5 - 0.5 - 65 - 40 MAX. 4 .6 V DD +0.5 V DD +0.5 150 85 1 25 260 2 UNITS V V V °C °C °C °C kV E xposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * N ote : Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 2 . Crystal Specifications P ARAMETERS C rystal Resonator Frequency C rystal Loading Rating I nterelectrode Capacitance C rystal Pullability R ecommended ESR SYMBOL F XIN C L (xtal) C0 C 0 /C 1 (xtal) RE CONDITIONS P arallel Fundamental Mode D ie at VCON = 1.65V A T cut A T cut MIN. 100 4 MAX. 200 3 .5 250 30 UNITS MHz pF pF Ω 3. Voltage Controlled Crystal Oscillator P ARAMETERS V CXO Stabilization Time * V CXO Tuning Range C LK output pullability O n-chip Varicaps control range L inearity V CXO Tuning Characteristic V CON input impedance V CON modulation BW SYMBOL T VCXOSTB CONDITIONS F rom power valid F XIN = 1 00 – 200MHz; XTAL C 0 /C 1 < 2 50 0V ≤ V CON ≤ 3 .3V VCON=1.65V, ± 1.65V V CON = 0 to 3.3V MIN. TYP. MAX. 10 UNITS ms ppm ppm pF % ppm/V kΩ kHz 200* ± 100* 4 – 18* 10* 65 60 0 V ≤ V CON ≤ 3 .3V, -3dB 25 N ote: P arameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 09/20/04 Page 3 P LL520-05/-06/-07/-08/-09 L ow Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal) 4 . General Electrical Specifications P ARAMETERS S upply Current (Loaded Outputs) O perating Voltage O utput Clock Duty Cycle S hort Circuit Current SYMBOL I DD V DD CONDITIONS P ECL/LVDS/CMOS @ 5 0% V DD ( CMOS) @ 1.25V (LVDS) @ V DD – 1 .3V (PECL) MIN. TYP. MAX. 100/80/40 UNITS mA V % mA 2 .97 45 45 45 50 50 50 ± 50 3.63 55 55 55 5 . Jitter Specifications P ARAMETERS P eriod jitter RMS P eriod jitter peak-to-peak A ccumulated jitter RMS A ccumulated jitter peak-to-peak R andom Jitter I ntegrated jitter RMS at 155MHz P eriod jitter RMS P eriod jitter peak-to-peak A ccumulated jitter RMS A ccumulated jitter peak-to-peak R andom Jitter I ntegrated jitter RMS at 622MHz M easured on Wavecrest SIA 3000 CONDITIONS At 155.52MHz, with capacitive decoupling between VDD and GND. Over 10,000 cycles At 155.52MHz, with capacitive decoupling between VDD and GND. Over 1,000,000 cycles. “RJ” measured on Wavecrest SIA 3000 Integrated 12 kHz to 20 MHz At 622.08MHz, with capacitive decoupling between VDD and GND. Over 10,000 cycles At 622.08MHz, with capacitive decoupling between VDD and GND. Over 1,000,000 cycles. “RJ” measured on Wavecrest SIA 3000 Integrated 12 kHz to 20 MHz MIN. TYP. 2.5 18.5 2.5 24 2.5 0.3 11 45 11 24 3 1.6 MAX. 20 27 0.4 49 27 1.8 UNITS ps ps ps ps ps ps ps ps 6 . Phase Noise Specifications P ARAMETERS P hase Noise relative to carrier FREQUENCY 1 55.52MHz 622.08MHz @10Hz -75 -75 @100Hz -95 -95 @1kHz -125 -110 @10kHz -140 -125 @100kHz -145 -120 UNITS dBc/Hz N ote: Phase Noise measured at VCON = 0V 7 . CMOS Electrical Specifications P ARAMETERS O utput drive current (High Drive) O utput drive current (Standard Drive) O utput Clock Rise/Fall Time (Standard Drive) O utput Clock Rise/Fall Time (High Drive) SYMBOL I OH I OL I OH I OL CONDITIONS V OH = V DD -0.4V, V DD =3.3V V OL = 0 .4V, V DD = 3 .3V V OH = V DD -0.4V, V DD =3.3V V OL = 0 .4V, V DD = 3 .3V 0 .3V ~ 3.0V with 15 pF load 0 .3V ~ 3.0V with 15 pF load MIN. 30 30 10 10 TYP. MAX. UNITS mA mA mA mA 2.4 1.2 ns * N ote: High Drive CMOS is available on PLL520-06 through DRIVSEL selector input on pin 12. 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 09/20/04 Page 4 P LL520-05/-06/-07/-08/-09 L ow Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal) 8 . LVDS Electrical Characteristics P ARAMETERS O utput Differential Voltage V DD M agnitude Change O utput High Voltage O utput Low Voltage O ffset Voltage O ffset Magnitude Change P ower-off Leakage O utput Short Circuit Current SYMBOL V OD ∆ V OD V OH V OL V OS ∆ V OS I OXD I OSD CONDITIONS MIN. 2 47 - 50 TYP. 355 1 .4 1.1 1.2 3 ±1 - 5.7 MAX. 454 50 1.6 1.375 25 ± 10 -8 UNITS mV mV V V V mV uA mA R L = 1 00 Ω ( see figure) 0 .9 1 .125 0 V out = V DD o r GND V DD = 0 V 9 . LVDS Switching Characteristics P ARAMETERS D ifferential Clock Rise Time D ifferential Clock Fall Time LVDS Levels Test Circuit OUT SYMBOL tr tf CONDITIONS R L = 1 00 Ω C L = 1 0 pF (see figure) MIN. 0 .2 0.2 TYP. 0.7 0.7 MAX. 1.0 1.0 UNITS ns ns LVDS Switching Test Circuit OUT 50Ω CL = 10pF VOD VOS VDIFF RL = 100Ω 50Ω CL = 10pF OUT OUT LVDS Transistion Time Waveform OUT 0V (Differential) OUT 80% VDIFF 20% 0V 80% 20% tR tF 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 09/20/04 Page 5 P LL520-05/-06/-07/-08/-09 L ow Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal) 1 0. PECL Electrical Characteristics P ARAMETERS O utput High Voltage O utput Low Voltage SYMBOL V OH V OL CONDITIONS R L = 5 0 to (V DD – 2 V) (see figure) MIN. V DD – 1 .025 MAX. V DD – 1 .620 UNITS V V 1 1. PECL Switching Characteristics P ARAMETERS C lock Rise Time C lock Fall Time SYMBOL tr tf CONDITIONS @ 20/80% - PECL @ 80/20% - PECL MIN. TYP. 0.6 0.5 MAX. 1.5 1.5 UNITS ns ns PECL Levels Test Circuit OUT VDD OUT PECL Output Skew 50Ω 2.0V 50% 50Ω OUT OUT tSKEW PECL Transistion Time Waveform DUTY CYCLE 45 - 55% 55 - 45% OUT 80% 50% 20% OUT tR tF 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 09/20/04 Page 6 P LL520-05/-06/-07/-08/-09 L ow Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal) P ACKAGE INFORMATION 16 PIN TSSOP ( m m ) Sym bol A A1 B C D E H L e M in. M ax. 1.20 0.05 0.15 0.19 0.30 0.09 0.20 4.90 5.10 4.30 4.50 6.40 BSC 0.45 0.75 0.65 BSC E H D A A1 e B C L 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 09/20/04 Page 7 P LL520-05/-06/-07/-08/-09 L ow Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal) O RDERING INFORMATION F or part ordering, please contact our Sales Department: 4 7745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 P ART NUMBER T he order number for this device is a combination of the following: Device number, Package type and Operating temperature range P LL520-0x O C P ART NUMBER T EMPERATURE C=COMMERCIAL I=INDUSTRAL P ACKAGE TYPE O=TSSOP Q=QFN O rder Number P LL520-05OC PLL520-05OC-R PLL520-05QC PLL520-05QC-R PLL520-06QC PLL520-06QC-R PLL520-07OC PLL520-07OC-R PLL520-08OC PLL520-08OC-R PLL520-08QC PLL520-08QC-R PLL520-09OC PLL520-09OC-R PLL520-09QC PLL520-09QC-R Marking P520-05OC P520-05OC P520-05QC P520-05QC P520-06QC P520-06QC P520-07OC P520-07OC P520-08OC P520-08OC P520-08QC P520-08QC P520-09OC P520-09OC P520-09QC P520-09QC Package Option 16-Pin 16-Pin 16-Pin 16-Pin TSSOP (Tube) TSSOP (Tape and Reel) 3x3 QFN (Tube) 3x3 QFN (Tape and Reel) 16-Pin 3x3 QFN (Tube) 16-Pin 3x3 QFN (Tape and Reel) 16-Pin TSSOP (Tube) 16-Pin TSSOP (Tape and Reel) 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin TSSOP (Tube) TSSOP (Tape and Reel) 3x3 QFN (Tube) 3x3 QFN (Tape and Reel) TSSOP (Tube) TSSOP (Tape and Reel) 3x3 QFN (Tube) 3x3 QFN (Tape and Reel) P haseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. L IFE SUPPORT POLICY : PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 09/20/04 Page 8