P580-35QCL

( Preliminary) P L580-35/37/38/39 3 8MHz-320MHz Low Phase Noise VCXO F EATURES • • • L ess than 0.4ps RMS (12KHz-20MHz) phase jitter for a ll frequencies . L ess than 25ps (typ.) peak to peak jitter for all frequencies. L ow phase noise output (@ 1MHz frequency offset ∗ - 144dBc/Hz for 155.52MHz ∗ - 140dBC/Hz for 311.04MHz 1 9MHz-40MHz crystal input. 3 8MHz-320MHz output. A vailable in PECL, LVDS, or CMOS outputs. N o external varicap required. O utput Enable selector. W ide pull range (+/-200ppm). 3 .3V operation. A vailable in 3x3 QFN or 16-pin TSSOP packages. PACKAGE PIN ASSIGNMENT VDDANA XIN XOUT SEL2^ OE_CTRL VCON GNDANA LP 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 SEL0^ SEL1^ GNDBUF QBAR VDDBUF Q GNDBUF LM PL580-3X • • • • • • • • 16-pin TSSOP VDDANA SEL0^ 10 XOUT 12 13 14 15 16 1 11 SEL1^ 9 XIN 8 7 6 GNDBUF QBAR VDDBUF Q D ESCRIPTION T he PL580-3X is a monolithic low jitter and low phase noise VCXO, capable of 0.4ps RMS phase jitter and CMOS, LVDS, or PECL outputs, covering a wide frequency output range up to 320MHz. It allows the control of the output frequency with an input voltage (VCON), using a low cost crystal. The frequency selector pads of PL580-3X enable output frequencies of (2, 4, 8, or 16) * F XIN . The PL580-3X is designed to address the demanding requirements of high performance applications such as SONET, GPS, Video, etc. SEL2^ OE_CTRL VCON PL580-3X 2 3 4 5 GNDANA 3x3 QFN Note1: QBAR is used for single ended CMOS output. Note2: ^ Denotes internal pull up resistor. B LOCK DIAGRAM VCON VARICAP VCO Divider Charge Pump + Loop Filter Output Divider (1,2,4,8) GNDBUF LP LM XIN XOUT XTAL OSC Phase Detector VCO (F XiN x16) QBAR Q Performance Tuner OE 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 12/14/06 Page 1 ( Preliminary) P L580-35/37/38/39 3 8MHz-320MHz Low Phase Noise VCXO O UTPUT ENABLE LOGICAL LEVELS P art # P L580-38 (PECL) P L580-35 (PECL) PL580-37 (CMOS) PL580-39 (LVDS) OE 0 ( Default) 1 0 1 (Default) S tate Output enabled Tri-state T ri-state Output enabled P IN DESCRIPTIONS N ame V DDANA X IN X OUT S EL2 O E_CTRL V CON G NDANA LP LM G NDBUF Q V DDBUF Q BAR G NDBUF S EL1 S EL0 TSSOP Pin number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 3x3mm QFN Pin number 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 Type P I O I I I P P O P O P I I VDD for analog Circuitry. Description Crystal input pin. (See Crystal Specifications on page 4). Crystal output pin. (See Crystal Specifications on page 4). Output frequency Selector pin. Output enable control pin. (See OE_CTRL Logic Levels). Voltage control input. Ground for analog circuitry. Tuning inductor connection. The inductor is recommended to be a high Q small size 0402 or 0603 SMD component, and must be placed between LP and adjacent LM pin. Place inductor as close to the IC as possible to minimize parasitic effects and to maintain inductor Q. GND connection for output buffer circuitry. PECL or LVDS output. VDD connection for output buffer circuitry. VDDBUF should be separately decoupled from other VDDs whenever possible. Complementary PECL, LVDS, Or single ended CMOS output. GND connection for output buffer circuitry. Output frequency Selector pin. Output frequency Selector pin. 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 12/14/06 Page 2 ( Preliminary) P L580-35/37/38/39 3 8MHz-320MHz Low Phase Noise VCXO F REQUENCY SELECTION TABLE S EL2 0 0 0 0 1 1 1 1 SEL1 0 0 1 1 0 0 1 1 S EL0 0 1 0 1 0 1 0 1 S elected Multiplier/Output Frequency V CO Max* V CO Min* R eserved R eserved F in x 2 F in x 8 F in x 16 F in x 4 A ll SEL pads have internal pull-ups (default value is ‘1’). Bond to GND to set to 0. * Special Test Modes to help selecting the inductor value for the target output frequency. P ERFORMANCE TUNING & INDUCTOR VALUE SELECTION P lease refer to PhaseLink’s ‘PhasorV Tuning Assistance’ software to automatically calculate the optimum inductor values for your application. In addition, the chart below could be used as a reference for quick inductor value selection. Please note that the inductor values mentioned in the table below, or when using ‘PhasorV Tuning Assistance’ are derived based on the parasitic values of PhaseLink’s evaluation board. For performance enhancement of your custom board design, please follow the following instruction: Use the special test modes “VCO Max” and “VCO Min” to determine the optimum inductor value. “VCO Max” represents the high end of the VCO range and “VCO Min” represents the low end of the VCO range. The output frequency in the “VCO Max” and “VCO Min” test modes is VCO/16. This means that the output frequencies are around the crystal frequency that will be used. The optimum inductor value is where the target crystal frequency is closest to the middle between the “VCO Max” and “VCO Min” output frequencies. In this case the VCO will lock in the middle of its tuning range with maximum margin on either side. 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 12/14/06 Page 3 ( Preliminary) P L580-35/37/38/39 3 8MHz-320MHz Low Phase Noise VCXO E LECTRICAL SPECIFICATIONS 1 . Absolute Maximum Ratings P ARAMETERS S upply Voltage I nput Voltage, dc O utput Voltage, dc S torage Temperature A mbient Operating Temperature* J unction Temperature L ead Temperature (soldering, 10s) E SD Protection, Human Body Model SYMBOL V DD VI VO TS TA TJ MIN. - 0.5 - 0.5 - 65 - 40 MAX. 4 .6 V DD +0.5 V DD +0.5 150 85 1 25 260 2 UNITS V V V °C °C °C °C kV E xposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * N ote : Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 2 . Crystal Specifications P ARAMETERS C rystal Resonator Frequency C rystal Loading Rating C rystal Pullability R ecommended ESR SYMBOL F XIN C L (xtal) C 0 /C 1 (xtal) RE CONDITIONS P arallel Fundamental Mode a t VCON = 0V a t VCON = 1.65V a t VCON = 3.3V A T cut A T cut MIN. 19 TYP. 17.7 9.5 5.4 MAX. 40 UNITS MHz pF 250 30 Ω N ote : Crystal Loading rating: The listed numbers are for the IC only. Specify the crystal for the value at VCON = 1.65V and add the PCB & package parasitic. A round number (i.e. 12pF) can be achieved by adding external capacitors. Try to add the same value to XIN and XOUT, and please note, that frequency pulling and oscillator gain may decrease. 3 . Voltage Control Crystal Oscillator P ARAMETERS V CXO Stabilization Time * V CXO Tuning Range C LK output pullability V CXO Tuning Characteristic P ull range linearity V CON pin input impedance V CON modulation BW SYMBOL T VCXOSTB CONDITIONS F rom power valid F XIN = 1 9 – 40MHz; XTAL C 0 /C 1 < 2 50 0V ≤ V CON ≤ 3 .3V VCON=1.65V, ± 1.65V MIN. TYP. MAX. 10 UNITS ms ppm ppm ppm/V % kΩ kHz 500 ± 200 1 50 10 60 25 80 0 V ≤ V CON ≤ 3 .3V, -3dB N ote: P arameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 12/14/06 Page 4 ( Preliminary) P L580-35/37/38/39 3 8MHz-320MHz Low Phase Noise VCXO 4 . General Electrical Specifications P ARAMETERS S upply Current, Dynamic (with Loaded Outputs) O perating Voltage O utput Clock Duty Cycle S hort Circuit Current N ote: C MOS operation is not advised above 200MHz with 15pF load; and 320MHz with 10pF load. SYMBOL I DD V DD CONDITIONS P ECL/LVDS/CMOS 3 8MHz