PL560-68

A nalog Frequency Multiplier P L560-xx VCXO Family P RODUCT DESCRIPTION P haseLink’s Analog Frequency Multiplier TM ( AFM) is the industry’s first ‘Balanced Oscillator’ utilizing analog multiplication of the fundamental frequency (at double or quadruple frequency), combined with an attenuation of the fundamental of the reference crystal, without the use of a phase-locked loop (PLL), in CMOS technology. PhaseLink’s patent pending PL560-xx family of AFM products can achieve up to 800 MHz output frequency with little jitter or phase noise deterioration. In addition, the low frequency input crystal requirement makes the AFMs the most affordable high-performance timing-source in the market. PL560-xx family of products utilize low-power CMOS technology and are housed in G REEN / R oHS compliant 1 6-pin TSSOP, and 16-pin 3x3 QFN packages. F EATURES • • • • • • N on-PLL frequency multiplication I nput frequency from 30-200 MHz O utput frequency from 60-800 MHz L ow phase noise and jitter (equivalent to fundamental crystal at the output frequency) U ltra-low jitter o R MS phase jitter < 0.25 ps (12kHz-20MHz) o R MS period jitter < 2.5 ps L ow phase noise o - 142 dBc/Hz @100kHz offset from 155.52 MHz o - 150 dBc/Hz @10MHz offset from 155.52 MHz H igh linearity pull range (typ. 5%) + /- 120 PPM pullability VCXO L ow input frequency eliminates the need for expensive crystals D ifferential output levels (PECL, LVDS), or singleended CMOS S ingle 2.5V or 3.3V +/- 10% power supply O ptional industrial temperature range (-40 ° C to +85 ° C) A vailable in 16-pin G REEN / RoHS c ompliant T SSOP, and 3x3 QFN • • • • • • • Figure 1: 2x AFM Phase Noise at 311.04MHz 4 7745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991 w ww.phaselink.com R ev. 02/09/07 Page 1 A nalog Frequency Multiplier P L560-xx V CXO Family VCON L2X OE X IN O s c illa to r A m p lifie r F re q u e n c y X2 F re q u e n c y X4 QBAR Q XOUT O n ly r e q u ir e d in x 4 d e s ig n s L4X F igure 2: Block Diagram of VCXO AFM Figure 3 shows the period jitter histogram of the 2x Analog Frequency Multiplier at 311.04 MHz, while Figure 4 shows the very low rejection levels of sub-harmonics that correspond to the exceptionally low jitter performance. Figure 3: Period Jitter Histogram at 311.04 MHz A nalog Frequency Multiplier (2x) with 155.52MHz crystal Figure 4: Spectrum Analysis at 311.04 MHz Analog Frequency Multiplier (2x) with sub-harmonics below –72 dBc O E LOGIC SELECTION OUTPUT OESEL 0 (Default) PECL 1 OE 0 (Default) 1 0 1 (Default) 0 1 (Default) 0 (Default) 1 Output State Enabled Tri-state Tri-state Enabled Tri-state Enabled Enabled Tri-state 0 (Default) LVDS or CMOS 1 O ESEL and OE: Connect to VDD to set to “1”, connect to GND to set to “0”. Internally set to default through pull-down / -up. 4 7745 Fremont Blvd., Fremont, CA 94538 TEL (510) 492-0990, FAX (510) 492-0991 w ww.phaselink.com R ev.:02-09-07 Page 2 A nalog Frequency Multiplier P L560-xx V CXO Family P RODUCT SELECTION GUIDE FREQUENCY VERSUS PHASE NOISE PERFORMANCE Part Number Input Frequency Range (MHz) Analog Frequency Multiplication Factor 4 4 4 4 4 2 2 2 2 2 Output Frequency Range (MHz) Phase Noise at Frequency Offset From Carrier (dBc/Hz) Output Type Carrier Freq. (MHz) 622.08 622.08 155.52 155.52 155.52 155.52 155.52 155.52 311.04 311.04 10 KHz -130 -130 -128 -128 -128 -138 -138 -138 -135 -135 100 KHz -137 -137 -142 -142 -142 -142 -142 -142 -142 -142 10 MHz -150 -150 -150 -150 -150 -149 -149 -149 -151 -151 10 Hz -55 -55 -50 -50 -50 -65 -65 -65 -60 -60 100 Hz -85 -85 -82 -82 -82 -95 -95 -95 -85 -85 1 KHz -110 -110 -110 -110 -110 -122 -122 -122 -112 -112 1 MHz -148 -148 -148 -148 -148 -148 -148 -148 -150 -150 PL560-08 PL560-09 PL560-37 PL560-38 PL560-39 PL560-47 PL560-48 PL560-49 PL560-68 PL560-69 75 - 200 75 - 200 30 - 80 30 - 80 30 - 80 30 - 80 30 - 80 30 - 80 75 - 200 75 - 200 300 - 800 300 - 800 120 - 320 120 - 320 120 - 320 60 - 160 60 - 160 60 - 160 150 - 400 150 - 400 PECL LVDS CMOS PECL LVDS CMOS PECL LVDS PECL LVDS P hase noise was measured using Agilent E5500. F REQUENCY VERSUS JITTER, AND SUB-HARMONIC PERFORMANCE RMS Period Jitter (ps) Peak to Peak Period Jitter (ps) RMS Accumulated (L.T.) Jitter (ps) RMS Phase Jitter (12 KHz-20MHz) (ps) Typ. 0.09 0.09 0.25 0.25 0.25 0.25 0.25 0.27 0.18 0.18 Spectral Specifications / Sub-harmonic Content (dBc), Frequency (MHz) Carrier @ @ @ @ @ @ Max. Freq. -75% -50% -25% +25% +50% +75% (Fc) (Fc) (Fc) (Fc) (Fc) (Fc) (Fc) 622 622 155.52 155.52 155.52 155.52 155.52 155.52 311.04 311.04 -50 -50 -75 -75 -75 -50 -50 -62 -62 -62 -68 -68 -68 -72 -72 -45 -45 -47 -47 -47 -47 -65 -65 -65 -68 -68 -68 -85 -85 -55 -55 -75 -75 -75 Part Number Output. Freq. (MHz) Min. Typ. Max. Min. Typ. Max. Min. Typ. 4 4 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 6 6 3 3 3 3 3 3 3 3 25 25 18 18 18 18 18 18 18 18 30 30 20 20 20 20 20 20 20 20 Max. Min. 6 6 3 3 3 3 3 3 3 3 PL560-08 PL560-09 PL560-37 PL560-38 PL560-39 PL560-47 PL560-48 PL560-49 PL560-68 PL560-69 622 622 155 155 155 155 155 155 311 311 N ote: W avecrest data 10,000 hits. No filtering was used in jitter calculations. Agilent 5500 was used for phase jitter measurements. Spectral specifications were obtained using Agilent E7401A. 4 7745 Fremont Blvd., Fremont, CA 94538 TEL (510) 492-0990, FAX (510) 492-0991 w ww.phaselink.com R ev.:02-09-07 Page 3 A nalog Frequency Multiplier P L560-xx V CXO Family C RYSTAL SPECIFICATIONS AND BOARD LAYOUT CONSIDERATIONS BOARD LAYOUT CONSIDERATIONS AFM IC X TAL X IN (Pin # 4) X OUT (Pin # 5) AFM IC X TAL C eramic SMD X IN (Pin # 4) X OUT (Pin # 5) To minimize parasitic effects, and improve performance: • Place the crystal as close as possible to the IC. • Make the board traces that are connected to the crystal pins symmetrical. • The board trace symmetry is important, as it reduces the negative parasitic effects to produce a clean frequency multiplication with low jitter. Parasitic effects reduce frequency pulling of the VCXO and increase jitter. C RYSTAL SPECIFICATIONS & TUNING PERFORMANCE CRYSTAL SPECIFICATIONS PART NUMBER CRYSTAL RESONATOR FREQUENCY (FXIN) TUNING PERFORMANCE ESR (RE) Max. CRYSTAL FREQ (MHz) 155.52 5pF 30 Ω 155.52 30.72 1.8pF 2.8pF 4.5pF 5.1pF 5.3pF 2.0pF 5.7fF 12.4fF 19.1fF 20.9fF 25.6fF 6.7fF 316 228 236 242 207 305 -134 ppm -167ppm -163 ppm -131 ppm -157 ppm -92 ppm +87 ppm +176 ppm +167 ppm +98 ppm +141 ppm +110 ppm CL (xtal) MODE CONDITIONS At VCON CRYSTAL C0 3.0pF C1 12.2fF C0/C1 245 TUNING (Typical) VC: 1.65V 0V -145 ppm VC: 1.65V 3.4V +108 ppm TYP. PL560-08/09 PL560-68/69 75~200MHz Fundamental = 1.65V PL56037/38/39 PL56047/48/49 At 30.72 5pF 30 Ω 38.88 38.88 77.76 30~80MHz Fundamental VCON = 1.65V N ote: N on specified parameters can be chosen as standard values from crystal suppliers. CL ratings larger than 5pF require a crystal frequency adjustment. Request detailed crystal specifications from PhaseLink. 4 7745 Fremont Blvd., Fremont, CA 94538 TEL (510) 492-0990, FAX (510) 492-0991 w ww.phaselink.com R ev.:02-09-07 Page 4 A nalog Frequency Multiplier P L560-xx V CXO Family V OLTAGE CONTROL SPECIFICATION PARAMETERS VCXO Stabilization Time V CXO Tuning Range C LK Output Pullability Linearity VCON Input Impedance VCON Modulation BW SYMBOL TVCXOSTB CONDITIONS From power valid X TAL C 0 / C 1 < 300 V CON= 1.65V ± 1 .65V XTAL C 0 / C 1 < 300 MIN. TYP. MAX. 10 UNITS ms ppm 2 00 ± 100 ± 120 ppm 5 130 0V < VCON < 3.3V, -3dB 25 10 % kΩ kHz E XTERNAL COMPONENT VALUES INDUCTOR VALUE OPTIMIZATION T he required inductor value(s) for the best performance depends on the operating frequency, and the board layout specifications. The listed values in this datasheet are based on the calculated parasitic values from PhaseLink’s evaluation board design. These inductor values provide the user with a starting point to determine the optimum inductor values. Additional fine-tuning may be required to determine the optimal solution. To assist with the inductor value optimization, PhaseLink has developed the “AFM Tuning Assistant” software. You can download this software from PhaseLink’s web site (www.phaselink.com). The software consists of two worksheets. The first worksheet (named L2) is used to fine-tune the ‘L2’ inductor value, and the second worksheet (named L4) is used for fine tuning of the ‘L4’ (used in 4x AFMs only) inductor value. For those designs using PhaseLink’s recommended board layout, you can use the “AFM Tuning Assistant” to determine the optimum values for the required inductors. This software is developed based on the parasitic information from PhaseLink’s board layout and can be used to determine the required inductor and parallel capacitor (see LWB1 and Cstray parameters) values. For those employing a different board layout in their design, we recommend to use the parasitic information of their board layout to calculate the optimized inductor values. Please use the following fine tuning procedure: 4 7745 Fremont Blvd., Fremont, CA 94538 TEL (510) 492-0990, FAX (510) 492-0991 w ww.phaselink.com R ev.:02-09-07 Page 5 A nalog Frequency Multiplier P L560-xx V CXO Family F igure 5: Diagram Representation of the Related System Inductance and Capacitance D IE SIDE - C internal = Based on AFM device - Cpad = 2.0 pF, Bond pad and its ESD circuitry - C11 = 0.4 pF, The following amplifier stage PCB side - LWB1 = 2 nH, (2 places), Stray inductance - Cstray = 1.0 pF, Stray capacitance - L2X (L4X) = 2x or 4x inductor - C2X (C4X) = range (0.1 to 2.7 pF), Fine tune inductor if used • T here are two default variables that normally will not need to be modified. These are Cpad, and C11 and are found in cells B22 and B27 of ‘AFM Tuning Assistant’, respectively. • L WB1 is the combined stray inductance in the layout. The DIE wire bond is ~ 0.6 nH and in the case of a leaded part an additional 1.0 nH is added. Your layout inductance must be added to these. There are 2 of these and they are assumed to be approximately symmetrical so you only need to enter this inductance once in cell B23. • E nter the stray parasitic capacitance into cell B26. An additional 0.5 pF must be added to this value if a leaded part is used. • E nter the appropriate value for Cinternal into B21 based on the device used (see column D). Use the ‘AFM Tuning Assistant’ software to calculate L2X (and C2X if used) for your resonance frequency. • F or 4X AFMs, repeat the same procedure in the L4X worksheet. • S ee the examples in the following section. 4 7745 Fremont Blvd., Fremont, CA 94538 TEL (510) 492-0990, FAX (510) 492-0991 w ww.phaselink.com R ev.:02-09-07 Page 6 A nalog Frequency Multiplier P L560-xx V CXO Family D ETERMINING STRAY L’s AND C’s IN A LAYOUT F igure 6: Diagram Representation of the Board Layout L ets take the PL560-38 (4x VCXO) for example. This takes a crystal input in the range of 30 to 80 MHz and multiplies it to an output of 120 to 320 MHz. To determine the stray L’s and C’s of the layout we will assemble two test units. One AFM will be tuned to the lower range of the device (120 MHz), and the other to the upper range of the device (320 MHz). 1 20 MHz AFM Tuning: U sing the “AFM Tuning Assistant” find the PL560-3x in the L2X worksheet. Enter the Cinternal value found next to it into cell B21. In cell B24 enter the closest standard inductor value (see CoilCraft 0603CS series for example) to achieve the closest peak frequency to 60 MHz. Repeat the same procedure for L4X at 120 MHz. R esults: L2X = 180 nH, L4X = 82 nH . 3 20 MHz AFM tuning: R epeat the previous procedure for L2X at 120 MHz and L4X at 320 MHz. R esults: L2X = 24 nH, L4X = 10 nH . Proceed and assemble the test units. M easuring 120 MHz L2X: C onnect the RF generator and scope probe as shown in Figure 6, above. While power is applied to the PCB, set the generator output to +12 dBm and the frequency to 30 MHz. Since this is the 2x port, the scope will show 60 MHz with ~ 3V pk-pk amplitude. Vary the generator above and below 30 MHz until 4 7745 Fremont Blvd., Fremont, CA 94538 TEL (510) 492-0990, FAX (510) 492-0991 w ww.phaselink.com R ev.:02-09-07 Page 7 A nalog Frequency Multiplier P L560-xx V CXO Family t he amplitude on the scope is maximum and record the generator frequency. For example, the peak is recorded at 29.8x2 or 59.6 MHz. M easuring 320 MHz L2X: C onnect the RF generator and scope probe as shown in Figure 6, above. While power is applied to the PCB, set the generator output to +12 dBm and the frequency to 80 MHz. Since this is the 2x port the scope will show 160 MHz with ~ 3V pk-pk amplitude. Vary the generator above and below 80 MHz until the amplitude on the scope is maximum and record the generator frequency. For example, the peak is recorded at 78.0 x 2 = 156 MHz In the AFM Tuning Assistant, add the scope’s probe capacitance to the Cstray cell. For our example 0.5 pF + 1.0 pF = 1.5 pF. With L2X at 24 nH adjust LWB1 (cell B23) until the peak frequency reads 156 MHz. Next replace the L2X value with 180 nH and see if it peaks at 59.6 MHz. If it does not, adjust Cstray until 59.4 MHz is achieved. Again enter 24 nH for L2X and fine tune LWB1 for 156 MHz. R esults: LWB1 = 1.6 nH, Cstray = 2.9 pF-0.5 pF = 2.4 pF (subtract scope probe stray capacitance) R epeat the same steps for the L4X: Set the generator to 80 MHz. The 82 nH peaks at 118 MHz and the 10 nH peaks at 304 MHz. R esults: LWB1 = 1.8 nH, Cstray = 2.5 pF-0.5 pF = 2.0 pF (subtract scope probe stray capacitance) Internal Capacitor Selection by Device D evice Number 2X P560-0x P560-3x P560-4x P560-6x 7.625 34.125 34.125 7.625 Cinternal (pF) 4X 6.250 16.500 4 7745 Fremont Blvd., Fremont, CA 94538 TEL (510) 492-0990, FAX (510) 492-0991 w ww.phaselink.com R ev.:02-09-07 Page 8 A nalog Frequency Multiplier P L560-xx V CXO Family E LECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS P ARAMETERS S upply Voltage I nput Voltage, DC O utput Voltage, DC S torage Temperature A mbient Operating Temperature, Industrial Temperature A mbient Operating Temperature, Commercial Temperature J unction Temperature L ead Temperature (soldering, 10s) I nput Static Discharge Voltage Protection SYMBOL V DD VI VO TS T A_I T A_C TJ MIN. MAX. 4 .6 UNITS V V V °C °C °C °C °C kV G ND-0.5 G ND-0.5 - 65 - 40 0 V DD +0.5 V DD +0.5 150 +85 + 70 1 25 260 2 E xposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. P ECL ELECTRICAL CHARACTERISTICS PARAMETERS Supply Current (with loaded outputs) Operating Voltage Output Clock Duty Cycle Short Circuit Current Output High Voltage Output Low Voltage Clock Rise Time Clock Fall Time VOH VOL tr tf @20/80% @80/20% 0.25 0.25 RL = 50 Ω to (VDD – 2V) VDD – 1.025 VDD – 1.620 0.45 0.45 SYMBOL IDD VDD CONDITIONS Fout = 622 MHz MIN. 2.25 TYP. 75 MAX. 80 3.63 55 UNITS mA V % mA V V ns ns @ Vdd – 1.3V 45 50 ±50 PECL Transition Time Waveform DUTY CYCLE PECL Levels Test Circuit OUT VDD OUT PECL Output Skew 45 - 55% 55 - 45% OUT 50Ω 2.0V 50% 80% 20% 50Ω OUT OUT tSKEW OUT tR tF 4 7745 Fremont Blvd., Fremont, CA 94538 TEL (510) 492-0990, FAX (510) 492-0991 w ww.phaselink.com R ev.:02-09-07 Page 9 A nalog Frequency Multiplier P L560-xx V CXO Family L VDS ELECTRICAL CHARACTERISTICS PARAMETERS Supply Current (with loaded outputs) Operating Voltage Output Clock Duty Cycle Short Circuit Current Output Differential Voltage VDD Magnitude Change Output High Voltage Output Low Voltage Offset Voltage Offset Magnitude Change Power-off Leakage Output Short Circuit Current Differential Clock Rise Time Differential Clock Fall Time VOD ∆VOD VOH VOL VOS ∆VOS IOXD IOSD tr tf RL = 100 CL = 10 pF (see figure) 0.2 0.2 Vout = VDD or GND VDD = 0V RL = 100 (see figure) 247 -50 1.4 0.9 1.125 0 1.1 1.2 3 ±1 -5.7 0.5 0.5 LVDS Transition Time Waveform SYMBOL IDD VDD CONDITIONS Fout = 622 MHz MIN. TYP. 55 MAX. 60 3.63 UNITS mA V % mA 2.25 @ 1.25V (LVDS) 45 50 ±50 355 55 454 50 1.6 mV mV V V 1.375 25 ±10 -8 0.7 0.7 V mV A mA ns ns LVDS Levels Test Circuit OUT LVDS Switching Test Circuit OUT OUT 0V (Differential) OUT 50Ω CL = 10pF VOD VOS VDIFF RL = 100Ω VDIFF 0V 20% 80% 80% 50Ω CL = 10pF OUT OUT tR tF 20% 4 7745 Fremont Blvd., Fremont, CA 94538 TEL (510) 492-0990, FAX (510) 492-0991 w ww.phaselink.com R ev.:02-09-07 Page 10 A nalog Frequency Multiplier P L560-xx V CXO Family C MOS ELECTRICAL CHARACTERISTICS PARAMETERS S upply Current, Dynamic, with Loaded Outputs O perating Voltage O utput High Voltage (LVTTL) O utput Low Voltage (LVTTL) O utput High Voltage (LVCMOS) O utput High Voltage O utput Low Voltage O utput drive current Output Clock Rise/Fall Time Output Clock Duty Cycle Short Circuit Current SYMBOL I DD V DD V OH3.3 V OL3.3 V OHC3.3 V OH2.5 V OL2.5 CONDITIONS A t 100MHz, load=15pF MIN. TYP. 16 MAX. 20 3.63 UNITS mA 2 .25 I OH = - 8.5mA, 3.3V Supplies I OL = 8 .5mA, 3.3V Supplies I OH = - 4mA, 3.3V Supplies I OH = 1 mA, 2.5V Supplies I OL = 1 mA, 2.5V Supplies V OL = 0 .4V, V OH = 2 .4V (per output), 3.3V Supplies 1 0% ~ 90% VDD with 10 pF load M easured @ 50% VDD 45 8.5 1.2 50 ±50 V DD – 0 .4 V DD – 0 .2 2.4 V V 0.4 V V V 0.2 V I OSD3.3 T r ,T f mA 1.6 55 ns % mA IS 4 7745 Fremont Blvd., Fremont, CA 94538 TEL (510) 492-0990, FAX (510) 492-0991 w ww.phaselink.com R ev.:02-09-07 Page 11 A nalog Frequency Multiplier P L560-xx V CXO Family BOARD DESIGN AND LAYOUT CONSIDERATIONS L 2X and L4X: T ry to reduce the PCB trace inductance to a minimum by placing L2X and L4X as physically close to their respective pins as possible. Also be sure to bypass each Vdd connection especially taking care to place a 0.01 uF bypass at the Vdd side of L2X and L4X (see recommended layout). C rystal connections: B e sure to keep the ground plane under the crystal connections continuous so that the stray capacitance is consistent on both crystal connections. Also be sure to keep the crystal connections symmetrical with respect to one another and the crystal connection pins of the IC. If you chose to use a series capacitance and or inductor to fine tune the crystal frequency be sure to put symmetrical pads for this cap on both crystal pins (see Cadj in recommended layout), even if one of the capacitors will be a 0.01 uF and the other is used to tune the frequency. To further maintain a symmetrical balance on a crystal that may have more internal Cstray on one pin or the other, place capacitor pads (Cbal) on each crystal lead to ground (see recommended layout). R3rd is only required if a 3 rd o vertone crystal is used. V DD a nd GND: B ypass VDDANA and VDDBUF with separate bypass capacitors and if a V DD p lane is used, feed each bypass cap with its own via. Be sure to connect any ground pin including the bypass caps with short via connections to the ground plane. O ESEL: J 1 is recommended so the same PCB layout can be used for both OESEL settings. 2 X Layout (TSSOP) 4X Layout (TSSOP) 4 7745 Fremont Blvd., Fremont, CA 94538 TEL (510) 492-0990, FAX (510) 492-0991 w ww.phaselink.com R ev.:02-09-07 Page 12 A nalog Frequency Multiplier P L560-xx V CXO Family P ACKAGE PIN DESCRIPTION AND ASSIGNMENT GNDBUF VDDBUF QBAR Q OSCOFFSEL GNDOSC 1 2 16 15 L2X VDDOSC OESEL VDDANA VDDBUF QBAR Q GNDBUF VDDANA OESEL VDDOSC L2X 13 14 15 16 OSCOFFSEL GNDOSC VCON XIN XOUT OE DNC GNDANA 1 2 16 15 L2X VDDOSC 12 11 10 9 8 7 6 5 GNDBUF VDDBUF QBAR Q VDDANA 14 13 12 11 10 9 OESEL 12 13 14 15 16 11 10 9 8 7 6 5 GNDANA DNC OE VDDOSC L4X OE XOUT PLL560-0X PLL560-4X 3 4 5 6 7 8 VCON XIN XOUT 3 4 5 6 7 8 14 13 12 11 10 9 OESEL VDDANA VDDBUF QBAR P560-4X 1 2 3 4 P560-0X 1 2 3 4 VDDOSC L2X XOUT OE L4X VDDOSC OSCOFF SEL GNDOSC OSCOFF SEL GNDOSC Q GNDBUF 2 X AFM Package Pin Out VCON XIN 4 X AFM Package Pin Out P IN ASSIGNMENTS Name OSCOFFSEL GNDOSC VCON XIN XOUT OE DNC L4X 7 I Pin# 1 2 3 4 5 6 Type I P I I O I Product 2X & 4X 2X & 4X 2X & 4X 2X & 4X 2X & 4X 2X & 4X 2X 4X Description Set to “0” (GND) to choose to turn off the oscillator when outputs are disabled (OE). Default (no connect) is OSC always on. GND connection for oscillator circuitry. Control Voltage input. Use this pin to change the output frequency by varying the applied Control Voltage. Input from crystal oscillator circuitry. Output from crystal oscillator circuitry. Output Enable input (see "OE LOGIC SELECTION TABLE"). Do Not Connect. External inductor connection. The inductor is recommended to be a high Q small size 0402 or 0603 SMD component, and must be placed between L4X and adjacent VDDOSC. Place inductor as close to the IC as possible to minimize parasitic effects and to maintain inductor Q. This inductor is used with 4X AFMs. GND connection. VDD connection for oscillator circuitry. VDDOSC should be separately decoupled from other VDDs whenever possible. GND connection for output buffer circuitry. PECL/LVDS or CMOS output. Complementary PECL/LVDS output or in phase CMOS. VDD connection for output buffer circuitry. VDDBUF should be separately decoupled from other VDDs whenever possible. VDD connection for analog circuitry. VDDANA should be separately decoupled from other VDDs whenever possible. Selector input to choose the OE control logic (see “OE SELECTION TABLE”). Internal pull-down. VDD connection for oscillator circuitry. VDDOSC should be separately decoupled from other VDDs whenever possible. External inductor connection. The inductor is recommended to be a high Q small size 0402 or 0603 SMD component, and must be placed between L2X and adjacent VDDOSC. Place inductor as close to the IC as possible to minimize parasitic effects and to maintain inductor Q. GNDANA 8 VDDOSC GNDBUF Q QBAR VDDBUF VDDANA OESEL VDDOSC 9 10 11 12 13 14 15 P O O P P I P P 2X 4X 2X & 4X 2X & 4X 2X & 4X 2X & 4X 2X & 4X 2X & 4X 2X & 4X L2X 16 I 2X & 4X 4 7745 Fremont Blvd., Fremont, CA 94538 TEL (510) 492-0990, FAX (510) 492-0991 w ww.phaselink.com R ev.:02-09-07 Page 13 VCON XIN A nalog Frequency Multiplier P L560-xx V CXO Family P ACKAGE INFORMATION 16 PIN TSSOP 16 PIN TSSOP ( mm ) Symbol A A1 B C D E H L e Min. Max. 1.20 0.05 0.15 0.19 0.30 0.09 0.20 4.90 5.10 4.30 4.50 6.40 BSC 0.45 0.75 0.65 BSC E H D A A1 e B C L 1 6 PIN 3x3 QFN 4 7745 Fremont Blvd., Fremont, CA 94538 TEL (510) 492-0990, FAX (510) 492-0991 w ww.phaselink.com R ev.:02-09-07 Page 14 A nalog Frequency Multiplier P L560-xx V CXO Family O RDERING INFORMATION F or part ordering, please contact our Sales Department: 4 7745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER T he order number for this device is a combination of the following: Device number, Package type and Operating temperature range PL560-XX X X X X P ART NUMBER N ONE= TUBE R = TAPE AND REEL N ONE= NORMAL PAC KAGE L = GREEN PACKAGE T EMPERATURE C =COMMERCIAL I=INDUSTRIAL P ACKAGE TYPE O =TSSOP Q= QFN 3x3 O rder Number P L 560 - XXOC P L 560 - XXOC - R P L 560 - XXOCL P L 560 - XXOC L - R P L 560 - XXQC P L 560 - XXQC - R P L 560 - XXQC L P L 560 - XXQC L - R M arking P 560 - XX P 560 - XX P 560 - XX P 560 - XX P 560 - XX P 560 - XX P 560 - XX P 560 - XX OC OC OC OC QC QC QC QC P ackage Option T SSOP – T ube T SSOP – T ape and Reel T SSOP (GREEN) – Tube T SSOP (GREEN) – T ape and Reel Q FN – T ube Q FN – T ape and Reel Q FN (GREEN) – T ube Q FN (GREEN) – T ape and Reel P haseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. L IFE SUPPORT POLICY : PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 4 7745 Fremont Blvd., Fremont, CA 94538 TEL (510) 492-0990, FAX (510) 492-0991 w ww.phaselink.com R ev.:02-09-07 Page 15