PL610-01-XXXTI-R

( Preliminary) PL610 - 01 1.8V to 3 .3V , 1MHz to 130MHz XO IC FEATURES  W ide frequency coverage, programmable , a dvanced oscillator design.  Programmable “Odd/Even” Divider up to ÷63  D irect oscillation operation with optional programmable features: o Output Drive Strength (4, 8, or 16mA) o 6 - bit Odd/Even Output Divider  Input Frequency: o Fundamental C rystal: 5MHz to 1 3 0MHz o Reference Clock : 1 MHz to 1 3 0MHz  Supports CMOS or Sine Wave input clock  Output F requency: 20kHz to 1 3 0MHz  Very low Jitter and Phase Noise  Low current consumption  Single 1.8V, 2.5V, or 3.3V ± 10% power supply  Operating temperature range from - 40  C to 85  C DESCRIPTION The PL610 is a high performance general purpose oscillator IC for outputs up to 130MHz . Desi gned to fit in a small 2 x 1.3 mm DFN or 3 x 3mm SOT23 package , the PL610 offers the best phas e noise and jitter performance and lowest power consumption of any comparable IC. In addition, there is a ‘6’ bit optional programmable Odd/Even divider (default= ٪ 1), and ‘3’ programmable output drive strengths (4mA, 8mA (default), 16mA) to choose from. The full feature set of the PL610 makes it the most versatile XO for any application. P ACKAGE PIN CONFIGURATION OE^, PDB^, CLK1 XIN, FIN OE^, PDB^, CLK1 GND 1 2 3 6 5 4 CLK0 VDD XOUT 1 2 3 6 5 4 XOUT VDD CLK0 GND XIN, FIN DFN-6L (2.0mmx1.3mmx0.6mm) SOT23-6L (3.0mmx3.0mmx1.35mm) BLOCK DIAGRAM 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492 - 0990 Fax (510) 492 - 0991 www.phaselink.com Rev 4/2 /07 Page 1 ( Preliminary) PL610 - 01 1.8V to 3 .3V , 1MHz to 130MHz XO IC KEY PROGRAMMING PARAMETERS (Optional) CLK[0:1] Output Frequency F OUT = F REF / P * ( *: P is an Odd/Even Divider) Where P = 6 bit CLK0 = F REF , F REF /2 or F REF / P CLK1 = F REF , F REF /2 or CLK0 Output Drive Strength Three optional drive st rengths to choose from:  Low: 4mA  Std: 8mA (default)  High: 16mA Programmable Input/Output One output pin can be configured as:  OE - input  PDB - input  CLK1 – output PACKAGE PIN AND DIE PAD ASSIGNMENT Name XIN, FIN Pin Assignment DFN - 6L 1 SOT 23 - 6L 3 Type I Description Cr ystal or Reference Clock input pin This programmable I/O pin can be configured as an Output Enable (OE) input, Power Down input (PDB) input or CLK1 clock output . This pin has an internal 60K Ω p u l l u p r e s i s t o r for OE and 10M Ω p u l l up resistor for PDB . 2 1 I/O State 0 1 (default) GND CLK0 VDD XOUT 3 4 5 6 2 6 5 4 P O P O GND connection Programmable Clock Output VDD connection Crystal Output pin Do Not Connect (DNC ) w hen FIN is present OE Tri - state CLK Normal mode PDB Power Down Mode Normal mode OE, PDB, CLK1 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492 - 0990 Fax (510) 492 - 0991 www.phaselink.com Rev 4/2 /07 Page 2 ( Preliminary) PL610 - 01 1.8V to 3 .3V , 1MHz to 130MHz XO IC FUNCTIONAL DESCRIPTION PL610 - 01 is a highly featured, very flexible, advanced XO design for high performance, low - power, small form factor applications. The PL610 - 01 accepts a fundamental input crystal of 5 MHz to 130 MHz or a refere nce clock input of 1MHz to 1 3 0MHz and is capable of producing two outputs up to 1 3 0MHz. This flexible design allows the PL610 - 01 to deliver any frequency, FREF (Crystal or Ref Clk) frequency , FREF / 2 or FREF / P to CLK0 and/or CLK1. Some of the design f eatures of the PL610 - 01 are mentioned below: Clock Output (CLK0) CLK0 is the main clock output. The output from CLK0 can be FREF (Crystal or Ref Clk), F REF/ 2 or FREF/P output. The output drive level can be programmed to Low Drive (4mA), Standard Drive (8mA) or High Drive (16mA). Programmable I/O (OE/PDB /CLK1) The PL610 - 01 provides one programmable I/O pin which can be configured as one of the following functions: Output Enable (OE) The Output Enable feature allows the user to enable and disable the clo ck output(s) by toggling the OE pin. The OE pin incorporates a 60k Ω p u l l u p r esistor giving a default condition of logic “1”. Power - Down Control (PDB) The Power Down (PDB) feature allows the user to put the PL610 - 01 into “Sleep Mode”. When activated (lo gic ‘0’), PDB ‘Disables the PLL, the oscillator circuitry, counters, and all other active circuitry. In Power Down mode the IC consumes 50MHz. Series and parallel capacitors used to fine tune the crystal load to the circuit load. Crystal Cst XIN 1 Cpt 8 Cpt XOUT – Series Capacitor, used to lower circuit load to match crystal load. Raises frequency offset. This can be eliminated by using a crystal with a Cload of equal or greater value than the oscillator. – Parallel Capacitors, Used to raise the circuit load to match the crystal load. Lowers frequency offset. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492 - 0990 Fax (510) 492 - 0991 www.phaselink.com Rev 4/2 /07 Page 4 ( Preliminary) PL610 - 01 1.8V to 3 .3V , 1MHz to 130MHz XO IC ELECTRICAL SPECIFICATIONS ABSOLUT E MAXIMUM RATINGS PARAMETERS Supply Voltage Range Input Voltage Range Output Voltage Range Storage Temperature Ambient Operating Temperature * SYMBOL V DD VI VO TS MIN. - 0.5 - 0.5 - 0.5 - 65 - 40 MAX. 4.6 V DD +0.5 V DD +0.5 150 85 UNITS V V V C C Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only. AC SPECIFICATIONS PARAMETERS Crystal Input Frequency Input (FIN) Frequency Input (FIN) Signal Amplitude Input (FIN) Signal Amplitude Output Frequency VDD Sensitivity Output Rise Time (See MTC - 1) Output Fall Time (See MTC - 1) Duty Cycle (See MTC - 1) CONDITIONS Fundamental Crystal @ V DD =3.3V @ V DD =2.5V @ V DD =1.8V Internally AC coupled (High Frequency) Internally AC coupled (Low Frequency) 3.3V < 50MHz, 2.5V < 40MHz, 1.8V < 15MHz @ Vdd= 1.8V - 3.3V Frequency vs. VDD+/ - 10% 15pF Load, 10/90%VDD, H igh Drive, 3.3V 15pF Load, 90/10%VDD, High Drive, 3.3V 45 0.9 0.1 20kHz -2 1 1 50 V DD V DD 130 2 1.2 1.2 55 Vpp Vpp MHz ppm ns ns % 1 130 MHz MIN. 5 TY P. MAX. 130 UNITS MHz 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492 - 0990 Fax (510) 492 - 0991 www.phaselink.com Rev 4/2 /07 Page 5 ( Preliminary) PL610 - 01 1.8V to 3 .3V , 1MHz to 130MHz XO IC DC SPECIFICATIONS PARAMETERS Supply Current, Dynamic, with Loaded CMOS Output SYMBOL CONDITIONS @Vdd=3.3V, 25MHz, load=15pF I DD @Vdd=2.5V, 25MHz, load=10pF @Vdd=1.8V, 25MHz, load=5pF @Vdd=1.8V, 2.0MHz, load=5pF Operating Voltage Output Low Voltage Output High Voltage Output Current, Low Drive (See MCT - 2) Output Current, Standard Drive (See MCT - 2) Output Current, High Drive (Se e MCT - 2) V DD V OL V OH I OLD I OSD I OHD I OL = +4mA Standard Drive I OH = - 4mA Standard Drive V OL = 0.4V, V OH = 2.4V V OL = 0.4V, V OH = 2.4V V OL = 0.4V, V OH = 2.4V V DD – 0.4 4 8 16 1.62 MIN TYP 3.4 2.1 0.9 0.65 3.63 0 .4 MAX UNITS mA mA mA mA V V V mA mA mA CRYSTAL SPECIFICATIONS (5MHz - 60MHz) PARAMETERS Fundamental Crystal Resonator Frequency Crystal Loading Ra t ing (The IC can be programmed for any value in this range.) Maximum Sustainable Drive Level Operating Drive Level Crystal Shunt Capacitance Effective Series Resistance, Fundamental, 5 - 60MHz (See MTC - 1) C0 ESR 25 3 50 SYMBOL F XIN C L (xtal) MIN. 5 8 TYP. MAX. 60 12 100 UNITS MHz pF W W pF   47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492 - 0990 Fax (510) 492 - 0991 www.phaselink.com Rev 4/2 /07 Page 6 ( Preliminary) PL610 - 01 1.8V to 3 .3V , 1MHz to 130MHz XO IC CRYSTAL SPECIFICATIONS (60MHz - 130MHz) PARAMETERS Fundamental Crystal Reson ator Frequency Crystal Loading Ra t ing (The IC can be programmed for any value in this range.) Maximum Sustainable Drive Level Operating Drive Level Crystal Shunt Capacitance Effective S eries Resistance, Fundamental, 60 - 130MHz (See MTC - 1) C0 ESR 25 2.5 30 SYMBOL F XIN C L (xtal) MIN. 60 5 TYP. MAX. 130 8 100 UNITS MHz pF W W pF   47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492 - 0990 Fax (510) 492 - 0991 www.phaselink.com Rev 4/2 /07 Page 7 ( Preliminary) PL610 - 01 1.8V to 3 .3V , 1MHz to 130MHz XO IC MEASUREMENT TEST CIRCUITS (MTC) MTC-1: Rise Time, Fall Time, Duty Cycle, VOL, VOH, Idd, Power Down Current, Output Enable/Disable MTC-3: Jitter and Phase Noise A 0.1µF VDD XIN 0.1µF VDD XIN CLK XOUT OE^ GND CL FET Probe R CLK 0.1µF XOUT OE^ GND MTC-2: Output Drive Current and Output Impedance MTC-4: Negative Resistance 0.1µF VDD XIN CLK XOUT OE^ GND 0.1µF V FET Probe Network Analyzer VDD XIN CLK XOUT OE^ GND 0.1µF 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492 - 0990 Fax (510) 492 - 0991 www.phaselink.com Rev 4/2 /07 Page 8 ( Preliminary) PL610 - 01 1.8V to 3 .3V , 1MHz to 130MHz XO IC WAVEFORM SWITCHING CHARACTERISTICS Rise and Fall times: 90%Vdd 10%Vdd tr tf Duty Cycle: 50%Vdd Tw T Tw T Duty Cycle = 100% × VOH, VOL: VDD VOH VOL GND 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492 - 0990 Fax (510) 492 - 0991 www.phaselink.com Rev 4/2 /07 Page 9 ( Preliminary) PL610 - 01 1.8V to 3 .3V , 1MHz to 130MHz XO IC PACKAGE DRAWINGS ( GREEN PACKAGE COMPLIANT) Symbol A A1 A3 b e D E D1 E1 L Dimension (MM) Min. Max. 0.5 0.6 0 0.05 0.152 REF 0.15 0.25 0.40BSC 1.25 1.35 1.95 2.05 0.75 0.85 0.95 1.05 0.2 0.3 Recommended Land Pattern (MM) Dimension (MM) Symbol Min A A1 A2 b c D E H L e 1.05 0.05 1.00 0.35 Max 1.45 0.15 1.30 0.50 Pin1 Dot 1.905 E H 3.785 ±0.50 D 2.362 C L A2 A1 e b A 0.95 0.482 ±0.050 1.473 0.915 ±0.05 0.127 Typical 2.80 1.50 2.60 0.35 3.00 1.70 3.00 0.55 0.95 Typical 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492 - 0990 Fax (510) 492 - 0991 www.phaselink.com Rev 4/2 /07 Page 10 ( Preliminary) PL610 - 01 1.8V to 3 .3V , 1MHz to 130MHz XO IC ORDERING INFORMATION ( GREEN PACKAGE) For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492 - 0990 Fax: (510) 492 - 0991 PART NUMBER The order number for this device is a combination of the following: Part number, Package type and Operating temperature range PL6 10 - 01 - XX X X X X PART NUMBER 3 DIGIT ID Code * (will be assigned at programming time) PACKAGE TYPE T=SOT23-6L G=DFN-6L Part/Order Number Marking† NONE= TUBE R=TAPE and REEL TEMPERATURE C=COMMERCIAL I=INDUSTRIAL Package Option PL610-01-XXXGC-R PL610-01-XXXTC-R † XXX E1XXX 6-Pin DFN (Tape and Reel) 6-Pin SOT-23 (Tape and Reel) Note: ‘XXX’ designates marking identifier that could be independent of the part number. PhaseLink Corporation, reserves the right to make changes in i ts products or specifications, or both at any time without notice. The information fu r nished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY : PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the e x press written approval of the President of PhaseLink Corporation. Solder reflow profile available at www.phaselink.com/QA/solderingGreen.pdf 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492 - 0990 Fax (510) 492 - 0991 www.phaselink.com Rev 4/2 /07 Page 11