PL611S-02-XXXGIR

( Preliminary) PL611s-02 1 .8V-3.3V PicoPLL TM , World’s Smallest Programmable Clock F EATURES • L owest-power, smallest Programmable PLL • V ery low Jitter and Phase Noise • O utput Frequency up to: o 1 33MHz @ 1.8V operation o 1 66MHz @ 2.5V operation o 2 00MHz @ 3.3V operation • I nput Frequency: o F undamental Crystal: 10MHz to 50MHz o R eference Clock: 1MHz to 200MHz • A ccepts > 0.1V reference signal input voltage • O ne I/O pin can be configured as Output Enable (OE), Frequency switching (FSEL), Power Down (PDB) input, or CLK1 output. • < 10 A current consumption with PDB active. • S ingle 1.8V, 2.5V, or 3.3V ± 10% power supply • O perating temperature range from -40 ° C to 85 ° C • A vailable in 6-pin DFN, SOT23, and SC70 G REEN /RoHS compliant packages. D ESCRIPTION T he PL611s-02 is a low-power, small form factor, high performance OTP-base programmable frequency synthesizer and a member of PhaseLink’s PicoPLL Factory Programmable ‘Quick Turn Clocks. Designed to fit in a small DFN, SC70, or SOT23 package for a broad range of applications, the PL611s-02 offers the best phase noise and jitter performance, and power consumption of its rivals. . In addition, one programmable I/O pin can be configured as Output Enable (OE), Frequency switching (FSEL), Power Down (PDB) input, or CLK1 (F OUT , F REF , F REF /2) output. The power down feature of PL611s-02, when activated, allows the IC to consume less than 10 A of power, while its programming flexibility allows generating any output, up to 200MHz using a low-cost crystal or reference input. P ACKAGE PIN CONFIGURATION GND XIN/FIN OE, PDB, FSEL, CLK1 GND 1 2 3 6 5 4 XOUT VDD CLK0 611s-02 1 2 3 6 5 4 CLK0 VDD XOUT OE, PDB, FSEL, CLK1 GND XIN/FIN PL611s-02 1 2 3 6 5 4 CLK0 VDD XOUT PL611s-02 OE, PDB, FSEL, CLK1 XIN/FIN DFNDFN-6L (2.0mmx1.3mmx0.6mm) SC70SC70-6L 70 (2.3mmx2.25mmx1.0mm) SOT23SOT23-6L 23 (3.0mmx3.0mmx1.35mm) BLOCK DIAGRAM XIN/FIN XOUT XTAL OSC Programmable CLoad FREF R-Counter (8-bit) M-Counter (11-bit) Phase Detector Charge Pump Loop Filter F VCO = F REF * (2 * M/R) VCO P-Counter (5-bit) FOUT = F VCO / (2 * P) Programmable Function CLK0 Programming Logic OE, PDB, FSEL, CLK1 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 12/12/06 Page 1 ( Preliminary) PL611s-02 1 .8V-3.3V PicoPLL TM , World’s Smallest Programmable Clock K EY PROGRAMMING PARAMETERS CLK Output Frequency FOUT = FREF * M / (R * P) Where M = 11 bit R = 8 bit P = 5 bit CLK0 = FOUT, FREF or FREF / (2*P) CLK1 = FREF, FREF/2, CLK0 or CLK0/2 Output Drive Strength Three optional drive strengths to choose from: • Low: 4mA • Std: 8mA (default) • High: 16mA Programmable Input/Output One output pin can be configured as: • OE - input • PDB - input • FSEL - input • CLK1 – output P ACKAGE PIN ASSIGNMENT P in Assignment N ame S OT23 Pin # S C70 Pin# D FN Pin# T ype Description This programmable I/O pin can be configured as an Output Enable (OE) input, Power Down input (PDB), On-the-Fly Frequency Switching Selector (FSEL), or CLK1 clock output This pin has an internal 60K pull up resistor for OE, PDB & FSEL. S tate 0 1 ( default) OE T ri-State CLK Normal mode PDB Power Down Mode Normal mode FSEL Frequency ‘2’ Frequency ‘1’ O E, PDB, FSEL, CLK1 1 2 2 I/O G ND X IN, FIN X OUT V DD C LK0 2 3 4 5 6 1 3 4 5 6 3 1 6 5 4 P I O GND connection Crystal or Reference Clock input pin C rystal Output pin Do Not Connect (DNC ) when FIN is present P O VDD connection Programmable Clock Output 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 12/12/06 Page 2 ( Preliminary) PL611s-02 1 .8V-3.3V PicoPLL TM , World’s Smallest Programmable Clock F UNCTIONAL DESCRIPTION P L611s-02 is a highly featured, very flexible, advanced programmable PLL design for high performance, lowpower, small form-factor applications. The PL611s-02 accepts a fundamental input crystal of 10MHz to 50MHz or reference clock input of 1MHz to 200MHz and is capable of producing two outputs up to 200MHz. This flexible design allows the PL611s-02 to deliver any PLL generated frequency, F REF ( Crystal or Ref Clk) frequency or F REF / (2*P) to CLK0 and/or CLK1. Some of the design features of the PL611s-02 are mentioned below: P LL Programming T he PLL in the PL611s-02 is fully programmable. The PLL is equipped with an 8-bit input frequency divider (R-Counter), and an 11-bit VCO frequency feedback loop divider (M-Counter). The output of the PLL is transferred to a 5-bit post VCO divider (PCounter). The output frequency is determined by the following formula [F OUT = F REF * M / ( R * P) ]. C lock Output (CLK0) C LK0 is the main clock output. The output of CLK0 can be configured as the PLL output (F VCO /(2*P)), F REF ( Crystal or Ref Clk) output, or F REF /(2*P) output. The output drive level can be programmed to Low Drive (4mA), Standard Drive (8mA) or High Drive (16mA). The maximum output frequency is determined by the Power Supply Voltage; 200MHz at 3.3V, 166MHz at 2.5V and 133MHz at 1.8V. Clock Output (CLK1) T he CLK1 feature allows the PL611s-02 to have an additional clock output programmed to one of the following: F REF - R eference (Crystal or Ref Clk) Frequency F REF / 2 C LK0 CLK0 / 2 Output Enable (OE) T he Output Enable feature allows the user to enable and disable the clock output(s) by toggling the OE pin. The OE pin incorporates a 60k pull up resistor giving a default condition of logic “1”. Power-Down Control (PDB) T he Power Down (PDB) feature allows the user to put the PL611s-02 into “Sleep Mode”. When activated (logic ‘0’), PDB ‘Disables the PLL, the oscillator circuitry, counters, and all other active circuitry. In Power Down mode the IC consumes 1 inch) to a CMOS output, it is important to design the traces as a transmission line or ‘stripline’, to avoid reflections or ringing. In this case, the CMOS output needs to be matched to the trace impedance. Usually ‘striplines’ are designed for 50 impedance and CMOS outputs usually have lower than 50 impedance so matching can be achieved by adding a resistor in series with the CMOS output pin to the ‘stripline’ trace. - Please contact PhaseLink for additional information on how to design outputs driving long traces or for the Gerber files for the PL611s-02 eval board shown. D FN-6L Evaluation Board 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 12/12/06 Page 6 ( Preliminary) PL611s-02 1 .8V-3.3V PicoPLL TM , World’s Smallest Programmable Clock PACKAGE DRAWINGS ( GREEN P ACKAGE COMPLIANT) SOT23-6 L Symbol A A1 A2 b c D E H L e SC70-6L Symbol A A1 A2 b c D E H L e DFN-6L D1 Dimension in MM Min. Max. 1.05 1.35 0.05 0.15 1.00 1.20 0.30 0.50 0.08 0.20 2.80 3.00 1.50 1.70 2.60 3.0 0.35 0.55 0.95 BSC Pin1 Dot E H D A2 A A1 e b C L Dimension in MM Min. Max. 0.80 1.00 0.00 0.09 0.80 0.91 0.15 0.30 0.08 0.25 1.85 2.25 1.15 1.35 2.00 2.30 0.21 0.41 0.65BSC Pin1 Dot E H D A2 A A1 e b C L Symbol A A1 A3 b e D E D1 E1 L Dimension in MM Min. Max. 0.50 0.60 0.00 0.05 0.152 0.152 0.15 0.25 0.40BSC 1.25 1.35 1.95 2.05 0.75 0.85 0.95 1.05 0.20 0.30 b e Pin 6 ID Chamfer E1 E D L Pin1 Dot A A1 A3 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 12/12/06 Page 7 ( Preliminary) PL611s-02 1 .8V-3.3V PicoPLL TM , World’s Smallest Programmable Clock O RDERING INFORMATION ( GREEN P ACKAGE) For part ordering, please contact our Sales Department: 4 7745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 P ART NUMBER The order number for this device is a combination of the following: Part number, Package type and Operating temperature range P L611s-02-XXX X X X P ART NUMBER 3 DIGIT ID Code * (will be assigned at programming time) PACKAGE TYPE G=DFN-6L U=SC70-6L T=SOT23-6L Part/Order Number PL611s-02-XXXGC-R PL611s-02-XXXUC-R PL611s-02-XXXTC-R † NONE= TUBE R=TAPE and REEL T EMPERATURE C=COMMERCIAL I=INDUSTRIAL Marking† XXX XXX 02XXX Package Option 6-Pin DFN (Tape and Reel) 6-Pin SC70 (Tape and Reel) 6-Pin SOT23 (Tape and Reel) N ote: ‘XXX’ designates marking identifier that could be independent of the part number. P haseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. L IFE SUPPORT POLICY : PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. S older reflow profile available at w ww.phaselink.com/QA/solderingGreen.pdf 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 12/12/06 Page 8